A downwardly arched bridge VDMOSFET device

Abstract

The application discloses a downward arch bridge type VDMOSFET device, which has symmetrical stepped grooves formed by etching a semiconductor layer; the inner wall and both sides of the stepped grooves are covered with a first gate dielectric; the first gate dielectric in the stepped grooves is further provided with a second gate dielectric; the first gate dielectric and the second gate dielectric jointly form a thickened gate dielectric layer of the downward arch bridge type VDMOSFET device; the semiconductor layer is provided with a current conducting area and a drift area, and the current conducting area extends downward from the surface of the stepped grooves to the drift area. The application reduces the size of the arch bridge type VDMOSFET cell without reducing the minimum line width of the device, and obtains better dynamic characteristics by reducing the gate-drain capacitance; and the deeper P well and the thicker gate dielectric layer thickness ensure the reliability of the device.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of microelectronics, and particularly relates to a downward arch bridge type VDMOSFET device. BACKGROUND

[0002] Under the overall good environment of the power electronics industry, power semiconductor devices, which play a decisive role in power electronics, become a direct factor affecting the cost and efficiency of power electronic equipment. Although silicon-based power devices are very mature at this stage, with the development of power semiconductors towards high power, high frequency and low power consumption, silicon (Si) based devices begin to be difficult to apply to some high voltage, high temperature, high efficiency and high power density application scenarios due to their own physical characteristics.

[0003] Silicon carbide (SiC) material has begun to attract widespread attention from practitioners due to its superior physical properties, and therefore SiC MOSFET (silicon carbide metal oxide semiconductor field effect transistor) technology has developed. Compared with silicon-based devices, the high thermal conductivity and large bandgap of silicon carbide material determine its application in high current density, high breakdown field strength and high working temperature scenarios. Compared with Si MOSFET of the same level, the specific on-resistance and switching loss of SiC MOSFET make it suitable for higher working frequency, and its high thermal conductivity greatly improves the high temperature stability.

[0004] VDMOSFET (Vertical Double-diffused Metal-Oxide Semiconductor Field-Effect Transistor), also known as vertical double-diffused MOS transistor, is a basic structure of power MOSFET like LDMOSFET (Lateral Diffused Metal-Oxide Semiconductor Field-Effect Transistor), and belongs to semiconductor power devices. Compared with LDMOSFET, VDMOSFET occupies less area, and the corresponding frequency characteristics are also improved.

[0005] In related technologies, a structure of a common VDMOSFET is as shown in Figure 1 However, the electric field of the VDMOSFET will be concentrated in the middle part of the device gate oxide layer, and long-term electric field concentration will seriously affect the reliability of the device gate oxide layer. In order to solve this problem, a structure of an arch bridge type VDMOSFET is as shown in Figure 2 This arch bridge type VDMOSFET device reduces the gate-drain capacitance by increasing the thickness of the middle part. However, Figure 1 and Figure 2The gate-drain capacitance of the VDMOSFET shown cannot reduce the width of the gate electrode directly exposed to the drain end, resulting in difficulty in effectively reducing the switching characteristics of the device. Therefore, how to make the VDMOSFET have better reliability and switching characteristics is still a technical problem at present. SUMMARY

[0006] In order to solve the above problems existing in the prior art, the application provides a downward arch bridge type VDMOSFET device.

[0007] The technical problem to be solved by the application is solved by the following technical scheme:

[0008] A downward arch bridge type VDMOSFET device has a symmetrical stepped groove formed by etching a semiconductor layer; the inner wall and both sides of the stepped groove are covered with a first gate dielectric; wherein the first gate dielectric in the stepped groove is further provided with a second gate dielectric; the first gate dielectric and the second gate dielectric together constitute a thickened gate dielectric layer of the downward arch bridge type VDMOSFET device.

[0009] The semiconductor layer is provided with a current guide region and a drift region, and the current guide region extends downward from the surface of the stepped groove to the drift region.

[0010] Optionally, the second gate dielectric fills the remaining space outside the first gate dielectric in the stepped groove, and the upper surface of the second gate dielectric is flush with the upper surface of the first gate dielectric on both sides of the stepped groove.

[0011] Optionally, the second gate dielectric fills the remaining space outside the first gate dielectric in the stepped groove and protrudes from the stepped groove, and the both ends of the protruding part are overlapped with the first gate dielectric on both sides of the stepped groove.

[0012] Optionally, the protruding part partially covers the first gate dielectric directly above the uppermost layer of the current guide region.

[0013] Optionally, the remaining space outside the first gate dielectric in the stepped groove is filled with metal or polysilicon to form a ground electrode; and the second gate dielectric is stacked above the ground electrode and overlaps the first gate dielectric on both sides of the ground electrode.

[0014] The application further provides another downward arch bridge type VDMOSFET device, comprising:

[0015] An N-type substrate;

[0016] A semiconductor layer stacked on the upper surface of the N-type substrate;

[0017] An N-type drift region formed by element doping on the lower half of the semiconductor layer;

[0018] Symmetrical stepped recesses formed by etching the upper half of the semiconductor layer;

[0019] A current conducting region extending downward from the surface of the stepped recesses to the N-type drift region, wherein the bottom of the current conducting region is in contact with the N-type drift region;

[0020] Two-part P-wells, two-part N+ source regions and two-part P+ source regions formed by element doping on the semiconductor layer on both sides of the current conducting region, wherein the two-part P-wells are respectively located on both sides of the current conducting region; the upper ends of the two-part P-wells are inwardly recessed to form the two-part N+ source regions; the two-part P+ source regions are respectively located on both sides of the two-part P-wells;

[0021] A first gate dielectric layer superimposed on the inner wall and both sides of the stepped recesses;

[0022] A second gate dielectric layer located on the first gate dielectric layer in the stepped recesses, wherein the first gate dielectric layer and the second gate dielectric layer together form a thickened gate dielectric layer of the downward arch bridge type VDMOSFET device;

[0023] A gate electrode superimposed on the upper surface of the second gate dielectric layer and the upper surface of the first gate dielectric layer on both sides of the second gate dielectric layer;

[0024] An interlayer dielectric layer superimposed on the upper surface of the gate electrode and the upper surface of the first gate dielectric layer on both sides of the gate electrode;

[0025] A source electrode superimposed on the upper surface of the interlayer dielectric layer, the upper surface of the two-part N+ source regions and the upper surface of the two-part P+ source regions;

[0026] A drain electrode superimposed on the lower surface of the N-type substrate.

[0027] Optionally, the doping concentration of the current conducting region is 4E16cm -3 ~1E19cm -3 .

[0028] Optionally, the P-well is a multi-layer P-well formed by layered doping.

[0029] Optionally, the thickness of the thickened gate dielectric layer is greater than the thickness of the multi-layer P-well.

[0030] Optionally, in the multi-layer P-well, the doping concentration of the uppermost layer is 5E16cm -3 ~2E17cm -3 , and the doping concentration of the lowermost layer is 5E16cm -3 ~5E19cm-3 .

[0031] The downward-arched bridge type VDMOSFET device provided by the present application uses the stepped groove to lift the gate medium layer of the VDMOSFET, effectively increases the thickness of the gate oxide medium layer, so that the VDMOSFET has better reliability; at the same time, the semiconductor layer is provided with a current conducting area and a drift area, the current conducting area extends downward from the surface of the stepped groove to the drift area, is used for forming a current path in the semiconductor layer, and reduces the width of the gate electrode directly exposed to the drain end of the VDMOSFET, so that the width between the gate electrode directly exposed to the drain electrode is smaller, and therefore the VDMOSFET has better switching characteristics.

[0032] The present application will be further described in detail below with reference to the accompanying drawings and the present application. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a structural schematic diagram of a common VDMOSFET;

[0034] Figure 2 is a structural schematic diagram of an existing arch bridge type VDMOSFET;

[0035] Figure 3 is a partial structural schematic diagram of a first downward-arched bridge type VDMOSFET device provided by an embodiment of the present application;

[0036] Figure 4 is a partial structural schematic diagram of a second downward-arched bridge type VDMOSFET device provided by an embodiment of the present application;

[0037] Figure 5 is a partial structural schematic diagram of a third downward-arched bridge type VDMOSFET device provided by an embodiment of the present application;

[0038] Figure 6 is a partial structural schematic diagram of a fourth downward-arched bridge type VDMOSFET device provided by an embodiment of the present application;

[0039] Figure 7 is a partial structural schematic diagram of a first downward-arched bridge type VDMOSFET device provided by an embodiment of the present application;

[0040] Figure 8 is a partial structural schematic diagram of a second downward-arched bridge type VDMOSFET device provided by an embodiment of the present application;

[0041] Figure 9 is a partial structural schematic diagram of a third downward-arched bridge type VDMOSFET device provided by an embodiment of the present application;

[0042] Figure 10 is a schematic diagram of a fourth overall structure of a downward-arched bridge type VDMOSFET device provided by an embodiment of the present application;

[0043] Figure 11 The thickness of the thickened gate dielectric layer and the width of the gate electrode directly exposed between the drain electrodes are shown;

[0044] Figure 12 A schematic diagram of the embodiment of the present application in which the capacitance of the gate electrode and the drain electrode is shielded to the capacitance between the gate electrode and the P-well is shown;

[0045] Figure 13 is a schematic diagram in which the multi-layer P-well is thicker than the thickened gate dielectric layer;

[0046] Figure 14 A position of a channel of the downward-arched bridge type VDMOSFET device provided by an embodiment of the present application is shown;

[0047] Figure 15 A current path of the downward-arched bridge type VDMOSFET device provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0048] The present application will be further described in detail below with specific embodiments, but the embodiments of the present application are not limited thereto.

[0049] In order to make the VDMOSFET have better reliability and switching characteristics, an embodiment of the present application provides a downward-arched bridge type VDMOSFET device, which will be described below through specific embodiments.

[0050] Embodiment 1

[0051] The downward-arched bridge type VDMOSFET device provided in this embodiment 1 has a symmetric stepped groove formed by etching the semiconductor layer A; the inner wall and both sides of the stepped groove are covered with a layer of first gate dielectric 7; the first gate dielectric 7 in the stepped groove is further provided with a second gate dielectric 8; the first gate dielectric 7 and the second gate dielectric 8 together constitute the thickened gate dielectric layer of the downward-arched bridge type VDMOSFET device; and the semiconductor layer A is provided with a current conducting region 6 and a drift region, the current conducting region 6 extends downward from the surface of the stepped groove to the drift region, for forming a current path in the semiconductor layer A and reducing the width of the gate electrode 9 directly exposed to the drain end of the VDMOSFET.

[0052] For example, in one implementation, the current conducting region 6 can be formed by ion implantation from the surface of the stepped recess to the semiconductor layer A, so that the current conducting region 6 forms a current path along the stepped recess, and the width of the gate electrode 9 directly exposed between the drain electrodes 12 can be made smaller.

[0053] In this embodiment 1, there are various specific implementations of the combination of the first gate dielectric 7 and the second gate dielectric 8 to form the thickened gate dielectric layer, which are illustrated as follows:

[0054] In the first implementation, referring to Figure 3 , the second gate dielectric 8 fills the remaining space in the stepped recess other than the first gate dielectric 7, and the upper surface of the second gate dielectric 8 is flush with the upper surface of the first gate dielectric 7 on both sides of the stepped recess.

[0055] In the second implementation, referring to Figure 4 , the second gate dielectric 8 fills the remaining space in the stepped recess other than the first gate dielectric 7, and the second gate dielectric 8 is higher than the stepped recess, and the two ends of the overhanging part are connected to the first gate dielectric 7 on both sides of the stepped recess.

[0056] In the third implementation, based on Figure 4 , referring to Figure 5 , the second gate dielectric 8 fills the remaining space in the stepped recess other than the first gate dielectric 7, and the second gate dielectric 8 is higher than the stepped recess, and the two ends of the overhanging part are connected to the first gate dielectric 7 on both sides of the stepped recess; and the overhanging part partially covers the first gate dielectric 7 directly above the uppermost layer of the current conducting region 6.

[0057] In the fourth implementation, referring to Figure 6 , the remaining space in the stepped recess other than the first gate dielectric 7 is filled with metal or polysilicon to form a ground electrode 13; and the second gate dielectric 8 is stacked above the ground electrode 13 and connected to the first gate dielectric 7 on both sides of the ground electrode 13.

[0058] Thus, the stepped recess is used to raise the gate dielectric layer of the VDMOSFET, effectively increasing the thickness c of the gate oxide dielectric layer, so that the VDMOSFET has better reliability; at the same time, the existence of the current conducting region 6 can make the width of the gate electrode 9 directly exposed between the drain electrodes 12 smaller, so that the VDMOSFET also has better switching characteristics.

[0059] In this embodiment 1, other structures contained in the VDMOSFET device are not limited, and can be referred to existing VDMOSFET devices, or to the following embodiment 2.

[0060] Embodiment 2:

[0061] Based on the same inventive concept as example 1, a specific downward-arched bridge VDMOSFET device is provided in example 2, see Figures 7 to 10 , comprising: an N-type substrate 1, a semiconductor layer A, a first gate dielectric 7, a second gate dielectric 8, a gate electrode 9, an interlayer dielectric 10, a source electrode 11 and a drain electrode 12; wherein the semiconductor layer A is provided with an N-type drift region 2, a stepped groove, a current guide region 6, a P-well 3, an N+ source region 4 and a P+ source region 5. Figure 14 The location of the channel region b of the device is shown in Figure 15 The current path of the device is shown in

[0062] As to the N-type substrate 1, the doping element can be N (nitrogen), P (phosphorus) and the like impurity ions that can form N-type semiconductor, and the doping concentration can be 5E18cm -3 ~ 5E19cm -3 , and the thickness is preferably 200μm~400μm.

[0063] As to the semiconductor layer A, it is superimposed on the upper surface of the N-type substrate 1; preferably, the material of the semiconductor layer A can be SiC, so that the downward-arched bridge VDMOSFET device can be a silicon carbide device, which is more suitable for higher working frequency and has better stability at high temperature. Of course, the material of the semiconductor layer A is not limited to SiC, for example, the semiconductor layer A can also be a silicon-based semiconductor layer A.

[0064] As to the N-type drift region 2, it can be formed by doping the lower half of the semiconductor layer A with elements.

[0065] Preferably, the doping element of the N-type drift region 2 is N, P and the like impurity ions that can form N-type semiconductor, and the doping concentration is 5E14cm -3 ~ 2E16cm -3 , and the thickness of the N-type drift region 2 is determined by the required voltage level of the device. For example, for a general 1200V device, the doping concentration of the N-type drift region 2 is preferably 8E15cm -3 , and the thickness is preferably 9μm.

[0066] As to the stepped groove, it can be formed by etching the upper half of the semiconductor layer A; the stepped groove has groove widths increasing step by step from bottom to top.

[0067] It should be noted that the groove width, groove depth and step number in the stepped groove in the embodiments of the present application are not limited, and can be determined by simulation optimization in practice.

[0068] As to the current guide region 6, it extends downward from the surface of the stepped groove to the N-type drift region, and the bottom thereof is in contact with the N-type drift region.

[0069] In an alternative implementation, the upper half of the semiconductor layer A can be doped with N-type impurities from the surface of the stepped recess to form a current steering region 6.

[0070] The current steering region 6 is used to form a current path in the semiconductor layer A, as shown by the path formed by the arrows in Figure 15 , which extends from the upper surface of the semiconductor layer A through the P-well 3 and to the upper surface or inside of the N-type drift region 2; the current steering region 6 can reduce the width w of the gate electrode 9 directly exposed to the drain terminal of the VDMOSFET, as shown in Figure 11 .

[0071] Preferably, the doping element of the current steering region 6 is N, P or other impurity ions that can form N-type semiconductors, and the doping concentration is 4E16cm -3 ~ 1E19cm -3 .

[0072] As to the P-well 3, the N+ source region 4 and the P+ source region 5, they can be formed by doping the semiconductor layer A on both sides of the current steering region 6, which specifically forms two portions of the P-well 3, two portions of the N+ source region 4 and two portions of the P+ source region 5; the two portions of the P-well 3 are respectively located on both sides of the current steering region 6; the two portions of the P+ source region 5 are respectively located on both sides of the two portions of the P-well 3, and the upper ends of the two portions of the P-well 3 are inwardly spaced apart and provided with the two portions of the N+ source region 4; the two portions of the P+ source region 5 are respectively located on both sides of the two portions of the P-well 3 and the two portions of the N+ source region 4.

[0073] Preferably, the doping element of the P-well 3 can be B (boron), AL (aluminum) or other impurity ions that can form P-type semiconductors, and the doping concentration is preferably 5E16cm -3 ~ 5E19cm -3 , and the thickness is preferably 0.5μm ~ 1.5μm.

[0074] In a preferred implementation, the P-well 3 is a multi-layer P-well 3 formed by layered doping; the doping concentration of the uppermost layer determines the threshold voltage of the device, and the doping concentration is preferably 5E16cm -3 ~ 2E17cm -3 , and the doping concentration of the lowermost layer, i.e. the layer closest to the N-type drift region 2, is preferably 5E16cm -3 ~ 5E19cm -3 .

[0075] In a preferred implementation, the thickness c of the thickened gate dielectric layer is greater than the thickness k of the multi-layer P-well 3, as shown in Figure 13 . Thus, the multi-layer P-well 3 with a greater thickness can push the electric field into the corner portion of the body, as shown in Figure 13The two arcs in the middle represent the points where the electric field is concentrated. The P-wells 3 on the left and right sides push the electric field into the silicon carbide body away from the gate dielectric layer. Therefore, the combination of thickened gate dielectric layer and multi-layer P-well 3 can greatly improve the reliability of the gate dielectric layer.

[0076] Preferably, the doping elements of the N+ source region 4 are N, P and other impurity ions that can form an N-type semiconductor, and the doping concentration is 1E19cm -3 ~5E20cm -3 ; The thickness of the N+ source region 4 is preferably 0.1μm to 0.5μm.

[0077] Preferably, the doping elements of the P+ source region 5 are impurity ions such as B (boron) and Al (aluminum) that can form a P-type semiconductor, and the doping concentration is 1E19cm -3 ~5E20cm -3 , thickness is 0.5μm~1.5μm.

[0078] A first gate dielectric 7 is stacked on the bottom and both sides of the stepped groove. Exemplarily, the dielectric material of the first gate dielectric 7 can be silicon dioxide (SiO2), aluminum oxide (Al2O3), gallium oxide (Ga2O3), hafnium oxide (HfO2), hafnium silicon oxynitride (HfSiO N ), zirconium oxide (ZrO2) or zirconium oxynitride (ZrO N ) etc. The first gate dielectric 7 can be prepared by dry oxidation, wet oxidation, plasma oxidation, chemical vapor deposition (PECVD / LPCVD), atomic layer deposition and other methods.

[0079] The second gate dielectric 8 is located above the first gate dielectric 7 in the stepped groove. The first gate dielectric 7 and the second gate dielectric 8 together form a thickened gate dielectric layer of the downward arch bridge VDMOSFET device. The thickness of the thickened gate dielectric layer is represented by c. Figure 11 and 13 See also Figures 7 to 10 The specific implementation method of combining the first gate dielectric 7 and the second gate dielectric 8 to form a thickened gate dielectric layer is as follows: Figures 3 to 6 The same, no further description here.

[0080] Exemplarily, the dielectric material of the second gate dielectric 8 may be silicon dioxide (SiO2), aluminum oxide (Al2O3), gallium oxide (Ga2O3), hafnium oxide (HfO2), hafnium silicon oxynitride (HfSiON), zirconium oxide (ZrO2), zirconium oxynitride (ZrON), or spin-on glass. The second gate dielectric 8 may be prepared by chemical vapor deposition (PECVD / LPCVD), atomic layer deposition, or the like.

[0081] The gate electrode 9 is superimposed on the upper surface of the second gate dielectric 8 and the upper surface of the first gate dielectric 7 on both sides of the second gate dielectric 8. For specific superimposition manners, refer to Figures 7 to 10 .

[0082] Preferably, the gate electrode 9 can be doped polysilicon, but is not limited thereto.

[0083] The interlayer dielectric 10 is superimposed on the upper surface of the gate electrode 9 and the upper surface of the first gate dielectric 7 on both sides of the gate electrode 9. For specific superimposition manners, refer to Figures 7 to 10 .

[0084] Preferably, the interlayer dielectric 10 can be spin-on glass, but is not limited thereto.

[0085] The source electrode 11 is superimposed on the upper surface of the interlayer dielectric 10, the upper surface of the two-part N+ source region 4, and the upper surface of the two-part P+ source region 5. The N+ source region 4 and the P+ source region 5 form ohmic contacts with the source electrode 11.

[0086] Preferably, the source electrode 11 can be metal Al, but is not limited thereto.

[0087] The drain electrode 12 is superimposed on the lower surface of the N-type substrate 1.

[0088] Preferably, the drain electrode 12 can be metal Al, but is not limited thereto.

[0089] In this embodiment 2, the gate dielectric layer of the VDMOSFET is also lifted by the stepped groove, so that the VDMOSFET has better reliability. At the same time, the width w of the gate electrode 9 directly exposed between the drain electrodes 12 is small, and the P-well 3 below does not determine the threshold voltage of the device, so it can have a relatively high doping concentration, form a P-well 3 with good grounding quality, and shield most of the gate-drain capacitance (as shown in Figure 12 ), so that the VDMOSFET has better switching characteristics.

[0090] In this embodiment 2, the area of the gate electrode 9 directly exposed to the drain end can be made smaller, and the thicker dielectric layer below the gate electrode 9 also greatly reduces the gate-drain capacitance (as shown in Figure 12 ), further improving the switching characteristics of the device.

[0091] It should be noted that the terms "first", "second", and the like are used to distinguish similar objects, and are not necessarily used to describe a particular order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Rather, they are merely examples of devices and methods consistent with some aspects of the present disclosure.

[0092] In the description of the application, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" etc. means that the specific features or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the application. In the description of the application, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in the description.

[0093] Although the application is described herein in connection with various embodiments, those skilled in the art will understand and appreciate the disclosure of the disclosed embodiments upon reading the description of the application in conjunction with the accompanying drawings and the disclosure content. In the description of the application, the word "comprising" does not exclude other components or steps, "a" or "one" does not exclude a plurality, and "plurality" means two or more, unless otherwise explicitly specified. In addition, some measures are described in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0094] In the description of the application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the application.

[0095] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection", "fixing" and the like should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0096] In the present application, unless otherwise explicitly specified and limited, "on" or "under" of a first feature to a second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, "on", "above" and "over" of a first feature to a second feature includes that the first feature is directly above and obliquely above the second feature, or only means that the first feature is higher in horizontal height than the second feature. "Under", "below" and "underneath" of a first feature to a second feature includes that the first feature is directly below and obliquely below the second feature, or only means that the first feature is lower in horizontal height than the second feature.

[0097] The above description is further detailed in combination with specific preferred embodiments of the present application, and cannot be deemed to limit the specific implementation of the present application to these descriptions. For those of ordinary skill in the art to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, and all of them shall be deemed to fall within the protection scope of the present application.

Claims

1. A downwardly-arching bridge VDMOSFET device, characterized by, The downward-arched bridge VDMOSFET device has symmetrical stepped recesses formed by etching the semiconductor layer; the inner wall and both sides of the stepped recesses are covered with a first gate dielectric; the first gate dielectric in the stepped recesses is further provided with a second gate dielectric; the first gate dielectric and the second gate dielectric together form the thickened gate dielectric layer of the downward-arched bridge VDMOSFET device; The semiconductor layer is provided with a current guide region and a drift region, the current guide region extends downward from the surface of the stepped recesses to the drift region; the stepped recesses gradually increase in width from bottom to top; The gate electrode spans the stepped recesses and is located on the upper surface of the second gate dielectric and the upper surface of the first gate dielectric on both sides of the second gate dielectric; The current guide region is N-type and has a stepped edge formed along the surface of the stepped recesses; The P-well is located on both sides of the current guide region, the side surface of the P-well is adjacent to the stepped edge of the current guide region; The second gate dielectric fills the remaining space outside the first gate dielectric in the stepped recesses.

2. The downward arch bridge VDMOSFET device of claim 1, wherein, The upper surface of the second gate dielectric is flush with the upper surface of the first gate dielectric on both sides of the stepped recesses.

3. The downward arch bridge VDMOSFET device of claim 1, wherein, The second gate dielectric is higher than the stepped recesses, and the two ends of the overhanging part are overlapped with the first gate dielectric on both sides of the stepped recesses.

4. The downward arch bridge VDMOSFET device of claim 3, wherein, The overhanging part partially covers the first gate dielectric directly above the uppermost layer of the current guide region.

5. A downwardly-arching bridge VDMOSFET device characterized by, Comprise: An N-type substrate; A semiconductor layer superimposed on the upper surface of the N-type substrate; An N-type drift region formed by element doping the lower half of the semiconductor layer; Symmetrical stepped recesses formed by etching the upper half of the semiconductor layer; the stepped recesses gradually increase in width from bottom to top; A current guide region extending downward from the surface of the stepped recesses to the N-type drift region; wherein the bottom of the current guide region is in contact with the N-type drift region; the current guide region is N-type and has a stepped edge formed along the surface of the stepped recesses; Two-part P-wells, two-part N+ source regions and two-part P+ source regions formed by element doping the semiconductor layer on both sides of the current guide region; wherein the two-part P-wells are respectively located on both sides of the current guide region; the upper end of the two-part P-wells is inwardly recessed to provide the two-part N+ source regions; the two-part P+ source regions are respectively located on both sides of the two-part P-wells; the side surface of the P-well is adjacent to the stepped edge of the current guide region; A first gate dielectric superimposed on the inner wall and both sides of the stepped recesses; A second gate dielectric on the first gate dielectric in the stepped recesses; the second gate dielectric fills the remaining space outside the first gate dielectric in the stepped recesses; wherein the first gate dielectric and the second gate dielectric together form the thickened gate dielectric layer of the downward-arched bridge VDMOSFET device; A gate electrode spanning the stepped recesses and superimposed on the upper surface of the second gate dielectric and the upper surface of the first gate dielectric on both sides of the second gate dielectric; An interlayer dielectric superimposed on the upper surface of the gate electrode and the upper surface of the first gate dielectric on both sides of the gate electrode; a source electrode superposed on the upper surface of the interlayer dielectric, the upper surface of the portion of the two-part N+ source region, and the upper surface of the two-part P+ source region; a drain electrode superposed on the lower surface of the N-type substrate.

6. The downward arch bridge VDMOSFET device of claim 5, wherein, The doping concentration of the current steering region is 4E16 cm -3 1E19 cm -3 .

7. The downward arch bridge VDMOSFET device of claim 5, wherein, The P-well is a multi-layer P-well formed by layered doping.

8. The downward arch bridge VDMOSFET device of claim 7, wherein, The thickness of the thickened gate dielectric layer is greater than the thickness of the multi-layer P-well.

9. The downward arch bridge VDMOSFET device of claim 8, wherein, The doping concentration of the uppermost layer in the multi-layer P-well is 5E16 cm -3 ~2E17 cm -3 The doping concentration of the lowermost layer is 5E16 cm -3 ~5E19 cm -3 .

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