Semiconductor structure

Abstract

A semiconductor structure includes a middle-high voltage device region including a flat top surface, a low-voltage device region including a plurality of fin-shaped structures therein, and a protruding portion located at an interface between the middle-high voltage device region and the low-voltage device region, where a top surface of the protruding portion is in a flat shape and a bottom surface of the protruding portion is in a flat shape. And the top surface of the protruding part is flush with the flat top surface of the middle-high voltage element area.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a structure generated at the junction of a medium-high voltage component area and a low voltage component area in the semiconductor manufacturing technology. Background Art

[0002] In semiconductor manufacturing, nanometers are generally used to describe the precision of nano-manufacturing. For example, a 14-nanometer manufacturing process means that the minimum line width that can be formed in a component in this semiconductor manufacturing process is 14 nanometers. As the manufacturing process technology gradually improves, the line width of the nano-manufacturing process also gradually decreases.

[0003] However, even though nanofabrication technology is gradually improving, not all components are suitable for being formed using high-precision nanofabrication technology. For example, when the size of a component does not match the precision of the nanofabrication technology, not only will the yield of the component decrease, but it will also cost more. Therefore, in order to cope with components of different sizes or precision, different components are formed using nanofabrication processes of different precision.

[0004] On a chip, there may be components of different precision located in different areas, which may be formed by nano-manufacturing processes of different precisions. Therefore, various structural problems may be more likely to occur at the intersection of these areas. Summary of the invention

[0005] The present invention provides a semiconductor structure, comprising a medium-high voltage component area, comprising a flat top surface, a low voltage component area, comprising a plurality of fin-shaped structures therein, and a protruding portion, located at a junction of the medium-high voltage component area and the low voltage component area, wherein a top surface of the protruding portion is flat, and the top surface of the protruding portion is flush with the flat top surface of the medium-high voltage component area.

[0006] The present invention further provides a semiconductor structure, comprising a medium- and high-voltage component area, comprising a flat top surface, a low-voltage component area, comprising a plurality of fin-shaped structures therein, and a protruding sharp corner, located at a junction of the medium- and high-voltage component area and the low-voltage component area, wherein a top surface of the protruding sharp corner is in a pointed shape, and a top surface of the protruding sharp corner is lower than the flat top surface of the medium- and high-voltage component area.

[0007] The present invention is characterized in that a convex portion or a sharp corner portion is defined by deep grooves and shallow grooves at the boundary between a medium- and high-voltage component area (applicable voltage is above 5V, preferably above 10V) and a low-voltage component area (applicable voltage is below 5V, preferably below 1.5V) on the same chip. This convex portion or sharp corner portion can serve as a buffer between different areas to prevent the structures on both sides from affecting each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic top view of a junction between a medium- and high-voltage component area and a low-voltage component area of ​​the present invention;

[0009] Figures 2 to 3 This is the first embodiment of the present invention. Figure 1 A schematic diagram of a semiconductor cross-sectional structure obtained by a cross-sectional line AA';

[0010] Figure 4 This is the second embodiment of the present invention. Figure 1 A schematic diagram of a semiconductor cross-sectional structure obtained by a cross-sectional line AA';

[0011] Figure 5 This is the third embodiment of the present invention. Figure 1 Schematic diagram of the semiconductor cross-sectional structure obtained by the cross-sectional line AA'.

[0012] Explanation of symbols

[0013] 10: Medium and high voltage component area

[0014] 10A: Flat top surface

[0015] 11: Base

[0016] 12: Medium and high voltage components

[0017] 13: Mask layer

[0018] 14: Protection ring

[0019] 15: Mask layer

[0020] 16: Protection ring

[0021] 18: Deep groove

[0022] 20: Low voltage component area

[0023] 22: Virtual fin structure area

[0024] 24: Shallow groove

[0025] 26: Fin structure area

[0026] 30: Protruding part

[0027] 30A: Top surface

[0028] 32: Sharp corners

[0029] 34: Sharp corners

[0030] B: Junction

[0031] F: Fin structure

[0032] D1: Depth

[0033] D2: Depth

[0034] W1: Width

[0035] W2: Width DETAILED DESCRIPTION

[0036] In order to enable a person skilled in the art to further understand the present invention, the preferred embodiments of the present invention are listed below, and the components and intended effects of the present invention are described in detail with reference to the accompanying drawings.

[0037] For the convenience of explanation, the drawings of the present invention are only for illustration to make it easier to understand the present invention, and the detailed proportions can be adjusted according to the design requirements. The upper and lower relationships of the relative elements in the drawings described in the text should be understood by those skilled in the art to refer to the relative positions of the objects, so they can be flipped to present the same components, which should all fall within the scope of the disclosure of this specification, and will be explained here first.

[0038] Please refer to Figure 1 , Figure 1 A schematic top view of a junction between a high voltage component area and a low voltage component area of ​​the present invention is shown. Figure 1 As shown, the semiconductor structure 10 of the present invention includes a medium-high voltage component area 10 and a low-voltage component area 20, and there is a boundary B between the two. The difference between the medium-high voltage component area 10 and the low-voltage component area 20 is that the operating voltages of the components contained therein are different. Generally speaking, taking a display chip as an example, the low-voltage component area 20 includes, for example, a logic operation circuit, whose operating voltage is below 5 volts, and preferably within 1.5 volts. On the contrary, the operating voltage of the electronic components contained in the medium-high voltage component area 10 is greater than 5 volts, and is usually above 10 volts. For example, the driving components in the display chip require a higher voltage to drive the components therein, and these components belong to the medium-high voltage components of the present invention.

[0039] As described in the prior art, different components on the same chip may be formed separately by nano-fabrication processes of different precisions due to their different sizes or applications. In this embodiment, the medium-high voltage components or other related electronic components (such as wires or grooves, etc.) in the medium-high voltage component area 10 are formed, for example, by a 22-nanometer manufacturing process step, while the various low-voltage components (such as logic operation circuits) in the low-voltage component area 20 require a higher nano-precision, for example, formed by a 14-nanometer manufacturing process. However, it is worth noting that the above-mentioned 22-nanometer manufacturing process or 14-nanometer manufacturing process is only one example of the present invention, and the present invention is not limited thereto.

[0040] When the nanometer precision of semiconductor manufacturing technology is improved, it means that the size of the device is getting smaller and smaller, and the device can also develop towards a three-dimensional structure to increase the density per unit area. In this embodiment, the low-voltage device area 20 includes a plurality of fin structures ( Figure 1 (not shown), while the medium and high voltage component area 10 is mainly a planar structure. In other words, Figure 1 The top view of the semiconductor structure shown can be regarded as the boundary between two regions including two-dimensional electronic components and two-dimensional electronic components, wherein the two regions are formed by different nanometer precision manufacturing processes.

[0041] Please continue to refer to Figure 1 The medium and high voltage component area 10 includes medium and high voltage components 12 (such as the above-mentioned drive circuit), and a guard ring 14 may be included around the medium and high voltage components 12 to prevent noise or stabilize voltage. The guard ring 14 includes a dummy area 16 around it, wherein the components included in the dummy area 16 are also formed by a 22-nanometer manufacturing process, but the components in the dummy area 16 will not be connected to other electronic components. The dummy area 16 can be used as a buffer zone, located in the medium and high voltage components 12 to protect the medium and high voltage components from being affected by the manufacturing process of other areas. In addition, a deep trench 18 is included in the medium and high voltage component area 10.

[0042] The low-voltage component area 20 includes a dummy fin structure area 22, a shallow groove 24, and a fin structure area 26, wherein the function of the dummy fin structure area 22 is similar to the dummy area 16 in the above-mentioned medium and high voltage component area 10, and can be used to protect the electronic components in the fin structure area 26. Both the dummy fin structure area 22 and the fin structure area 26 contain multiple fin structures therein. However, in subsequent steps, only the fin structure in the fin structure area 26 will be made into an electronic component (such as a transistor, etc.) and electrically connected to other components. These features belong to the prior art in this field and will not be elaborated here.

[0043] Figure 2-Figure 3 According to the first embodiment of the present invention, Figure 1 The semiconductor cross-sectional structure obtained by the cross-sectional line A-A'. Figure 2As shown, the substrate 11 includes a mask layer 13 and a mask layer 15, wherein the material of the substrate 11 is, for example, silicon, and the material of the mask layer 13 and the mask layer 15 is, for example, silicon oxide, silicon nitride or silicon oxynitride, etc., but the present invention is not limited thereto. The mask layer 13 and the mask layer 15 can be used to define the position of the groove and the fin-shaped structure, as a mask for the etching step, or as an etching stop layer for the subsequent manufacturing process. Since the medium and high voltage component area 10 and the low voltage component area 20 are formed respectively by semiconductor manufacturing processes with different nanometer precision, the depths of the deep trench 18 and the shallow trench 24 therein are also different. The deep trench 18 is used to define the formation range of the medium and high voltage components, and because the operating voltage of the medium and high voltage components is higher, a deeper trench (i.e., the deep trench 18) is required to be surrounded to achieve a better isolation effect. On the contrary, because the shallow trench 24 may be made simultaneously with the fin-shaped structure F, the depth of the shallow trench 24 may be the same as the bottom depth of the fin-shaped structure F. In this embodiment, the depth D1 of the deep trench 18 is about 2500 angstroms, and the depth D2 of the shallow trench 24 is about 1300 angstroms, but the present invention is not limited thereto.

[0044] It is worth noting that the junction of the medium-high voltage component area 10 and the low voltage component area 20 of the semiconductor structure of the present invention also includes a protruding portion 30. In the present embodiment, the protruding portion 30 may have a flat top surface 30A, and the flat top surface 30A of the protruding portion 30 is aligned in the horizontal direction with the flat top surface 10A of the surrounding medium-high voltage component area 10. This protruding portion 30 is located between the deep groove 18 and the shallow groove 24, that is, the position is jointly defined by the deep groove 18 and the shallow groove 24. The protruding portion 30 is also located on the junction B between the medium-high voltage component area 10 and the low voltage component area 20, and can serve as a buffer structure between the two areas to avoid mutual influence between the deep grooves 18 and the shallow grooves 24 in different areas. In the present embodiment, the width W1 of the protruding portion 30 is preferably greater than the width W2 of each fin structure F, but the present invention is not limited to this.

[0045] Next, an insulating layer 40 may be filled into the deep trench 18 and the shallow trench 24, wherein the insulating layer 40 preferably fills the deep trench 18 and the shallow trench 24 first, and then a planarization step (such as chemical mechanical polishing) and a back-etching step are used to remove a portion of the insulating layer 40, and the fin structure F of the low-voltage device area 20 is exposed. Therefore, in the present invention, the height of the insulating layer 40 in the medium-high voltage device area 10 and the low-voltage device area 20 is different, for example, the top surface of the insulating layer 40 in the medium-high voltage device area 10 is higher than the top surface of the insulating layer 40 in the low-voltage device area 20. In addition, in the present embodiment, the mask layer 13 and the mask layer 15 are removed at the same time after the above-mentioned planarization step and back-etching step.

[0046] Figure 4 According to the second embodiment of the present invention, Figure 1The semiconductor cross-sectional structure obtained by the cross-sectional line AA'. Figure 5 According to the third embodiment of the present invention, Figure 1 The semiconductor cross-sectional structure obtained by the cross-sectional line AA'. In different embodiments of the present invention, the shape of the protruding portion may be affected by the change of etching parameters during the process of making the deep trench 18 and the shallow trench 24. In some embodiments, as Figure 4 As shown in FIG. 1 , the original protruding portion is etched to form a sharp corner portion 32. Here, the sharp corner portion 32 does not include a flat top surface, but includes a sharp top surface. However, in this embodiment, the top surface of the sharp corner portion 32 is substantially aligned with the flat top surface 10A of the medium and high voltage component area 10 in the horizontal direction. Or in another embodiment of the present invention, as Figure 5 As shown, the protruding portion may form a sharp corner portion 34 due to being etched more, wherein the height of the sharp corner portion 34 is also lower than the flat top surface 10A of the surrounding medium and high voltage component area 10, or lower than the top surface of the fin structure F. Such a variation structure also falls within the scope of the present invention. In addition, in these embodiments, an insulating layer will also be formed to fill the deep trench 18 and the shallow trench 24, which will not be repeated here.

[0047] In summary, the present invention provides a semiconductor structure, comprising a medium-high voltage component region 10, comprising a flat top surface 10A, a low voltage component region 20, comprising a plurality of fin-shaped structures F therein, and a protruding portion 30, located at a junction B between the medium-high voltage component region 10 and the low voltage component region 20, wherein a top surface 30A of the protruding portion 30 is flat, and the top surface 30A of the protruding portion 30 is flush with the flat top surface 10A of the medium-high voltage component region 10.

[0048] In some embodiments of the present invention, a deep trench 18 is further included, which is located in the medium and high voltage component area 10 , and the deep trench 18 is adjacent to the protruding portion 30 .

[0049] In some embodiments of the present invention, a shallow trench 24 is further included, which is located in the low-voltage component area 20 , and the shallow trench 24 is adjacent to the protruding portion 30 .

[0050] In some embodiments of the present invention, a depth D1 of the deep trench 24 is greater than a depth D2 of the shallow trench 24 .

[0051] In some embodiments of the present invention, a bottom surface of each fin structure F is aligned with a bottom surface of the shallow trench 24 (eg, Figure 2 shown).

[0052] In some embodiments of the present invention, from a cross-sectional view, a width W1 of the protruding portion 30 is greater than a width W2 of each fin-shaped structure F.

[0053] In some embodiments of the present invention, the medium-high voltage component area 10 includes multiple first components (i.e., medium-high voltage components 12), and a driving voltage of each first component 12 is greater than 10 volts. The low voltage component area 20 includes multiple second components (i.e., electronic components formed in the subsequent fin structure area 26), and a driving voltage of each second component is less than 1.5 volts.

[0054] In some embodiments of the present invention, each first component 12 includes a display driver chip.

[0055] In some embodiments of the present invention, each second element (an electronic element subsequently formed in the fin structure region 26 ) includes a transistor element for logic operation.

[0056] In some embodiments of the present invention, each first element and each second element are manufactured by nano-fabrication processes of different fineness (for example, in one embodiment, the first element is formed by a 22 nanometer manufacturing process, and the second element is formed by a 14 nanometer manufacturing process).

[0057] The present invention further provides a semiconductor structure, comprising a medium-high voltage device region 10, comprising a flat top surface 10A, a low voltage device region 20, comprising a plurality of fin-shaped structures F therein, and a protruding corner 34, located at a junction B between the medium-high voltage device region 10 and the low voltage device region 20, wherein a top surface of the protruding corner 34 is a pointed shape, and a top surface of the protruding corner 32 is lower than the flat top surface 10A of the medium-high voltage device region 10 (e.g., Figure 4 shown).

[0058] In some embodiments of the present invention, since the medium and high voltage component area 10 mainly includes planar electronic components, it can also be regarded as a planar component area. Conversely, since the low voltage component area 20 mainly includes fin structures, it can be regarded as a fin structure component area.

[0059] Therefore, in some embodiments of the present invention, a semiconductor structure is provided, comprising a planar component region (i.e., a medium- and high-voltage component region 10) comprising a flat top surface 10A, a fin-shaped component region (i.e., a low-voltage component region 20) comprising a plurality of fin-shaped structures F therein, and a protrusion 30 located at a boundary B between the planar component region 10 and the fin-shaped component region 20, wherein a top surface 30A of the protrusion 30 is flat, and the top surface 30A of the protrusion 30 is flush with the flat top surface 10A of the planar component region 10.

[0060] In some embodiments of the present invention, a semiconductor structure is provided, comprising a planar device region 10 including a flat top surface 10A, a fin structure device region 20 including a plurality of fin structures F therein, and a protruding corner 34 located at a boundary B between the planar device region 10 and the fin structure device region 20, wherein a top surface of the protruding corner 34 is in a pointed shape, and a top surface of the protruding corner 34 is lower than the flat top surface 10A of the planar device region 10.

[0061] The present invention is characterized in that a convex portion or a sharp corner portion is defined by deep grooves and shallow grooves at the boundary between a medium- and high-voltage component area (applicable voltage is above 5V, preferably above 10V) and a low-voltage component area (applicable voltage is below 5V, preferably below 1.5V) on the same chip. This convex portion or sharp corner portion can serve as a buffer between different areas to prevent the structures on both sides from affecting each other.

[0062] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor structure comprising: The medium and high voltage component area includes a flat top surface; a low voltage component area including a plurality of fin-shaped structures therein; and The protruding portion is located at the junction of the medium and high voltage component area and the low voltage component area, wherein the top surface of the protruding portion is flat and is flush with the flat top surface of the medium and high voltage component area. 2 . The semiconductor structure as claimed in claim 1 , further comprising a deep trench located in the medium and high voltage device region, and the deep trench is adjacent to the protruding portion. 3 . The semiconductor structure as claimed in claim 2 , further comprising a shallow trench located in the low voltage device region, and the shallow trench is adjacent to the protruding portion. The semiconductor structure as claimed in claim 3 , wherein a depth of the deep trench is greater than a depth of the shallow trench. 5 . The semiconductor structure as claimed in claim 3 , wherein a bottom surface of each of the fin structures is flush with a bottom surface of the shallow trench. 6 . The semiconductor structure as claimed in claim 1 , wherein from a cross-sectional view, a width of the protruding portion is greater than a width of each of the fin structures.

7. The semiconductor structure as described in claim 1, wherein the medium-high voltage component area includes a plurality of first components, each of which has a driving voltage greater than 10 volts, and the low voltage component area includes a plurality of second components, each of which has a driving voltage less than 1.5 volts. 8 . The semiconductor structure as claimed in claim 7 , wherein each of the first components comprises a display driver chip.

9. The semiconductor structure as claimed in claim 7, wherein each of the second elements comprises a transistor element used for logic operation. 10 . The semiconductor structure as claimed in claim 7 , wherein each of the first elements and each of the second elements are manufactured by nano-fabrication processes of different fineness.

11. A semiconductor structure comprising: The medium and high voltage component area includes a flat top surface; a low voltage component area including a plurality of fin-shaped structures therein; and The protruding corner is located at the junction of the medium and high voltage component area and the low voltage component area, wherein the top surface of the protruding corner is a pointed shape and the top surface of the protruding corner is lower than the flat top surface of the medium and high voltage component area. 12 . The semiconductor structure as claimed in claim 11 , further comprising a deep trench located in the medium and high voltage device region, and the deep trench is adjacent to the protruding corner. 13 . The semiconductor structure as claimed in claim 12 , further comprising a shallow trench located in the low voltage device region, and the shallow trench is adjacent to the protruding corner. The semiconductor structure as claimed in claim 13 , wherein a depth of the deep trench is greater than a depth of the shallow trench. 15 . The semiconductor structure as claimed in claim 13 , wherein a bottom surface of each of the fin structures is flush with a bottom surface of the shallow trench. 16 . The semiconductor structure of claim 11 , wherein from a cross-sectional view, a width of the protruding corner is greater than a width of each of the fin structures.

17. The semiconductor structure as described in claim 11, wherein the medium-high voltage device area includes a plurality of first devices, each of which has a driving voltage greater than 10 volts, and the low voltage device area includes a plurality of second devices, each of which has a driving voltage less than 1.5 volts. 18 . The semiconductor structure as claimed in claim 17 , wherein each of the first elements and each of the second elements are manufactured by nano-fabrication processes of different fineness.

19. A semiconductor structure comprising: A planar component region including a flat top surface; A fin-shaped structure component area includes a plurality of fin-shaped structures therein; as well as The protruding portion is located at the junction of the planar device region and the fin-shaped structure device region, wherein the top surface of the protruding portion is flat and the top surface of the protruding portion is aligned with the flat top surface of the planar device region.

20. A semiconductor structure comprising: A planar component region including a flat top surface; A fin-shaped structure component area includes a plurality of fin-shaped structures therein; as well as The protruding corner is located at the junction of the planar device area and the fin-shaped structure device area, wherein the top surface of the protruding corner is in a pointed shape and the top surface of the protruding corner is lower than the flat top surface of the planar device area.

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