A sensing, storage and computing integrated double-sided gate transistor single tube and its use method

Abstract

The present invention belongs to the field of integrated circuits and microelectronic devices, and specifically is a double-sided gate transistor single tube with integrated sensing, storage and computing, and a method of using the same. The present invention proposes to use a back-illuminated structure, combine SOI and floating gate transistor technology, and utilize the unique properties of the top single crystal silicon layer in SOI to effectively realize direct sensing and conversion of optical signals, thereby integrating multiple functions while maintaining electrical isolation to achieve the integration of sensing, storage and computing of a single transistor. The optical signal is directly incident on the channel region from the substrate on the back of the device, avoiding circuit obstruction in the optical path, and has high optical signal utilization efficiency; by adjusting the parameters of the back-illuminated structure, such as light intensity and silicon layer thickness, the carrier concentration and conductivity of the channel region are precisely controlled to achieve a high sensitivity response to the optical signal. The integration of sensing, storage and computing of a single transistor achieved by the present invention provides a basis for its further use in various scenarios, such as being embedded as a unit in an artificial neural network, and being applied to audio signal processing, etc.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits and microelectronic devices, and specifically relates to a sensing, storage and computing integrated double-sided gate transistor and a use method thereof. Background Art

[0002] In the field of modern microelectronics and integrated circuits, although the integrated sensing, storage and computing technology has made significant progress, the existing implementation schemes usually face multiple challenges. At present, most sensing, storage and computing systems rely on at least two transistors to handle the sensing and storage functions respectively. This separation method introduces the following problems: 1. High complexity and cost: The integration of multiple devices increases the complexity and manufacturing cost of the circuit; 2. Low response speed and efficiency: The signal is transmitted between different devices, resulting in increased delay and affecting system performance; 3. Occupy more chip area: The multi-device design occupies more chip space, which is not conducive to the miniaturization of the device.

[0003] Traditional CMOS image sensors use a front-illuminated structure, and light signals need to penetrate the circuit layer to reach the photosensitive element; the circuit layer blocks and absorbs light, which limits the efficiency of light reception and the quality of the image. In addition, in the prior art, photodiodes are used to sense light signals and convert them into electrical signals, but they cannot directly affect the conductance of the channel region of the transistor, which limits the flexibility and response speed of the device.

[0004] Because different functions in semiconductor devices need to be electrically isolated, sensing, storage and computing often involve different voltage and current characteristics. If they are in the same transistor, it is difficult to avoid mutual interference.

[0005] The above problems have resulted in the existing sensing, storage and computing systems being able to only adopt methods that process sensing and storage functions separately, which is contrary to the current requirements for miniaturization, high sensitivity and high precision of scientific and technological equipment. Summary of the invention

[0006] In view of the above problems, in order to solve the problem that existing sensing, storage and computing cannot be integrated into a single device, the present invention provides a double-sided gate transistor with sensing, storage and computing integrated into one and a method of using the same, which combines SOI (Silicon-On-Insulator) technology with a floating-gate transistor to integrate sensing, storage and computing functions into a single transistor, thereby improving response speed, reducing costs and reducing device size.

[0007] A double-sided gate transistor with integrated sensing, storage and computing functions, such as Figure 1 As shown, it includes: a substrate, a buried oxide layer, a top single crystal silicon layer, a floating gate, a gate dielectric layer and a top control gate.

[0008] The substrate is a basis for providing physical and electrical support, and a high-purity silicon substrate is generally used.

[0009] The buried oxide layer (BOX) is located above the substrate and is an insulating layer used as electrical isolation, effectively isolating the top single crystal silicon layer (active layer) above and the silicon substrate below, reducing bottom interference and enhancing device performance.

[0010] The top single crystal silicon layer is located above the buried oxide layer, in which the channel region of the transistor is formed, and source / drain electrodes connected to the channel region are constructed on both sides of the channel region to form the in and out paths of the current. The channel region absorbs photons to generate photogenerated electron-hole pairs; the conductivity of the channel region is controlled by the charge state of the floating gate and control gate located above it.

[0011] The floating gate is located on the channel region and is isolated from the channel region by a gate dielectric layer; the floating gate is used to capture and hold charges for a long time, and these charges directly affect the conductivity of the channel region to achieve a storage function.

[0012] The top control gate is located above the floating gate and is isolated from the floating gate by another dielectric material control gate dielectric layer; the top control gate is used to adjust the charge state in the floating gate, thereby regulating the switching state of the transistor.

[0013] The specific method of realizing the sensing, storage and computing of the above-mentioned double-sided gate transistor is as follows:

[0014] 1). Floating gate charge modulation:

[0015] Programming (writing) stage: By applying a high voltage between the top control gate and the source / drain, electrons are allowed to enter the floating gate through the tunneling effect or hot electron injection mechanism, increasing the negative charge in the floating gate and thus increasing the threshold voltage of the transistor.

[0016] Erase phase: A reverse high voltage is applied between the top control gate and the source / drain to return the electrons in the floating gate to the channel region or the source / drain, reducing the negative charge in the floating gate.

[0017] Fine control of charge state: The amount of charge in the floating gate can be precisely controlled by adjusting the amplitude and duration of the applied voltage, thereby achieving fine tuning of the threshold voltage.

[0018] 2). Adjustment of threshold voltage:

[0019] Charge in floating gate The threshold voltage of the transistor is changed, and the relationship is as follows:

[0020]

[0021] in is the threshold voltage, is the initial threshold voltage, is the capacitance between the floating gate and the channel region. , to dynamically adjust the threshold voltage so that the transistor exhibits different switching characteristics under different input signals.

[0022] 3). Control of conductivity in the channel region:

[0023] Input signal application: The signal to be processed is applied to the top control gate to control the conductance of the channel region.

[0024] Influence of floating gate charge: The charge state in the floating gate determines the threshold voltage of the transistor, thereby affecting the input signal's ability to control the channel region.

[0025] Conductivity modulation: Based on the combined effect of the floating gate charge and the input signal, the conductivity of the channel region changes, thereby amplifying or suppressing the input signal.

[0026] 4). Implementation of calculation function:

[0027] Analog calculation: Using the IV characteristics of the transistor, in the subthreshold range, Ids and Vgs are exponentially related. By modulating the top control gate voltage and floating gate charge, analog calculations such as multiplication and / or exponential are performed; where Vgs is the gate-source voltage and Ids is the drain current.

[0028] Digital logic operation: By setting the floating gate charge state, the transistor is turned on or off under a specific input voltage to realize the logic gate function.

[0029] Furthermore, if applied in a neural network, the floating gate charge can represent the weight value, the top control gate input signal represents the neuron input, and the output current is the result of weighted summation. After being processed by the activation function, the output of the neuron is obtained to realize neural network calculation.

[0030] 5). Data processing and signal output:

[0031] Source / drain current detection: Get the calculated result by measuring the current between source / drain.

[0032] Signal reading: The output current signal is directly used for the next step of processing, or converted to obtain the required output form.

[0033] Furthermore, a bottom control gate is provided between the substrate and the buried oxide layer. The bottom control gate provides an additional control dimension. By applying a control voltage from the back side of the double-sided gate transistor, the potential distribution in the channel region is independently adjusted to adjust the conductivity of the channel region, thereby performing complex data processing and calculations, thereby enhancing the functional diversity of the device and the adjustability of the electrical characteristics; the back side of the double-sided gate transistor refers to the substrate side thereof.

[0034] Furthermore, the bottom control gate can also work in conjunction with the top control gate to achieve complex electrical operations, such as adjusting the threshold voltage of the device, improving sensitivity and signal processing capabilities. The top control gate and the bottom control gate jointly adjust the electric field in the channel region, and the two control gates affect the electron distribution and potential in the channel region from both sides of the transistor.

[0035] Among them, the top control gate is responsible for quickly responding and directly controlling the upper electric field of the channel region, thereby affecting the basic switching operation of the transistor; while the bottom control gate fine-tunes the electric field at the bottom of the channel region, which helps to supplement the effect of top control, especially in the fine adjustment of the threshold voltage and the control of the short channel effect.

[0036] The present invention proposes to use a back-illuminated structure, in which the optical signal is directly incident on the channel region from the back side of the device (substrate side). This design avoids circuit shielding in the optical path and enhances the direct utilization efficiency of the optical signal. Photons are absorbed in the back channel region of the top single-crystalline silicon layer of the device, generating a large number of photogenerated electron-hole pairs. Due to the high absorption coefficient of the top single-crystalline silicon layer, especially in the short wavelength range, these photogenerated carriers are efficiently generated in the channel region and quickly distributed. By adjusting the parameters of the back-illuminated structure, such as light intensity and the thickness of the silicon layer, the carrier concentration and conductivity of the channel region can be precisely controlled to achieve a highly sensitive response to the optical signal. This response is not only suitable for image capture, but also provides new possibilities for complex data processing based on optical signals.

[0037] The innovation of the present invention lies in combining SOI and floating gate transistor technology and applying them to the integrated sensing, storage and computing technology, especially applying them to the sensing field; by utilizing the unique properties of the top single crystal silicon layer in the SOI structure, the present invention can effectively realize the direct sensing and conversion of optical signals, and then integrate storage and computing functions.

[0038] Due to the characteristics of the SOI structure, the top single-crystal silicon layer can directly receive and sense optical signals without being electrically interfered by the underlying silicon substrate. When the optical signal is irradiated to the top single-crystal silicon layer, the layer absorbs light energy and generates photogenerated electron-hole pairs. These photogenerated carriers can then be directly captured by the floating gate structure, thereby realizing the storage of electrical signals and further signal processing.

[0039] Therefore, the present invention integrates multiple functions while maintaining electrical isolation, realizing the integration of sensing, storage and computing in a single transistor, thereby providing a basis for its further use in various scenarios, such as being embedded as a unit in an artificial neural network and applied to audio signal processing, etc.

[0040] In summary, the present invention combines a floating-gate transistor with SOI technology to achieve the integrated sensing, storage and computing of a single transistor; and further provides a transistor with a double-sided gate structure, which can perform different functions on different control gates, and achieve more precise and complementary independent electric field control through the double-sided gate, especially in the fine adjustment of the threshold voltage and the control of the short channel effect, thereby improving the sensitivity and signal processing capability of the transistor, providing support for the current technological development demand for highly integrated devices, and thus providing a basis for its further use in various scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a structural cross-sectional view of an embodiment of the present invention;

[0042] Figure 2 is a Vgs-Vgate relationship curve diagram of an embodiment;

[0043] Figure 3 Graph showing the relationship between log(Ids) and Vgs of the embodiment. DETAILED DESCRIPTION

[0044] The present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0045] A double-sided gate transistor with integrated sensing, storage and computing functions. The specific structure of this embodiment is as follows: Figure 1 As shown, it includes: a substrate (silicon substrate), a bottom control gate, a buried oxide layer, a top single crystal silicon layer (silicon channel region, source and drain), a gate dielectric layer (silicon oxide layer), a floating gate, a control gate dielectric layer and a top control gate.

[0046] The silicon substrate is the foundation that provides physical and electrical support.

[0047] The bottom control gate is located above the silicon substrate and below the buried oxide layer; the bottom control gate is used to adjust the conductivity of the channel region from the back of the device according to the charge state stored in the floating gate, so as to perform complex data processing and calculations, realize computing functions, and enhance the functional diversity of the device and the adjustability of electrical characteristics. It can work independently or in conjunction with the top control gate to achieve complex electrical operations, such as adjusting the threshold voltage of the device and improving sensitivity and signal processing capabilities.

[0048] The bottom control gate may not exist, and its addition is mainly to enhance the performance and functionality of the overall device, providing additional electrical control, such as more fine-tuning the threshold voltage of the channel region and improving the short channel effect. This is particularly useful for devices that require high-precision control or operate under extreme conditions. In addition, in advanced applications such as neuromorphic computing, high-frequency signal processing, or low-power devices, the bottom control gate can help achieve more complex electrical operations and optimize overall device performance.

[0049] The buried oxide layer is located above the bottom control gate and is used as an insulating layer for electrical isolation. It effectively isolates the top single crystal silicon layer above and the silicon substrate below, reduces bottom interference, and enhances device performance.

[0050] The top single-crystal silicon layer is located above the buried oxide layer, in which the channel region of the transistor is formed, and source / drain electrodes connected to the channel region are constructed on both sides of the channel region to form the in and out paths of the current. The channel region absorbs photons and generates photogenerated electron-hole pairs; the conductivity of the channel region is controlled by the charge state of the floating gate and control gate located above it.

[0051] The floating gate is located on the channel region and is isolated from the channel region by a silicon oxide gate dielectric layer to capture and retain charges for a long time to achieve a storage function. These charges directly affect the conductivity of the channel region.

[0052] The top control gate is located above the floating gate and is isolated from the floating gate by another layer of dielectric material to adjust the charge state in the floating gate, thereby regulating the switching state of the transistor.

[0053] 1. Reception of optical signals: In the back-illuminated structure of the present invention, the optical signal is designed to be incident directly from the back of the transistor into the channel region, and the optical signal does not need to pass through a complex circuit layer and can directly reach the photosensitive area.

[0054] 2. Generation of photogenerated carriers: After photons are absorbed by the single crystal silicon layer at the top of the channel region, photogenerated electrons and holes are generated according to the formula G=α.Φ, where G is the photogenerated carrier generation rate, α is the absorption coefficient of silicon, and Φ is the photon flux density of the incident light; this process occurs inside the channel region, generating a large number of electron-hole pairs.

[0055] 3. Carrier distribution: The carrier distribution in the channel region is according to the formula Follow the exponential decay law. In this process, x represents the depth from the light incident surface, G x It is the photogenerated carrier generation rate at a depth x from the incident surface inside the material, G0 is the photogenerated carrier generation rate at the incident surface (x=0), and e is the base of the natural logarithm. Such a distribution ensures the effective distribution of carriers inside the channel region.

[0056] 4. Effect of carrier concentration on conductivity: The increase of photogenerated carriers leads to an increase in the free carrier concentration in the channel region, which is expressed as ,in and represent the changes in the free electron and hole concentrations caused by light,

[0057] is the effective lifetime of the carriers. The increase in carrier concentration increases the conductivity of the channel region. , whose expression is

[0058]

[0059] where q is the elementary charge, n and p are the concentrations of electrons and holes, are the mobility of electrons and holes.

[0060] 5. The impact of conductivity changes on transistor characteristics: The increase in channel region conductivity leads to a higher threshold voltage of the transistor. reduce;

[0061]

[0062] is the initial threshold voltage, Indicates the change of carrier concentration in the channel region; It represents the gate oxide capacitance (the capacitance between the floating gate and the channel region). The reduction of the threshold voltage enables the transistor to be turned on at a lower gate voltage, achieving efficient response to light signals.

[0063] 6. Charge storage (storage): The amount of charge stored in the floating gate affects the threshold voltage of the transistor, thereby changing the conductivity of the channel region. This storage mechanism allows the device to maintain the charge state for a long time without losing data even when the power is disconnected.

[0064] Specifically, the light signal is converted into an electrical signal, and these charges are attracted to the floating gate through the internal electric field, where the accumulation of positive or negative charges changes the total charge state of the floating gate. The charges stored in the floating gate directly affect the electric field in the channel region below, thereby changing the threshold voltage Vth of the transistor. The change in threshold voltage ΔVth is the change in the charge amount of the floating gate due to the change in the intensity of the light signal. The greater the light intensity, the more significant the charge change caused, and the correspondingly larger ΔVth. Therefore, ΔVth can be regarded as storing light intensity information.

[0065] 7. Signal processing and computing operations (calculation): The top control gate plays a major role in the computing process. By applying a specific voltage, the top control gate can accurately adjust the charge state in the floating gate, thereby changing the threshold voltage of the transistor. and the conductivity of the channel region to achieve signal processing and computing operations.

[0066] Furthermore, a bottom control gate can be added to adjust the conductivity of the channel region according to the charge state stored in the floating gate. The charge stored in the floating gate has a direct impact on the electric field in the channel region. These charges change the potential of the channel region through the electric field effect, thereby affecting the threshold voltage of the transistor. By applying a voltage to the bottom control gate, the potential at the bottom of the channel region can be independently adjusted; this potential adjustment can interact with the electric field generated by the floating gate to jointly determine the concentration and distribution of carriers (electrons or holes) in the channel region. By adjusting the bottom control gate voltage, the conductivity of the channel region can be fine-tuned to adapt to the impact of the floating gate charge change and perform complex computing tasks. By adjusting the voltage of the bottom control gate, logical operations and data processing based on stored information can be achieved.

[0067] 8. Comprehensive calculation result output: The current change between the source / drain of the transistor is used as output to reflect the calculation result. This output can be used for further signal analysis or directly drive peripheral devices to achieve advanced data processing functions.

[0068] 9. Working steps and operations:

[0069] Step 1: Optical information conversion: The incident light signal directly enters the channel region from the back of the transistor to generate electron-hole pairs, and some photogenerated electrons are injected into the floating gate to change Vth. This process is carried out under different lighting conditions to adjust the response characteristics of the device.

[0070] Step 2, information storage: The change in Vth ΔVth reflects the stored light intensity information. ΔVth changes the position of the Vgs-Vgate relationship curve (e.g. Figure 2 As shown), it reserves data for subsequent calculation operations, where Vgs is the gate-source voltage and Vgate is the gate voltage, showing the impact of threshold voltage changes on transistor characteristics.

[0071] Step 3, calculation preparation: convert the first half of the Vgs-Vgate curve (Vgs<Vth) into logarithmic coordinates. In this area, log(Ids)-Vgate presents a linear relationship (such as Figure 3 ), which is convenient for mathematical processing and illustrates the computing power of transistors in the subthreshold range.

[0072] Step 4: Simulate multiplication: Use the mathematical property of log(AB)=log(A)+log(B) for calculation.

[0073] For example, two input signals Vgate1 = 0.3V and Vgate2 = 0.5V are converted into corresponding voltage values ​​and applied to the two transistors respectively.

[0074] Step 5, result reading: measure the drain currents Ids1 and Ids2 of the two transistors respectively.

[0075] The results show that log(Ids1*Ids2)=log(Ids1)+log(Ids2) is equivalent to combining the mathematical products of the two input signals, demonstrating the effectiveness of the calculation.

[0076] For this embodiment:

[0077] Assume the initial threshold voltage Vth0 = 0.7V, ΔVth = 0.1V (caused by the stored light information);

[0078] When Vgate=0.3V: Vgs≈0.3-0.8=-0.5V;

[0079] log(Ids1)∝-0.5V, which represents the response of the first transistor at this Vgate voltage.

[0080] When Vgate=0.5V: Vgs≈0.5-0.8=-0.3V;

[0081] log(Ids2)∝-0.3V, which represents the response of the second transistor at this Vgate voltage.

[0082] Calculation result: log(Ids1*Ids2)=log(Ids1)+log(Ids2)∝-0.8V. This result is expressed by the logarithm of the drain current, reflecting the product of the two input signals and demonstrating the computing power of the transistor.

[0083] Combination of perception and storage: The channel region constructed by the top single-crystal silicon layer in the SOI structure can directly receive and sense optical signals without being electrically interfered by the underlying silicon substrate. When the optical signal is irradiated to the channel region, the silicon material directly absorbs the light energy to generate photogenerated electron-hole pairs without passing through other media or layers. These photogenerated carriers are then directly captured by the floating gate structure, and the photogenerated charges are stored by the floating gate to achieve long-term preservation of the sensing information, thereby realizing the storage of electrical signals and further signal processing.

[0084] Furthermore, the method for using the above-mentioned sensing, storage and computing integrated double-sided gate transistor is as follows:

[0085] Expansion of multi-device arrays: Using a single double-sided gate transistor that integrates sensing, storage and computing as a unit, multiple units are integrated on the same chip to form an array structure; by independently regulating the floating gate charge and control gate voltage of each unit, each unit can process different information, realizing parallel data processing and vector computing.

[0086] Further complex working condition applications: The double-sided gate transistor with integrated sensing, storage and computing functions of the present invention is used as a unit. Due to its high integration, this highly integrated feature is very suitable for application in artificial neural networks (ANN). Embedding the unit into the artificial neural network can achieve efficient and low-power neural network hardware, accelerating the development of deep learning and artificial intelligence applications.

[0087] Artificial neural networks consist of a large number of neurons and synaptic connections, and mainly involve the following functions:

[0088] Weight storage: The weights in a neural network represent the strength of the synapses, and a way is needed to store and adjust them. Weighted summation: Neurons receive multiple input signals and perform weighted summation on them. Nonlinear activation: The result of the weighted summation passes through an activation function to produce a nonlinear output. Learning and updating: Through training, the weight values ​​are adjusted to improve network performance.

[0089] The double-sided gate transistor with integrated sensing, storage and computing provided by the present invention has the following characteristics:

[0090] Sensing function: It can receive input signals (such as light signals) and convert them into electrical signals. Storage function: The floating gate can store charges, similar to storing weight values. Computing function: Through the dual-gate structure, the signal can be weighted and processed. Therefore, the synapses and neurons in the neural network can be simulated to realize weight storage and calculation functions.

[0091] The role of device units in neural networks:

[0092] Synapse: Using the storage function of the unit, the charge in the floating gate represents the synaptic weight value. Neuron: Using the calculation function of the unit, the bottom control gate receives the input signal, and generates the output signal after weighted processing determined by the floating gate charge. Weight update: The charge in the floating gate is adjusted through the top control gate to update the weight.

[0093] Design steps:

[0094] 1. Implementation of a single neuron:

[0095] Input signal: The output signal of the previous layer is used as input and applied to the bottom control gate. Weight storage: The amount of charge in the floating gate represents the weight value, which affects the conductivity of the channel region. Weighted summation: The unit weights the input signal (determined by the floating gate charge) and generates source / drain current, which represents the result of weighted summation. Activation function: The activation function is realized through the nonlinear characteristics of the unit or the peripheral circuit.

[0096] 2. Weight storage and adjustment:

[0097] Weight initialization: Apply a specific voltage through the top control gate to inject an initial charge into the floating gate to set the initial weight.

[0098] Weight update (learning process):

[0099] Positive update: If the weight needs to be increased, a voltage is applied to inject more electrons into the floating gate, increasing the negative charge.

[0100] Reverse update: If the weight needs to be reduced, a reverse voltage is applied to cause the electrons in the floating gate to escape and reduce the negative charge.

[0101] Precision control: By precisely controlling the applied voltage and time, the floating gate charge is adjusted to achieve fine adjustment of the weight.

[0102] 3. Implementation of activation function:

[0103] In-unit implementation: Utilize the nonlinear current-voltage characteristics of the unit to directly implement the activation function, such as ReLU or Sigmoid approximation.

[0104] Peripheral circuit implementation: Connect a dedicated activation circuit or amplifier at the unit output to achieve the required activation function.

[0105] 4. Construction of network structure:

[0106] Hierarchical connection: multiple units are connected according to the topological structure of the neural network to form input layer, hidden layer and output layer.

[0107] Array layout: A crossbar structure is used to arrange the units into a two-dimensional array to facilitate large-scale integration and signal transmission.

[0108] Signal transmission: The input signal is applied to the bottom control gate through the row lines (Word Lines), and the output signal is obtained from the source / drain through the column lines (Bit Lines).

[0109] As a further practical example, let’s implement a simple fully connected neural network layer:

[0110] Construction of cell array: A two-dimensional cell array is constructed on the wafer, with the number of rows being the number of input nodes and the number of columns being the number of output nodes.

[0111] Initialization of weights: Using the top control gate, program the floating gate of each cell to set the initial weight value.

[0112] Application of input signal: The input signal (analog or digital form) is applied to the row line corresponding to the bottom control gate.

[0113] Implementation of weighted summation: The unit performs a weighted summation of the input signals, and the source / drain current represents the total input to each output node.

[0114] Application of activation function: Apply the activation function to the source / drain current signal to obtain the output result.

[0115] Reading of output signals: Read the output signals from the column lines (Bit Lines) as the input or final result of the next layer.

[0116] Furthermore, the present invention can also be applied to audio signal processing:

[0117] 1. Volume screening: Signal amplification and threshold detection are achieved by adjusting the charge state of the floating gate in the transistor to change the gain and response threshold of the transistor. This enables the transistor to amplify or suppress the received audio signal according to the preset volume threshold.

[0118] 2. Volume type screening: Using the computing power of transistors, audio filtering is implemented to design filters for specific frequency responses, allowing the corresponding type of sound at that specific frequency to pass while blocking other sounds. In addition, pattern recognition can be implemented using machine learning technology, and the unit array can be trained to recognize specific audio patterns or signatures, such as the sirens of emergency vehicles or the calls of specific animals.

[0119] 3. Application scenarios: It can be used in security systems to implement real-time audio detection, identify abnormal sounds and issue alarms.

[0120] It can be seen from the above embodiments that the present invention proposes to use a back-illuminated structure, combine SOI and floating gate transistor technology, and utilize the unique properties of the top single-crystal silicon layer in SOI to effectively realize direct sensing and conversion of optical signals, thereby integrating multiple functions while maintaining electrical isolation to achieve the integration of sensing, storage and computing of a single transistor. The integration of sensing, storage and computing of a single transistor achieved by the present invention provides a basis for its application in various scenarios, for example, as a unit embedded in an artificial neural network, the array integration of multiple units to achieve complex parallel processing and vector operations, and application in audio signal processing, etc.

Claims

1. A double-sided gate transistor with integrated sensing, storage and computing, characterized in that: It includes a substrate, a buried oxide layer, a top single crystal silicon layer, a floating gate, a gate dielectric layer and a top control gate; The substrate provides physical and electrical support; The buried oxide layer is located above the substrate and is an insulating layer used for electrical isolation, effectively isolating the top single crystal silicon layer from the substrate; The top single crystal silicon layer is located above the buried oxide layer, in which the channel region of the transistor is formed, and source / drain electrodes connected to the channel region are constructed on both sides of the channel region to form an inlet and outlet path for current; the channel region absorbs photons to generate photogenerated electron-hole pairs; when in use, the optical signal is directly incident on the channel region from the substrate side on the back of the device; The floating gate is located on the channel region, and the floating gate is isolated from the channel region by a gate dielectric layer, so as to capture and hold charges for a long time, thereby realizing a storage function; The top control gate is located above the floating gate, and is isolated from the floating gate by another layer of dielectric material control gate dielectric layer, so as to adjust the charge state in the floating gate, thereby regulating the switching state of the transistor; The specific method of realizing the sensing, storage and computing of the double-sided gate transistor is as follows: 1). Floating gate charge modulation: Writing stage: By applying a high voltage between the top control gate and the source / drain, electrons enter the floating gate through the tunneling effect or hot electron injection mechanism, increasing the negative charge in the floating gate, thereby increasing the threshold voltage of the transistor; Erase phase: Apply a reverse high voltage between the top control gate and the source / drain to return the electrons in the floating gate to the channel region or the source / drain, reducing the negative charge in the floating gate; Fine control of charge state: By adjusting the amplitude and duration of the applied voltage, the amount of charge in the floating gate can be precisely controlled, thereby achieving fine adjustment of the threshold voltage; 2) Threshold voltage adjustment: charge Q in the floating gate fg The threshold voltage of the transistor is changed, and the relationship is as follows: Where V th is the threshold voltage, V th0 is the initial threshold voltage, C fg is the capacitance between the floating gate and the channel region; by changing Q fg , to dynamically adjust the threshold voltage so that the transistor exhibits different switching characteristics under different input signals; 3). Control of conductivity in the channel region: Input signal application: Apply the signal to be processed to the top control gate to control the conductance of the channel region; Influence of floating gate charge: The charge state in the floating gate determines the threshold voltage of the transistor, thus affecting the input signal's ability to control the channel region; Conductivity modulation: According to the combined effect of the floating gate charge and the input signal, the conductivity of the channel region changes, thereby amplifying or suppressing the input signal; 4). Implementation of calculation function: Analog computing: Using the IV characteristics of transistors, in the subthreshold region, I ds With V gs exponentially, performing multiplication and / or exponential analog calculations by modulating the top control gate voltage and floating gate charge; Among them, V gs is the gate-source voltage, I ds is the drain current; Digital logic operation: By setting the floating gate charge state, the transistor is turned on or off at a specific input voltage to realize the logic gate function; 5). Data processing and signal output: Source / drain current detection: obtain calculation results by measuring the current between source / drain; Signal reading: The output current signal is directly used for the next step of processing, or converted to obtain the required output form; A bottom control gate is also provided between the substrate and the buried oxide layer, and the potential distribution of the channel region is independently adjusted by applying a control voltage from the back side of the double-sided gate transistor to adjust the conductivity of the channel region, thereby performing complex data processing and calculation; the back side of the double-sided gate transistor refers to the substrate side thereof; The bottom control gate works together with the top control gate to jointly adjust the electric field in the channel region: the top control gate is responsible for quickly responding and directly controlling the upper electric field in the channel region, thereby affecting the basic switching operation of the transistor; while the bottom control gate fine-tunes the electric field at the bottom of the channel region, achieving fine adjustment of the threshold voltage and control of the short channel effect, supplementing the regulation effect of the top control gate.

2. The method for using the sensing, storage and computing integrated double-sided gate transistor as claimed in claim 1, characterized in that: A single double-sided gate transistor that integrates sensing, storage and computing is used as a unit, and multiple units are integrated on the same chip to form an array structure. By independently regulating the floating gate charge and control gate voltage of each unit, each unit can process different information, realizing parallel data processing and vector calculation.

3. The method for using the sensing, storage and computing integrated double-sided gate transistor as claimed in claim 1, characterized in that: A single double-sided gate transistor with integrated sensing, storage and computing is used as a unit to construct a neural network structure. The charge in the floating gate is used as the weight value of the neural network, and the top control gate is used to adjust the floating gate charge to achieve weight update. The bottom control gate receives the input signal and generates an output signal after weighted processing to achieve the computing function of the neural network. Synapse: Using the storage function of the unit, the charge in the floating gate represents the synaptic weight value; Neuron: Using the calculation function of the unit, the bottom control gate receives the input signal, and generates the output signal through weighted processing determined by the floating gate charge; Weight update: The charge in the floating gate is adjusted through the top control gate to achieve the update of the weight; 1). Implementation of a single neuron: Input signal: the output signal of the previous layer is used as input and applied to the bottom control gate; Weight storage: the amount of charge in the floating gate represents the weight value, which affects the conductivity of the channel region; Weighted summation: the unit weights the input signal to generate source / drain current, which represents the result of weighted summation; Activation function: the activation function is realized through the nonlinear characteristics of the unit or the peripheral circuit; 2) Weight storage and adjustment: Weight initialization: Apply a specific voltage through the top control gate to inject an initial charge into the floating gate to set the initial weight; Weight update: Positive update: If the weight needs to be increased, a voltage is applied to inject more electrons into the floating gate, increasing the negative charge; Reverse update: If the weight needs to be reduced, a reverse voltage is applied to make the electrons in the floating gate escape and reduce the negative charge; Precision control: By precisely controlling the applied voltage and time, the floating gate charge is adjusted to achieve fine adjustment of the weight; 3). Implementation of activation function: In-cell implementation: Utilize the nonlinear current-voltage characteristics of the cell to directly implement the activation function; Peripheral circuit implementation: Connect a dedicated activation circuit or amplifier to the unit output to achieve the required activation function; 4). Construction of network structure: Hierarchical connection: multiple units are connected according to the topological structure of the neural network to form input layer, hidden layer and output layer; Array layout: Adopt crossbar structure to arrange the units into a two-dimensional array; Signal transmission: The input signal is applied to the bottom control gate through the row lines Word Lines, and the output signal is obtained from the source / drain through the column lines BitLines.

4. The method for using the sensing, storage and computing integrated double-sided gate transistor as claimed in claim 3, characterized in that: Implement a fully connected neural network layer: Construction of cell array: A two-dimensional cell array is constructed on the wafer, with the number of rows being the number of input nodes and the number of columns being the number of output nodes; Initialization of weights: Use the top control gate to program the floating gate of each cell to set the initial weight value; Application of input signal: Apply the input signal to the row line corresponding to the bottom control gate; Implementation of weighted summation: The unit performs a weighted summation of the input signals, and the source / drain current represents the total input to each output node; Application of activation function: Apply activation function to source / drain current signal to get output result; Reading output signals: Read output signals from the column lines Bit Lines as input or final result of the next layer.

5. The method for using the sensing, storage and computing integrated double-sided gate transistor as claimed in claim 1, characterized in that: Applied to audio signal processing: using a single double-sided gate transistor with integrated sensing, storage and computing as a unit; Volume screening: Signal amplification and threshold detection are achieved by adjusting the charge state of the floating gate in the unit to change the gain and response threshold of the unit so that the unit amplifies or suppresses the received audio signal according to the preset volume threshold.

6. The method for using the sensing, storage and computing integrated double-sided gate transistor as claimed in claim 1, characterized in that: Applied to audio signal processing: using a single double-sided gate transistor with integrated sensing, storage and computing as a unit; Volume Type Filtering: Implements audio filtering using the unit's computational capabilities to design filters for a specific frequency response, allowing sounds of that specific frequency type to pass while blocking other sounds.

7. The method for using the sensing, storage and computing integrated double-sided gate transistor as claimed in claim 6, characterized in that: Application to audio signal processing: Using machine learning techniques to achieve pattern recognition, unit arrays are trained to recognize specific audio patterns or signatures, identify abnormal sounds and sound an alarm.

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