Display substrate, display panel and display device

Abstract

Disclosed are a display substrate, a display panel and a display device. The display substrate comprises: a substrate; a plurality of data lines on the substrate, the data lines extending along a first direction; a touch layer on a side of the layer where the data lines are located away from the substrate, the touch layer comprising a plurality of touch electrodes configured to be multiplexed as a common electrode, the touch electrodes comprising a plurality of touch sub-electrodes electrically connected to each other; wherein the touch sub-electrodes are arranged in an array along the first direction and a second direction, there is a first slit between two adjacent touch sub-electrodes along the second direction, a projection of the first slit on the substrate overlaps a projection of the data lines on the substrate, the first direction intersects the second direction; and a plurality of touch signal lines on a side of the touch layer away from the substrate, the touch signal lines being connected to the touch electrodes, and a projection of at least one touch signal line on the substrate covers a projection of the first slit on the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, specifically to a display substrate, a display panel, and a display device. Background Technology

[0002] A liquid crystal display panel includes a display substrate and a cell substrate disposed opposite each other, and a liquid crystal layer located between the two. The liquid crystal layer is deflected under the influence of an electric field between the pixel electrodes and a common electrode, thereby allowing light to pass through. In some products, a touch structure can also be integrated into the liquid crystal display panel, thus enabling touch functionality while displaying the image. Summary of the Invention

[0003] This disclosure provides a display substrate, a display panel, and a display device.

[0004] This disclosure provides a display substrate, including:

[0005] Substrate;

[0006] Multiple data lines located on the substrate, the data lines extending along a first direction;

[0007] A touch layer is located on the side of the layer containing the data line away from the substrate. The touch layer includes a plurality of touch electrodes configured to be reused as a common electrode. Each touch electrode includes a plurality of touch sub-electrodes electrically connected to each other. The touch sub-electrodes are arranged in an array along a first direction and a second direction. A first slit is formed between two adjacent touch sub-electrodes along the second direction. The orthographic projection of the first slit on the substrate overlaps with the orthographic projection of the data line on the substrate. The first direction and the second direction intersect.

[0008] Multiple touch signal lines are located on the side of the touch layer away from the substrate. The touch signal lines are connected to the touch electrodes. The orthographic projection of at least one of the touch signal lines on the substrate covers the orthographic projection of the first slit on the substrate.

[0009] In some embodiments, at least one of the touch signal lines overlaps with the orthographic projection of the touch sub-electrodes on both sides of the first slit onto the substrate.

[0010] In some embodiments, the overlap width along the second direction between the orthographic projection of the touch signal line on the substrate and the orthographic projection of the touch sub-electrodes on both sides of the first slit is a first width, which is 1 to 1.2 times a first preset width D.

[0011]

[0012] Wherein, D1 is the maximum displacement fluctuation value in the manufacturing process of the touch signal line; D2 is the maximum single-sided size fluctuation value in the manufacturing process of the touch signal line; and D3 is the maximum single-sided size fluctuation value in the manufacturing process of the touch sub-electrode.

[0013] In some embodiments, the first width is equal to D.

[0014] In some embodiments, the first width is between 1.69 μm and 2.0 μm.

[0015] In some embodiments, the orthographic projection of each of the touch signal lines on the substrate covers the orthographic projection of the first slit on the substrate, and overlaps with the orthographic projections of the touch sub-electrodes on both sides of the first slit on the substrate.

[0016] In some embodiments, the display substrate has a display area, at least a portion of the data lines and the touch layer are located in the display area, and the display area is further provided with a plurality of gate lines, the plurality of gate lines and the plurality of data lines dividing the display area into a plurality of pixel areas, a pixel electrode is provided in the pixel area, the pixel electrode is located on the side of the touch layer away from the substrate, and a second slit is provided on the pixel electrode.

[0017] In some embodiments, a first passivation layer is disposed between the touch layer and the touch signal line, a second passivation layer is disposed on the side of the layer where the touch signal line is located away from the substrate, and the pixel electrode is disposed on the side of the second passivation layer away from the substrate.

[0018] In some embodiments, the display substrate further has a peripheral region surrounding the display area, and the display substrate further includes components located in the peripheral region:

[0019] The first signal transmission element is disposed on the same layer as the gate line;

[0020] The second signal transmission component is disposed on the same layer as the data line;

[0021] The connector is disposed on the same layer as the pixel electrode. The connector is connected to the first signal transmission component through a first via and to the second signal transmission component through a second via.

[0022] In some embodiments, a passivation layer is disposed on the side of the touch layer away from the substrate, and the touch signal line and the pixel electrode are both located on the side of the passivation layer away from the substrate; a protective layer is also disposed on the side of the touch signal line away from the substrate, the protective layer covers the touch signal line and is disposed in the same layer as the pixel electrode.

[0023] In some embodiments, the orthographic projection of the protective layer onto the substrate extends beyond the orthographic projection of the touch signal line onto the substrate, and the width of the extended portion is 1 to 1.2 times the second preset width D'.

[0024]

[0025] Wherein, D1 is the maximum displacement fluctuation value in the manufacturing process of the touch signal line; D2 is the maximum single-sided size fluctuation value in the manufacturing process of the touch signal line; D4 is the maximum displacement fluctuation value in the manufacturing process of the protective layer; and D5 is the maximum single-sided size fluctuation value in the manufacturing process of the protective layer.

[0026] In some embodiments, the display substrate further has a peripheral region surrounding the display area, and the display substrate further includes components located in the peripheral region:

[0027] The first signal transmission element is disposed on the same layer as the gate line;

[0028] The second signal transmission component is disposed on the same layer as the data line;

[0029] A first connector and a second connector are stacked and connected together. The first connector is disposed on the same layer as the touch line. The first connector is connected to the first signal transmission element through a first via and to the second signal transmission element through a second via. The second connector is located on the side of the first connector layer away from the substrate and is disposed on the same layer as the pixel electrode.

[0030] In some embodiments, the orthographic projections of the first conductive layer and the second conductive layer on the substrate coincide.

[0031] In some embodiments, the display substrate further includes: a plurality of common electrode lines, the common electrode lines being located between the touch layer and the substrate, and the touch electrodes being electrically connected to the common electrode lines.

[0032] In some embodiments, the touch signal line includes: a plurality of first line segments arranged along a first direction and a second line segment connected between two adjacent first line segments, wherein the orthographic projection of the first line segment on the substrate overlaps with the orthographic projection of the first slit on the substrate, and at least a portion of the orthographic projection of the second line segment on the substrate does not overlap with the orthographic projection of the first slit on the substrate.

[0033] Each of the touch electrodes is connected to the second segment of a corresponding touch signal line.

[0034] In some embodiments, each of the touch electrodes is connected to a plurality of second segments of a corresponding touch signal line.

[0035] In some embodiments, in the same touch electrode, one of the touch sub-electrodes in each row is connected to the touch signal line; two adjacent touch sub-electrodes in the same row are connected by a connecting part, and the connecting part and the touch sub-electrode are integrally formed.

[0036] In some embodiments, the display substrate further includes a plurality of gate lines, wherein the orthographic projection of the second line segment on the substrate overlaps with the orthographic projection of the gate line on the substrate.

[0037] Secondly, this disclosure provides a display panel, including the aforementioned display substrate and color filter substrate disposed opposite to each other.

[0038] Thirdly, this disclosure provides a display device including the aforementioned display panel. Attached Figure Description

[0039] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:

[0040] Figure 1 This is a schematic diagram of a display substrate provided in some embodiments.

[0041] Figure 2 for Figure 1 A plan view of the touch electrodes, pixel electrodes, touch signal lines, and data lines in a local area of ​​the display substrate.

[0042] Figure 3 For along Figure 2 A cross-sectional view of line A-A' in the middle.

[0043] Figure 4 This is a schematic diagram of the region division of a display substrate provided in some embodiments of this disclosure.

[0044] Figure 5 This is a partial schematic diagram of a display substrate provided in some embodiments of this disclosure.

[0045] Figure 6 for Figure 5 A schematic diagram of the touch electrodes in the image.

[0046] Figure 7 for Figure 5 A schematic diagram of the touch electrodes, touch signal lines, and common electrode lines.

[0047] Figure 8 The following are provided in some embodiments of this disclosure: Figure 5 A cross-sectional view of line B-B' in the middle.

[0048] Figure 9 for Figure 5 A schematic diagram showing the connection between the pixel electrode and the thin-film transistor.

[0049] Figure 10 This is a partial structural diagram of the peripheral area and display area of ​​the display substrate provided in some embodiments of this disclosure.

[0050] Figure 11 This is a plan view showing the connection between a first signal transmitter and a second signal transmitter provided in some embodiments of this disclosure.

[0051] Figure 12 For other embodiments of this disclosure, along Figure 5 A cross-sectional view of line B-B' in the middle.

[0052] Figure 13 This is a partial structural diagram of the peripheral area and display area provided in some other embodiments of this disclosure.

[0053] Figure 14 This is a schematic diagram of a display panel provided in some embodiments of the present disclosure. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0055] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0056] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element.

[0057] It should also be noted that "same-layer arrangement" in the embodiments of this disclosure means that the two structures are formed by the same material layer through a patterning process, so they are in the same layer in terms of stacking relationship; however, this does not mean that the distance between the two and the substrate must be the same.

[0058] A liquid crystal display panel includes a display substrate and a cell substrate disposed opposite each other, and a liquid crystal layer located between the two. Figure 1 This is a schematic diagram of a display substrate provided in some embodiments. Figure 2 for Figure 1 A plan view of the touch electrodes, pixel electrodes, touch signal lines, and data lines in a local area of ​​the display substrate. Figure 3 For along Figure 2 A cross-sectional view of line A-A', as shown Figures 1 to 3 As shown, the display substrate includes multiple gate lines GL and multiple data lines DL (not shown) disposed on the substrate 10. The multiple gate lines GL and multiple data lines DL are arranged intersectingly to define multiple pixel regions PA. Each pixel region PA is provided with a pixel electrode 30. In addition, the display substrate may also include a common electrode. When the liquid crystal display panel is displaying, the common electrode line (not shown) provides a common voltage to the common electrode, and the data lines DL provide a pixel voltage to the pixel electrode 30, thereby generating an electric field between the common electrode and the pixel electrode 30 to drive the liquid crystal to deflect.

[0059] Furthermore, touch structures can be integrated within the LCD panel, enabling touch control and improving product integration. For example... Figure 1 As shown, the display substrate also includes touch signal lines TL, and the common electrode can be reused as a touch electrode 20. Each touch electrode 20 is connected to a touch signal line TL. In this case, the liquid crystal display panel realizes touch and display in a time-division manner. During the display stage, the common electrode line provides a common voltage signal to the common electrode; during the touch stage, the touch signal line TL provides a touch driving signal to the common electrode (i.e., the touch electrode 20).

[0060] like Figure 2 and Figure 3As shown, the orthographic projection of the touch signal line TL on the substrate 10 overlaps with the orthographic projection of the data line DL on the substrate 10. The orthographic projection of each touch electrode 20 on the substrate 10 overlaps with multiple pixel areas PA. For example, each touch electrode 20 includes an array of multiple touch sub-electrodes 21, and the orthographic projection of each touch sub-electrode 21 on the substrate 10 overlaps with the orthographic projection of a pixel electrode 30 on the substrate 10. Within the same touch electrode 20, adjacent touch sub-electrodes 21 located in the same row are connected by a connecting portion, and each row of touch sub-electrodes 21 is connected to the corresponding touch signal line TL of its respective touch electrode 20 through a fourth via V4.

[0061] like Figure 3 As shown, a first slit 20a is provided between two adjacent touch sub-electrodes 21 in the same row on the entire display substrate (e.g., a slit between two adjacent touch sub-electrodes 21 in the same row of the same touch electrode 20, or a slit between two adjacent touch electrodes 20 in the same row). The orthographic projections of the touch signal line TL and the data line DL on the substrate 10 overlap with the orthographic projections of the first slit 20a on the substrate 10. In some embodiments, the width of the touch signal line TL is smaller than the width of the first slit 20a. However, since the voltage on the data line DL is the same as that on the pixel electrode 30, therefore, for Figure 2 and Figure 3 The structure shown generates a lateral electric field between the data line DL and the touch sub-electrode 21, resulting in a lateral electric field in the pixel area PA near the data line DL (e.g., Figure 3 The liquid crystal deflection in the A1 and A2 regions of the image becomes disordered, resulting in pixel light leakage.

[0062] Figure 4 This is a schematic diagram of the region division of a display substrate provided in some embodiments of this disclosure. Figure 5 This is a partial schematic diagram of a display substrate provided in some embodiments of this disclosure. Figure 6 for Figure 5 A schematic diagram of the touch electrodes in the image. Figure 7 for Figure 5 A schematic diagram of the touch electrodes, touch signal lines, and common electrode lines. Figure 8 The following are provided in some embodiments of this disclosure: Figure 5 A cross-sectional view of line B-B', as shown Figures 4 to 8As shown, the display substrate includes a substrate 10 and, disposed on the substrate 10, a plurality of gate lines GL, a plurality of data lines DL, a plurality of touch signal lines TL, and a touch layer. The display substrate has a display area AA and a peripheral area WA surrounding the display area AA. At least a portion of the gate lines GL and at least a portion of the data lines DL are located within the display area AA. The data lines DL extend along a first direction, and the gate lines GL extend along a second direction. The plurality of gate lines GL and the plurality of data lines DL define a plurality of pixel areas PA within the display area AA. The first direction and the second direction intersect, for example, they are perpendicular.

[0063] It should be noted that the data line DL extending along the first direction does not necessarily mean that the data line DL is a straight line extending along the first direction; it can also have some bends, as long as the data line DL generally extends along the first direction. Similarly, the gate line GL extending along the second direction means that the gate line GL generally extends along the first direction.

[0064] The touch layer is located on the side of the layer containing the data line DL that is away from the substrate 10. The touch layer includes multiple touch electrodes 20, which are multiplexed as a common electrode. Each touch electrode 20 may include multiple electrically connected touch sub-electrodes 21; wherein, the multiple touch sub-electrodes 21 in the touch layer are arranged in an array along a first direction and a second direction. Specifically, the multiple touch sub-electrodes 21 in the touch layer are arranged in multiple rows along the first direction, and each row includes multiple touch sub-electrodes 21 arranged along the second direction. Figure 6 and Figure 8 As shown, there is a first slit 20a between two adjacent touch sub-electrodes 21 along the second direction, that is, there is a first slit 20a between two adjacent touch sub-electrodes 21 in the same row, and the orthographic projection of the first slit 20a on the substrate 10 overlaps with the orthographic projection of the data line DL on the substrate 10.

[0065] It should be understood that the so-called "two adjacent touch sub-electrodes 21 in the same row" can be two adjacent touch sub-electrodes 21 arranged along the second direction in the same touch electrode 20, or two adjacent touch sub-electrodes 21 located in two touch electrodes 20 respectively and arranged along the second direction.

[0066] The first slit 20a can be a strip-shaped structure extending along the first direction. It should be noted that the first slit 20a can be a straight strip-shaped structure extending along the first direction or a bent strip-shaped structure, as long as the first slit 20a generally extends along the first direction.

[0067] Multiple touch signal lines TL are located on the side of the touch layer away from the substrate 10. The touch signal lines TL are connected to the touch electrode 20, and the orthographic projection of at least one touch signal line TL on the substrate 10 covers the orthographic projection of the first slit 20a on the substrate 10. Specifically, the orthographic projection of at least one touch signal line TL on the substrate 10 completely covers the orthographic projection of the first slit 20a. In particular, the width of the touch signal line TL in the second direction is greater than the width of the first slit 20a in the second direction. For example, the first slit 20a has two first edges arranged in the second direction. The orthographic projection of the edge of the touch signal line TL on the substrate 10 can contact the edge of the first edge on the substrate 10, or the orthographic projection of the touch signal line TL on the substrate 10 can exceed the orthographic projection of the first slit 20a on the substrate 10 and overlap with the orthographic projection of the touch sub-electrode 21 on the substrate 10.

[0068] During the display phase, the touch sub-electrode 21 and the touch signal line TL receive a common voltage signal. Since in this embodiment, the orthographic projection of the touch signal line TL on the substrate 10 covers the orthographic projection of the first slit 20a on the substrate 10, the touch signal line TL can shield the electric field formed between the data line DL and the touch sub-electrode 21, preventing the electric field from affecting the liquid crystal deflection and causing light leakage, thereby ensuring the display effect.

[0069] In some embodiments, such as Figure 8 As shown, the orthographic projection of at least one touch signal line TL on the substrate 10 covers the orthographic projection of the first slit 20a on the substrate 10, and overlaps with the orthographic projection of the touch sub-electrodes 21 on both sides of the first slit 20a on the substrate 10, thereby further ensuring the shielding effect of the touch signal line TL on the electric field between the data line DL and the touch sub-electrodes 21.

[0070] It should be noted that the touch sub-electrodes 21 on both sides of the first slit 20a refer to the two sides of the first slit 20a along the second direction.

[0071] In some embodiments, the orthographic projection of each touch signal line TL on the substrate 10 covers the orthographic projection of the first slit 20a on the substrate 10, and overlaps with the orthographic projection of the touch sub-electrodes 21 on both sides of the first slit 20a on the substrate 10, so as to ensure that no light leakage occurs in the vicinity of each touch signal line TL.

[0072] In some embodiments, a data driver chip 71 is disposed on one side of the display area AA, which is used to provide data signals to the data line DL. The touch signal line TL extends from the end of the display area AA near the data driver chip 71 to the end away from the data driver chip 71, so that the orthographic projection of each first slit 20a on the substrate 10 is covered by the orthographic projection of the touch signal line TL on the substrate 10, thereby improving the light leakage prevention effect.

[0073] In some embodiments, the overlap width between the orthographic projection of the touch signal line TL on the substrate 10 and the orthographic projection of the touch sub-electrodes 21 on both sides of the first slit 20a on the substrate 10 is a first width W. It should be noted that the overlap width refers to the width of the overlapping area in the second direction. The first width W can be set according to a first preset width D, where D is a parameter related to the manufacturing process. Specifically,

[0074] Wherein, D1 is the maximum displacement fluctuation value in the manufacturing process of the touch signal line TL. The maximum positional fluctuation value of a device in the manufacturing process refers to the distance between the actual position and the target position of the device's center on the substrate 10 due to the precision of the manufacturing process. D2 is the maximum single-sided dimensional fluctuation value in the manufacturing process of the touch signal line TL. Specifically, if the target width of the touch signal line TL is W1 and the actual width is W2, then |W1-W2| / 2 is the single-sided dimensional fluctuation value, and the maximum value of |W1-W2| / 2 is D2. D3 is the maximum dimensional fluctuation value in the manufacturing process of the touch sub-electrode 21. Specifically, if the target width of the touch sub-electrode 21 is W3 and the actual width is W4, then the maximum value of |W3-W4| / 2 is D2.

[0075] In some embodiments, the first width W is 1 to 1.2 times D. In this case, even if there are process fluctuations during the manufacturing process, it can still be ensured that the orthogonal projection of the touch signal line TL on the substrate 10 covers the orthogonal projection of the first slit 20a on the substrate 10.

[0076] Preferably, the first width is D, so that when process fluctuations occur, the orthographic projection of the touch signal line TL on the substrate 10 covers the orthographic projection of the first slit 20a on the substrate 10, and the overlap area between the touch signal line TL and the touch electrode 20 is not too large, so as to prevent the generation of large parasitic capacitance and affect the touch effect.

[0077] In one example, D1 = 1.5μm, D2 = 0.6μm, D3 = 0.5μm, and D = 1.69. In this case, the first width W can be set between 1.69 and 2.0μm. For example, W can be set to 1.69μm, 1.7μm, 1.8μm, 1.9μm, or 2.0μm.

[0078] In the display panel, the opposing substrate, disposed opposite to the display substrate, includes a black matrix. The orthographic projection of the black matrix onto the substrate 10 covers the orthographic projections of the data line DL, gate line GL, and touch signal line TL onto the substrate 10. To increase the effective light-emitting area of ​​the pixel region, the touch signal line CL and the data line DL can be set to a smaller width. In one example, the width of the first slit 20a is between 3 and 7 μm, W is between 1.69 and 2.0 μm, and the width of the data line DL is between 4 and 6 μm, thereby making the touch signal line TL and the data line DL have a smaller width, which in turn makes the black matrix have a smaller width, thus increasing the effective light-emitting area of ​​the pixel region. For example, in Figure 8 In the structure, the width of the data line DL is 5μm, the width of the touch signal line TL is 7μm, the width of the first slit 20a is 3.6μm, and W is set to 1.7μm.

[0079] like Figure 5 and Figure 8 As shown, each pixel region PA is provided with a pixel electrode 30. The pixel electrode 30 is located on the side of the touch layer away from the substrate 10, and a second slit 30a is provided on the pixel electrode 30. The second slit 30a can be a zigzag shape. It should be noted that... Figure 8 Only the structure of the data line DL and the film layer above it is shown in the figure. The structure between the data line DL and the substrate 10 can be found in [reference needed]. Figure 9 As shown in the image. Figure 9 for Figure 5 A schematic diagram of the connection between the pixel electrode and the thin-film transistor is shown in the figure. Figure 5 and Figure 9 As shown, each pixel region PA corresponds to a thin film transistor 50, and the thin film transistor 50 includes a gate 51, an active layer 52, a source 53, and a drain 54.

[0080] In this thin-film transistor 50, the gate 51 and the gate line GL are formed as an integral structure, and a gate insulating layer GI is disposed on the side of the layer where the gate line GL is located away from the substrate 10. The materials of the gate 51 and the gate line GL may include metals, metal alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. For example, gate 51 and gate line GL may include gold (Au), gold alloys, silver (Ag), silver alloys, aluminum (Al), aluminum alloys, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), copper alloys, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), molybdenum alloys, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc. Gate 51 and gate line GL may have a single layer or multiple layers.

[0081] The gate insulating layer GI can include, for example, silicon compounds and metal oxides. For instance, the gate insulating layer GI can include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The gate insulating layer GI can be formed as a single layer or multiple layers.

[0082] The active layer 52 is located on the side of the gate insulating layer GI away from the substrate 10. The active layer 52 may include, for example, inorganic semiconductor materials (e.g., polycrystalline silicon, amorphous silicon, etc.), organic semiconductor materials, or oxide semiconductor materials. The active layer 52 includes a source contact region, a drain contact region, and a channel region located between the two. The gate in the channel region is disposed opposite to the channel region. Both the source contact region and the drain contact region may include impurities with a higher impurity concentration than the channel region. The impurities may include N-type impurities or P-type impurities.

[0083] Source 53 and drain 54 are located on the side of active layer 52 away from substrate 10. Source 53 is connected to the source contact region, and drain 54 is connected to the drain contact region. Source 53 and data line DL are formed as an integral structure. Source 53 and drain 54 are disposed in the same layer. The materials of source 53 and drain 54 may include metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc., and both source 53 and drain 54 may be single-layer or multi-layer metals. For example, source 53 and drain 54 are Mo / Al / Mo or Ti / Al / Ti.

[0084] like Figure 5 and Figure 9 As shown, the pixel electrode 30 is connected to the drain 54 of the thin-film transistor 50 through a fifth via V5. For example, the pixel electrode 30 includes a connected electrode body portion 31 and an electrode connection portion 32, which can be an integral structure with the electrode body portion 31. A second slit 30a is provided on the electrode body portion 31, which is located on one side and connected to the drain 54 of the thin-film transistor 50 through the fifth via V5. The fifth via V5 penetrates all film layers between the layer containing the pixel electrode 30 and the drain 54. Both the pixel electrode 30 and the touch electrode 20 can be made of transparent conductive materials such as indium tin oxide (ITO).

[0085] like Figure 5 As shown, the display substrate also includes multiple common electrode lines CL, which are located between the touch layer and the substrate 10. The touch electrode 20 is electrically connected to the common electrode lines CL. The common electrode lines CL can be disposed on the same layer as the gate lines GL, and the touch layer is connected to the common electrode lines CL through a third via V3 that penetrates the gate insulating layer GI and the planarization layer PLN.

[0086] The multiple pixel areas PA in the display area AA can be grouped into multiple repeating units, each of which includes multiple pixel areas PA, for example, three pixel areas PA (red, green, and blue, respectively). In one example, the orthographic projection of the touch electrode 20 onto the substrate 10 overlaps with the multiple repeating units. Each repeating unit is provided with a third via V3, thereby connecting the touch electrode 20 to the common electrode line CL through multiple third vias V3, so that the common voltage received at different locations on the touch electrode 20 is more evenly distributed. For example, each repeating unit is provided with one third via V3.

[0087] Continue to refer to Figure 8 and Figure 9 A planarization layer PLN is provided on the side of the layer containing the source electrode 53 and the drain electrode 54 away from the substrate 10. The planarization layer PLN may include an organic insulating material, such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane, and other resin-based materials. Alternatively, the organic insulating material may include an elastic material, such as urethane or thermoplastic polyurethane (TPU).

[0088] The touch layer is located on the side of the planarization layer PLN away from the substrate 10. A passivation layer PVX is disposed on the side of the touch layer away from the substrate 10, and the touch signal line TL and pixel electrode 30 are both located on the side of the passivation layer PVX away from the substrate 10. The passivation layer PVX can include, for example, silicon compounds and metal oxides. For example, the passivation layer PVX may include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The passivation layer PVX can be formed as a single layer or multiple layers.

[0089] In some embodiments, a protective layer 60 is further provided on the side of the touch signal line TL away from the substrate 10, and the protective layer 60 is disposed in the same layer as the pixel electrode 30. The touch signal line TL can be made of a metallic material, and the protective layer 60 can be made of a transparent conductive material such as indium tin oxide (ITO). The protective layer 60 can cover the touch signal line TL, thereby protecting the touch signal line TL from corrosion, and the overall resistance of the touch signal line TL and the protective layer 60 will be less than the resistance of the touch signal line TL itself, thus facilitating the transmission of touch signals. The touch signal line TL has an upper surface away from the substrate 10, a lower surface facing the substrate 10, and a side surface connecting the upper and lower surfaces. The protective layer 60 covering the touch signal line TL can mean that the protective layer 60 covers the upper surface and the side surface of the touch signal line TL.

[0090] In some embodiments, the orthographic projection of the protective layer 60 onto the substrate 10 extends beyond the orthographic projection of the touch signal line TL onto the substrate 10, and the width W' of the extended portion is greater than or equal to a second preset width D'. D' is a parameter related to the manufacturing process. Specifically,

[0091] As mentioned above, D1 is the maximum displacement fluctuation value in the manufacturing process of the touch signal line TL; D2 is the maximum single-sided dimensional fluctuation value in the manufacturing process of the touch signal line TL. Additionally, D4 is the maximum displacement fluctuation value in the manufacturing process of the protective layer 60; and D5 is the maximum single-sided dimensional fluctuation value in the manufacturing process of the protective layer 60.

[0092] Setting W' to be greater than or equal to the second preset width D' ensures that even if process fluctuations occur, the orthogonal projection of the protective layer 60 on the substrate 10 can cover the orthogonal projection of the touch signal line TL on the substrate 10, thereby ensuring the protective effect of the protective layer 60 on the touch signal line TL.

[0093] In one example, D1 = 1.5 μm, D2 = 0.6 μm, D4 = 1.5 μm, and D5 = 0.5 μm. In this case, W' can be set between 2.26 μm and 2.8 μm. For example, W' can be set to 2.26 μm, 2.3 μm, 2.45 μm, or 2.5 μm.

[0094] In some embodiments, the touch signal line TL is connected to the touch electrode 20 through a fourth via V4 penetrating the passivation layer PVX. Figures 5 to 7 As shown, the touch signal line TL includes: a plurality of first segments TL1 arranged along a first direction and a second segment TL2 connected between two adjacent first segments TL1. The orthographic projection of the first segment TL1 on the substrate 10 overlaps with the orthographic projection of the first slit 20a on the substrate 10, and also overlaps with the orthographic projection of the data line DL on the substrate 10. The second segment TL2 bends toward one side of the data line DL along its width direction. At least a portion of the orthographic projection of the second segment TL2 on the substrate 10 does not overlap with the orthographic projection of the data line DL on the substrate 10 or the orthographic projection of the first slit 20a on the substrate 10. The orthographic projection of the second segment TL2 on the substrate 10 overlaps with the orthographic projection of the gate line GL on the substrate 10. Each touch electrode 20 is connected to the second segment TL2 of a corresponding touch signal line TL.

[0095] In some embodiments, each touch electrode 20 is connected to a plurality of second segments TL2 of a corresponding touch signal line TL. For example, each touch electrode 20 includes multiple rows of touch sub-electrodes 21, such as... Figure 6 As shown, in the same touch electrode 20, two adjacent touch sub-electrodes 21 located in the same row are connected by a connecting portion 20b, which is an integral structure with the touch sub-electrode 21. For example, two adjacent touch sub-electrodes 21 are connected by two connecting portions 20b, and the gap between the two connecting portions 20b and the two touch sub-electrodes 21 can serve as a first slit 20a. In the same touch electrode 20, one of the touch sub-electrodes 21 in each row is connected to the second segment TL2 of the touch signal line TL.

[0096] In some embodiments, combined with Figure 5 and Figure 7 As shown, the touch sub-electrode 21 includes a first part 21a and a second part 21b, which are connected as a single structure. The orthographic projection of the first part 21a on the substrate 10 overlaps with the orthographic projection of the pixel electrode 30 on the substrate 10. The second part 21b is located on one side of the first part 21a and is connected to the touch signal line TL through a fourth via V4. The fourth via V4 corresponding to the touch sub-electrode 21 and the first part 21a of the touch sub-electrode 21 can be located on opposite sides of the gate line GL.

[0097] Figure 10 This is a partial structural diagram of the peripheral area and display area of ​​the display substrate provided in some embodiments of this disclosure. Figure 11 This is a plan view showing the connection between the first signal transmission element and the second signal transmission element provided in some embodiments of this disclosure, such as... Figure 10 As shown, the display substrate also includes, in the peripheral area WA: a first signal transmission element 91, a second signal transmission element 92, a first connector 81, and a second connector 82, which are stacked and in contact with each other. The first signal transmission element 91 is disposed on the same layer as the gate line GL, and the second signal transmission element 92 is disposed on the same layer as the data line DL. The first connector 81 is disposed on the same layer as the touch signal line TL, as shown. Figure 10 and Figure 11 As shown, the first connector 81 is connected to the first signal transmission component 91 through a first via V1 and to the second signal transmission component 92 through a second via V2. The number of first vias V1 and second vias V2 can be one or more. The second connector 82 is located on the side of the first connector 81 away from the substrate 10, and the second connector 82 is disposed on the same layer as the pixel electrode 30.

[0098] In some embodiments, the first signal transmitter 91, the second signal transmitter 92, and the touch signal line TL are made of the same metal composition. In this case, setting the first connector 81 to be on the same layer as the touch signal line TL can prevent the first signal transmitter 91 and the second signal transmitter 92 from being corroded during the etching process of the touch signal line TL, without adding process steps. The specific reason is as follows: Taking the touch signal line TL and the second signal transmitter line as both Mo / Al / Mo stacks, and the first signal transmitter line as MoNb / Cu (all three contain the same metal composition Mo) as an example, if the first connector 81 is not set, and the first signal transmitter 91 and the second signal transmitter 92 are connected only through the second connector 82 on the same layer as the pixel electrode 30, then after the formation of the first via V1 and the second via V2, when performing the patterning process of the touch signal line TL, the etching solution will enter the first via V1 and the second via V2, thereby corroding the first signal transmitter 91 and the second signal transmitter 92. If the first connector 81 is provided, then during the patterning process of the touch signal line TL, it is not necessary to etch away the metal material above the first via V1 and the second via V2, and the etching solution will not enter the first via V1 and the second via V2 and corrode the first signal transmission element 91 and the second signal transmission element 92.

[0099] In some embodiments, the first signal transmission element 91 and the second signal transmission element 92 can be used to realize the connection between the gate drive circuit and the gate line GL. For example... Figure 4As shown, the peripheral region WA is provided with a gate driving circuit 72, which includes multiple shift register units. Each shift register unit corresponds to a gate line GL and is used to provide a scan signal for the corresponding gate line GL. The peripheral region WA is provided with gate line leads GL1 that correspond one-to-one with the gate lines GL. The gate line leads GL1 and the gate lines GL are integrally structured and connected to the signal output section of the shift register unit. The first signal transmission element 81 can be used as the gate line lead GL1, and the second signal transmission element 82 can be used as the signal output section of the shift register unit.

[0100] In other embodiments, the first signal transmission element 91 and the second signal transmission element 92 can also be used to realize the electrical connection between the data driver chip 71 and the data line DL. For example... Figure 4 As shown, the peripheral area WA includes a transition area DA located on one side of the display area AA. The transition area DA has multiple data line leads DL1, each connected to a corresponding data line DL. For example, the data line leads DL1 and data lines DL can be integrated into a single structure. Fan-out lines 202 are connected to the data line leads DL1 one-to-one, and are used to transmit data signals provided by the data driver chip 71 to the corresponding data lines DL. Specifically, the first signal transmission element 91 can be used as the fan-out line 202, and the second signal transmission element 92 can be used as the data line lead DL1.

[0101] Alternatively, a portion of the first signal transmission element 91 and the second signal transmission element 92 are used to realize the electrical connection between the data driver chip 71 and the data line DL, while another portion of the first signal transmission element 91 and the second signal transmission element 92 are used to connect the gate drive circuit 72 and the gate line GL.

[0102] Of course, the first signal transmission element 91 and the second signal transmission element 92 can also be used as other signal transmission structures, which will not be listed here.

[0103] Figure 12 For other embodiments of this disclosure, along Figure 5 A sectional view of line B-B' in the middle. Figure 12 and Figure 8 Similar, the difference lies in, in Figure 12In this design, a first passivation layer PVX1 and a second passivation layer PVX2 are disposed on the side of the touch layer away from the substrate 10. The second passivation layer PVX2 is located on the side of the first passivation layer PVX1 away from the substrate 10. The touch signal line TL is located between the first passivation layer PVX1 and the second passivation layer PVX2. The pixel electrode 30 is located on the side of the second passivation layer PVX2 away from the substrate 10. At this time, a fourth via V4 for connecting the touch signal line TL and the touch electrode 20 penetrates the first passivation layer PVX1, and a third via V3 for connecting the touch electrode 20 and the common electrode line CL penetrates the first passivation layer PVX1, the second passivation layer PVX2, the planarization layer PLN, and the gate insulating layer GI.

[0104] The materials of the first passivation layer PVX1 and the second passivation layer PVX2 can both be selected from the passivation layer PVX materials listed above.

[0105] Figure 12 and Figure 8 compared to, Figure 12 The display substrate shown has two passivation layers, and Figure 8 The display substrate shown has a passivation layer PVX, which reduces the number of film layers and simplifies the manufacturing process.

[0106] exist Figure 12 In this configuration, the orthographic projection of the touch signal line TL onto the substrate 10 can overlap with the orthographic projection of the touch sub-electrodes 21 on both sides of the first slit 20a onto the substrate 10. The width of the overlapping area is between D and 1.2D, for example, the first width is between 1.69 μm and 2.0 μm. In one example, the width of the first slit 20a is 6.6 μm, the width of the touch signal line TL is 10.0 μm, the first width is 1.7 μm, and the width of the data line DL is 4.2 μm.

[0107] Figure 13 This is a partial structural diagram of the peripheral area and display area provided in some other embodiments of this disclosure, such as... Figure 13 As shown, when the display substrate includes a first passivation layer PVX1 and a second passivation layer PVX2, and the touch signal line TL is located between the first passivation layer PVX1 and the second passivation layer PVX2, and the pixel electrode 30 is located on the side of the second passivation layer PVX2 away from the substrate 10, the first signal transmission element 91 and the second signal transmission element 92 in the peripheral region WA can be connected by a connector 80. The connector 80 is disposed on the same layer as the pixel electrode 30, and the connector 80 is connected to the first signal transmission element 91 through a first via V1 and to the second signal transmission element 92 through a second via V2. For Figure 13In the manufacturing process of the display substrate shown, the first via V1 and the second via V2 can be formed after the second passivation layer PVX2 is formed. The patterning process of the touch signal line TL is completed after the first passivation layer PVX1 is formed. Therefore, during the patterning process of the touch signal line TL, the etching solution will not come into contact with the first signal transmission element 91 and the second signal transmission element 92.

[0108] This disclosure also provides a display panel. Figure 14 This is a schematic diagram of a display panel provided in some embodiments of this disclosure, such as... Figure 14 As shown, the display panel includes the display substrate and the cell substrate 100 described in the above embodiments. The display substrate and the cell substrate 100 are disposed opposite to each other. Additionally, the display panel may include a liquid crystal layer 200 located between the display substrate and the cell substrate 100. Specifically, the cell substrate 100 can be a color filter substrate, which includes a color filter layer and a black matrix 102 disposed on a substrate 101. The color filter layer includes multiple color filter sections 103, such as red, green, and blue filters, with each pixel area disposed opposite to one color filter section 103. The red pixel area mentioned above refers to the pixel area opposite to the red filter section, the green pixel area refers to the pixel area opposite to the green filter section, and the blue pixel area refers to the pixel area opposite to the blue filter section. The orthographic projection of the black matrix 102 onto the substrate 10 covers the gate lines, data lines DL, touch signal lines TL, and the orthographic projection of the thin-film transistors onto the substrate 10.

[0109] In one example, the width of the first slit 20a is between 3 and 7 μm, the overlap width between the orthographic projection of the touch signal line TL on the substrate 10 and the orthographic projection of the touch sub-electrode 21 on the substrate 10 is between 1.69 and 2.0 μm, and the width of the data line DL is between 4 and 6 μm. Since in this embodiment, the touch signal line TL can shield the electric field formed between the data line DL and the touch sub-electrode 21, preventing the electric field from affecting the liquid crystal deflection and causing light leakage, the width of the black matrix 102 does not need to be large. For example, the width of the black matrix 102 can be smaller than the width of the touch signal line TL.

[0110] This disclosure also provides a display device, including the display panel described in the above embodiments. The display device can be any product or component with display functionality, such as electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0111] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0112] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A display substrate, comprising: Substrate; Multiple data lines located on the substrate, the data lines extending along a first direction; A touch layer is located on the side of the layer containing the data line away from the substrate. The touch layer includes a plurality of touch electrodes configured to be reused as a common electrode. Each touch electrode includes a plurality of touch sub-electrodes electrically connected to each other. The touch sub-electrodes are arranged in an array along a first direction and a second direction. A first slit is formed between two adjacent touch sub-electrodes along the second direction. The orthographic projection of the first slit on the substrate overlaps with the orthographic projection of the data line on the substrate. The first direction and the second direction intersect. Multiple touch signal lines are located on the side of the touch layer away from the substrate. The touch signal lines are connected to the touch electrodes. The orthographic projection of at least one of the touch signal lines on the substrate covers the orthographic projection of the first slit on the substrate. The display substrate has a display area, which includes multiple pixel areas, and pixel electrodes are disposed in the pixel areas; a passivation layer is disposed on the side of the touch layer away from the substrate, and the touch signal line and the pixel electrode are both located on the side of the passivation layer away from the substrate; a protective layer is also disposed on the side of the touch signal line away from the substrate, the protective layer covers the touch signal line and is disposed in the same layer as the pixel electrode.

2. The display substrate according to claim 1, wherein, At least one of the touch signal lines overlaps with the orthographic projection of the touch sub-electrodes on both sides of the first slit onto the substrate.

3. The display substrate according to claim 2, wherein, The overlap width along the second direction between the orthographic projection of the touch signal line on the substrate and the orthographic projection of the touch sub-electrodes on both sides of the first slit is a first width, which is 1 to 1.2 times a first preset width D. Wherein, D1 is the maximum displacement fluctuation value in the manufacturing process of the touch signal line; D2 is the maximum single-sided size fluctuation value in the manufacturing process of the touch signal line; and D3 is the maximum single-sided size fluctuation value in the manufacturing process of the touch sub-electrode.

4. The display substrate according to claim 3, wherein, The first width is equal to D.

5. The display substrate according to claim 3, wherein, The first width is between 1.69 μm and 2.0 μm.

6. The display substrate according to any one of claims 2 to 5, wherein, The orthographic projection of each of the touch signal lines on the substrate covers the orthographic projection of the first slit on the substrate, and overlaps with the orthographic projections of the touch sub-electrodes on both sides of the first slit on the substrate.

7. The display substrate according to any one of claims 1 to 5, wherein, At least a portion of the data line and the touch layer are located in the display area. The display area is also provided with multiple gate lines. The multiple gate lines and the multiple data lines divide the display area into multiple pixel areas. The pixel electrode is located on the side of the touch layer away from the substrate. A second slit is provided on the pixel electrode.

8. The display substrate according to claim 7, wherein, A first passivation layer is disposed between the touch layer and the touch signal line, and a second passivation layer is disposed on the side of the layer where the touch signal line is located away from the substrate. The pixel electrode is disposed on the side of the second passivation layer away from the substrate.

9. The display substrate according to claim 8, wherein, The display substrate further has a peripheral region surrounding the display area, and the display substrate also includes components located in the peripheral region: The first signal transmission element is disposed on the same layer as the gate line; The second signal transmission component is disposed on the same layer as the data line; The connector is disposed on the same layer as the pixel electrode. The connector is connected to the first signal transmission component through a first via and to the second signal transmission component through a second via.

10. The display substrate according to claim 1, wherein, The orthographic projection of the protective layer on the substrate extends beyond the orthographic projection of the touch signal line on the substrate, and the width of the extended portion is 1 to 1.2 times the second preset width D'. Wherein, D1 is the maximum displacement fluctuation value in the manufacturing process of the touch signal line; D2 is the maximum single-sided size fluctuation value in the manufacturing process of the touch signal line; D4 is the maximum displacement fluctuation value in the manufacturing process of the protective layer; and D5 is the maximum single-sided size fluctuation value in the manufacturing process of the protective layer.

11. The display substrate according to claim 7, wherein, The display substrate further has a peripheral region surrounding the display area, and the display substrate also includes components located in the peripheral region: The first signal transmission element is disposed on the same layer as the gate line; The second signal transmission component is disposed on the same layer as the data line; A first connector and a second connector are stacked and connected together. The first connector is disposed on the same layer as the touch signal line. The first connector is connected to the first signal transmission element through a first via and to the second signal transmission element through a second via. The second connector is located on the side of the first connector away from the substrate and is disposed on the same layer as the pixel electrode.

12. The display substrate according to claim 11, wherein, The first connector and the second connector have their orthographic projections on the substrate coincide.

13. The display substrate according to any one of claims 1 to 5, wherein, The display substrate further includes: multiple common electrode lines, the common electrode lines being located between the touch layer and the substrate, and the touch electrodes being electrically connected to the common electrode lines.

14. The display substrate according to any one of claims 1 to 5, wherein, The touch signal line includes: a plurality of first line segments arranged along a first direction and a second line segment connected between two adjacent first line segments, wherein the orthographic projection of the first line segment on the substrate overlaps with the orthographic projection of the first slit on the substrate, and at least a portion of the orthographic projection of the second line segment on the substrate does not overlap with the orthographic projection of the first slit on the substrate. Each of the touch electrodes is connected to the second segment of a corresponding touch signal line.

15. The display substrate according to claim 14, wherein, Each of the touch electrodes is connected to a plurality of second segments of a corresponding touch signal line.

16. The display substrate according to claim 14, wherein, In the same touch electrode, one of the touch sub-electrodes in each row is connected to the touch signal line; two adjacent touch sub-electrodes in the same row are connected by a connecting part, and the connecting part and the touch sub-electrode are an integral structure.

17. The display substrate according to claim 14, wherein, The display substrate also includes multiple gate lines, and the orthographic projection of the second line segment on the substrate overlaps with the orthographic projection of the gate line on the substrate.

18. A display panel comprising a display substrate and a color filter substrate disposed opposite to each of claims 1 to 17.

19. A display device comprising the display panel of claim 18.

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