Enhanced global tagging for co-processors in synchronous processing systems

Abstract

Systems and methods for synchronizing enhanced global markers of a coprocessor. An example processor system includes a plurality of co-processors configured to compute processing tasks, where an individual co-processor is connected to individual remaining co-processors via a plurality of connections, where each connection from a co-processor to a different co-processor is configured to be asserted or de-asserted, the plurality of co-processors are configured to indicate a state associated with a global tag of the plurality of global tags, and wherein the global tag is set based on the plurality of co-processors asserting the global tag.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 336,718, filed on April 29, 2022, and entitled “ENHANCED GLOBAL FLAGS FOR SYNCHRONIZING COPROCESSORS INPROCESSING SYSTEM,” the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates to synchronizing processors, and more particularly to synchronizing processors using global flags. Background Art

[0004] As the foundation of modern software and hardware innovation, there is an increasing reliance on machine learning models such as neural networks. In fact, neural networks can be used for image analysis and classification techniques for recommendation engines used to enhance end-user content consumption. Some innovations may rely on the vast computing power provided by remote cloud systems. For example, machine learning processing can be offloaded to remote cloud systems so that the end-user's device may not require a complex neural network processor. These remote cloud systems can include specialized neural processors that can quickly perform forward passes through complex deep learning models.

[0005] However, other innovations may benefit from running on end-user devices. For example, an autonomous vehicle may include a dedicated graphics or neural processor that is capable of processing complex deep learning models using locally acquired sensor data (e.g., images). As another example, a user's smartphone may include a graphics or neural processor to perform image classification techniques locally. For this example, the smartphone may associate a person detected in an image captured by the smartphone with a specific person.

[0006] With the increased reliance on specialized processors, there is a need to enhance the operation and design of these processors to increase the speed at which they can compute machine learning models. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a block diagram illustrating an example processor system including multiple coprocessors and using global tags.

[0008] Figure 1B is a block diagram showing a coprocessor communicating with an operating system.

[0009] Figure 2A is a block diagram illustrating a shared mask that may be used to select a subset of coprocessors to use a global tag.

[0010] Figure 2B is a block diagram illustrating an example of selecting a subset of coprocessors to use a globally marked shared mask.

[0011] Figure 3 is a flow chart of an exemplary process for using global tags by an exemplary processor system.

[0012] Figure 4 is a block diagram illustrating an example vehicle including a processor system.

[0013] Embodiments of the present disclosure and their advantages may be best understood by reference to the following detailed description. It should be understood that the same reference numerals are used to identify the same elements shown in one or more of the accompanying drawings, wherein the display is for the purpose of illustrating embodiments of the present disclosure, rather than for limiting embodiments of the present disclosure. DETAILED DESCRIPTION

[0014] The present application describes techniques for synchronizing processors (e.g., coprocessors) included in a processing system. As an example, a coprocessor can be a neural processing unit that is capable of quickly performing operations associated with processing a neural network (e.g., computing a forward pass). As will be described, one or more inter-coprocessor tags (e.g., global tags) can be used to at least partially synchronize tasks performed by the coprocessor. Advantageously, these tags can be asynchronous to reduce the complexity, such as hardware or software complexity, required to achieve such synchronization of the coprocessors.

[0015] Embodiments of the processing systems described herein include multiple coprocessors to perform specialized processing, such as processing associated with a machine learning model (e.g., a neural network). Thus, one or more central processing units may at least partially offload processing associated with the neural network to these coprocessors. In some embodiments, there may be 3 coprocessors. In some embodiments, there may be 2, 5, 8, etc. coprocessors.

[0016] It will be appreciated that processing of a neural network may require considerable data and computer models. For example, for the example of an autonomous vehicle, a coprocessor may receive sensor data from multiple cameras or sensors positioned around the vehicle. In this example, the sensor data may be received at a particular frequency (e.g., 30 Hz, 60 Hz, etc.) and may be combined or otherwise aggregated for processing. With respect to a convolutional neural network, a volume of filters may be convolved with the received sensor data.

[0017] Due to the size of the data involved and / or the complexity associated with processing data at a particular frequency, a coprocessor may be assigned a portion of a processing task (e.g., a computational problem). For example, a first coprocessor may receive a portion of the data. In this example, the first coprocessor may therefore determine the processing result associated with the portion. Similarly, other coprocessors may determine the processing result associated with the remaining portion. These portions may then be aggregated or otherwise combined to determine the final processing result associated with the processing task. As another example, a first coprocessor may determine the processing result, and a second and third coprocessor may utilize the processing result in their own processing. Therefore, the second and third coprocessors may require techniques for them to receive information indicating the completion of the processing result.

[0018] A first example method of synchronizing coprocessors (such as synchronizing the processing tasks described above) may rely on software synchronization techniques. For example, software synchronization may be used with interrupts to control a central processing unit (CPU). However, this first example method is cumbersome; particularly if the controlling CPU runs a full operating system rather than a microkernel. For example, interrupt latency may cause communication of dependencies between coprocessors to slow down.

[0019] In order to ensure the appropriate synchronization of the above-mentioned coprocessors, while limiting the degree of additional hardware and / or software complexity, the application describes the use of global tags. Each coprocessor can be connected to the remaining coprocessors, for example, via asynchronous connections or wires. In some embodiments, this can be referred to as an all-to-all connection between coprocessors. As will be described, there can be multiple connections (e.g., 'N' connections) between each processor and the individual remaining processors. With regard to the example of N connections, there can be N tags that can be set by the coprocessor.

[0020] For example, with respect to the first flag, each coprocessor may assert the first flag. A coprocessor may work on a problem that is too large for a single coprocessor to work on. Due to interdependencies between data or operations, these coprocessors may have to complete their respective computational portions associated with the problem. In some embodiments, asserting the first flag may indicate that the coprocessors have completed their respective computational portions. For example, asserting the first flag may indicate that the coprocessor has completed an intermediate result. The first flag may then be cleared (e.g., deasserted) to indicate that another actor (e.g., another coprocessor, a central processing unit) has successfully received (e.g., copied out) the intermediate result.

[0021] In some embodiments, asserting the first flag may indicate that the coprocessor has initiated work on its corresponding computational portion. Once completed, the coprocessor may then de-assert the first flag.

[0022] With respect to asserting the first flag described above, each coprocessor may assert the first flag asynchronously. As described above, the coprocessors may be connected to each other such that each coprocessor receives the asserted first flag from all remaining coprocessors. The assertion by a coprocessor may represent, for example, the setting of a value (e.g., a logical 1) on an asynchronous wire connected to another coprocessor.

[0023] Thus, these tags may represent an enhanced and structurally simplified extension of dependency tags, which may be used for local data dependencies, as an example. Thus, the tags may be extended to the hardware of the coprocessor by using wires connecting the coprocessor. In this way, the coprocessor may separate and manipulate complex issues when considering data dependencies.

[0024] In some embodiments, a central processing unit (CPU) may form part of the tag assertion technique described herein. As an example, the CPU may receive from a coprocessor and send to the coprocessor. For example, the CPU may assert the first tag described above. In this example, the CPU may write the assertion to a first register (e.g., a control register) that is routed to the coprocessor. In addition, the CPU may read from a second register (e.g., an interrupt register) to identify the state of the first tag as asserted or de-asserted by the coprocessor. In the present application, the state may indicate whether the first tag has been asserted or de-asserted. In this way, the CPU may identify the state associated with the processing task separated between the coprocessors. In addition, the CPU may assert one or more tags based on the processing task being performed by the CPU. For example, the CPU may be used to extract data from a memory. In this example, the CPU may assert one or more tags when completing a memory extraction.

[0025] block diagram

[0026] Figure 1A 1 is a block diagram illustrating an example processor system 100 including multiple coprocessors 102A-102C and using global tags 104A-104C. In the illustrated embodiment, the coprocessors 102A-102C may represent neural processing units. However, in some embodiments, the coprocessors 102A-102C may be used to perform any operations associated with breaking down one or more computational problems into smaller blocks or fragments. Figure 1A Three coprocessors 102A-102C are shown in FIG. 1 , but in some embodiments there may be 5, 6, 8, etc. coprocessors.

[0027] In some embodiments, the processor system 100 may represent a system included in a vehicle. For example, the processor system 100 may be used at least in part to perform autonomous or semi-autonomous driving of a vehicle. In this example, the processor system 100 may acquire sensor data from sensors (e.g., image sensors) positioned around the vehicle. The sensor data may then be analyzed, for example, using one or more machine learning models. At least a portion of the processing of the machine learning model may be implemented via coprocessors 102A-102C.

[0028] As shown, coprocessor A 102A is connected to coprocessor B 102B and coprocessor C 102C via a plurality of connections. As an example, a portion of the connections between coprocessor A 102A and coprocessor B 102B represent connections for a plurality of flags (e.g., A flag 104A) that may be asserted or deasserted by coprocessor A 102. Similarly, a portion of the connections between coprocessor A 102A and coprocessor C 102C represent connections for A flag 104A.

[0029] Thus, each coprocessor may assert or deassert multiple flags. For example, coprocessor A 102A may control the state of A flag 104A. As another example, coprocessor B 102B may control the state of B flag 104B. As another example, coprocessor C 102C may control the state of C flag 104C. Together, these flags 104A-104C form a plurality of flags that may be asserted or deasserted by coprocessors 102-102C. For example, there may be 3 flags, 5 flags, 9 flags, 15 flags, etc. In this example, and with respect to the 3 flags, A flag 104A may represent the state of each of the flags asserted or deasserted by coprocessor A 102A. B flag 104B may represent the state of each of the flags asserted or deasserted by coprocessor B 102B. C flag 104C may represent the state of each of the flags asserted or deasserted by coprocessor C 102C.

[0030] In this way, the coprocessors may collectively utilize multiple tags to represent different data dependencies, processing dependencies, times when the coprocessors have collectively completed corresponding computations associated with a computational task or problem, and the like. In some embodiments, the tag is set (e.g., enabled) if all coprocessors 102A-102C have asserted the tag. With respect to the first tag, the first tag may be set if coprocessor A 102A has asserted the first tag (e.g., included in A tags 104A) and coprocessor B 102B has asserted the first tag (e.g., included in B tags 104B) and coprocessor C 102C has asserted the first tag (e.g., included in C tags 104C). Since the coprocessors 102A-102C are connected to each other, for example, via asynchronous wires, each coprocessor may receive information indicating assertion of the first tag from the remaining coprocessors.

[0031] It will be appreciated that the first flag may be set based on instructions executed by the coprocessor 102A-102C. For example, the software instructions may be associated with a computing task. In this example, the computing task may be separated into partial operations or subtasks. As an example, a compiler may perform the separation, or the separation may be performed substantially in real time during operation of the processor system 100. For some computing tasks, there may be data dependencies introduced when the tasks are separated.

[0032] For example, there may be data processed by coprocessors 102A-102C that is subsequently used to determine a processing result. Thus, the processing result depends on the processing being performed by each coprocessor. With respect to the first tag described above, coprocessors 102A-102C may assert the first tag when completing their respective processing. Thus, the first tag may be associated with determining a processing result. Similarly, other tags may be associated with other data dependencies. Thus, the coprocessors may ensure that data dependencies, data movement, etc. are constrained based on the tags.

[0033] In some embodiments, when all coprocessors 102A-102C de-assert the flag, the flag may be de-asserted. For example, for the first flag described above, the coprocessors 102A-102C may de-assert the first flag after removing the dependency associated with the first flag. As described above, example dependencies may be related to data dependencies, process dependencies, etc.

[0034] As another example, there may be a computing task (e.g., a workload) that has a large working set at the beginning, but then gradually decreases to a smaller working set toward the end. This computing task may be started on coprocessors 102A-102C, where each coprocessor obtains approximately 1 / 3 of the input data. Subsequently, for example, during approximately the middle of the computing task, as the size of the working set decreases, each coprocessor may assert a global flag. Since in some embodiments, the coprocessors may not operate in lockstep, each coprocessor may assert the global flag at a different time. For example, a particular coprocessor may have different programs that wait for the global flag to be true. In this example, once the global flag is set (e.g., asserted by all coprocessors), all coprocessors will have reached the same point.

[0035] The specific coprocessor may then fetch (e.g., direct memory access) the corresponding intermediate results from the remaining coprocessors into its own local memory. The specific coprocessor may then deassert its global flag, or set a different global flag, to indicate to the remaining coprocessors that it has successfully copied the data, and the remaining coprocessors may terminate their workloads based on the flag change, and optionally receive new workloads (e.g., from a task scheduler). The specific coprocessor may continue the remaining portion of the workload on its own until completion.

[0036] Figure 1B 1 is a block diagram showing coprocessors 102A-102C communicating with operating system 110. Figure 1A As shown, coprocessors 102A-102C can control the state of multiple flags. For example, each coprocessor can assert or deassert a flag to collectively cause the flag to be set (e.g., enabled) or de-set (e.g., disabled). In some embodiments, operating system 110 being executed by processor system 100 can allow central processing unit 120 to participate in setting or de-setting a flag.

[0037] In the illustrated example, the operating system 110A routes the state of the flag to the coprocessors 102A-102C. For example, the central processing unit 120 may assert or deassert the flag based on a write to one or more control registers. In this example, the central processing unit 120 may interface with control registers that are mapped to global physical addresses at the system level. Therefore, the operating system 110 may provide information from these control registers to the coprocessors 102A-102C.

[0038] Similarly, the operating system 110 may route the state of a tag as set or unset by the coprocessor 102A-102C via one or more interrupts. For example, the central processing unit 120 may receive the state via one or more interrupt registers. In this example, the coprocessor 102A-102C may provide information read by the central processing unit 120 via these interrupt registers. Alternatively, the central processing unit 120 may request the state of the tag from the coprocessor 102A-102C. For example, the central processing unit 120 may request the state, in contrast to the coprocessor 102A-102C providing an interrupt based on asserting or unasserting a tag. In response, the operating system 110 may provide information about the state to the central processing unit 120. In some embodiments, the coprocessor 102A-102C may provide an interrupt when any change occurs to the tag. For example, if the coprocessor 102A-102C asserts a tag together, the assertion may cause an interrupt to be triggered to the central processing unit 120.

[0039] In this way, the central processing unit 120 can engage with the coprocessor 102A-102C to assert the tag. Therefore, the central processing unit 120 can participate in ensuring that the dependency is enforced. For example, one or all of the coprocessors 102A-102C may need data for processing a computing task. In this example, the central processing unit 120 can extract data and indicate the completion of the extraction via one of the asserted tags. Without being limited by the example, as can be understood, there may be many computing tasks involving the central processing unit 120. For example, the central processing unit 120 can obtain sensor data at a threshold frequency from multiple sensors used by the coprocessor each time. In this example, the coprocessor can obtain data after the central processing unit 120 completes the acquisition process. For example, the central processing unit 120 can assert a tag read by the coprocessor (e.g., via a control register). The coprocessor can also assert the tag when completing its task (e.g., processing the acquired data). Therefore, the central processing unit 120 can set and unset the tag according to the technology described herein.

[0040] Figure 2A2 is a block diagram illustrating a shared mask 204 that may be used to select a subset of coprocessors 102A-102C to use a global tag 202. In the illustrated example, a representation of the global tag 202 is included. Each of the global tags 0-N is represented as a column, where each row of the column corresponds to one of the coprocessors 206 or the operating system 208. Thus, each coprocessor may assert or deassert each of the 0-N tags 202. As described above, in some embodiments, if all coprocessors and optionally an operating system (e.g., a central processing unit) assert the tag, the tag may be indicated as being set. Similarly, in some embodiments, if all coprocessors (and optionally an operating system) deassert the tag, the tag may be indicated as being unset.

[0041] Figure 2A Also shown is a tag mask 204 that may be shared with the coprocessors 102A-102C and the operating system 208. The tag mask 204 may be used to indicate which of the coprocessors 102A-102C and optionally the operating system 208 will be involved in tagging. For example, a particular computing task or series of tasks may utilize the global tags 0-N 202. In this example, there may be multiple dependencies of different tags that need to be enforced by the coprocessors 102A-102C and optionally the operating system 208. These dependencies may involve only a subset of the coprocessors 102A-102C and the operating system 208, such that the tag mask 208 may remove one or more actors (e.g., coprocessors, operating system) from enforcing the global tags.

[0042] In some embodiments, the tag mask 204 can be provided via a central processing unit. For example, a process scheduler can run on a central processing unit. In this example, the central processing unit can set the tag mask 204 (e.g., as described above) via one or more control registers written to the coprocessor.

[0043] Although the marking mask 204 is Figure 2A 202, but it is understood that there may be more than one tag mask. For example, each global tag or a subset of global tags may have a flask mask that identifies which of the coprocessors and optionally the operating system 208 are associated with the global tag or a subset of global tags.

[0044] Figure 2B is a block diagram illustrating an example of selecting a subset of coprocessors to use a globally marked shared mask 208. Figure 2BIn the embodiment, when the coprocessor 102C is not used, the coprocessors 102A-102B will be used for a specific computing task or a series of tasks. For example, the coprocessor 102C may be performing other computing tasks or not performing tasks.

[0045] Thus, the tag mask 208 may include a logical 1 for coprocessors 102A-102B and the operating system 208. The tag mask may include a logical 0 for coprocessor C 102C. In this way, the coprocessors 102A-102B and the operating system 208 may obtain information identifying that coprocessor C 102C is not associated with the global tag 202.

[0046] Example Flowchart

[0047] Figure 3 is a flow chart of an exemplary process 300 for using global tags by an exemplary processor system. For convenience, process 300 is described as being performed by a processor system (eg, processor system 100).

[0048] At block 302, a processor system receives a computing task. As described, the computing task may involve processing or training of one or more machine learning models (e.g., neural networks). For example, a machine learning model may be used to determine information that may be used to enable autonomous or semi-autonomous driving of a vehicle. The computing task may include one or more operations that are separated into subtasks or operations to be performed by multiple coprocessors (e.g., neural processing units).

[0049] At block 304, the processor system associates the dependency with one or more global tags. A computing task may have one or more dependencies, such as data or processing dependencies, that are mandatory for the computing task to be completed. For example, each coprocessor may need to compute certain information that is then aggregated or combined to form a processing result. Thus, in this example, the coprocessors may need a technique by which the coprocessors can indicate when certain dependencies are complete.

[0050] Thus, each tag can be associated with a dependency. When coprocessors complete certain tasks, they can assert one or more global tags to indicate the completion of those tasks. Figure 1A-1B As described, the coprocessors may have full-to-full connectivity with each other (eg, via asynchronous wires). In this way, each coprocessor may identify flags being asserted by the remaining coprocessors.

[0051] In some embodiments, after assertion of a flag that may indicate completion or removal of a particular dependency, the coprocessor may perform subsequent processing. For example, an operation for computing a computational task may require that a particular dependency be completed before performing additional operations. In this example, the coprocessor may therefore assert a particular flag to indicate that an additional operation is to be performed.

[0052] At block 306, the processor system causes execution of operations associated with the computing task. As described above, the coprocessor may perform operations to work toward completing the computing task. These operations may have data or processing dependencies, causing the coprocessor to assert or deassert flags to indicate when such dependencies are completed.

[0053] Although Figure 3 describes the use of a coprocessor assertion or deassertion global flag, but as Figure 1B As described in , an additional processor (e.g., a central processing unit) can assert or deassert a global flag. For example, the central processing unit can fetch data from a storage device for use by one or more coprocessors. In this example, the central processing unit can assert a specific flag when fetching data. In addition, as Figure 2A-2B As described in , a shared mask can be used to indicate which coprocessors will be involved in asserting or deasserting a global flag.

[0054] With respect to the central processing unit, as an example of using a tag, the central processing unit may synchronize with another processor that may not have a global tag. For example, the other processor may be a graphics processing unit (GPU). For example, when processing a lengthy neural network, there may be (multiple) operations during the neural network that require the GPU to process information. For this example, a coprocessor (e.g., a neural processor) may not have features associated with the (multiple) operations. Therefore, when the coprocessor completes an intermediate result, a global tag may be used to notify the central processing unit. The central processing unit can then start a GPU task that can safely assume that its input data (e.g., intermediate results) is ready at a known location. Then, when the GPU finishes, the central processing unit can set a global tag that indicates that the coprocessor can resume processing the neural network and it can safely assume that the result of the function is available at a known location.

[0055] Vehicle Block Diagram

[0056] Figure 4 A block diagram of a vehicle 400 (e.g., vehicle 102) is shown. Vehicle 400 may include one or more electric motors 402 that cause vehicle 400 to move. Electric motor 402 may include, for example, an induction motor, a permanent magnet motor, etc. As known to those skilled in the art, battery 404 (e.g., one or more battery packs each including a plurality of cells) may be used to power electric motor 402.

[0057] Vehicle 400 also includes a propulsion system 406 that can be used to set a gear (eg, a direction of propulsion) for the vehicle. With respect to electric vehicles, propulsion system 406 can adjust the operation of electric motor 402 to change the direction of propulsion.

[0058] In addition, the vehicle includes a matrix processor system 100 configured to perform matrix multiplication using a convolution engine (e.g., matrix processor 110). The matrix processor system 100 can process data, such as images received from image sensors (e.g., cameras) positioned around the vehicle 400. The matrix processor system 100 can also output information to a display 408 included in the vehicle 400 and receive information (e.g., user input) from a display 408 included in the vehicle 400.

[0059] Other embodiments

[0060] All processes described herein can be implemented and fully automated via software code modules executed by a computing system including one or more computers or processors. The code modules can be stored in any type of non-transitory computer-readable medium or other computer storage device. Some or all of the methods can be implemented in dedicated computer hardware.

[0061] According to the disclosure, many other changes except those described herein will be apparent.For example, according to an embodiment, some actions, events or functions of any algorithm described herein can be performed in different orders, or can be added, merged or completely omitted (for example, not all described actions or events are necessary for the practice of the algorithm). In addition, in certain embodiments, actions or events can be performed concurrently rather than sequentially, for example, by multithreading, interrupt processing or multiple processors or processor cores or on other parallel architectures. In addition, different tasks or processes can be performed by different machines and / or computing systems that can act together.

[0062] The various illustrative logic blocks, modules, and engines described in conjunction with the embodiments disclosed herein may be implemented or executed by a machine designed to perform the functions described herein, such as a processing unit or processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The processor may be a microprocessor, but in an alternative, the processor may be a controller, a microcontroller, or a state machine, or a combination thereof, etc. The processor may include a circuit system configured to process computer executable instructions. In another embodiment, the processor includes an FPGA or other programmable device that performs logic operations without processing computer executable instructions. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a combination of multiple microprocessors, a combination of one or more microprocessors and a DSP core, or any other such configuration. Although primarily described herein for digital technology, the processor may also primarily include analog components. For example, some or all of the signal processing algorithms described herein may be implemented in an analog circuit system or a mixed analog and digital circuit system. The computing environment may include any type of computer system, including but not limited to a microprocessor-based computer system, a mainframe computer, a digital signal processor, a portable computing device, a device controller, or a computing engine within an appliance, etc.

[0063] Unless otherwise specifically stated, conditional language such as "may," "can," "might," or "could" is understood in the context to be generally used to express that some embodiments include and other embodiments do not include certain features, elements, and / or steps. Thus, such conditional language is generally not intended to imply that one or more embodiments require features, elements, and / or steps in any way, or that one or more embodiments must include logic for deciding, with or without user input or prompting, whether such features, elements, and / or steps are included or to be performed in any particular embodiment.

[0064] Unless expressly stated otherwise, disjunctive language, such as the phrase "at least one of X, Y, or Z," is understood along with the context to be generally used to indicate that an item, term, etc. may be X, Y, or Z, or any combination thereof (e.g., X, Y, and / or Z). Thus, such disjunctive language is generally not intended to, and should not, imply that certain embodiments require that at least one of X, at least one of Y, or at least one of Z each be present.

[0065] Any process description, element or block in the flowcharts described herein and / or depicted in the accompanying drawings should be understood to potentially represent a module, segment or portion of code including one or more executable instructions for implementing a specific logical function or element in the process. Alternative implementations are included within the scope of the embodiments described herein, where elements or functions may be deleted, executed from the order shown or discussed, including substantially simultaneously or in reverse order, depending on the functions involved as will be understood by those skilled in the art.

[0066] Unless expressly stated otherwise, articles such as "a" or "an" should generally be interpreted as including one or more of the described items. Thus, a phrase such as "a device configured to..." is intended to include one or more of the described devices. Such one or more recited devices may also be configured together to perform the recited statements. For example, "a processor configured to perform statements A, B, and C" may include a first processor configured to perform statement A, working in conjunction with a second processor configured to perform statements B and C.

[0067] It should be emphasized that many changes and modifications may be made to the above-described embodiments, and the elements of these embodiments should be understood to be among other acceptable examples. All such modifications and changes are intended to be included within the scope of the present disclosure.

Claims

1. A processor system, comprising: a plurality of coprocessors configured to compute processing tasks, wherein individual coprocessors are connected to individual remaining coprocessors via a plurality of connections, wherein each connection from a coprocessor to a different coprocessor is configured to be asserted or de-asserted by the coprocessor to indicate a state associated with a global tag of a plurality of global tags, And wherein the global flag is set based on the plurality of coprocessors asserting the global flag.

2. The processor system of claim 1, wherein the coprocessor is a neural processing unit.

3. The processor system of claim 1, wherein each global tag is associated with a dependency. 4 . The processor system of claim 3 , wherein asserting a particular global tag indicates removal of a particular dependency. 5 . The processor system of claim 4 , wherein a specific operation associated with the processing task is initiated based on the removal of the specific dependency.

6. The processor system of claim 1, wherein the plurality of connections are asynchronous conductors.

7. The processor system of claim 1, wherein the coprocessors utilize a shared mask, and wherein the shared mask indicates which of the coprocessors are to be included in asserting or deasserting the global flag.

8. The processor system of claim 1, wherein the processor system communicates with a central processing unit via an operating system, and wherein the central processing unit is configured to assert or deassert the flag.

9. The processor system of claim 8, wherein the global flag is set based on the plurality of coprocessors and the central processing unit asserting the global flag.

10. The processor system of claim 8, wherein the central processing unit is configured to write a status of the global flag to a control register, and wherein the operating system routes the status to the coprocessor.

11. The processor system of claim 1, wherein the processing task is associated with a plurality of operations, and wherein the operations are associated with a plurality of dependencies associated with the global tag.

12. A method implemented by a processor system, the method comprising: receiving a computing task, wherein the computing task is configured to be completed via a plurality of coprocessors included in the processor system, wherein an individual coprocessor is connected to an individual remaining coprocessor via a plurality of connections, and wherein the computing task is associated with a plurality of dependencies; associating the individual dependency with an individual global tag from a plurality of global tags, wherein each connection from a coprocessor to a different coprocessor is configured to be asserted or deasserted by the coprocessor to indicate a state associated with the individual global tag, and wherein the individual global tag is set based on assertion of the individual global tag by the plurality of coprocessors; as well as Execution of operations associated with the computing task is caused by the coprocessor.

13. The method of claim 12, wherein the coprocessor is a neural processing unit.

14. The method of claim 12, wherein the plurality of connections are asynchronous conductors.

15. The method of claim 12, wherein the coprocessors utilize a shared mask, and wherein the shared mask indicates which of the coprocessors are to be included in asserting or deasserting the global flag.

16. The method of claim 12, wherein the processor system communicates with a central processing unit via an operating system, and wherein the central processing unit is configured to assert or deassert the flag.

17. The method of claim 16, wherein the global flag is set based on the plurality of coprocessors and the central processing unit asserting the global flag.

18. The method of claim 16, wherein the central processing unit is configured to write a status of the global flag to a control register, and wherein the operating system routes the status to the coprocessor.

19. The method of claim 12, wherein asserting a particular global flag indicates removal of a particular dependency.

20. The method of claim 19, wherein a specific operation associated with the processing task is initiated based on the removal of the specific dependency.

Images