Memory architecture

Abstract

A memory includes: a memory cell array; memory access logic programmable to generate a write allocation to map an input including data elements in a first order to memory cells of the array and a read allocation to map memory cells of the array to an output including data elements in a second order; and a memory controller arranged to write the data elements at the input to the array based on the write allocation and read the data elements stored in the array to the output based on the read allocation.

Description

Technical Field

[0001] The present disclosure relates to a memory, and is particularly, but not exclusively, applicable to methods and apparatus for programmable non-random access memory arrays that can provide cell-based memory reading and writing. Background Art

[0002] In intensive computational applications such as fully homomorphic encryption, Fourier transforms, and artificial intelligence, memory architecture is critical to reducing latency.

[0003] Data stored in random access memory (RAM) is usually stored in rows, and read / write operations are usually performed on a whole row of data (composed of multiple columns). Data throughput from RAM can be affected by read / write conflicts, also known as non-repeatable reads or read uncommitted data. Uncommitted data is data that is being updated but not yet permanently committed back to the database. In other words, it is data that is being updated but not yet permanently updated. In memory architectures, read / write conflicts occur when a read operation and a write operation are attempted at the same location in memory at the same time, so the value written by the write operation makes the database inconsistent compared to the value read by the read operation. This can reduce the processing rate of intensive computing tasks. Many traditional computer architectures are limited by having fast processing power but slow memory access, which is the so-called von-Neumann bottleneck.

[0004] Register memory is a fast memory that is usually used to buffer data. However, the capacity of register memory is limited. Therefore, register memory is generally only used to store commonly used data, instructions, and memory addresses for easy access. Summary of the invention

[0005] The invention is defined by the appended independent claims.

[0006] This summary introduces some concepts that are described in greater detail in the detailed description. This concept should not be used to identify essential features of the claimed subject matter, nor should it be used to limit the scope of the claimed subject matter.

[0007] The present disclosure describes a hybrid memory architecture that allows data to be stored discontinuously at any memory cell location, which is programmed and synchronized using a state machine controller and a write state counter. Similarly, data can also be read from any memory cell location, which is determined using a similar program and synchronized by another state machine controller and a read state counter. A state machine controller is a controller that can be under a finite number of different conditions, where a state machine is a behavioral model that can be called a finite state machine (FSM). The memory architecture also includes in-memory compute logic that allows simple arithmetic operations (such as addition, binary complement conversion, increment, decrement, and bit shift) and logical operations (such as AND, OR, XOR, NOR, NAND) to be performed on data. The in-memory compute logic allows arithmetic and logical operations to be performed on data stored in memory cells, and reduces latency.

[0008] The present disclosure provides a memory, which includes: a memory cell array; memory access logic that is programmable to generate write allocations that map inputs containing data elements to memory cells of the array and read allocations that map memory cells of the array to outputs containing data elements; and a memory controller that is arranged to write data elements at the input to the array based on the write allocations and read data elements stored in the array to the outputs based on the read allocations.

[0009] Thus, a memory is provided, comprising: an array of memory cells; memory access logic programmable to generate write allocations that map inputs comprising data elements in a first order to memory cells of the array, and read allocations that map memory cells of the array to outputs comprising data elements in a second order; and a memory controller arranged to write data elements at the input to the array based on the write allocations, and to read data elements stored in the array to the output based on the read allocations.

[0010] Optionally, the first order is different from the second order, such that the first order sequence of data elements at the input is different from the second order sequence of data elements at the output.

[0011] Optionally, the input is a parallel input of a first width, and the output is a parallel output of a second width, wherein preferably, the first width is the same as the second width.

[0012] Optionally, the memory access logic is configured to be reprogrammable to generate different write allocations and read allocations.

[0013] Optionally, the data elements at the input and at the output are one of: a single bit of a data word or a multi-bit word of a data string.

[0014] Optionally, the most significant bit or word to the least significant bit or word of each single-bit word or multi-bit word is mapped to the input in parallel, or read to the output in parallel.

[0015] Optionally, the write allocation maps inputs to a respective first subset of memory cells of the array in a first subset order and the read allocation reads a respective second subset of memory cells to outputs in a second subset order.

[0016] Optionally, each first subset comprises a respective first arrangement of memory cells of the array and each second subset comprises a respective second arrangement of memory cells of the array.

[0017] Optionally, each respective first arrangement is different from each respective second arrangement.

[0018] Optionally, a width of each first arrangement is equal to a first width of the input and a second width of the output.

[0019] Optionally, the widths of the first arrangement and the second arrangement are respectively equal to the first width of the input and the second width of the output.

[0020] Optionally, the first subset order is different from the second subset order.

[0021] Optionally, each first subset comprises a row or a column of memory cells of the array.

[0022] Optionally, each first subset comprises a row of memory cells of the array.

[0023] Optionally, each first subset comprises a column of memory cells of the array.

[0024] Optionally, each second subset comprises a row or a column of memory cells of the array.

[0025] Optionally, each second subset comprises a row of memory cells of the array.

[0026] Optionally, each second subset comprises a column of memory cells of the array.

[0027] Optionally, each first subset of the array's memory cells is adjacent such that inputs are mapped to the corresponding first subset of the array's adjacent memory cells, and each second subset of the array's memory cells is adjacent such that outputs are read from the corresponding second subset of the array's adjacent memory cells.

[0028] Optionally, each single-bit word or multi-bit word is mapped to a respective first subset of adjacent memory cells of the array, and each single-bit word or multi-bit word is read to an output from a respective second subset of adjacent memory cells of the array.

[0029] Optionally, the second subset order of the memory cells of the array that are read to the output is a predetermined shift of the first subset order of the memory cells of the array.

[0030] Optionally, the second subset order of the memory cells of the array that is read to the output is a rotation of the first subset order of the memory cells of the array.

[0031] Optionally, the first subset order is a butterfly transpose of the data elements at the input.

[0032] Optionally, each respective first subset of memory cells of the array and each respective second subset of memory cells of the array comprises at input at least one single bit from each data word or at least one multi-bit word from each data string.

[0033] Optionally, each row memory cell or each column memory cell of the array of the first subset comprises a plurality of multi-bit words of one of a plurality of data strings at the input, and wherein each corresponding second subset of memory cells of the array comprises at the input at least one multi-bit word from each of the plurality of data strings.

[0034] Optionally, the memory access logic includes read logic and write logic, wherein the read logic generates read allocations and the write logic generates write allocations.

[0035] Optionally, the memory access logic includes: a read state controller and a write state controller.

[0036] Optionally, the memory further comprises a memory interface configured to transfer data elements at the input to the memory cells of the array and to transfer data elements stored in the memory cells of the array to the output.

[0037] Optionally, the memory interface comprises a read data bus and a write data bus, wherein the read data bus and the write data bus are configured to transmit instructions for programming the memory access logic to the memory access logic.

[0038] Optionally, the read data bus and the write data bus are further configured to provide a read counter, a write counter and a status control for the memory access logic.

[0039] Optionally, the read state controller and the write state controller are configured to use the read counter and the write counter and the state to set, reset, read or write both data and sequence counters within the memory access logic.

[0040] Optionally, the memory further comprises a data distributor switch structure configured to connect the memory unit with the memory access logic and the memory controller.

[0041] Optionally, the data distributor switch structure includes a switch structure, a read data distributor and a write data distributor, wherein the read data distributor and the write data distributor are configured to decode an address of the array corresponding to the read distribution or the write distribution.

[0042] Optionally, the switch fabric is mapped to the bus size according to the bit number of individual data.

[0043] Optionally, the memory cells of the array are divided into a first memory cell subset and a second memory cell subset; the input comprises a first input frame and a second input frame; the first input frame comprises a first data element and a second data element; the second input frame comprises a third data element and a fourth data element.

[0044] Optionally, the write allocation maps: a first data element to a first memory cell in a first subset of memory cells; a second data element to a first memory cell in a second subset of memory cells; a third data element to a second memory cell in the first subset of memory cells; and a fourth data element to a second memory cell in the second subset of memory cells.

[0045] Optionally, the transformation relationship between the positions of the first memory cell and the second memory cell in the first memory cell subgroup corresponds to or is identical to the transformation relationship between the positions of the first memory cell and the second memory cell in the second memory cell subgroup.

[0046] Optionally, the transformation relationship is a translation relationship or a rotation relationship, and optionally, wherein the transformation relationship is a rotation or translation from one memory unit to an adjacent memory unit through a single memory unit.

[0047] Optionally, the order of the first data elements in the first input frame corresponds to the order of the third data elements in the second input frame, and the order of the second data elements in the first input frame corresponds to the order of the fourth data elements in the second input frame.

[0048] Optionally, the read allocation maps memory cells of the array to outputs comprising a first output frame (which comprises the first data element and the third data element) and a second output frame (which comprises the second data element and the fourth data element).

[0049] Optionally, the order of the first data elements in the first output frame corresponds to the order of the second data elements in the second output frame.

[0050] Optionally, the order of the third data elements in the first output frame corresponds to the order of the fourth data elements in the second output frame.

[0051] Optionally, the first input frame and the second input frame each comprise data corresponding to light intensity values ​​detected at an output plane of the optical Fourier transform stage.

[0052] Optionally, each of the first data element and the second data element corresponds to a light intensity value detected at a port in a port array at an output plane of the optical Fourier transform stage, wherein each of the third data element and the fourth data element corresponds to a light intensity value detected at a port in a port array at an output plane of the same or another optical Fourier transform stage.

[0053] Optionally, the relative order of the first data element and the second data element in the first input frame and the relative order of the third data element and the fourth data element in the second input frame respectively correspond to the relative positions of the ports in the port array at the output plane in the corresponding optical Fourier transform stage, optionally, wherein the relative order is adjacent positions or subsequent positions in the sequence and the relative positions are adjacent positions in the port array.

[0054] Optionally, the first data element corresponds to a first detected intensity at a first port in the array of ports at an output plane of the optical Fourier transform stage, and the third data element corresponds to a second detected intensity at the first port.

[0055] Optionally, the second data element corresponds to a third detection intensity at a second port in the port array, and the fourth data element corresponds to a fourth detection intensity at the second port.

[0056] A method is also provided, the method comprising: generating a write allocation and a read allocation in memory access logic, the write allocation mapping inputs to memory cells of a memory cell array in a first order, and the read allocation mapping memory cells of the array to outputs in a second order; writing data elements at the input to the array based on the write allocation; and reading data elements stored in the array to the output based on the read allocation. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The following is a description of specific embodiments by way of example only, with reference to the accompanying drawings:

[0058] Figure 1A-1B is an example of using the butterfly transpose to reposition data;

[0059] Figure 2 is an example of using rotation to reposition data;

[0060] Figure 3 is an example of using shifting to reposition data;

[0061] Figure 4 A memory including key features is shown;

[0062] Figure 5A-Figure 5B are example embodiments of a memory architecture and memory access logic;

[0063] Figure 6 are example embodiments of a memory architecture and memory access logic;

[0064] Figure 7 is an example state diagram of a memory architecture; and

[0065] Figure 8A-8B are examples of reading and writing data to memory.

[0066] In the drawings, like reference numerals refer to like parts. DETAILED DESCRIPTION

[0067] Data reordering or data transposition is very useful in intensive computing, such as fully homomorphic encryption (FHE), Fourier transform (FT), and convolutional neural network (CNN) based on artificial intelligence (AI) operations. Using existing memory architectures, data needs to be moved multiple times or kept in expensive register memories to facilitate data reordering or transposition needs. In addition, with the emergence of optical and photonic computing (in which photons are used to perform mathematical operations), memory access and latency become more important due to the inherently fast operations of optical and photonic computing.

[0068] The Optical Fourier Transform (OFT) can compute one Fourier transform in a single clock cycle. In order to compute large Fourier transforms of arbitrary dimensions and precision, the native OFT data needs to be reordered or transposed in memory. Performing such operations in traditional (SRAM / DRAM / cache or register) memory requires multiple data shifts and multiple data reads and writes. For high-performance computing applications and workflows, this is a large bottleneck and introduces latency, which reduces the overall performance of the computation. Data transposition in data shifts is particularly common in systems where processing speed is much faster than memory access speed, such as optical computing. In such systems, processing speed is limited by memory access speed.

[0069] exist Figure 1A-Figure 3In each of the example memory architectures, the inputs may be parallel inputs of a first width and the outputs may be parallel outputs of a second width. The width of the input or output refers to the number of bits or words. The write allocation maps the inputs to a corresponding first subset of memory cells of the array in a first subset order, and the read allocation reads a corresponding second subset of memory cells to the outputs in a second subset order. Figure 1A-Figure 3 , the first subset order is different from the second subset order.

[0070] In OFT, the native FT data needs to be fragmented, reordered or transposed and written to the memory. The native FT data may be referred to as input, or data element, or data element in first order, or frame, or native FT frame, which consists of FT of a given size, which may be one-dimensional (1D) or two-dimensional (2D) and is determined by the native resolution of the photonic core of the photonic device in use. An example of data reordering is Figure 1AAs shown in , where the input 110, input 111 includes data elements in a first order, or in other words, the native FT frame 110, native FT frame 111 includes a plurality of data points. A plurality of native FT frames 100, native FT frames 101 (write frame 1, ..., write frame N) are successively reordered or transposed according to a predefined mapping. The predefined mapping is programmed by a memory access logic, which generates a write allocation and a read allocation. The write allocation maps the input 110, input 111 (or the native FT frame 110, native FT frame 111 containing a plurality of data points) including the data elements in the first order to the memory cells of the array 120, and the read allocation maps the memory cells of the array 120 to the output 110, 111 (or the reordered or transposed native FT frame 110, native FT frame frame 111) including the data elements in the second order. In the present embodiment, the first order is different from the second order, so that the first order order of the data elements at the input is different from the second order order of the data elements at the output, but the first order and the second order may also be the same. This mapping may be a butterfly reordering used in fast FT (FFT) calculations. The memory controller writes data elements at the input to the array 120 based on the write allocation, and reads data elements stored in the array 120 to the output based on the read allocation. The write allocation may map the inputs 100 and 101 to the corresponding first subsets of the memory cells of the array 120 in a first subset order, and the read allocation may read the corresponding second subsets of the memory cells of the array 120 to the outputs 110 and 111 in a second subset order. The first subset order is different from the second subset order. Each first subset includes a corresponding first arrangement of the memory cells of the array 120, and each second subset includes a corresponding second arrangement of the memory cells of the array 120. Each corresponding first arrangement is different from each corresponding second arrangement. The first width of the inputs 100 and 101 and the second width of the outputs 110 and 111 are the same. The widths of the first arrangement and the second arrangement are equal to the first width of the inputs 100 and 101 and the second width of the outputs 110 and 111, respectively.

[0071] The butterfly reorder logic may be programmed by a processor, or microcontroller, or coprocessor, or secondary host, or other similar logic circuitry, using a dedicated instruction set architecture (ISA). In the illustrated embodiment, each native FT frame 100, native FT frame 101 includes 9 data points representing an array, more specifically, a two-dimensional array, and even more specifically, a two-dimensional mathematical array. The total data set processed includes 9×9 data points, where each frame contains a 3×3 subset of the total array. In addition, each of the 9 native FT frames constitutes a logical constellation of 3×3 frames, or 3x3 subsets, i.e., a total data set of 9×9 data points is processed, where each frame contains a 3×3 subset of the total array. Each data point is shown in a different shade for differentiation purposes only. According to a predetermined logic, the incoming frames containing native FT data 100, 101 are fragmented or reordered so that each data point in the array 120 is offset by 2 positions (one horizontal position and one vertical position) relative to its original position in the array and frame number. The above operation is repeated for N=9 frames so that the data of all 9 frames are transposed to form an array of 9×9 data points.

[0072] like Figure 1AAs described above, the array or the total data set 120 of 9×9 data points can be viewed as a logical arrangement of 9 3×3 memory cell subgroups, where the first memory cell subgroup, the second memory cell subgroup, and the third memory cell subgroup constitute the first row of the total data set, the fourth memory cell subgroup, the fifth memory cell subgroup, and the sixth memory cell subgroup constitute the second row of the total data set, and the seventh memory cell subgroup, the eighth memory cell subgroup, and the ninth memory cell subgroup constitute the third row of the total data set. In this manner, the first memory cell subgroup, the fourth memory cell subgroup, and the seventh memory cell subgroup constitute the first column of the total data set, the second memory cell subgroup, the fifth memory cell subgroup, and the eighth memory cell subgroup constitute the second column of the total data set, and the third memory cell subgroup, the sixth memory cell subgroup, and the ninth memory cell subgroup constitute the third column of the total data set. The write allocation maps each input frame to a corresponding first subset of memory cells of the array (the first memory cell subgroup to the ninth memory cell subgroup) in the first subset order. Each data point in the first frame 100 (write frame 1) is reordered or transposed so that it is located at the position of row 1 and column 1 in each corresponding memory cell subgroup. Data is written to each position simultaneously from left to right, thereby writing the first row of the total data set, the second row of the total data set, and the third row of the total data set. For example, the data points in the 1st row and 1st column of the first frame are transposed to the 1st row and 1st column of the first memory cell subgroup, the data points in the 1st row and 2nd column of the first frame are transposed to the 1st row and 1st column of the second memory cell subgroup, the data points in the 1st row and 3rd column of the first frame are transposed to the 1st row and 1st column of the third memory cell subgroup, the data points in the 2nd row and 1st column of the first frame are transposed to the 1st row and 1st column of the fourth memory cell subgroup, the data points in the 2nd row and 2nd column of the first frame are transposed to the 1st row and 1st column of the fifth memory cell subgroup, the data points in the 2nd row and 3rd column of the first frame are transposed to the 1st row and 1st column of the sixth memory cell subgroup, the data points in the 3rd row and 1st column of the first frame are transposed to the 1st row and 1st column of the seventh memory cell subgroup, the data points in the 3rd row and 2nd column of the first frame are transposed to the 1st row and 1st column of the eighth memory cell subgroup, and the data points in the 3rd row and 3rd column of the first frame are transposed to the 1st row and 1st column of the ninth memory cell subgroup. The 1st row and the 1st column may be referred to as the first position, the 1st row and the 2nd column may be referred to as the second position, the 1st row and the 3rd column may be referred to as the third position, the 2nd row and the 1st column may be referred to as the fourth position, the 2nd row and the 2nd column may be referred to as the fifth position, the 2nd row and the 3rd column may be referred to as the sixth position, the 3rd row and the 1st column may be referred to as the seventh position, the 3rd row and the 2nd column may be referred to as the eighth position, and the 3rd row and the 3rd column may be referred to as the ninth position. Each data point in the second frame is transposed in the same manner, but transposed to the second position of each corresponding memory unit subset. It can be said that each data point in the first frame to the Nth frame is transposed to the first position to the Nth position of each corresponding memory unit subset of the total data set in the first subset order.

[0073] Once all data points from the native FT frames 100, 101 (write frame 1, ..., write frame N) have been transposed and the total data set 120 is ready for processing, the total data set 120 is logically divided into a number of individual frames 110, 111 (read frame 1, ..., read frame N), such as Figure 1A , and are read from the memory for further processing by the read allocation, which reads the corresponding second subsets 110, 111 of the memory cells into the output in the second subset order. As previously mentioned, in this embodiment, the total data set 120 can be viewed as nine 3×3 memory cell subsets, so each individual read frame is the first memory cell subset to the ninth memory cell subset. In this case, the first memory cell subset to the ninth memory cell subset corresponds to the first read frame to the nth read frame (defined as the second subset herein) (read frame 1,..., read frame N). If the data elements at the input 110, 101 and at the output 110, 111 are one of the following: single-bit data words or multi-bit words of a data string, then each corresponding first subset of the memory cells of the array 120 and each corresponding second subset of the memory cells of the array 120 includes at least one single bit from each data word at the input or at least one multi-bit word from each data string. In this way, the first subset order is a butterfly transposition of the data elements at the input.

[0074] about Figure 1A The described embodiment can be more generally described as follows. The memory cells of the array are divided into a first memory cell subgroup and a second memory cell subgroup; the input includes a first input frame (or write frame) and a second input frame (or write frame); the first input frame includes a first data element and a second data element; the second input frame includes a third data element and a fourth data element. Here, the write allocation maps: the first data element to the first memory cell in the first memory cell subgroup; the second data element to the first memory cell in the second memory cell subgroup; the third data element to the second memory cell in the first memory cell subgroup; and the fourth data element to the second memory cell in the second memory cell subgroup.

[0075] The transformation relationship between the positions of the first memory cell and the second memory cell in the first memory cell subgroup corresponds to or is identical to the transformation relationship between the positions of the first memory cell and the second memory cell in the second memory cell subgroup.

[0076] The transformation relationship may be a translation relationship or a rotation relationship. Optionally, the transformation relationship may be a single memory unit being rotated or translated from one memory unit to an adjacent memory unit, but the present disclosure is not limited thereto, and other transformations may also be envisioned.

[0077] The order of the first data elements in the first input frame corresponds to the order of the third data elements in the second input frame, and the order of the second data elements in the first input frame corresponds to the order of the fourth data elements in the second input frame.

[0078] The read allocation maps memory cells of the array to outputs, the outputs comprising a first output frame (or read frame) comprising a first data element and a third data element and a second output frame (or read frame) comprising a second data element and a fourth data element.

[0079] The order of the first data elements in the first output frame may correspond to the order of the second data elements in the second output frame.The order of the third data elements in the first output frame may correspond to the order of the fourth data elements in the second output frame.

[0080] The first input frame and the second input frame each comprise data corresponding to light intensity values ​​detected at an output plane of the optical Fourier transform stage.

[0081] In some embodiments, the memory is read in a manner that the data of one of the memory cell subgroups is read each time (optionally, but not necessarily in the order in which the data appears in the memory cell subgroup), wherein one read frame corresponds to one memory cell subgroup. In other embodiments, the read frame may sample data from different memory cell subgroups respectively, and / or may sample a subset of data from one memory cell subgroup.

[0082] It will be appreciated that these general principles (and by analogy, the embodiments described herein, including for example reference Figure 1A and 1BThe described embodiments) may be applied to submit (write) an output frame of an OFT stage or OFT device to a memory. The OFT device type discussed is a device that performs an optical Fourier transform on an optical input function. The optical output (Fourier transform) function is obtained by sampling the interference pattern at the Fourier plane of the OFT stage or OFT device. Sampling may be performed using detectors distributed in an array. The detector may detect light collected at an array of output ports located in the Fourier plane. A frame may be considered as a snapshot of the entire OFT or a sample thereof. The frame of the output of the OFT device will correspond to one of the input frames of the memory unit (e.g., the first input frame and the second input frame as described above) (i.e., one of the written frames). Alternatively, multiple written frames may correspond to a single optical Fourier transform output frame (or different regions or areas of a single optical Fourier transform output frame may be sampled).

[0083] In particular, according to Figure 1A In a more general description of the illustrated principle, the first input frame and the second input frame can be light intensity values ​​detected at a port in a port array at an output plane of an optical Fourier transform stage, and each of the third data element and the fourth data element corresponds to a light intensity value detected at a port in a port array at an output plane of the same or another optical Fourier transform stage.

[0084] The relative order of the first data element and the second data element in the first input frame and the relative order of the third data element and the fourth data element in the second input frame respectively correspond to the relative positions of the ports in the port array at the output plane in the corresponding optical Fourier transform stage, optionally, wherein the relative order is adjacent positions or subsequent positions in the sequence and the relative positions are adjacent positions in the port array.

[0085] In this sense, it can be said that the first data element corresponds to a first detected intensity at a first port in the array of ports at the output plane of the optical Fourier transform stage, and the third data element corresponds to a second detected intensity at the first port. The second data element corresponds to a third detected intensity at a second port in the array of ports, and the fourth data element corresponds to a fourth detected intensity at the second port. In other words, the first input frame and the second input frame sample different frames of the optical Fourier transform, so that two different optical Fourier transform functions (or samples thereof) can be written to the memory.

[0086] Figure 1B Shows the Figure 1A A similar embodiment is another example of how to implement the above general principles. Figure 1B In the example, the memory cell subgroups are not composed of Figure 1A is defined by a 9×9 array, but by Figure 1BThe diagonal rows of memory cells in FIG. 1 are represented by numbers 1-9 and arrows. Applying the above general description to Figure 1B , the first memory cell subgroup is the memory cell group indicated by the diagonal arrows labeled with the number 1. The second memory cell subgroup is the memory cell group indicated by the diagonal arrows labeled with the number 2 (including the cell in the 9th row and the 1st column), etc. Then, the first memory cell of the first memory cell subgroup is the cell in the 1st row and the 1st column; the first memory cell of the second memory cell subgroup is the cell in the 1st row and the 2nd column; the second memory cell of the first memory cell subgroup is the cell in the 2nd row and the 2nd column; the second memory cell of the second memory cell subgroup is the cell in the 2nd row and the 3rd column.

[0087] exist Figure 1B In another aspect of the invention, rather than each respective first subset of memory cells of array 120 and each respective second subset of memory cells of array 120 including at least one single bit from each data word or at least one multi-bit word from each data string at the input, each first subset includes a row of memory cells of the array and the first subset includes a multi-bit word of one of the plurality of data strings. Thus, Figure 1B Each row of memory cells of the array of a first subset includes multiple multi-bit words of one data string among a plurality of data strings at input, wherein each corresponding second subset of memory cells of the array includes at least one multi-bit word from each data string among the plurality of data strings at input.

[0088] Go to Figure 2 , another data transposition useful in OFT processing can be seen. In this embodiment, the data is rotated, more specifically, the data points are shuffled, similar to a left-right rotation. Each of the first subset and the second subset includes a row of memory cells or a column of memory cells of the array, and in this embodiment, the first subset and the second subset each include a row of memory cells of the array. As described above, the write allocation maps the input to each first subset of the memory cells of the array in the first subset order 200, and the read allocation reads each second subset of the memory cells to the output in the second subset order 210. Figure 2The second subset order of the memory cells of the array read to the output is a rotation of the first subset order of the memory cells of the array. In this embodiment, the array 200 is reordered or transposed so that the data points are rotated, in this example, the data points are rotated 180 degrees around the center data point (numbered 41). In this way, the first row 201 of the array or input frame 200 contains data points 1-9, from the 1st column to the 9th column. In the transposed array or transposed frame 210, the data points 1-9 are located on the ninth row 211 (in reverse order), from the 9th column to the 1st column. Each first subset includes a corresponding first arrangement of the memory cells of the array, and each second subset includes a corresponding second arrangement of the memory cells of the array. Each corresponding first arrangement is different from each corresponding second arrangement.

[0089] Figure 3 Another transposition of ordered data by a memory architecture and memory access logic is shown, which can be programmed using dedicated read / write access logic built into the memory driver circuit. An arithmetic and logic unit (ALU) can also be integrated into the memory driver to enable in-memory calculations and logic operations on the data. During read / write operations in the memory, in-memory calculations are performed on the transposed data. In this embodiment, the first subset and the second subset each include a row of memory cells or a column of memory cells of the array. The second subset order of the memory cells of the array read to the output is a predetermined shift or an arbitrary shift of the first subset order of the memory cells of the array. Each first subset includes a corresponding first arrangement of the memory cells of the array, and each second subset includes a corresponding second arrangement of the memory cells of the array. Each corresponding first arrangement is different from each corresponding second arrangement. Figure 3 The data points in the 9×9 array 300 shown in FIG. 3 are shifted down by one row and to the right by one column to output a transposed array 310 .

[0090] The memory 40 is suitable for transposing ordered data and can be viewed as having five key elements, such as reference Figure 4As described. The memory unit 400 includes a memory cell array. The memory unit 400 stores data. The data distributor switch (or switch) structure 410 allows parallel read / write data transmission between the memory unit 400 and the storage controller and driver 420. In general, the data distributor switch structure 410 controls the traffic between two nodes / ports and is a combination of hardware and software. The data distributor switch structure 410 may include a read data distributor and a write data distributor, and can be used as a structure of a switch, more specifically, as a structure of a switch and a multiplexing / demultiplexing network. Compared with other memory architectures, the data distributor switch structure 410 allows data transmission reading and writing at a higher rate. It allows dynamic allocation, thereby increasing the flexibility of determining network throughput. The memory controller and driver 420 (or memory controller and driver circuit) can write and read data to and from the memory unit 400. The memory access logic 430 processes access control instructions to regulate access to the memory and control the order in which the memory controller and driver 420 serve memory requests (from the memory interface 440). The memory interface 440 interfaces the memory 40 with a read bus and a write bus, both of which transmit instructions for programming, controlling, and accessing the memory 40. The write bus transmits data to the memory 40, and the read bus transmits data from the memory 40.

[0091] The details of certain aspects of the memory 40, such as the structure of the memory access logic 430 and the memory unit 400, depend on the size of the data to be transposed, that is, whether the data is single-bit or multi-bit. When the data to be transposed and processed is single-bit data, such as Figure 5A As shown, in which a single bit of a data word or bits of a multi-bit word from a data string are transposed, the data transposition occurs at the bit level, so each bit is transposed individually. Figure 5B and Figure 6 As shown, when the data for transposition and processing is multi-bit data forming a multi-bit word as part of a data string, the data transposition occurs on the multi-bit word, so each word is transposed individually to ensure that each word remains unchanged. Figure 5B In the embodiment, Figure 5A The single-bit cells in the data distributor switch fabric 410 are replaced with multi-bit cells, and the data distributor switch fabric 410 is a multi-dimensional switch network that allows multi-bit parallel data transmission between each multi-bit cell and the controller circuit. Figure 6 In an embodiment, multiple memory blocks are provided whose width is equal to the multi-bit word width. Since multiple memory blocks are required, the data distributor switch structure can be a wide bus, thereby allowing parallel data transfer between the memory access logic and the multiple memory blocks.

[0092] Figure 5A , Figure 5B and Figure 6 Each shows an example embodiment of a memory architecture and memory access logic. Figure 5A An embodiment of storing and reading / writing a single bit is shown, while Figure 5B and Figure 6 An embodiment of storing and reading / writing multi-bit words is shown. Figure 5A , Figure 5B and Figure 6 Each contains as reference Figure 4 The elements described will be described in general terms covering both embodiments.

[0093] Memory unit

[0094] Memory cell 400 may comprise any conventional memory cell.

[0095] Data distributor switch structure

[0096] The data distributor switch fabric 410 acts as a bridge between the memory unit 400, the memory controller and driver 420, and the memory access logic 430. The data distributor switch fabric 410 decodes the address (or location) of the memory unit 400 and opens a channel in the data distributor switch fabric 410, thereby connecting the memory unit 400 with the memory controller and driver 420, through which data is transferred to or from the memory unit 400. The data distributor switch fabric 410 can help move data being transferred to and from the memory unit 400, where the data distributor switch fabric 410 is an interconnect architecture between connection points or nodes. In the current embodiment, the connection points are the memory unit 400, the memory controller and driver 420, and the memory access logic 430. The channels in the data distributor switch fabric 410 ensure that data can be transferred to or from the correct location (such as the memory unit 400, the memory controller and driver 420, or the memory access logic 430). The use of the data distributor switch structure 410 and the memory access logic 430 ensures that read / write collisions are avoided. The data distributor switch structure 410 in this embodiment includes a read data distributor and a write data distributor. This is because the data distributor switch structure 410 decodes the cell address of the memory cell 400 required for data transmission, while the memory access logic 430 controls the read / write access to the memory cell 400. The decoding scheme of the data distributor switch structure 410 depends on the size of the data that needs to be reordered or transposed. The decoding scheme can be referred to Figure 5A , Figure 5B and Figure 6 Give a description.

[0097] Transposition and processing of single-bit data

[0098] When the data that needs to be reordered or transposed is a data word with a single bit, the design of the memory unit 400 makes each unit in the memory have a unique address. Each memory unit is connected to the read / write data distributor through an M-dimensional structure, where M is the width of the data bus. The width of the data bus refers to the maximum amount of data that the bus can transmit, or the number of bits that make up the bus. Therefore, the size of the structure depends on the number of bits in the data bus. The structure is mapped to the bus size according to the bit number of each data bit. The bit number identifies the bit position in the binary number, which may be from the most significant bit (MSB) to the least significant bit (LSB).

[0099] The memory access logic 430 includes a read / write address FIFO (ADDR FIFO) that stores a sequence of memory addresses (or a sequence of multiple memory addresses) generated by the read / write address logic (ADDR logic). As described above, the data distributor switch structure 410 and the memory access logic 430 interact when data is being transferred to and from the memory unit 400. Here, when the address of the unit appears in the address sequence obtained from the FIFO, access to the memory unit 400 is granted, or data is transferred to or from the memory unit 400.

[0100] All M bits of a word transferred to or from the memory unit 400 are read and written in parallel. The addresses of all M bits are obtained from the read / write FIFO. The address of each bit in the M-bit word is sent to the corresponding layer in the structure according to the bit number of each data bit. The structure opens the link between the memory unit and the memory controller, allowing data transfer to take place.

[0101] Processing and transposing or reordering of multi-bit data

[0102] In embodiments where data transposition occurs on multi-bit data words (i.e., the bits constituting the words remain unchanged), where the multi-bit data constitutes words of width W bits, and many words constitute a data string consisting of K words, a memory block of width W can be used. Each memory block is connected to a read data distributor and a write data distributor (or a data distributor switch) via a K×A address structure (where A is the address of the X row in the memory block, which is used to store a word in the data string) and a K×W data structure. The address structure and data structure have high bandwidth. The structure is mapped according to the bit number of each word. The bit number identifies the word position in the multi-word binary string, which can be from the most significant word (MSW) to the least significant word (LSW). The memory access logic 430 includes a read / write address FIFO (ADDR FIFO) that stores a sequence of memory addresses (or a sequence of multiple memory addresses) generated by the read / write address logic (ADDR logic). As described above, the data distributor switch fabric 410 and the memory access logic 430 interact when data is being transferred to and from the memory unit. Here, when the address of the row or block is present in the address FIFO, access to the memory unit 400 storing the word is granted, or data is being transferred to or from the memory unit.

[0103] All K×W bits transferred to or from the memory unit 400 are read and written in parallel. The addresses of all K words are obtained from the read / write FIFO. The address of each word is sent to the corresponding layer in the address structure according to the bit number of each data word. This structure opens the link between the row in the selected memory block and the memory controller, allowing data transfer.

[0104] Memory controllers and drivers

[0105] The memory controller and driver 420 includes a controller and input / output (IO) buffers, read and write address decoders, sense amplifiers, and write drivers. The address decoder is a binary decoder having two or more inputs of address bits and one or more outputs of select signals. The inputs of the read and write address decoders are the controller and IO buffers including address bits, and the outputs of the read and write address decoders are memory cell select signals, which enter the data distributor switch structure 410 to select the memory cells 410. The sense amplifier inputs data to the controller and IO buffers. Generally speaking, the sense amplifier receives the stored data signals from the memory cells and amplifies these data signals appropriately so that the amplified values ​​conform to recognizable logic levels and the read data can be correctly interpreted by the remaining digital circuits outside the memory. When single-bit data needs to be reordered or transposed, the write driver sends data to the memory cell through the write distributor switch structure; or when multi-bit data needs to be reordered or transposed, the write driver sends data directly to the row selected memory cell. When single-bit data needs to be transposed, the in-memory ALU is integrated with the memory controller and driver circuit. When multi-bit data needs to be transposed, the ALU is integrated with the memory access logic, which allows arithmetic and logic operations to be performed on multi-bit words fetched from one or more memory blocks.

[0106] Memory access logic

[0107] As previously described, read and write access to the memory cell 400 is controlled by the memory access logic 430. The memory access logic is configured to be reprogrammable to generate different write allocations and read allocations to eliminate conflicts and improve latency. The read and write access logic can eliminate conflicts and improve latency. Both the read and write logic are composed of similar logic and circuits, including read / write logic and read / write state machine controllers, read / write address logic, read / write address FIFOs, read / write counters, and in-memory ALUs.

[0108] The read / write logic is used to program and control the order and sequence of accessing the memory cells to read / write data. During the programming process, the read / write logic can read the initial or starting address of the memory cell to calculate the address of the requested cell and instruct the read / write address logic to generate the address sequence in which the access to the memory cell will occur. The read / write state machine controller in the read / write logic is used to set / reset / read / write the data and sequence counters inside the memory access logic based on the read / write counters and the state provided by the read / write data bus. The state machine is a behavioral model that includes the states that the system may be in to simulate the behavior of the system. Different states of the system can be displayed using the state machine. The sequence counter appears because the memory architecture relies on current inputs and historical inputs to generate the address sequence. The state machine sends a read signal to the read / write FIFO to send the read / write address of the memory cell to the memory controller and driver.

[0109] The read / write address logic generates the address sequence that will read / write the memory.

[0110] When single bits of a data word are reordered or transposed, each address sequence includes the memory addresses of a number of memory cells, each memory cell corresponding to a bit in the data word. The addresses can be arranged according to the bit number of the individual data bits. When multi-bit words are reordered or transposed, each address sequence includes the memory addresses of a number of memory cells ( Figure 5B ), or an identifier of a memory block and the row address where the data will be stored in the memory block ( Figure 6 ). The addresses will be arranged according to the word number of each data word.

[0111] The read / write address FIFO stores the memory addresses generated by the read / write address logic. When the memory address is triggered by the read / write logic and the read / write state machine controller, the memory address is read and sent to the memory controller driver. Only the read / write address logic can write to the FIFO. If the state machine is programmed to repeat similar transpositions for multiple batches of data, the read value of the FIFO will be written back to the FIFO, that is, the read value is pushed to the back of the FIFO queue. In this way, the memory access logic does not need to generate the same address for each data set. Reusing addresses in the FIFO speeds up the access logic.

[0112] The read / write counter is used to synchronize the read / write address FIFO read value with the request issued through the read / write bus. The data / value in the counter is set / reset according to the access workflow programmed into the read / write logic and the read / write state machine controller.

[0113] When multi-bit data needs to be transposed, the in-memory ALU is integrated with the memory controller and driver 420.

[0114] Memory Interface

[0115] The memory interface 440 that interfaces with the memory 40 is a write and read data and control bus. The write data bus and the read data bus can transfer information to or from the memory 40. The write and read control buses transfer additional information, such as instructions for calculating the ALU logic in the memory; instructions for programming the state machine in the access control logic (or read / write logic) and the read / write state machine controller; state control (such as handshake signals and access modes (such as page or burst, etc.) for configuring the memory access logic; and read / write counters for synchronization with the read / write state machine. The state control can be (but is not limited to) a handshake signal or an access mode (such as page or burst). Page mode and burst mode can improve performance by supporting high-speed data transmission. Specific embodiments

[0117] exist Figure 5A , Figure 5B and Figure 6 In each of the illustrated embodiments, black arrows represent data flow, grey arrows represent address flow, and dashed arrows represent instruction flow.

[0118] Figure 5A and Figure 5B Has the same configuration, but Figure 5A The memory cell 501 in is configured to store single bit data, and Figure 5B The memory cell 502 in is configured to store multi-bit data. In other words, Figure 5A The example shown is one in which the data is a single-bit word. Figure 5B Shown is an embodiment where the data is a multi-bit word that may be part of a string.

[0119] exist Figure 5A and Figure 5BIn the embodiment of the present invention, the data in and out of the memory cells 501, 502 is configured to flow into the data distributor switch structure 410, in particular, the data is configured to flow from the memory cells 501, 502 into the read data distributor 511, and from the write data distributor 512 into the memory cells 501, 502. This is to connect the memory cells 501, 502 with the storage controller and driver circuit. The memory controller and driver 420 may include at least one of the following items: a controller and IO buffer 525, a read address decoder 521, a write address decoder 522, a sense amplifier 523, and a write driver 524. The data is configured to flow from the read data distributor 511 to the controller and IO buffer 525 and the in-memory ALU 539 of the memory access logic 430, preferably through the sense amplifier 523. Then, the data is configured to flow from the controller and IO buffer 525 and the in-memory ALU 539 to the write data distributor 512, preferably through the write driver 524. As described above, data is configured to flow from the write data distributor 512 back to the memory cells 501, 502. In this data flow, the address is configured to flow from the controller and IO buffer 525 to the read address decoder 521 and the write address decoder 522, and enter the read data distributor 511 and the write data distributor 512. The address is also configured to flow between the memory cells 501, 502 and the read and write address decoders 521, 522. The read data distributor 511 and the write data distributor 512 may include a row decoder and a column decoder. The read address decoder 521 and the write address decoder 522 may include a row decoder and a column decoder.

[0120] For such data flow, data is configured to flow into and out of the interface of the memory circuit via a read data bus 541 and a write data bus 542. The data bus may implement a bit-wise data flow. The interface may also include a read control bus 543 and a write control bus 544, which transmit at least one of the following instructions through the data flow: instructions for the in-memory ALU 539, instructions for programming the read address logic 531, the write address logic 532, the read logic state machine controller 533, and the write logic state machine controller 534. The read address logic 531 and the write address logic 532 are configured to send read and write addresses to the controller and IO buffer 525 via a read address FIFO 535 and a write address FIFO 536. The controller IO buffer 525 may be configured to send address information back to the memory access logic, or more specifically, to the read logic state machine controller 533 and the write logic state machine controller 534. The interface, or more specifically, the read control bus 553 and the write control bus 554 may also transmit state control information to the read logic state machine controller 533 and the write logic state machine controller 534. The read counters and write counters in the read and write control buses 553, 554 and the read counters 537 and write counters 538 in the memory access logic facilitate synchronization.

[0121] exist Figure 6 In the embodiment shown, there is no reference in the memory Figure 5A and Figure 5B Instead of the memory cells 501 and 502 described above, there is a memory cell 602 in the memory block 654, and the memory cell 602 is configured to store multi-bit data. Figure 5B The memory cell 502 in is slightly different. Figure 5B The data in the example shown is the same as Figure 6 The data in may be multi-bit words, which may be part of a string.

[0122] exist Figure 6613 , data in and out of each memory cell 602 is configured to flow into a column decoder in a read decoder 621. Each memory cell 602 is connected to a memory controller and driver 420. Each memory controller and driver 420 may include at least one of the following: a controller and IO buffer 625, a read decoder 621, a write decoder 622, a sense amplifier 623, and a write driver 624. Data is configured to flow from each controller and IO buffer 625 to a read data distributor 611 through a structure 613, and from a write data distributor 612 to each controller and IO buffer 625 through a structure 613. This connects each memory cell 602 with the read data distributor 611 and write data distributor 612, the memory access logic 430, and the memory interface 440. The structure 613 may be an address and data structure, allowing addresses and data to be transferred into or out of each memory cell 602. The structure 613 is preferably configured to have a high bandwidth. Data flows from the controller and IO buffer 625 to the memory cell 602 through the write driver 624 and the column decoder in the write decoder 622. Data flows out of the memory cell 602 and enters the controller and IO buffer 625 through the column decoder and sense amplifier 623 in the read decoder 621. Then, the data is configured to flow from each controller and IO buffer 625 to the ALU 639 and the write data distributor 612. In this data flow, the address is configured to flow from the read data distributor 611 and the write data distributor 612 to the controller and IO buffer 625 through the structure 613, and from the controller and IO buffer 625 to the read decoder 621 and the write decoder 622 through the structure 613. The address can flow from the read data distributor 611 and the write data distributor 612 to the row decoder of the read and write decoders 621, 622 through the structure 613, thereby bypassing the flow between the read data distributor 611 and the write data distributor 612 and the controller and IO buffer 625 through the structure 613. The address is also configured to flow between each memory cell 602 in each block and each read and write address decoder 621, 622, respectively. The read data distributor 611 and the write data distributor 612 may include a decoder, or more specifically, a block and address decoder. The read decoder 621 and the write decoder 622 may include a row decoder and a column decoder.

[0123] For such data flow, data is configured to enter and exit the memory interface 440 of the memory through a read data bus 641 and a write data bus 642. The data bus can realize a bit-type data flow. The memory interface 440 may also include a read control bus 643 and a write control bus 644, which transmit at least one of the following instructions through the data flow: instructions for the ALU 639, instructions for programming the read address logic 631, the write address logic 632, the read logic state machine controller 633, and the write logic state machine controller 634. The read address logic 631 and the write address logic 632 are configured to send read and write addresses to the controller and the IO buffer 621 through the read address FIFO 635 and the write address FIFO 636. The read address logic 631 and the write address logic 632 can directly send read and write addresses to the row decoders in the read decoder 621 and the write decoder 622 through the read address FIFO 635 and the write address FIFO 636. The controller IO buffer 625 may be configured to send address information from the fabric 613 back to the memory access logic 430, or more specifically, to the read logic state machine controller 633 and the write logic state machine controller 634. The memory interface 440, or more specifically, the read and write control buses 643, 644 may also communicate state control information to the read and write logic state machine controllers 633, 634. The read counters and write counters in the read and write control buses 643, 644 and the read counters and write counters 637, 638 in the memory access logic facilitate synchronization.

[0124] This application includes Figure 5A , Figure 5B and Figure 6 The method of any embodiment of the memory architecture in the embodiment may be used Figure 7 Specifically, Figure 7 A method is described, the method comprising: generating, in memory access logic, a write allocation that maps inputs to memory cells of a memory cell array in a first order and a read allocation that maps memory cells of the array to outputs in a second order; writing data elements at the inputs to the array based on the write allocations; and reading data elements stored in the array to the outputs based on the read allocations. A state diagram illustrates various states of the system through transpositions in the diagram and is used to illustrate the functionality of a state machine.

[0125] The first step of the method is to initialize 701 the system. Initializing 701 the system includes resetting 702 the counters of the system. The memory interface 440, or more specifically the read and write control bus, instructs 703 the read and write logic. The read and write logic is programmed 704 to generate read and write addresses and store 705 the read and write addresses in the read and write FIFOs, thereby enabling data storage and retrieval, preferably in parallel. The system state becomes ready 706. Each time data is input to or output from a memory cell, an address is written or read from the read or write address FIFO. The address can be written back to the read and write address FIFO for use the next time data is input to or output from a memory cell. This allows "recycling" of addresses. For example, in one clock cycle, an address is used to write data to a memory cell of an array, and in another clock cycle, the same address can be used to write data to a memory cell of the array until the read and write address FIFO receives an instruction and no longer writes data back to the read and write address FIFO. Once the system is in the ready state, the read and write logic state machine controller is able to respond to requests and instructions from the read and write control bus.

[0126] When a write instruction is transmitted via the write control bus, data is read 707 from the write data bus and made to flow to the ALU. If an indication of a write instruction is received from the write control bus, the ALU processes 712 the data and sends 713 the data to the write data distributor via the write driver. The write address FIFO provides 714 the write address location and the write logic state machine controller updates 715 the write counter. The write address location is sent 709 to the controller via the write address decoder and then sent 710 to the write data distributor. When both the data and address from the ALU are sent to the write data distributor, the write data distributor writes 711 the data to the memory cell. The write logic state machine controller may then send 716 a confirmation to the write control bus, or more specifically, a write success status.

[0127] When a read instruction is transmitted 717 via the read control bus, the read address FIFO provides 718 the read address location and the read logic state machine controller updates 719 the read counter. The read address location is sent 720 to the controller via the read address decoder and then sent 721 to the read data distributor switch. The read data distributor reads 722 the data from the memory cell and the data is sent to the ALU. If the instruction is received, the ALU will process 712 the data and send it to the read data bus to write 723 the data to the read data bus or the data distributor to write the data back to the memory cell via the write logic state machine controller. The read logic state machine controller may then send 724 an acknowledgement to the read control bus, or more specifically, a read success status.

[0128] Fig. 8A and Figure 8B The embodiments show the use of a distributor switch structure or a distributor switch or a switch structure or a structure. Fig. 8A The distributor switch structure 800 in FIG. 8 is configured for single-bit operation, while Figure 8B The distributor switch structure 810 is configured for multi-bit operation. In other words, Fig. 8A The distributor switch structure 800 allows single-bit data transmission while Figure 8B The distributor switch structure 810 allows multi-bit data transmission.

[0129] In each embodiment, the read data distributor and the write data distributor read or write data according to the position of the bit of data in the row address and column address from the read and write address FIFO. Fig. 8A and Figure 8B In the , each bit word or multi-bit word is assigned a corresponding color according to the importance of the bit. For example, blue represents the most important bit or word, and red represents the least important bit or word.

[0130] exist Fig. 8A In the example, the width of the distributor switch structure 800 is M×B, where M is the number of bits in a single data set and B is the bit length. Fig. 8AA single bit is processed, so the bit length is always 1, that is, B=1. In this example, the number of bits is 3, that is, M=3. The distributor switch structure reads or writes data to the array of memory cells 801 according to the position of the bit in the data set, so that the most significant bit (MSB), the least significant bit (LSB) and all other bits in the data set are read from different memory cells or written to different memory cells. The array of memory cells 801 is in bits, so each bit can be written to a different memory cell or read from a different memory cell. The write allocation generated by the memory access logic 430 maps the input to the corresponding first subset of the memory cells 801 of the array in a first subset order, and the read allocation reads the second subset of the memory cells to the output in a second subset order. The input and output in this embodiment are both single-bit data or single-bit words. The read distributor includes a row address, a column address and data. The MSB is read from the coordinate (7, 0) of the first memory cell 804 in the array of memory cells 801, the adjacent bit is read from the coordinate (0, 0) of the second memory cell 803 in the array of memory cells 801, and the LSB is read from the coordinate (7, 7) of the third memory cell 802 in the array of memory cells 801. The write distributor includes a row address, a column address, and data. The MSB is written to the coordinate (3, 3) of the fourth memory cell 807 in the array of memory cells 801, the adjacent bit is read from the coordinate (0, 6) of the fifth memory cell 806 in the array of memory cells 801, and the LSB is read from the coordinate (6, 6) of the sixth memory cell 805 in the array of memory cells 801.

[0131] Go to Figure 8B, the width of the distributor switch structure 810 is M×B, where M is the number of words in a single data set and B is the bit length of each word. In this example, the number of words is 3, that is, M=3; the bit length of each word is 3, that is, B=3. The distributor switch structure reads or writes data to the array of memory cells 811 according to the position of the word in the string, so the most significant word (MSW), the least significant word (LSW) and all other words in the string are read from different memory cells or written to different memory cells. The memory cell 811 is in units of words, so each word can be written to a different memory cell (or a different subset of memory cells) or read from a different memory cell (or a different subset of memory cells) without transposition. As described above, the write allocation generated by the memory access logic 430 maps the input to the corresponding first subset of the memory cells 811 of the array in the first subset order, and the read allocation reads the corresponding second subset of the memory cells to the output in the second subset order. Each memory cell in each first subset is adjacent so that input is mapped to a corresponding adjacent memory cell in each first subset, and each memory cell in each second subset is adjacent so that output is read from an adjacent memory cell in each second subset of the array. The read distributor includes a row address, a column address, and data. The MSW is read from the first memory cell 814 of the first of the plurality of second subsets 821, an adjacent word (e.g., an adjacent word in a data stream) is read from the second memory cell 813 of the second of the plurality of second subsets 822, and the LSW is read from the third memory cell 812 of the third of the plurality of second subsets 823. The write distributor includes a row address, a column address, and data. The MSW is written to the fourth memory cell 817 of the first of the plurality of first subsets, the adjacent word is read from the fifth memory cell 816 of the second of the plurality of first subsets, and the LSW is read from the sixth memory cell 815 of the third of the plurality of first subsets. The address in the column decoder of the read distributor may include the address of the MSB or LSB and the width of the multi-bit data. This enables relative addressing, allowing adjacent memory cells storing a word of data to be accessed from only a single address.

[0132] The first, second and third of the plurality of first subsets of the plurality of memory cells 811 of the array are in a first subset order, wherein the coordinates of the first subset order are (7, 0), (0, 0) and (7, 7). The first, second and third of the plurality of first subsets each include a corresponding first arrangement of the memory cells 811 of the array, and the corresponding first arrangement has coordinates (7, 0), (0, 0) and (7, 7). The first, second and third of the plurality of second subsets of the plurality of memory cells 811 of the array are in a second subset order, wherein the coordinates of the second subset order are (3, 3), (0, 6) and (6, 6). The first, second and third of the plurality of second subsets each include a corresponding second arrangement of the memory cells 811 of the array, and the corresponding second arrangement has coordinates (3, 3), (0, 6) and (6, 6). Each corresponding first arrangement is different from each corresponding second arrangement.

[0133] The described embodiments are for illustrative purposes only and are not intended to be limiting. As will be appreciated by those skilled in the art, various modifications may be made to the embodiments of the present invention. The present invention is limited by the scope of the appended claims.

[0134] The following numbered embodiments are also described herein:

[0135] Embodiment 1. A memory, comprising:

[0136] an array of memory cells;

[0137] memory access logic programmable to generate write assignments that map inputs comprising data elements to memory cells of the array in a first order and read assignments that map memory cells of the array to outputs comprising data elements in a second order; and

[0138] A memory controller is arranged to write data elements at an input to an array based on a write allocation and to read data elements stored in the array to an output based on a read allocation.

[0139] Embodiment 2. The memory of embodiment 1, wherein the first order is different from the second order, such that the first order sequence of data elements at the input is different from the second order sequence of data elements at the output.

[0140] Embodiment 3. The memory according to embodiment 1 or embodiment 2, wherein the input is a parallel input of a first width and the output is a parallel output of a second width, preferably wherein the first width is the same as the second width.

[0141] Embodiment 4. The memory according to any preceding embodiment, wherein the memory access logic is configured to be reprogrammable to generate different write allocations and read allocations.

[0142] Embodiment 5. The memory of any preceding embodiment, wherein the data elements at the input and at the output are one of: single-bit data words or multi-bit words of a data string.

[0143] Embodiment 6. A memory according to embodiment 5, wherein the most significant bit or word to the least significant bit or word of each single-bit word or multi-bit word is mapped to the input or read to the output in parallel.

[0144] Embodiment 7. The memory of any preceding embodiment, wherein the write allocation maps inputs to a respective first subset of memory cells of the array in a first subset order, and the read allocation reads a respective second subset of memory cells to outputs in a second subset order.

[0145] Embodiment 8. The memory of Embodiment 7, wherein each first subset comprises a respective first arrangement of memory cells of the array and each second subset comprises a respective second arrangement of memory cells of the array.

[0146] Embodiment 9. The memory of embodiment 8, wherein each respective first arrangement is different from each respective second arrangement.

[0147] Embodiment 10. The memory according to embodiment 8 or embodiment 9, wherein the width of each first arrangement is equal to the first width of the input and the second width of the output.

[0148] Embodiment 11. The memory according to embodiment 8 or embodiment 9, wherein the widths of the first arrangement and the second arrangement are respectively equal to the first width of the input and the second width of the output.

[0149] Embodiment 12. The memory of any one of embodiments 7 to 11, wherein the first subset order sequence is different from the second subset order sequence.

[0150] Embodiment 13. The memory of any one of Embodiments 7 to 12, wherein each first subset comprises a row or a column of memory cells of the array.

[0151] Embodiment 14. The memory of any one of Embodiments 7 to 13, wherein each second subset comprises a row or a column of memory cells of the array.

[0152] Embodiment 15. A memory according to any one of embodiments 7 to 14, wherein each first subset of the memory cells of the array are adjacent such that inputs are mapped to the corresponding first subset of the adjacent memory cells of the array, and each second subset of the memory cells of the array are adjacent such that outputs are read from the corresponding second subset of the adjacent memory cells of the array.

[0153] Embodiment 16. A memory according to any one of embodiments 7 to 15 when dependent on embodiment 5, wherein each single-bit word or multi-bit word is mapped to a corresponding first subset of adjacent memory cells of the array, and each single-bit word or multi-bit word is read to an output from a corresponding second subset of adjacent memory cells of the array.

[0154] Embodiment 17. The memory of any of Embodiments 7 to 14, wherein the second subset order of the memory cells of the array that is read to the output is a predetermined shift of the first subset order of the memory cells of the array.

[0155] Embodiment 18. The memory of any of Embodiments 7 to 14, wherein the second subset order of the memory cells of the array that is read to the output is a rotation of the first subset order of the memory cells of the array.

[0156] Embodiment 19. The memory of any one of Embodiments 7 to 12, wherein the first subset order is a butterfly transposition of the data elements at the input.

[0157] Embodiment 20. A memory according to any one of embodiments 7 to 19, wherein each respective first subset of memory cells of the array and each respective second subset of memory cells of the array includes at least one single bit from each data word or at least one multi-bit word from each data string at the input.

[0158] Embodiment 21. A memory according to embodiment 15 or embodiment 19 when based on embodiment 13, wherein each row memory cell or each column memory cell of the array of the first subset includes multiple multi-bit words of one data string among multiple data strings at the input, and wherein each corresponding second subset of the memory cells of the array includes at least one multi-bit word from each data string among the multiple data strings at the input.

[0159] Embodiment 22. The memory of any preceding embodiment, wherein the memory access logic comprises read logic and write logic, wherein the read logic generates read allocations and the write logic generates write allocations.

[0160] Embodiment 23. The memory according to any preceding embodiment, wherein the memory access logic comprises:

[0161] Reading the state controller; and

[0162] Write to the state controller.

[0163] Embodiment 24. The memory according to any preceding embodiment, further comprising a memory interface configured to transfer data elements at an input to a memory cell of the array, and to transfer data elements stored in the memory cell of the array to an output.

[0164] Embodiment 25. The memory according to embodiment 24, wherein the memory interface comprises a read data bus and a write data bus, wherein the read data bus and the write data bus are configured to transmit instructions for programming the memory access logic to the memory access logic.

[0165] Embodiment 26. The memory according to embodiment 24 or embodiment 25, wherein the read data bus and the write data bus are further configured to provide a read counter, a write counter and a status control to the memory access logic.

[0166] Embodiment 27. According to the memory of embodiment 26 when based on embodiment 23,

[0167] Wherein, the read state controller and the write state controller are configured to use the read counter and the write counter and the state to set, reset, read or write both the data and the sequence counter in the memory access logic.

[0168] Embodiment 28. The memory according to any preceding embodiment, further comprising a data distributor switch structure configured to connect the memory cells with the memory access logic and the memory controller.

[0169] Embodiment 29. A memory according to embodiment 28, wherein the data distributor switch structure includes a switch structure, a read data distributor and a write data distributor, wherein the read data distributor and the write data distributor are configured to decode the address of the array corresponding to the read allocation or the write allocation.

[0170] Embodiment 30. A memory according to embodiment 28 or embodiment 29, wherein the switch structure is mapped to the bus size according to the bit number of a single data.

[0171] Embodiment 31. The memory according to any preceding embodiment, wherein the memory cells of the array are divided into a first subgroup of memory cells and a second subgroup of memory cells;

[0172] The input includes a first input frame and a second input frame;

[0173] The first input frame includes a first data element and a second data element;

[0174] The second input frame includes a third data element and a fourth data element; and

[0175] Write allocation:

[0176] mapping a first data element to a first memory cell in a first subset of memory cells;

[0177] mapping a second data element to a first memory cell in a second subset of memory cells;

[0178] mapping the third data element to a second memory cell of the first subset of memory cells; and

[0179] The fourth data element is mapped to a second memory cell of the second subset of memory cells.

[0180] Embodiment 32. A memory according to embodiment 31, wherein a transformation relationship between positions of a first memory cell and a second memory cell in a first memory cell subgroup corresponds to or is equivalent to a transformation relationship between positions of the first memory cell and the second memory cell in a second memory cell subgroup.

[0181] Embodiment 33. A memory according to embodiment 32, wherein the transformation relationship is a translation relationship or a rotation relationship, optionally wherein the transformation relationship is a rotation or translation from one memory unit to an adjacent memory unit through a single memory unit.

[0182] Embodiment 34. A memory according to any one of embodiments 31 to 33, wherein the order of the first data elements in the first input frame corresponds to the order of the third data elements in the second input frame, and the order of the second data elements in the first input frame corresponds to the order of the fourth data elements in the second input frame.

[0183] Embodiment 35. A memory according to any one of embodiments 31 to 34, wherein the read allocation maps memory cells of the array to an output comprising a first output frame and a second output frame, the first output frame comprising the first data element and the third data element, and the second output frame comprising the second data element and the fourth data element.

[0184] Embodiment 36. The memory of Embodiment 35, wherein an order of first data elements in the first output frame corresponds to an order of second data elements in the second output frame.

[0185] Embodiment 37. A memory according to any one of Embodiments 35 or 36, wherein an order of third data elements in the first output frame corresponds to an order of fourth data elements in the second output frame.

[0186] Embodiment 38. A memory according to any one of embodiments 31 to 37, wherein the first input frame and the second input frame each comprise data corresponding to light intensity values ​​detected at an output plane of the optical Fourier transform stage.

[0187] Embodiment 39. A memory according to any one of embodiments 31 to 38, wherein each of the first data element and the second data element corresponds to a light intensity value detected at a port in a port array at an output plane of an optical Fourier transform stage, and wherein each of the third data element and the fourth data element corresponds to a light intensity value detected at a port in a port array at an output plane of the same or another optical Fourier transform stage.

[0188] Embodiment 40. A memory according to embodiment 39, wherein the relative order of the first data element and the second data element in the first input frame and the relative order of the third data element and the fourth data element in the second input frame each correspond to the relative position of the ports in the port array at the output plane in the corresponding optical Fourier transform stage, optionally wherein the relative order is adjacent positions or subsequent positions in the sequence, and the relative positions are adjacent positions in the port array.

[0189] Embodiment 41. A memory according to any one of Embodiments 31 to 40, wherein the first data element corresponds to a first detected intensity at a first port in an array of ports at an output plane of the optical Fourier transform stage, and the third data element corresponds to a second detected intensity at the first port, and

[0190] Optionally, the second data element corresponds to a third detection intensity at a second port in the port array, and the fourth data element corresponds to a fourth detection intensity at the second port.

[0191] Embodiment 42. A method comprising:

[0192] generating, in the memory access logic, a write allocation that maps inputs to memory cells of the memory cell array in a first order and a read allocation that maps memory cells of the array to outputs in a second order;

[0193] writing the data elements at the input to the array based on the write allocation; and

[0194] Based on the read allocation, the data elements stored in the array are read to the output.

[0195] Embodiment 43. A method comprising performing any of the steps performed by a memory and a component of a memory as described in any of embodiments 1 to 41.

Claims

1. A memory, comprising: an array of memory cells; memory access logic programmable to generate write assignments that map inputs comprising data elements in a first order to the memory cells of the array and read assignments that map the memory cells of the array to outputs comprising data elements in a second order; as well as A memory controller is arranged to write the data elements at the input to the array based on the write allocation and to read the data elements stored in the array to the output based on the read allocation.

2. The memory according to claim 1, wherein: The first order is different from the second order such that a first order sequence of the data elements at the input is different from a second order sequence of the data elements at the output.

3. The memory according to claim 1 or claim 2, wherein: The inputs are parallel inputs of a first width and the outputs are parallel outputs of a second width, preferably wherein the first width is the same as the second width.

4. A memory according to any preceding claim, wherein: The memory access logic is configured to be reprogrammable to generate different write allocations and read allocations.

5. A memory according to any preceding claim, wherein: The data elements at the input and at the output are one of: single-bit data words or multi-bit words of a data string.

6. The memory according to claim 5, wherein: The most significant bit or word to the least significant bit or word of each single-bit word or multi-bit word is mapped to the input or read to the output in parallel.

7. A memory according to any preceding claim, wherein: The write allocation maps the inputs to a corresponding first subset of the memory cells of the array in a first subset order, and the read allocation reads a corresponding second subset of the memory cells to the outputs in a second subset order.

8. The memory according to claim 7, wherein: Each of the first subsets includes a respective first arrangement of the memory cells of the array, and each of the second subsets includes a respective second arrangement of the memory cells of the array.

9. The memory according to claim 8, wherein: Each respective first arrangement is different from each respective second arrangement.

10. The memory according to claim 8 or claim 9, wherein: The width of each of the first arrangements is equal to the first width of the input and the second width of the output.

11. The memory according to claim 8 or claim 9, wherein: The widths of the first arrangement and the second arrangement are respectively equal to the first width of the input and the second width of the output.

12. The memory according to any one of claims 7 to 11, wherein: The first subset order is different from the second subset order.

13. The memory according to any one of claims 7 to 12, wherein: Each of the first subsets includes a row or a column of memory cells of the array.

14. The memory according to any one of claims 7 to 13, wherein: Each of the second subsets includes a row or a column of memory cells of the array.

15. The memory according to any one of claims 7 to 14, wherein: Each first subset of the memory cells of the array is adjacent such that the inputs are mapped to the corresponding first subset of the adjacent memory cells of the array, and each second subset of the memory cells of the array is adjacent such that the outputs are read from the corresponding second subset of the adjacent memory cells of the array.

16. A memory according to any one of claims 7 to 15 when dependent on claim 5, wherein: Each single-bit word or multi-bit word is mapped to a respective first subset of adjacent memory cells of the array, and each single-bit word or multi-bit word is read to the output from a respective second subset of adjacent memory cells of the array.

17. The memory according to any one of claims 7 to 14, wherein: The second subset order of the memory cells of the array that are read to the output is a predetermined shift of the first subset order of the memory cells of the array.

18. The memory according to any one of claims 7 to 14, wherein: The second subset order of the memory cells of the array that is read to the output is a rotation of the first subset order of the memory cells of the array.

19. The memory according to any one of claims 7 to 12, wherein: The first subset order is a butterfly transpose of the data elements at the input.

20. The memory according to any one of claims 7 to 19, wherein: Each respective first subset of the memory cells of the array and each respective second subset of the memory cells of the array includes at least one single bit from each data word or at least one multi-bit word from each data string at the input.

21. A memory according to claim 15 or claim 19 depending on claim 13, wherein: Each row memory cell or each column memory cell of the array of the first subset includes a plurality of multi-bit words of one of a plurality of data strings at the input, and wherein each respective second subset of the memory cells of the array includes at least one multi-bit word from each of the plurality of data strings at the input.

22. A memory according to any preceding claim, wherein: The memory access logic includes read logic and write logic, wherein the read logic generates the read allocation and the write logic generates the write allocation.

23. A memory according to any preceding claim, wherein: The memory access logic comprises: Reading the state controller; and Write to the state controller.

24. A memory according to any preceding claim, further comprising a memory interface configured to transfer the data elements at the input to the memory cells of the array, and to transfer the data elements stored in the memory cells of the array to the output.

25. The memory according to claim 24, wherein: The memory interface includes a read data bus and a write data bus, wherein the read data bus and the write data bus are configured to transmit instructions for programming the memory access logic to the memory access logic.

26. A memory according to claim 24 or claim 25, wherein: The read data bus and the write data bus are further configured to provide a read counter, a write counter, and status control to the memory access logic.

27. A memory according to claim 26 when dependent on claim 23, in, The read state controller and the write state controller are configured to use the read counter and the write counter and the state to set, reset, read or write both data and sequence counters in the memory access logic.

28. The memory of any preceding claim, further comprising a data distributor switch fabric configured to connect the memory cells with the memory access logic and the memory controller.

29. The memory according to claim 28, wherein: The data distributor switch fabric includes a switch fabric, a read data distributor, and a write data distributor, wherein the read data distributor and the write data distributor are configured to decode an address of the array corresponding to the read distribution or the write distribution.

30. A memory according to claim 28 or claim 29, wherein: The switch structure is mapped to the bus size according to the bit number of individual data.

31. A memory according to any preceding claim, wherein: The memory cells of the array are divided into a first subgroup of memory cells and a second subgroup of memory cells; The input includes a first input frame and a second input frame; The first input frame includes a first data element and a second data element; The second input frame includes a third data element and a fourth data element; and The write assignment: mapping the first data element to a first memory cell in the first subset of memory cells; mapping the second data element to a first memory cell in the second subset of memory cells; mapping the third data element to a second memory cell of the first subset of memory cells; as well as The fourth data element is mapped to a second memory cell of the second subset of memory cells.

32. The memory according to claim 31, wherein: The transformation relationship between the positions of the first memory cell and the second memory cell in the first memory cell subgroup corresponds to or is identical to the transformation relationship between the positions of the first memory cell and the second memory cell in the second memory cell subgroup.

33. The memory according to claim 32, wherein: The transformation relationship is a translation relationship or a rotation relationship. Optionally, the transformation relationship is a rotation or translation from one memory unit to an adjacent memory unit through a single memory unit.

34. A memory according to any one of claims 31 to 33, wherein: An order of the first data elements in the first input frame corresponds to an order of the third data elements in the second input frame, and an order of the second data elements in the first input frame corresponds to an order of the fourth data elements in the second input frame.

35. A memory according to any one of claims 31 to 34, wherein: The read allocation maps the memory cells of the array to an output including a first output frame including the first data element and the third data element and a second output frame including the second data element and the fourth data element.

36. The memory of claim 35, wherein: An order of the first data elements in the first output frame corresponds to an order of the second data elements in the second output frame.

37. A memory according to any one of claims 35 or 36, wherein: The order of the third data elements in the first output frame corresponds to the order of the fourth data elements in the second output frame.

38. A memory according to any one of claims 31 to 37, wherein: The first input frame and the second input frame each comprise data corresponding to light intensity values ​​detected at an output plane of an optical Fourier transform stage.

39. A memory according to any one of claims 31 to 38, wherein: Each of the first data element and the second data element corresponds to a light intensity value detected at a port in a port array at an output plane of an optical Fourier transform stage, and wherein each of the third data element and the fourth data element corresponds to a light intensity value detected at a port in a port array at an output plane of the same or another optical Fourier transform stage.

40. The memory of claim 39, wherein: The relative order of the first data element and the second data element in the first input frame and the relative order of the third data element and the fourth data element in the second input frame each correspond to the relative positions of ports in a port array at an output plane in a corresponding optical Fourier transform stage, optionally wherein the relative order is adjacent positions or subsequent positions in the sequence and the relative positions are adjacent positions in the port array.

41. A memory according to any one of claims 31 to 40, wherein: the first data element corresponds to a first detected intensity at a first port in an array of ports at an output plane of an optical Fourier transform stage, and the third data element corresponds to a second detected intensity at the first port, and Optionally, the second data element corresponds to a third detection intensity at a second port in the port array, and the fourth data element corresponds to a fourth detection intensity at the second port.

42. A method comprising: generating in memory access logic a write allocation that maps inputs to memory cells of an array of memory cells in a first order and a read allocation that maps the memory cells of the array to outputs in a second order; writing the data elements at the input to the array based on the write allocation; as well as Based on the read allocation, data elements stored in the array are read to the output.

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