Method and device for data information transmission

Abstract

Methods, apparatus, and systems related to designing a rate matching scheme for polarization coding, PAC coding, or other pre-transformed polarization codes are disclosed herein. In one example aspect, a method for digital communication includes determining, by a first node, an output bit sequence having E bits based on an input bit sequence having K bits, the output bit sequence is determined by 1) performing polarization transformation with H components and 2) not performing pre-transformation or performing at least two pre-transformation operations; wherein the polarization transformation is based on H polarization matrixes # imgabs0 #, H, K and E are integers greater than 1, and the size of the polarization matrix # imgabs1 # is Ni. The method further includes transmitting, by the first node to a second node, a signal including the output bit sequence.

Description

Technical Field

[0001] The present invention relates to channel coding technology in communication systems. Background Art

[0002] Mobile communication technology is driving the world towards an increasingly connected and networked society. Compared with existing wireless networks, next-generation systems and communication technologies will need to support a wider range of use case characteristics and provide more complex and sophisticated access requirements and flexibility.

[0003] Long Term Evolution (LTE) is a wireless communication standard for mobile devices and data terminals developed by the Third Generation Partnership Project (3GPP). LTE Evolution (LTE-A) is a wireless communication standard that enhances the LTE standard. The fifth-generation wireless system, known as 5G, advances the LTE and LTE-A wireless standards and is committed to supporting higher data rates, a large number of connections, ultra-low latency, high reliability, and other emerging business requirements. Summary of the invention

[0004] Among other things, this patent application discloses techniques for rate matching design for polar coding, PAC coding, and / or other pre-transformed polar coding schemes.

[0005] In one example aspect, a first digital communication method is disclosed. The method includes: determining, by a first node, an output bit sequence having E bits based on an input bit sequence having K bits, wherein the output bit sequence is determined by 1) performing a polarization transformation having H components and 2) not performing a pre-transformation operation or performing at least two pre-transformation operations; wherein the polarization transformation is based on H polarization matrices Where H, K and E are integers greater than 1, where the polarization matrix The size is N i ; and sending a signal including the output bit sequence by the first node to the second node.

[0006] In another example aspect, another wireless communication method is disclosed. The method includes: receiving, by a second node, a signal including an output bit sequence having E bits from a first node; and determining, by the second node, an input bit sequence having K bits based on the signal, wherein the output bit sequence is determined by 1) performing a polarization transformation having H components and 2) not performing a pre-transformation operation or performing at least two pre-transformation operations; wherein the polarization transformation is based on H polarization matrices Where H, K and E are integers greater than 1, where the polarization matrix The size is N i .

[0007] In another example aspect, a wireless communication device is disclosed, the wireless communication device comprising a process configured or operable to perform the above method.

[0008] In another exemplary aspect, a computer-readable storage medium is disclosed. The computer-readable storage medium stores codes, which, when executed by a processor, cause the processor to implement the above method. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 The polarization matrix G is shown (32) Example of a factor graph for .

[0010] Figure 2A A schematic diagram showing polar coding with rate matching in the 3GPP 5G standard.

[0011] Figure 2B A schematic diagram of PAC encoding is shown.

[0012] Figure 3 A schematic diagram of a convolution transformation with a convolution vector g or a convolution polynomial g(D) is shown.

[0013] Figure 4A A first example of rate-matched polar coding with repetition is shown.

[0014] Figure 4B A second example of rate-matched polar coding with repetition is shown.

[0015] Figure 4C A third example of rate-matched polar coding with repetition is shown.

[0016] Figure 4D A fourth example of rate-matched polar coding with repetition is shown.

[0017] Figure 4E A fifth example of rate-matched polar coding with repetition is shown.

[0018] Figure 4F A sixth example of rate-matched polar coding with repetition is shown.

[0019] Figure 5 A schematic diagram of component polar coding is shown.

[0020] Figure 6 A schematic diagram showing polarization coding after component pre-transformation is shown.

[0021] Figure 7 A specific example of a pre-transformation defined by a recursive feedback polynomial q(D) is shown.

[0022] Figure 8Another specific example of pre-transformation defined by the generator polynomial g(D) and the recursive feedback polynomial q(D) is shown.

[0023] Fig. 9 An exemplary block diagram of a hardware platform that may be part of a network device or a communication device is shown.

[0024] Fig.10 An example of network communication including a base station (BS) and a user equipment (UE) based on some embodiments of the disclosed technology is shown.

[0025] Fig.11 is a flowchart representation of a method for digital communications in accordance with one or more embodiments of the present technology.

[0026] Fig.12 is a flowchart representation of another method for digital communications in accordance with one or more embodiments of the present technology. DETAILED DESCRIPTION

[0027] The titles of the following sections are used to facilitate understanding of the disclosed subject matter and do not limit the scope of the claimed subject matter in any way. Therefore, one or more features of one section may be combined with one or more features of another section. In addition, for clarity of explanation, 5G terminology is used, but the technology disclosed in this application is not limited to 5G technology and can be used in wireless systems implementing other protocols.

[0028] The present application proposes a method and an apparatus related to a rate matching scheme for pre-transformed polarization coding in a wireless communication system.

[0029] In the fifth generation (5G) mobile communication standard of the 3rd Generation Partnership Project (3GPP), low-density parity-check (LDPC) codes are used for data transmission. However, LDPC codes are inferior to polar codes in terms of short payload size, also known as transport block size (TBS). In addition, LDPC codes have a high error floor (block error rate (BLER) of 0.0001). In order to meet the future ultra-reliable low-latency communication (URLLC), we must design more powerful channel codes.

[0030] Polarization adjusted convolutional (PAC) codes can achieve finite length boundaries with moderate decoding complexity. PAC codes are a revolution of polar codes. Therefore, PAC codes have a power of 2 (N = 2 n , where n is a positive integer) as a polar code. However, in order to effectively transmit the payload (or transport block (TB)) in different wireless channel environments, it is not always necessary to have N=2 in the time and frequency resources allocated by the base station (BS). nTherefore, the application of PAC code in wireless communication requires a rate matching scheme. In this application, a method and apparatus for rate matching design with good performance for polar code, PAC coding or other pre-transformed polar code are proposed.

[0031] introduce

[0032] Notes

[0033] GF(2) denotes a Galois field of size 2 having two elements "0" and "1".

[0034] br(i) is the bit reversal function.

[0035] floor(x) represents the largest integer not greater than x.

[0036] ceil(x) represents the smallest integer not less than x.

[0037] round(x) is the round function so that round(x) is the integer closest to x, for example, round(3.2)=3, round(4.8)=5, round(2.5)=3, round(-1.9)=-2, round(-3.4)=-3.

[0038] max(x,y) represents the maximum value between x and y, that is

[0039] mod(x,y) represents the remainder when x is divided by y. For example, mod(5,3)=2, and mod(3,5)=3.

[0040] X i,j represents the element in the i-th row and j-th column of the matrix X, where bold uppercase letters are used to represent matrices.

[0041] [x 0 ,x 1 ,...,x Y-1 ] indicates a containing element x with a length of Y 0 、x 1 , …, x Y-1 A bold lowercase letter x is used to denote a sequence (or vector) [x 0 ,x 1 ,…,x Y-1 ].

[0042] {x 0 ,x 1 ,...,x Y-1} means there are Y different elements x 0、x 1 , …, x Y-1 The set of x, that is, for any i≠j, i ≠x j .

[0043] <x 0 ,x 1 ,...,x Y-1 > represents a number of Y different elements x 0 、x 1 , …, x Y-1 , that is, for any i≠j, x i ≠x j . Let X = <x 0 ,x 1 ,...,x Y-1 >, X(i) represents the i-th element x in the ordered set X i .

[0044] For a set X, |X| represents the set size, that is, the number of elements in set X.

[0045] Z N ={0,1,...,N-2,N-1} represents the set of integers containing all non-negative integers less than N.

[0046] Indexing of sequences, vectors, or matrices starts at zero.

[0047] Introduction to Polarization Matrix

[0048] This section introduces some concepts for using polarization matrices according to various embodiments.

[0049] We will G (N) It is represented as a polarization transformation matrix (or simply polarization matrix) with N rows and N columns, where N is a power of 2, that is, N=2 n , and n is a positive integer. n is called G (N) The order of the polarization matrix of G and N is called (N) The size of the polarization matrix, that is, G (N) The size of is N.

[0050] G (N) Can be one of:

[0051]

[0052] 3) G (N) =P (N) ;

[0053] 4) G (N) =B (N) ·P (N) ;

[0054] Here, all matrix operations are performed over GF(2). For example, is the n-th Kronecker power of matrix P (2) , and B (N) is the bit-reversal permutation matrix with N rows and N columns, and 0 is the all-zero matrix with N / 2 rows and N / 2 columns.

[0055] Let be the element in the i-th row and j-th column of the bit-reversal permutation matrix B (N) . Then, for 0 ≤ i < N and 0 ≤ j < N, where br(i) is the bit-reversal function, defined as and [b n-1 , b n-2 , …, b 1 , b 0 is the n-bit binary expansion of the integer i, i.e.,

[0056] The multiplication of a sequence (or vector) x of length N over GF(2) with the polarization matrix G (N) is called the polarization transformation of the sequence (vector) x. It is denoted as y = x · G (N) , where the vector-matrix multiplication is performed over GF(2). Then, y is the polarization transformation of x.

[0057] Figure 1 shows the factor graph of the polarization matrix G (32) of size N = 32, and the matrix G (32) is as follows:

[0058]

[0059] The polarization matrix G (32)

[0060] Introduction to 3GPP 5G Polarization Coding

[0061] Some example embodiments using polarization coding according to the 3GPP 5G standard are disclosed in this section.

[0062] In the 3GPP 5G standard, polarization codes are used for control channel transmission. Figure 2A shows a schematic diagram of 5G polarization coding with rate matching.

[0063] Let Q be the set of data bit indices of size K, i.e., |Q| = K, where Q is the set of integers Z that contains all non-negative integers less than NN is a subset of {0, 1, …, N - 2, N - 1}. Then, for 5G polar coding performed by the polarization matrix G (N) , encoding the input bit sequence c = [c 0 , c 1 , …, c K-2 , c K-1 into the output bit sequence e = [e 0 , e 1 , …, e E-2 , e E-1 includes the following operations, where K is the length of the input bit sequence, E is the length of the output bit sequence, K and E are positive integers, K < N and K < E.

[0064] As Figure 2A shown, there are 3 main steps involved in this process: adding frozen bits, polarization transformation, and rate matching. The rate matching step also includes sub-block interleaving and bit selection.

[0065] (1) Adding frozen bits: The operation of adding frozen bits combines N - K zero bits with the input bit sequence c to form a polarization transformation input sequence u = [u 0 , u 1 , …, u N-2 , u N-1 of length N according to the data bit index set Q.

[0066] The polarization transformation input sequence u is determined by the input bit sequence c, the data bit index set Q, and the polarization matrix size N, as follows:

[0067]

[0068] (2) Polarization transformation: Polarization transformation is to convert a first bit sequence of length N into a second bit sequence of length N by multiplying the first bit sequence of length N with the polarization matrix G (N) over GF(2). The polarization transformation output bit sequence d = [d 0 , d 1 , …, d N-2 , d N-1 of length N is determined by the polarization transformation input sequence u and the polarization matrix G (N) as d = u · G (N) , where the vector-matrix multiplication is performed over GF(2).

[0069] (3) Rate matching: Rate matching in 5G polar coding includes two operations: sub-block interleaving and bit selection.

[0070] (3.1) Sub-block interleaving: The interleaved output bit sequence d' = [d'0 ,d' 1 ,…,d' N-2 ,d' N-1 ] is determined by the sub-block interleaving pattern π of length 32, the polarization transformation output bit sequence d and the polarization matrix size N as follows:

[0071]

[0072] Where, π=[π 0 ,π 1 ,π 2 ,π 3 ,π 4 ,π 5 ,π 6 ,π 7 ,π 8 ,π 9 ,π 10 ,π 11 ,π 12 ,π 13 ,π 14 ,π 15 ,π 16 ,π 17 ,π 18 ,π 19 ,π 20 ,π 21 ,π 22 ,π 23 ,π 24 ,π 25 ,π 26 ,π 27 ,π 28 ,π 29 ,π 30 ,π 31 ]=[0,1,2,4,3,5,6,7,8,16,9,17,10,18,11,19,12,20,13,21,14,22,15,23,24,25,26,28,27,29,30,31], and J=[J 0 ,J 1 ,…,J N-2 ,J N-1 ] is an interleaving pattern of length N determined by the sub-block interleaving pattern π and the polarization matrix size N. The interleaving pattern J is a permutation of the integer sequence [0, 1, 2, ..., N-2, N-1].

[0073] (3.2) Bit selection: There are three types of bit selection: repetition, puncturing, and truncation. According to the interleaved output bit sequence d', the length K of the input bit sequence, the length E of the output bit sequence, and the size N of the polarization matrix, the output bit sequence e is determined as follows:

[0074] · Repetition: For E ≥ N, e k = d' mod(k,N) , k = 0, 1, 2, …, E-2, E-1.

[0075] · Puncturing: For E < N and K / E ≤ 7 / 16, e k = d' N-E+k , k = 0, 1, 2, …, E-2, E-1.

[0076] · Truncation: For E < N and K / E > 7 / 16, e k = d' k , k = 0, 1, 2, …, E-2, E-1.

[0077] Polarization Adjusted Convolutional (PAC) Coding

[0078] Some example embodiments of PAC coding are disclosed in this section.

[0079] PAC codes are a class of pre-transformed polar codes. Specifically, PAC codes are polar codes using a convolutional transform.

[0080] The schematic diagram of PAC coding is as Figure 2B shown. Denote Q as the set of data bit indices of size K, i.e., |Q| = K, where Q is a subset of the set of integers Z N = {0, 1, …, N-2, N-1} that contains all non-negative integers less than N. Then, through the polarization matrix G (N) the input bit sequence c = [c 0 , c 1 , …, c K-2 , c K-1 is encoded into the output bit sequence e = [e 0 , e 1 , …, e E-2 , e E-1 including the following operations, where K is the length of the input bit sequence, E is the length of the output bit sequence, K < N, K < E and both K and E are positive integers.

[0081] Figure 3 The schematic diagram of the convolutional transform using the convolutional vector g = [g 0 , g 1 , …, g m or the convolutional polynomial g(D) = g 0 + g 1 · D + … + g m-1 · D m-1 + g m · D m is disclosed over GF(2).

[0082] (1) Rate configuration: Rate configuration is the same operation as the add frozen bit operation in 5G polar coding. Therefore, in this application, the terms "add frozen bits" and "rate configuration" can be used interchangeably to refer to the same operation. The rate configuration operation combines NK zero bits with the input bit sequence c to form a rate configuration output sequence v = [v 0 ,v 1 ,…,v N-2 ,v N-1 ]. Specifically, the rate configuration output bit sequence v is determined by the input bit sequence c, the data bit index set Q and the polarization matrix size N as follows.

[0083]

[0084]

[0085] (2) Convolution transformation: Convolution transformation is performed on GF(2) by convolving the input bit sequence and defining the generating polynomial g(D) = g 0 +g 1 ·D+…+g m-1 ·D m-1 +g m ·D m The length of the generated bit sequence g is (m+1) = [g 0 ,g 1 ,…,g m-1 ,g m ] performs a convolution, an operation that transforms a convolution input bit sequence of length N into a convolution output bit sequence of length N, where m is the memory length of the convolution transform, or equivalently, the generating polynomial order of the generating polynomial g(D), and D is a dummy variable representing delay in a digital circuit.

[0086] Figure 3 The convolution transform with the generator polynomial g(D) is shown in FIG. Specifically, the convolution transform output bit sequence u=[u 0 ,u 1 ,…,u N-2 ,u N-1 ] is determined by the rate configuration output bit sequence v, the generator polynomial g(D) (or equivalently, the generator bit sequence g) and the polarization matrix size N as follows, where for i <k,v i-k =0.

[0087]

[0088] Polarization conversion: Polarization conversion is the same as that in 5G polarization coding. The polarization conversion output bit sequence d = [d 0 ,d 1 ,…,d N-2 ,d N-1 ] According to the convolution transformation, the bit sequence u and polarization matrix G are output (N) It is determined as d = u·G (N) , where the vector-matrix multiplication is performed over GF(2).

[0089] Example Introduction

[0090] This section discloses several examples related to rate matching with polar coding, PAC coding or other pre-transformed polar coding with good performance.

[0091] Fig. 4 shows a schematic diagram of six exemplary rate matching methods. The details of the examples will be explained in the following embodiments.

[0092] Example 1

[0093] This section discloses a coding method in a wireless communication system.

[0094] In one example, a digital communication method includes: determining, by a first node, an output bit sequence having E bits based on an input bit sequence having K bits, wherein the output bit sequence is determined by 1) performing a polarization transformation having H components and 2) not performing a pre-transformation or performing at least two pre-transformation operations; wherein the polarization transformation is based on H polarization matrices Among them, E, K, H are integers greater than 1, and the polarization matrix The size is N i .

[0095] The method also includes: sending, by the first node, a signal including the output bit sequence to the second node.

[0096] In another example, a digital communication method includes: obtaining, by a first node, an input bit sequence c=[c 0 ,c 1 ,…,c K-1 ]; and the first node determines the output bit sequence e=[e 0 ,e 1 ,…,e E-1 ]: Repeated, based on H polarization matrices H component polarization coding, based on H polarization arrays Polarization encoding, W-component interleaving, and concatenation after pre-transformation of H components; and transmitting a signal including an output bit sequence e from a first node to a second node.

[0097] Here, K is the input length of the input bit sequence c; E is the output length of the output bit sequence e; H is the number of component polarization matrices; W is the number of component interleavers; K, E, and H are positive integers; K < E and H < E; H is an integer greater than 1; W is an integer not greater than H; for h = 0, 1,..., H - 1, the h-th component polarization encoding is based on the h-th component polarization matrix And the polarization encoding after pre-transformation of the h-th component is based on the h-th component polarization matrix where, N h is the size of the h-th component polarization matrix, and is a power of 2, where n h is a non-negative integer; the sum of the sizes of the H component polarization matrices is equal to the output length E, that is, N 0 + N 1 +... + N H-1 = E.

[0098] Example 2

[0099] This section discloses a decoding method used in a wireless communication system.

[0100] In one example, a digital communication method includes: receiving, by a second node, a signal including an output bit sequence having E bits from a first node. The method further includes: determining, by the second node, an input bit sequence having K bits based on the signal, where the output bit sequence is determined by 1) performing a polarization transformation having H components and 2) not performing a pre-transformation or performing at least two pre-transformation operations; where the polarization transformation is based on H polarization matrices where, E, K, H are integers greater than 1, where the polarization matrix has a size of N i .

[0101] In another example, a digital communication method includes: receiving, by a second node, a signal transmitted by a first node and including an output bit sequence e = [e 0 , e 1 ,..., e E-1 ; and determining, by the second node, an estimate of the input bit sequence c = [c 0 , c 1 , …, c K-1 .

[0102] Here, the output bit sequence e can be determined by the first node through at least one of the following: repetition, H-component polar coding based on H polarization matrices of H polarization matrices of H-component pre-transformed polar coding, W-component interleaving, concatenation; K is the input length of the input bit sequence c; E is the output length of the output bit sequence e; H is the number of component polarization matrices; W is the number of component interleavings; K, E, and H are positive integers; K < E and H < E; H is an integer greater than 1; W is an integer not greater than H; for h = 0, 1,..., H - 1, the h-th component polar coding is based on the h-th component polarization matrix and the h-th component pre-transformed polar coding is based on the h-th component polarization matrix where N h is the polarization matrix size of the h-th component, and is a power of 2, where n h is a non-negative integer; the sum of the H-component polarization matrix sizes is equal to the output length E, that is, N 0 + N 1 +... + N H-1 = E.

[0103] Example 3

[0104] This section discloses the parameters for determining the output bit sequence e.

[0105] Example 3 is based on the above example.

[0106] In the first specific example, for H = 2 polarization matrix sizes of output length E = 24 are N 0 = 16 and N 1 = 8. In the second specific example, for H = 3 polarization matrix sizes of output length E = 24 are N 0 = 8, N 1 = 8, and N 2 = 8. In the third specific example, for H = 3 polarization matrix sizes of output length E = 26 are N 0 = 16, N 1 = 8, and N 2 = 2.

[0107] The output bit sequence e is determined by the first node through at least one of the following:

[0108] The input bit sequence length K,

[0109] The output bit sequence length E,

[0110] The H-component polarization matrix sizes N 0 、N1 ,…,N H-1 ,

[0111] H components with a repetition length of K 0 , K 1 , …, K H-1 ,

[0112] H components repeated index set R (0) , R (1) , …, R (H-1) ,

[0113] The first data bit index set Q = {Q 0 ,Q 1 ,…,Q K-1},

[0114] H component data bit index set Q (0) , Q (1) ,…,Q (H-1) ,

[0115] H component generating polynomials g over GF(2) (0) (D) g (1) (D), ..., g (H-1) (D)

[0116] H-component recursive feedback polynomial q over GF(2) (0) (D), q (1) (D),…,q (H-1) (D)

[0117] H component polarization matrices

[0118] W component interleaving patterns J (0) , J (1) , …, J (W-1) ,

[0119] Where H is the number of component polarization matrices; W is the number of component interleaving patterns, W is a non-negative integer not greater than H; for h = 0, 1, ..., H-1, the hth component repetition length K H is a positive integer, and the hth component repetition length K h Smaller than the size N of the polarization matrix of the hth component h .

[0120] H components polarization matrix size N 0 、N 1 ,…,N H-1 Description

[0121] For h = 0, 1, ..., H-1, the component polarization matrix size N h is the hth component polarization matrix The size of the polarization matrix.

[0122] In some embodiments, the size of all H component polarization matrices is N 0 、N 1 ,…,N H-1 are the same, that is, N 0 =N 1 =…=N H-1 A specific example of a polarization matrix size of H=3 for an output length of E=24 is N 0 =N 1 =N 2 =8.

[0123] In some embodiments, not all H component polarization matrices have size N 0 、N 1 ,…,N H-1 are the same, that is, there exists h≠k such that N h ≠N k A specific example of the size of the polarization matrix for H=3 with an output length of E=24 is N 0 =16, N 1 =4 and N 2 =4, where N 0 ≠N 1 .

[0124] In some embodiments, all H component polarization matrices have a size N 0 、N 1 ,…,N H-1 are different, that is, if h≠k, then N h ≠N k A first specific example of a matrix size of H=2 polarizations for an output length E=24 is N 0 =16 and N 1 =8, where N 0 ≠N 1 A second specific example of a matrix size of H=3 polarizations for an output length of E=26 is N 0 =16, N 1 =8 and N 2 =2, where N 0 ≠N 1 , N 0 ≠N 2 , and N 1 ≠N 2 .

[0125] H components with a repetition length of K 0 , K 1 , …, K H-1 Description

[0126] In some embodiments, the H components have a repetition length K 0 , K 1 , …, K H-1= equal to the input length K. In the first specific example where H = 3 polarization matrix sizes and K = 6, K 0 =6, K 1 =3 and K 2 =1, where K 0 =K=6. In the second specific example where H=3 polarization matrix sizes and K=6, there are K 0 =6, K 1 =6 and K 2 =1, where K 0 =K 1 =K=6.

[0127] In some embodiments, all H components are repeated for length K 0 , K 1 , …, K H-1 are the same, that is, K 0 =K 1 =…=K H-1 In a specific example of H = 3 polarization matrix sizes, there are K 0 =K 1 =K 2 =2.

[0128] In some embodiments, not all H components have a repeat length K. 0 , K 1 , …, K H-1 are the same, that is, there exists h≠k, such that K h ≠K k In a specific example of H = 3 polarization matrix sizes, there are K 0 =6, K 1 =2 and K 2 =2, where K 0 ≠K 1 .

[0129] In some embodiments, all H components are repeated for length K 0 , K 1 , …, K H-1 are all different, that is, if h≠k, then K h ≠K k In a specific example of H = 3 polarization matrix sizes, there are K 0 =6, K 1 =3 and K 2 =1, where K 0 ≠K 1 , K 0 ≠K 2 And K 1 ≠K 2 .

[0130] Component repeat index set R (0) ,R (1) ,…,R (H-1) Description

[0131] For h = 0, 1, ..., H-1, the hth component repetition set With K h elements, that is, the size of the h-th component repetition set is |R (h) |=K h , where K h is the hth component repetition length. For h = 0, 1, ..., H-1, the hth component repetition index set is the set Z of integers of the first type K = a subset of {0, 1, ..., K-2, K-1}, where the first type integer set Z K = {0, 1, ..., K-2, K-1} includes all non-negative integers less than K. In some embodiments, the H component repetition index set R (0) , R (1) , …, R (H-1) Equal to the set Z of integers of the first type K ={0,1,2,…,K-1}, where the first type integer set Z K = {0, 1, 2, ..., K-1} includes all non-negative integers less than K. In which K = 6, E = 24, the size of the polarization matrix is ​​N 0 =16 and N 1 = 8, H = 2 component repetition index sets R (0) and R (1) They are: R (0) =Z 6 ={0,1,2,3,4,5}(where K 0 =K=6) and R (1) ={0,1,2}(where K 1 =3).

[0132] In some embodiments, the H component repetition index set R (0) , R (1) , …, R (H-1) There is no set Z that is equal to the first type integer set K ={0,1,2,…,K-1}, where the first type integer set Z K = {0, 1, 2, ..., K-1} includes all non-negative integers less than K. In which K = 6, E = 24, H = 3 polarization matrices of size N 0 =16, N 1 =4 and N 2 =4, H=3 component repetition index sets are R (0) ={0,1,2,3,4}(where K0 =5) R (1) ={5,0}(where K 1 =2) and R (2) ={1,2}(where K 1 =2), where R (0) ≠Z 6 , R (1) ≠Z 6 , and R (2) ≠Z 6 , where Z 6 ={0,1,2,3,4,5}.

[0133] In some embodiments, for h=0, 1, ..., H-2, the (h+1)th component repeats the index set R (h+1) is the hth component repetition index set A subset of, that is, Where K = 6, E = 24, H = 3 polarization matrices of size N 0 =8, N 1 =8 and N 2 = 8, H = 3 component repetition index sets R (0) , R (1) , R (2) R (0) =Z 6 ={0,1,2,3,4,5}(where K 0 =K=6), R (1) ={0,2,1}(where K 1 =3) and R (2) ={0}(where K 2 =1), where and

[0134] In some embodiments, for h, h' is a non-negative integer less than H and h is not equal to h', the hth component repeats the index set R (h) and the h'th component repeats the index set R (h') The intersection of is an empty set, that is, R (h) ∩R (h') =Φ={}, where Φ represents an empty set. In which K=6, E=24, H=3 polarization matrices of size N 0 =16, N 1 =4 and N 2 =4, the H=3 component repetition index sets are: R (0) ={0,1}(where K 0 =2) R (1) ={2,3}(where K 1=2) and R (2) ={4,5}(where K 1 =2).

[0135] In some embodiments, there exists h and k are non-negative integers less than H, and h is not equal to k (h≠k), such that the hth component repeats the index set R (h) and the kth component copy index set R (k) The intersection of is not an empty set, that is, R (h) ∩R (k) ≠Φ, where Φ = {} is an empty set. In which K = 6, E = 24, the size of the polarization matrix is ​​N 0 =16 and N 1 = 8, H = 2 component repetition index set R (0) and R (1) R (0) =Z 6 ={0,1,2,3,4,5}(where K 0 =K=6) and R (1) ={0,1,2}(where K 1 =3), where R (0) ∩R (1) ={0,1,2}≠{}=Φ; where Φ represents an empty set. In which K=6, E=24, H=3 polarization matrices of size N 0 =8, N 1 =8 and N 2 = 8, H = 3 component repetition index set R (0) , R (1) , R (2) R (0) =Z 6 ={0,1,2,3,4,5}(where K 0 =K=6), R (1) ={0,1,2}(where K 1 =3) and R (2) ={4}(where K 2 =1), where R (0) ∩R (1) ={0,1,2}≠Φ and R (0) ∩R (2) ={4}≠Φ; where Φ represents an empty set. In which K=6, E=26, H=3 polarization matrices of size N 0 =16, N 1 =8 and N 2 = 2, H = 3 component repetition index set R (0) , R (1) , R (2)They are: R (0) ={0,1,2,3,4}(where K 0 =5) R (1) ={0,5}(where K 1 =2) and R (2) ={4}(where K 2 =1), where R (0) ∩R (1) = {0}≠Φ and R (0) ∩R (2) ={4}≠Φ; where Φ represents an empty set. In some embodiments, all H components repeat the index set R (0) , R (1) , …, R (H-1) A set of repeated indices R with H = 3 components (0) , R (1) , R (2) The specific examples are R (0) ={0,1,2,3,4}(where K 0 =5) R (1) ={5,0,2}(where K 1 =2) and R (2) ={4,0}(where K 2 =2), where H = 3 component repetition index sets R (0) , R (1) , R (2) Including index k=0.

[0136] Component data bit index set Q (0) , Q (1) ,…,Q (H-1) Description

[0137] For h = 0, 1, ..., H-1, the hth component data bit index set With K h elements, that is, the size of the hth component data bit index set is |Q (h) |=K h , where K h is the hth component repetition length. For h = 0, 1, ..., H-1, the hth component data bit index set is the hth set of integers of the second type A subset of h is the size of the h-th polarization matrix, and the h-th set of second-type integers Includes all values ​​less than N h For h = 0, 1, ..., H-1, the hth data bit index set Q h The elements in are smaller than the hth component polarization matrix The polarization matrix size N hIn some embodiments, the size of the H component data bit index set K 0 , K 1 , …, K H-1 At least one of them is equal to the input length K. When K=6, E=24, the size of H=2 polarization matrices is N 0 =16 and N 1 = 8, H = 2 component data bit index sets Q (0) and Q (1) Q (0) ={12,7,11,13,14,15}(where K 0 =K=6) and Q (1) ={12,7,11}(where K 1 =3), where the 0th component data bit index set Q (0) ={12,7,11,13,14,15} corresponds to the 0th component polarization matrix And the first component data bit index set Q (1) ={5,6,7} corresponds to the first component polarization matrix Where K = 6, E = 24, H = 3 polarization matrices of size N 0 =8, N 1 =8 and N 2 =8, H = 3 component data bit index sets Q (0) , Q (1) , Q (2) Q (0) ={2,4,3,5,6,7}(where K 0 =K=6), Q (1) ={2,4,5}(where K 1 =3) and Q (2) ={3}(where K 2 =1). In which K=6, E=26, the size of the polarization matrix is ​​N 0 =16, N 1 =8 and N 2 = 2, H = 3 component repetition index set Q (0) , Q (1) , Q (2) Q (0) ={7,11,13,14,15}(where K 0 =5), Q (1) ={6,7}(where K 1 =2) and Q (2) ={1}(where K 2= 1). In some embodiments, for certain h, if k < k', then the k-th element in the h-th component data bit index set Q (h) is less than the k'-th element in the h-th component data bit index set Q i.e., the h-th component data bit index set Q (h) is sorted in ascending order according to the index value as Q <Q (h) ... 0 <Q 1< ... < Q K-2< Q K-1 In some embodiments, for certain h, if k < k', then the k-th element in the h-th component data bit index set Q (h) is greater than the k'-th element in the h-th component data bit index set Q i.e., the h-th component data bit index set Q (h) is sorted in descending order according to the index value as Q <Q (h) ... 0> Q 1> ... > Q K-2> Q K-1 In some embodiments, for certain h, if k < k, then the reliability of the -th polaron channel (denoted as ) corresponding to the h-th component polarization matrix is less than the reliability of the -th polaron channel (denoted as ) corresponding to the h-th component polarization matrix, i.e., the h-th component data bit index set Q is sorted in ascending order according to the polaron channel reliability as . In some embodiments, for certain h, if k < k, then the reliability of the (h) -th polaron channel (denoted as ) corresponding to the h-th component polarization matrix is greater than the reliability of the -th polaron channel (denoted as ) corresponding to the h-th component polarization matrix, i.e., the h-th component data bit index set Q is sorted in descending order according to the polaron channel reliability as -th polaron channel (denoted as ) corresponding to the h-th component polarization matrix, i.e., the h-th component data bit index set Q) corresponding to the h-th component polarization matrix, i.e., the h-th component data bit index set Q (h) is sorted in descending order according to the polaron channel reliability as .

[0138] Description of the first data bit index set Q

[0139] The first data bit index set Q = {Q 0 , Q1 ,...,Q K-1} has K elements, that is, the size of the input data bit index set is |Q|=K, where K is the input length. The first data bit index set Q={Q 0 ,Q 1 ,…,Q K-1} is a set of integers of the third type A subset of m There are H polarization matrices with size N 0 、N 1 ,…,N H-1 The maximum value in N m =max 0≤h<H N h , and the set of integers of the third type Includes all values ​​less than N m In some embodiments, the H component data bit index set Q (0) ,Q (1) ,...,Q (H-1) Equal to the first data bit index set Q = {Q 0 ,Q 1 ,…,Q K-1}. In which K = 6, N m =16 and E=24, the first data bit index set is Q={12,7,11,13,14,15}. In which K=6 and H=3 polarization matrices of size N 0 =8, N 1 =8 and N 2 = 8, we get N m =max(max(N 0 ,N 1 ),N 2 )=8, data bit index set Q={2,4,3,5,6,7}, and H=3 component data bit index sets

[0140] Where K = 6 and H = 3 polarization matrix size is N 0 =16, N 1 =8 and N 2 = 2, we get N m =max(max(N 0 ,N 1 ),N 2 )=16, and data bit index set Q={12,7,11,13,14,15}.

[0141] Component Generator Polynomial g (0) (D) g (1) (D), ..., g (H-1) (D) Description

[0142] In this application, the generating polynomial g(D)=g 0+ g 1 ·D+...+g m ·D m The corresponding generated bit sequence g=[g 0 ,g 1 ,…,g m ]. The generating polynomial g(D) and its corresponding generating bit sequence g can be used interchangeably in this application. For h=0, 1, ..., H-1, the generating polynomial of the hth component is Corresponding to the hth polarization matrix and can be any bivariate polynomial over GF(2), where m h is the hth component generating polynomial g (h) (D) The memory length or the hth component generating polynomial g (h) In some embodiments, the H component generating polynomial g (0) (D) g (1) (D), ..., g (H-1) (D) are the same as each other, that is, g (0) (D) = g (1) (D) = ... = g (H -1) (D) In ​​some embodiments, the H component generating polynomials g (0) (D),g (1) (D),...,g (H-1) (D) are not the same, that is, there are two integers h and h' such that h ≠ h' and g (h) (D)≠g (h′) (D) Where H = 1 and the memory length is m 0 =6, the 0th component generating polynomial

[0143] In the second specific example where H=3, H=3 component generating polynomials g (0) (D),g (1) (D),g (2) (D) are the same, that is, g (0) (D) = g (1) (D) = g (2) (D) = 1 + D 2+ D 3 +D 5 +D 6 , where the memory length is m 0 =m 1=m 2 = 6. In which H = 3 and the memory length is m 0 =6, m 1 =3, m 2 =2, the generating polynomial of the 0th component is The first component generating polynomial is

[0144] And the second component generating polynomial is Component Generator Polynomial g (h) (D) = g (h) 0 +g (h) 1 ·D+...+g (h) m ·D m A more specific example is as follows:

[0145] (1) For m = 1, g (h) (D) = g (h) 0+ g (h) 1 ·D+...+g (h) m ·D m =g (h) 0+ g (h) 1 D = 1 + D;

[0146] (2) For m = 2, g (h) (D) = g (h) 0+ g (h) 1 ·D+...+g (h) m ·D m =g (h) 0+ g (h) 1 ·D + g (h) 2 ·D 2 =1+D 2 ;

[0147] (3) For m=3, g (h) (D) = g (h) 0 +g (h) 1 ·D+...+g (h)m ·D m = g (h) 0 + g (h) 1 ·D + g (h) 2 ·D 2 + g (h) 3 ·D 3 = 1 + D + D 2 + D 3 ;

[0148] (4) For m = 4, g (h) (D) = g (h) 0 + g (h) 1 ·D +... + g (h) m ·D m = g (h) 0 + g (h) 1 ·D + g (h) 2 ·D 2 + g (h) 3 ·D 3 + g (h) 4 ·D 4 = 1 + D + D 2 + D 4 and g (h) (D) = g (h) 0 + g (h) 1 ·D +... + g (h) m ·D m = g (h) 0 + g (h) 1 ·D + g (h) 2 ·D 2 + g (h) 3 ·D 3 + g (h) 4 ·D 4 = 1 + D 2 + D 3 + D 4 ;

[0149] (5) For m = 5, g (h) (D) = g(h) 0 +g (h) 1 ·D +... + g (h) m ·D m =g (h) 0 +g (h) 1 ·D + g (h) 2 ·D 2 +... + g (h) 5 ·D 5 =1 + D + D 3 +D 5 以及g (h) (D) = g (h) 0 +g (h) 1 ·D +... + g (h) m ·D m =g (h) 0 +g (h) 1 ·D + g (h) 2 ·D 2 +... + g (h) 5 ·D 5 =1 + D 2 +D 4 +D 5 ;

[0150] (6) 对于m = 6,g (h) (D) = g (h) 0 +g (h) 1 ·D +... + g (h) m ·D m =g (h) 0 +g (h) 1 ·D + g (h) 2 ·D 2 +... + g (h) 6 ·D 6 =1 + D 6 ;

[0151] (7) 对于m = 7,g (h) (D) = g (h)0 +g (h) 1 ·D +... + g (h) m ·D m =g (h) 0 +g (h) 1 ·D + g (h) 2 ·D 2 +... + g (h) 7 ·D 7 =1 + D 3 +D 5 +D 7 以及g (h) (D)=g (h) 0 +g (h) 1 ·D +... + g (h) m ·D m =g (h) 0 +g (h) 1 ·D + g (h) 2 ·D 2 +... + g (h) 7 ·D 7 =1 + D 2 +D 4 +D 7 ;

[0152] (8)对于m=8,g (h) (D)=g (h) 0 +g (h) 1 ·D +... + g (h) m ·D m =g (h) 0 +g (h) 1 ·D + g (h) 2 ·D 2 +... + g (h) 8 ·D 8 =1 + D 4 +D 8 ;;

[0153] (9)对于m=9,g (h) (D)=g(h) 0 +g (h) 1 ·D +... + g (h) m ·D m =g (h) 0 +g (h) 1 ·D + g (h) 2 ·D 2 +... + g (h) 9 ·D 9 =1 + D 3 +D 4 +D 5 +D 7 +D 9 and g (h) (D)=g (h) 0 +g (h) 1 ·D +... + g (h) m ·D m =g (h) 0 +g (h) 1 ·D + g (h) 2 ·D 2 +... + g (h) 9 ·D 9 =1 + D 2 +D 4 +D 5 +D 6 +D 9 ;

[0154] (10) For m = 10, g (h) (D)=g (h) 0 +g (h) 1 ·D +... + g (h) m ·D m =g (h) 0 +g (h) 1 ·D + g (h) 2 ·D 2 +... + g (h) 10 ·D 10 =1 + D 2+D 6 +D 7 +D 10 and g (h) (D) = g (h) 0 +g (h) 1 ·D +... + g (h) m ·D m = g (h) 0 +g (h) 1 ·D + g (h) 2 ·D 2 +... + g (h) 10 ·D 10 = 1 + D 3 +D 4 +D 8 +D 10 ;

[0155] (11) For m = 11, g (h) (D) = g (h) 0 +g (h) 1 ·D +... + g (h) m ·D m = g (h) 0 +g (h) 1 ·D + g (h) 2 ·D 2 +... + g (h) 11 ·D 11 = 1 + D + D 2 +D 4 +D 8 +D 10 +D 11 and g (h) (D) = g (h) 0 +g (h) 1 ·D +... + g (h) m ·D m = g (h) 0 +g (h) 1 ·D + g (h) 2 ·D 2 +... + g(h) 11 ·D 11 =1 + D + D 3 + D 7 + D 9 + D 10 + D 11 ;

[0156] (12) For m = 12, g (h) (D)= g (h) 0 + g (h) 1 ·D +... + g (h) m ·D m = g (h) 0 + g (h) 1 ·D + g (h) 2 ·D 2 +... + g (h) 12 ·D 12 =1 + D 2 + D 5 + D 6 + D 7 + D 8 + D 9 + D 10 + D 11 + D 12 and g (h) (D)= g (h) 0 + g (h) 1 ·D +... + g (h) m ·D m = g (h) 0 + g (h) 1 ·D + g (h) 2 ·D 2 +... + g (h) 12 ·D 12 =1 + D + D 2 + D 3 + D 4 + D 5 + D 6 + D 7 + D 10 + D 12 ;

[0157] (13) For m = 13, g (h) (D) = g (h) 0 + g (h) 1 · D +... + g (h) m · D m = g 0 + g 1 · D + g 2 · D 2 +... + g 13 · D 13 = 1 + D + D 4 + D 5 + D 9 + D 10 + D 13 and g (h) (D) = g (h) 0 + g (h) 1 · D +... + g (h) m · D m = g (h) 0 + g (h) 1 · D + g (h) 2 · D 2 +... + g (h) 13 · D 13 = 1 + D 3 + D 4 + D 8 + D 9 + D 12 + D 13 ;

[0158] (14) For m = 14, g (h) (D) = g (h) 0 + g (h) 1 · D +... + g (h) m · D m = g 0 + g 1 · D + g 2 · D 2 +... + g 14 · D 14 = 1 + D + D 2 + D 7 + D 8 + D 10+D 12 +D 14 and g (h) (D) = g (h) 0 +g (h) 1 ·D +... + g (h) m ·D m = g (h) 0 +g (h) 1 ·D + g (h) 2 ·D 2 +... + g (h) 14 ·D 14 = 1 + D 2 +D 4 +D 6 +D 7 +D 12 +D 13 +D 14 ;

[0159] (15) For m = 15, g (h) (D) = g (h) 0 +g (h) 1 ·D +... + g (h) m ·D m = g 0 +g 1 ·D + g 2 ·D 2 +... + g 15 ·D 15 = 1 + D + D 4 +D 6 +D 7 +D 8 +D 9 +D 15 and g (h) (D) = g (h) 0 +g (h) 1 ·D +... + g (h) m ·D m = g (h) 0 +g (h) 1 ·D + g (h) 2 ·D 2 +... + g (h)15 ·D 15 =1+D 6 +D 7 +D 8 +D 9 +D 11 +D 14 +D 15 ;

[0160] (16) For m = 16, g (h) (D) = g (h) 0 +g (h) 1 ·D+...+g (h) m ·D m =g (h) 0 +g (h) 1 ·D+g (h) 2 ·D 2 +...+g (h) 16 ·D 16 =1+D 2 +D 4 +D 6 +D 8 +D 13 +D 14 +D 16 and (h) (D) = g (h) 0 +g (h) 1 ·D+...+g (h) m ·D m =g (h) 0 +g (h) 1 ·D+g (h) 2 ·D 2 +...+g (h) 16 ·D 16 =1+D 2 +D 3 +D 8 +D 10 +D 12 +D 14 +D 16 ;

[0161] Where m is the memory length.

[0162] Recursive feedback polynomial q (0) (D), q (1) (D),…,q (H-1) (D) Description

[0163] In this application, the recursive feedback polynomial q(D)=q 0+ q 1 ·D+...+q m ·D m The corresponding recursive feedback bit sequence q=[q 0 ,q 1 ,…,q m ]. The recursive feedback polynomial q(D) and its corresponding recursive feedback bit sequence q may be used interchangeably in this application.

[0164] For h = 0, 1, ..., H-1, the hth component recursive feedback polynomial Corresponding to the hth polarization matrix and can be any bivariate polynomial over GF(2), where m h is the hth component recursive feedback generator polynomial q (h) (D) The memory length or the hth component recursive feedback polynomial q (h) In some embodiments, the H component recursive feedback polynomial q (0) (D), q (1) (D),…,q (H-1) (D) are the same as each other, that is, q (0) (D) = q (1) (D) = ... = q (H-1) (D) In ​​some embodiments, the H components recursively feedback polynomial q (0) (D), q (1) (D),…,q (H-1) are not the same, that is, there exist two integers h and h' such that h≠h' and q (h) (D)≠q (h′) (D) Where H = 1 and the memory length is m 0 =6In the first specific example, the 0th recursive feedback polynomial is

[0165] In the second specific example where H=3, H=3 recursive feedback polynomials q (0) (D), q (1) (D), q (2) (D) are the same, and q (0) (D) = q (1) (D) = q (2) (D) = 1 + D 2+ D 4 +D 5+D 6 , where the memory length is m 0 =m 1 =m 2 = 6. In which H = 2 and the memory length is m 0 =6 and m 1 =3, the 0th recursive feedback polynomial is

[0166] And the first recursive feedback polynomial is

[0167] Component interleaving pattern J (0) , J (1) , …, J (W-1) Description

[0168] For h = 0, 1, ..., H-1, the hth component interleaving pattern Size is N h , where N h is the size of the h-th polarization matrix, and J (h) is the sequence [0,1,2,…,N h -1] substitution. In which H = 2, W = 2, N 0 =16, N 1 = 8, the 0th component interleaving pattern

[0169]

[0170] is a permutation of the array [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15], and the first component is an interleaved pattern is a permutation of the array [0,1,2,3,4,5,6,7]. In which H = 3, W = 2, N 0 =N 1 =N 2 = 8, the 0th component interleaving pattern is a permutation of the array [0,1,2,3,4,5,6,7], and the first component is an interleaved pattern

[0171] is a permutation of the array [0,1,2,3,4,5,6,7]. In it, H=3, W=3, N 0 =16, N 1 =8 and N 2 = 2, the 0th component interleaving pattern

[0172] is a permutation of the array [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15], with the first component interleaved pattern is a permutation of the array [0,1,2,3,4,5,6,7], and the second component interleaved pattern 0] is a permutation of the array [0,1]. In which H = 3, W = 1, N 0 =8, N 1 =16 and N 2 = 2, the second component interleaving pattern is a permutation of the array [0,1].

[0173] In some embodiments, the first node obtains an input bit sequence c of length K and determines H components to repeat the output bit sequence c. (0) 、c (1) 、c (2) ,…,c (H-1) To perform repetition, where for h = 0, 1, ..., H-1, the hth component repeats the output bit sequence The length is K h In some embodiments, for h=0, 1, 2, ..., H-1, the first node repeatedly outputs the bit sequence by obtaining the hth component And determine the length to be N h The polarization matrix of the hth component The corresponding h-th component polarization coded output bit sequence is To perform component polar coding, where N h yes In some embodiments, the first node obtains the H component polarization coded output bit sequence d (0) d (1) d (2) ,…,d (H-1) And determine the output bit sequence of length E = [e 0 ,e 1 ,…,e E-1 ] to perform the cascade, where Figure 4A A specific example is shown in FIG.

[0174] In some embodiments, the first node obtains an input bit sequence c of length K and determines H components to repeat the output bit sequence c. (0) 、c (1) 、c (2) ,…,c (H-1)To perform repetition, where for h = 0, 1, ..., H-1, the hth component repeats the output bit sequence The length is K h In some embodiments, for h=0, 1, 2, ..., H-1, the first node repeatedly outputs the bit sequence by obtaining the hth component And determine the length to be N h The polarization matrix of the hth component The corresponding polarization coded output bit sequence after pre-transformation of the hth component is To perform polar coding after component pre-transformation, where N h yes In some embodiments, the first node obtains the polarization coded output bit sequence d after the H components are pre-transformed. (0) d (1) d (2) ,…,d (H-1) And determine the output bit sequence of length E = [e 0 ,e 1 ,…,e E-1 ] to perform the cascade. Among them, Figure 4B A specific example is shown in FIG.

[0175] In some embodiments, the first node obtains an input bit sequence c of length K and determines H components to repeat the output bit sequence c. (0) 、c (1) 、c (2) ,…,c (H-1) To perform repetition, where for h = 0, 1, ..., H-1, the hth component repeats the output bit sequence The length is K h In some embodiments, for h=0, 1, 2, ..., H-1, the first node repeatedly outputs the bit sequence by obtaining the hth component And determine the length to be N h The polarization matrix of the hth component The corresponding h-th component polarization coded output bit sequence d (h) To perform component polar coding, where N h The polarization matrix size is In some embodiments, the number of component interleaving patterns W is equal to the number of component polarization matrices H, and for h=0, 1, ..., H-1, the first node obtains a length of N h The h-th component polar coding output bit sequence And determine the length to be N h The hth component of the interleaved output bit sequence To perform component interleaving, where N h yes In some embodiments, the first node obtains W=H components by interleaving the output bit sequence d' (0)、 d' (1) , d' (2) ,…,d' (H-1) And determine the output bit sequence of length E = [e 0 ,e 1 ,…,e E-1 ] to perform the cascade, where Figure 4C A specific example is shown in FIG.

[0176] In some embodiments, the first node obtains an input bit sequence c of length K and determines H components to repeat the output bit sequence c. (0) 、c (1) 、c (2) ,…,c (H-1) To perform repetition, where for h = 0, 1, ..., H-1, the hth component repeats the output bit sequence The length is K h In some embodiments, for h=0, 1, 2, ..., H-1, the first node repeatedly outputs the bit sequence by obtaining the hth component And determine the length to be N h The polarization matrix of the hth component The corresponding polarization coded output bit sequence after pre-transformation of the hth component is To perform polar coding after component pre-transformation, where N h The polarization matrix size is In some embodiments, the number of component interleaving patterns W is equal to the number of component polarization matrices H, and for h=0, 1, ..., H-1, the first node obtains a length of N h The hth component is pre-transformed into the polar coded output bit sequence And determine the length to be N h The hth component of the interleaved output bit sequence To perform component interleaving, where Nh is the polarization matrix size In some embodiments, the first node obtains W=H components by interleaving the output bit sequence d′ (0)、 d' (1) , d' (2) ,…,d' (H-1) And determine the output bit sequence of length E = [e 0 ,e 1 ,…,e E-1 ] to perform the cascade, where Figure 4DA specific example is shown in FIG.

[0177] In some embodiments, the first node obtains an input bit sequence c of length K and determines H components to repeat the output bit sequence c. (0) 、c (1) 、c (2) ,…,c (H-1) To perform repetition, where for h = 0, 1, ..., H-1, the hth component repeats the output bit sequence The length is K h In some embodiments, for h=0, 1, 2, ..., H-1, the first node repeatedly outputs the bit sequence by obtaining the hth component And determine the length to be N h The polarization matrix of the hth component The corresponding h-th component polarization coded output bit sequence is To perform component polar coding, where N h yes In some embodiments, for h=0, 1, ..., W-1, the first node obtains a polarization matrix size of N h The h-th component polar coding output bit sequence And determine the length to be N h The hth component of the interleaved output bit sequence To perform component interleaving, where N h yes In some embodiments, the first node obtains the W component interleaved output bit sequence d' (0) , d' (1) , d' (2) ,…,d' (W-1) and HW component polarization coded output bit sequence d (W) d (W+1) ,…,d (H-1) to perform concatenation to determine the output bit sequence of length E = [e 0 ,e 1 ,…,e E-1 ],in, Figure 4E A specific example is shown in FIG.

[0178] In some embodiments, the first node obtains an input bit sequence c of length K and determines H components to repeat the output bit sequence c. (0) 、c (1) 、c (2) ,…,c (H-1) To perform repetition, where for h = 0, 1, ..., H-1, the hth component repeats the output bit sequence The length is Kh In some embodiments, for h=0, 1, 2, ..., H-1, the first node repeatedly outputs the bit sequence by obtaining the hth component And determine the length to be N h The polarization matrix of the hth component The corresponding polarization coded output bit sequence after pre-transformation of the hth component is To perform polar coding after component pre-transformation, where N h The polarization matrix size is In some embodiments, for h=0, 1, ..., W-1, the first node obtains a length of N h The hth component is pre-transformed into the polar coded output bit sequence And determine the length to be N h The hth component of the interleaved output bit sequence To perform component interleaving, where N h yes In some embodiments, the first node obtains the W component interleaved output bit sequence d' (0) , d' (1) , d' (2) ,…,d' (W-1) The polarization coded output bit sequence d after pre-transformation of HW components (W) d (W +1) ,…,d (H-1) to perform concatenation to determine the output bit sequence of length E = [e 0 ,e 1 ,…,e E-1 ],in, Figure 4F A specific example is shown in FIG.

[0179] In some embodiments, the first node polarizes and encodes the H components to output a bit sequence d (0) d (1) d (2) ,…,d (H-1) Component interleaving is performed on the W bit sequences to determine W component interleaved output bit sequences, where W is a non-negative integer not greater than H. Where H=3 component polar coded output bit sequences d (0) d (1) d (2) In the first specific example where W=2, the first node polarizes and encodes W=2 components to output a bit sequence d (0) d (2) Perform component interleaving to determine W component interleaved output bit sequences d' (0) , d' (2), where the 0th component interleaved output bit sequence d' (0) Corresponding to the polarization coded output bit sequence d of the 0th component (0) ; The second component interleaved output bit sequence d' (2) Corresponding to the second component polarization coded output bit sequence d (2) . In which H = 3 components polarization coding output bit sequence d (0) d (1) d (2) In the second specific example where W=1, the first node polarizes and encodes W=1 components to output a bit sequence d (1) Perform component interleaving to determine W = 1 component interleaved output bit sequence d' (1) , where the first component interleaved output bit sequence d' (1) Corresponding to the first component polarization coded output bit sequence d (1) .

[0180] In some embodiments, the first node outputs the polarization coding bit sequence d after the pre-transformation of the H components. (0) d (1) d (2) ,…,d (H-1) Component interleaving is performed on the W bit sequences to determine W component interleaved output bit sequences, where W is a non-negative integer not greater than H. Where H=3 component pre-transformed polar coded output bit sequences d (0) d (1) d (2) In the first specific example where W=2, the first node outputs the polarization coding bit sequence d after pre-transformation of W=2 components. (0) d (2) Perform component interleaving to determine W component interleaved output bit sequences d' (0) , d' (2) , where the 0th component interleaved output bit sequence d' (0) Corresponding to the polarization coded output bit sequence d after pre-transformation of the 0th component (0) ; The second component interleaved output bit sequence d' (2) Corresponding to the polarization coded output bit sequence d after pre-transformation of the second component (2) . In which H = 3 components, the polarization coded output bit sequence after pre-transformation is d (0) d (1) d (2) In the second specific example where W=1, the first node outputs the polarization coding bit sequence d after the W=1 component pre-transformation. (1) Perform component interleaving to determine W = 1 component interleaved output bit sequence d' (1), where the first component interleaved output bit sequence d' (1) Corresponding to the polarization coded output bit sequence d after pre-transformation of the first component (1) .

[0181] Example 4

[0182] This section discloses examples involving cascade blocks that can perform cascade operations.

[0183] Embodiment 4 is based on the embodiment disclosed above.

[0184] The input to the cascade operation may be based on the input sequence c.

[0185] In one example, a concatenation block may be associated with one or more component polar coding blocks.

[0186] In another example, the concatenation block may be associated with one or more component pre-transformed polar coding blocks.

[0187] In another example, a concatenation block may be associated with one or more component interleaving blocks.

[0188] An example of a cascade block is 4A to 4F shown.

[0189] The concatenation operation can combine multiple input sequences into an output sequence.

[0190] In one example, the concatenation includes: obtaining, by a first node, H concatenated input bit sequences x (0) 、x (1) , …, x (H -1) ; and the first node converts the output bit sequence of length E into [e 0 ,e 1 ,…,e E-1 ]Determined as

[0191] Here, E is the length of the output.

[0192] For h = 0, 1, ..., H-1, the hth concatenated input bit sequence The length is N h ; where N h is the size of the polarization matrix of the hth component.

[0193] The output length is equal to H concatenated input bit sequences x (0) 、x (1) , …, x (H-1) The sum of the lengths, that is, E = N 0 +N 1 +...+NH-1 .

[0194] In some embodiments, the concatenated input bit sequence x (h) is the component polarization coded output bit sequence, such as Figure 4A and Figure 4E as shown in the example.

[0195] In some embodiments, the concatenated input bit sequence x (h) is the polarization coded output bit sequence after component pre-transformation, such as Figure 4B and Figure 4F as shown in the example.

[0196] In some embodiments, the concatenated input bit sequence x (h) is the component interleaved output bit sequence, such as FIG. 4C to FIG. 4F as shown in the example.

[0197] In some embodiments, the HW concatenated input bit sequences are component polar coded output bit sequences and the W concatenated input bit sequences are component interleaved output bit sequences, where H is the number of component polar matrices and W is the number of component interleaving patterns.

[0198] In some embodiments, the HW concatenated input bit sequences are component pre-transformed polar coded output bit sequences, and the W concatenated input bit sequences are component interleaved output bit sequences, where H is the number of component polar matrices and W is the number of component interleaving patterns.

[0199] In the first specific example where H=3 and W=2, the 0th concatenated input bit sequence and the 1st concatenated input bit sequence are both component interleaved output bit sequences, and the 2nd concatenated input byte sequence is a component interleaved output bit sequence.

[0200] In the second specific example where H=3 and W=1, the 1st concatenated input bit sequence is a component interleaved output bit sequence, and the 0th and 2nd concatenated output bit sequences are both polarization coded output bit sequences after component pre-transformation.

[0201] Example 5

[0202] This section discloses examples involving interleaving operations.

[0203] Embodiment 5 is based on all the above embodiments.

[0204] One or more component interleaving blocks may be included in an encoding or decoding system.

[0205] The input to the component interleaving block is based on the input sequence c.

[0206] In one example, the component interleaving block may be associated with the component polarization coding block. In another example, the component interleaving block may be associated with the component pre-transformed polarization coding block.

[0207] In some embodiments, Figure 4C and Figure 4D As shown, the number of component interleaving patterns W is equal to the number of component polarization matrices H, and for h = 0, 1, ..., H-1, the h-th concatenated input bit sequence x (h) is of length N h The hth component of the interleaved output bit sequence Where N h is the size of the polarization matrix of the hth component.

[0208] Output bit sequence e = [e 0 ,e 1 ,…,e E-1 ] includes W = H components interleaved output bit sequence d' (0) , d' (1) ,…,d' (H-1) , where for h = 0, 1, ..., H-1, the hth component interleaved output bit sequence The length is equal to the size N of the polarization matrix of the hth component h .

[0209] In some embodiments, the output bit sequence e=[e 0 ,e 1 ,…,e E-1 ] is the H component interleaved output bit sequence d' (0) , d' (1) ,…,d' (H-1) The cascade is as follows:

[0210]

[0211] In another example, a component interleaving block may be associated with a concatenation block.

[0212] In some embodiments, the output bit sequence e=[e 0 ,e 1 ,…,e E-1 ] is the H component interleaved output bit sequence d' (0) , d' (1) ,…,d' (H-1) The cascade is as follows:

[0213]

[0214] Figure 4C and Figure 4DTwo specific examples of output bit sequence e are given, which is the H component output bit sequence d' (0) , d' (1) ,…,d' (H-1) cascade.

[0215] Example 6

[0216] This section discloses example systems that include component interleaving.

[0217] Example 6 is based on the above example.

[0218] In some embodiments, for h=0, 1, ..., W-1, the hth component interleaved output bit sequence d' (h) is the output bit sequence of the hth component interleaving, where the hth component interleaving consists of a length of N h The hth component interleaving pattern Determine, where N h is the size of the polarization matrix of the hth component. In some embodiments, using the method in Example 1, with the polarization matrix size N=N h To determine the hth component interleaving pattern J (h) , where N h is the size of the polarization matrix of the hth component. In some embodiments, using the method in Example 2, with the polarization matrix size N=N h To determine the hth component interleaving pattern J (h) , where N h is the size of the polarization matrix of the hth component.

[0219] The component interleaving pattern J = [J 0 ,J 1 ,…,J N-2 ,J N-1 ] The determined component interleaving includes:

[0220] The first node obtains a component interleaved input bit sequence d=[d 0 ,d 1 ,…,d N-1 ];as well as

[0221] The first node interleaves the components of length N to output a bit sequence d'=[d' 0 ,d' 1 ,…,d' N-1 ], determined as

[0222] d' i =d Ji ,i=0,1,2,...,N-2,N-1,

[0223] That is, the i-th bit of the interleaved output bit sequence d' is equal to the interleaved input bit sequence d = [d 0 ,d 1 ,…,d N-1 ] i bits, where the component interleaving pattern J can be any permutation of the integer sequence [0, 1, 2, …, N-2, N-1].

[0224] Example 1 : Component interleaving pattern J = [J 0 ,J 1 ,…,J N-2 ,J N-1 The first specific example of ] consists of a polarization matrix size N and a sub-block interleaving pattern π=[π 0 ,π 1 ,π 2 ,π 3 ,π 4 ,π 5 ,π 6 ,π 7 ,π 8 ,π 9 ,π 10 ,π 11 ,π 12 ,π 13 ,π 14 ,π 15 ,π 16 ,π 17 ,π 18 ,π 19 ,π 20 ,π 21 ,π 22 ,π 23 ,π 24 ,π 25 ,π 26 ,π 27 ,π 28 ,π 29 ,π 30 ,π 31 ]=[0,1,2,4,3,5,6,7,8,16,9,17,10,18,11,19,12,20,13,21,14,22,15,23,24,25,26,28,27,29,30,31] is determined as follows.

[0225]

[0226] Example 2 : Interlaced pattern J = [J 0 ,J 1 ,…,J N-2 ,JN-1 A second specific example of ] is that the index i is interleaved with the i-th element J in the pattern J. i The relationship between satisfies the following quadratic form:

[0227] J i =mod(f 1 ·i+f 2 ·i 2 ,N),

[0228] Among them, Table 1 summarizes the parameters f that depend on the polarization matrix size N. 1 and f 2 Some specific examples.

[0229] N <![CDATA[f 1 ]]> <![CDATA[f 2 ]]> 64 7 16 128 15 32 256 15 32 512 31 64 1024 31 64 2048 31 64 4096 31 64

[0230] Table 1 Interleaving parameters for Example 2

[0231] Example 3 : Where N = 8 component interleaving pattern J = [J 0 ,J 1 ,…,J N-2 ,J N-1 A third specific example of J = [J 0 ,J 1 ,J 2 ,J 3 ,J 4 ,J 5 ,J 6 ,J 7 ]=[5,4,7,1,6,0,2,3].

[0232] In some embodiments, for some h less than H, the following is equivalent to not having the hth component polarization matrix The corresponding components are interleaved:

[0233] For any value less than N h The non-negative integer i, the hth component interleaving pattern J (h) The i-th element of is equal to i, that is,

[0234] Therein, in other words, in this case the number of component interleaving patterns is considered to be smaller than the number of component polarization matrices.

[0235] Example 7

[0236] This section discloses examples involving using component interleaved input bit sequences as component polar coded output bit sequences.

[0237] Example 7 is based on Example 6.

[0238] In some embodiments, the input of component interleaving depends on the output of component polar coding. In other words, the output of component polar coding can be the input of component interleaving.

[0239] In some embodiments, Figure 4C and Figure 4E As shown, the component interleaved input bit sequence d of length N is a component polarization coded output bit sequence of length N, where N is the size of the component polarization matrix.

[0240] In some embodiments, for h=0, 1, ..., H-1, the output bit sequence d' is interleaved with the hth component (h) The corresponding h-th component interleaved input bit sequence is of length N h The h-th component polar coding output bit sequence is h is the size of the polarization matrix of the hth component, and Figure 4C A specific example is given in .

[0241] In some embodiments, for h=0, 1, ..., W-1, the output bit sequence d' is interleaved with the hth component (h) The corresponding h-th component interleaved input bit sequence is of length N h The h-th component polar coding output bit sequence is h is the size of the polarization matrix of the hth component; W is the number of component interleavings; Figure 4E A specific example is given in .

[0242] Example 8

[0243] This section discloses examples of output bit sequences including component polar coded output bit sequences.

[0244] Example 8 is based on the above example.

[0245] In some embodiments, Figure 4A As shown, for h = 0, 1, ..., H-1, the hth cascade input bit sequence x (h) is of length N h The h-th component polar coding output bit sequence Where N h is the size of the polarization matrix of the hth component. Output bit sequence e = [e 0 ,e 1 ,…,e E-1 ] includes H component polarization coded output bit sequences d (0) d (1) ,…,d (H-1), where for h = 0, 1, ..., H-1, the hth component polar coding output bit sequence is The length is equal to the size N of the polarization matrix of the hth component h .

[0246] In some embodiments, the output bit sequence e=[e 0 ,e 1 ,…,e E-1 ] is the H component polarization coded output bit sequence d (0) d (1) ,…,d (H-1) The cascade is as follows:

[0247]

[0248] In some embodiments, the output bit sequence e=[e 0 ,e 1 ,…,e E-1 ] is the H component polarization coded output bit sequence d (0) d (1) ,…,d (H-1) The cascade is as follows:

[0249]

[0250] Figure 4A A specific example of an output bit sequence e is given, where the output bit sequence e is an H-component polarization coded output bit sequence d (0) d (1) ,…,d (H-1) cascade.

[0251] Example 9

[0252] This section introduces examples involving component polar coding blocks.

[0253] Example 9 is based on the above example.

[0254] In some examples, the input to the polar coding block is based on the input sequence c.

[0255] In some examples, polar coded blocks are associated with repetition blocks.

[0256] In some examples, the polar coding block is associated with the concatenation block.

[0257] In some embodiments, for h=0, 1, ..., H-1, the length is N h The h-th component polar coding output bit sequence is the output of the h-th component polarization code, where the h-th component polarization code corresponds to the h-th component polarization matrix Among them, the hth component polarization coding is K h The hth component data bit index set Q (h) and size N h The h-th component polarization matrix Determine the polarization coded output bit sequence of the hth component Among them, K h is the hth component repetition length, and N h is the size of the polarization matrix of the hth component.

[0258] like Figure 5 As shown, the component polarization coding includes: obtaining a component polarization coding input bit sequence c'=[c' 0 ,c' 1 ,…,c' K'-1 ]; by the first node by using the component data bit index set Q'={Q' 0 ,Q' 1 ,…,Q' K'-1} to determine the added frozen bit output bit sequence u = [u 0 ,u 1 ,…,u N-1 ]; and by the first node by using a component polarization matrix G of size N (N) The polarization transformation of the component with length N is polarized and the output bit sequence d = [d 0 ,d 1 ,…,d N-1 ] is determined as d = u·G (N) .

[0259] Here, polarization conversion is to add frozen bits to output the bit sequence u = [u 0 ,u 1 ,…,u N-1 ] and the component polarization matrix G (N) The vector matrix is ​​multiplied on GF(2) to obtain the component polar coding output bit sequence d, that is, d = u·G (N) ; K' is the component repetition length; K' is a non-negative integer less than N; N is the component polarization matrix G (N) The size of the polarization matrix.

[0260] Added description of freeze bit operation

[0261] Determine the output bit sequence u = [u 0 ,u 1 ,…,u N-1 The operation of adding frozen bits includes obtaining a component polarization coded input bit sequence c'=[c'0 ,c' 1 ,…,c' K'-1 ]; by the first node by using the component data bit index set Q'={Q' 0 ,Q' 1 ,…,Q' K'-1} to determine the added frozen bit output bit sequence u = [u 0 ,u 1 ,…,u N-1 ].

[0262] Here, K can be the component repetition length; N is the component polarization matrix G (N) The size of the polarization matrix; Figure 5 A specific example is given in .

[0263] Description of component data bit index set Q'

[0264] In some embodiments, the component data bit index set Q' is a fourth type of integer set Z N = a subset of {0, 1, 2, ..., N-2, N-1}, where the fourth type integer set Z N = {0, 1, 2, ..., N-2, N-1} including and only including all non-negative integers less than N. Component data bit index set Q' = {Q' 0 ,Q' 1 ,…,Q' K'-1} has K' non-negative elements Q' 0 , Q' 1 ,…,Q' K-2 , Q' K-1 , that is, the size of the component data bit index set Q' is K'.

[0265] In some embodiments, for k=0, 1, ..., K-2, the element Q' in the component data bit index set Q' k Less than Q' k+1 , that is, the component data bits are indexed to Q' according to the index value Q' 0< Q' 1< ... < Q' K'-2< Q' K'-1 In some embodiments, for k=0, 1, ..., K-2, the Q'th k polarization subchannel (denoted as W(Q' k )) is less reliable than Q' k+1 polarization subchannel (denoted as W(Q' k+1 ), that is, the component data bit index set Q' is calculated according to the reliability of the polarization subchannel according to W(Q' 0) <W(Q' 1 )<... <W(Q' K'-2 ) <W(Q' K'-1 ) in ascending order. In some embodiments, for k=0, 1, ..., K-2, the element Q' in the component data bit index set Q' k Greater than Q' k+1 , that is, the component data bit index set Q' is sorted by the index value Q' 0> Q' 1> ... > Q' K'-2> Q' K'-1 In some embodiments, for k=0, 1, ..., K-2, the Q'th k polarization subchannel (denoted as W(Q' k )) is more reliable than Q' k+1 polarization subchannel (denoted as W(Q' k+1 ), that is, the component data bit index set Q' is calculated according to the reliability of the polarization subchannel according to W(Q' 0 ) > W(Q' 1 ) > ... > W(Q' K'-2 ) > W(Q' K'-1 ) in descending order.

[0266] In the first specific example where N=8 and K=4, the component data bit index set is Q'={Q' 0 ,Q' 1 ,Q' 2 ,Q' 3}={3,5,6,7}. In the second specific example where N=32 and K=25, the component data index set is Q′={Q′ 0 ,Q' 1 ,Q' 2 ,Q' 3 ,Q' 4 ,Q' 5 ,Q' 6 ,Q' 7 ,Q' 8 ,Q' 9 ,Q' 10 ,Q' 11 ,Q' 12 ,Q' 13 ,Q' 14 ,Q' 15 ,Q' 16 ,Q' 17 ,Q' 18 ,Q'19 ,Q' 20 ,Q' 21 ,Q' 22 ,Q' 23 ,Q' 24}={5,9,6,17,10,18,12,20,24,7,11,19,13,14,21,26,25,22,28,15,23,31,27,29,30}, where the polarimetric channel reliability is calculated according to W(Q' 0 ) <W(Q' 1 ) <W(Q' 2 ) <W(Q' 3 ) <W(Q' 4 ) <W(Q' 5 ) <W(Q' 6 ) <W(Q' 7 ) <W(Q' 8 ) <W(Q' 9 ) <W(Q' 10 ) <W(Q' 11 ) <W(Q' 12 ) <W(Q' 13 ) <W(Q' 14 ) <W(Q' 15 ) <W(Q' 16 ) <W(Q' 17 ) <W(Q' 18 ) <W(Q' 19 ) <W(Q' 20 ) <W(Q' 21 ) <W(Q' 22 ) <W(Q' 23 ) <W(Q' 24 In the third specific example where N=8 and K′=4, the component data bit index set is Q′={Q′ 0 ,Q' 1 ,Q' 2 ,Q' 3}={7,6,5,3}.

[0267] In some embodiments, according to the component data bit index set Q', the add frozen bit operation determines the same as the add frozen bit input bit sequence c'=[c' 0 ,c' 1 ,…,c' K'-1 ] The corresponding added frozen bits output bit sequence u=[u 0 ,u 1 ,…,u N-1 ] as shown below.

[0268]

[0269] The specific example pseudo code for adding the frozen bit operation is as follows.

[0270]

[0271] In some embodiments, for index i belonging to component data bit index set Q', bit u in output bit sequence u is added with frozen bits i is set to add frozen bits to the bits in the input bit sequence c'.

[0272] Where N = 8, K' = 3 and component data bit index set Q' = {5, 6, 7}, add frozen bit input bit sequence c' = [c' 0 ,c' 1 ,c' 2 In the first specific example of ], after adding the frozen bits, the output bit sequence u=[u 0 ,u 1 ,u 2 ,u 3 ,u 4 ,u 5 ,u 6 ,u 7 ] is the bit u whose index belongs to the component data bit index set Q' = {5,6,7} 5 、u 6 、u 7 Set to u 5 =c' 0 、u 6 =c' 1 , and u 7 =c' 2 .

[0273] Where N = 16, K' = 6 and component data bit index set Q' = {12, 7, 11, 13, 14, 15}, add frozen bit input bit sequence c' = [c' 0 ,c' 1 ,c' 2 ,c' 3 ,c' 4 ,c' 5 In the second specific example of ], after adding the frozen bits, the output bit sequence u=[u 0 ,u 1 ,u 2 ,u 3 ,u 4 ,u 5 ,u 6 ,u 7 ,u 8 ,u 9 ,u10 ,u 11 ,u 12 ,u 13 ,u 14 ,u 15 ] is the bit u whose index belongs to the data bit index set Q' = {12,7,11,13,14,15} 12 、u 7 、u 11 、u 13 、u 14 、u 15 Set to u 12 =c' 0 、u 7 =c' 1 、u 11 =c' 2 、u 13＝ c' 3 、u 14 =c' 4 , and u 15 =c' 5 The third specific example is as follows:

[0274]

[0275] In some embodiments, for index i that does not belong to the component data bit index set Q', bit u in the output bit sequence u is added as frozen bit i is equal to 0.

[0276] In the first specific example where N=8, K′=3 and Q′={5,6,7}, the frozen bit output bit sequence u=[u 0 ,u 1 ,u 2 ,u 3 ,u 4 ,u 5 ,u 6 ,u 7 ] is the bit u whose index does not belong to the component data bit index set Q' = {5,6,7} 0 、u 1 、u 2 、u 3 、u 4 Set to u 0 =0,u 1＝ 0.u 2 =0,u 3 = 0, and u 4 =0.

[0277] In the second specific example where N=16, K′=6 and Q′={7, 11, 12, 13, 14, 15}, the frozen bit output bit sequence u=[u 0 ,u 1 ,u 2 ,u 3 ,u 4 ,u 5 ,u 6 ,u 7 ,u 8 ,u 9 ,u 10 ,u 11 ,u 12 ,u 13 ,u 14 ,u 15 ] is the bit u whose index does not belong to the component data bit index set Q' = {7, 11, 12, 13, 14, 15} 0 、u 1 、u 2 、u 3 、u 4 、u 5 、u 6 、u 8 、u 9 、u 10 Set to u 0 =0,u 1＝ 0.u 2 =0,u 3 =0,u 4 =0,u 5 =0,u 6 =0,u 8 =0,u 9 = 0, and u 10 = 0. The third specific example is as follows:

[0278]

[0279] In some embodiments, the added frozen bits output bit sequence u is a multiplex of the added frozen bits input bit sequence c' and an all-zero sequence of length N-K', where N is the polarization matrix size and K' is the added frozen bits input bit sequence length.

[0280] A first specific example with N=8 and K'=3 is to add a frozen bit input bit sequence c'=[c' 0 ,c' 1 ,c' 2 ] and a zero sequence of length N-K'=8-3=5, then add the frozen bits to output the bit sequence u=[u 0 ,u 1,u 2 ,u 3 ,u 4 ,u 5 ,u 6 ,u 7 ]=[0,0,0,0,0,c 0 ,c 1 ,c 2 ].

[0281] A second specific example where N=16 and K'=4 is to add a frozen bit input bit sequence c'=[c' 0 ,c' 1 ,c' 2 ,c' 3 ,c' 4 ,c' 5 ] and a zero sequence of length N-K'=16-4=12, then add the frozen bits to output the bit sequence u=[u 0 ,u 1 ,u 2 ,u 3 ,u 4 ,u 5 ,u 6 ,u 7 ,u 8 ,u 9 ,u 10 ,u 11 ,u 12 ,u 13 ,u 14 ,u 15 ]=[0,0,0,0,0,0,0,0,0,0,c 0 ,0,c 1 ,c 2 ,c 3 ] was determined.

[0282] Example 10

[0283] This section discloses examples involving using a component interleaved input bit sequence as a component pre-transformed polarization coded output bit sequence.

[0284] Embodiment 10 is based on the above-mentioned related embodiments.

[0285] In some embodiments, the input of component interleaving depends on the output of polarization coding after component pre-transformation. In other words, the output of polarization coding after component pre-transformation can be the input of component interleaving.

[0286] In one example, the component interleaved input bit sequence d of length N is a component pre-transformed polarization coded output bit sequence of length N, where N is the component polarization matrix size.

[0287] In some embodiments, for h=0, 1, ..., H-1, the output bit sequence d' is interleaved with the hth component (h) The corresponding h-th component interleaved input bit sequence is of length N h The hth component is pre-transformed into the polar coded output bit sequence Where N h is the size of the polarization matrix of the hth component, and a specific example is Figure 4D Given in.

[0288] In some embodiments, for h=0, 1, ..., W-1, the output bit sequence d' is interleaved with the hth component (h) The corresponding h-th component interleaved input bit sequence is of length N h The hth component is pre-transformed into the polar coded output bit sequence Among them, N h is the size of the hth component polarization matrix, W is the number of component interleavings; a specific example is Figure 4F Given in.

[0289] Embodiment 11

[0290] This section discloses examples of output bit sequences including polarization coded output bit sequences after component pre-transformation.

[0291] Embodiment 11 is based on the above-mentioned related embodiments.

[0292] In some embodiments, Figure 4B As shown, for h = 0, 1, ..., H-1, the hth cascade input bit sequence x (h) is of length N h The hth component is pre-transformed into the polar coded output bit sequence Among them, N h is the size of the polarization matrix of the hth component. The output bit sequence e = [e 0 ,e 1 ,…,e E-1 ] includes the polarization coded output bit sequence d after H components are pre-transformed (0) d (1) ,…,d (H-1) , where for h = 0, 1, ..., H-1, the polar coding output bit sequence after the hth component pre-transformation is The length is equal to the size N of the polarization matrix of the hth component h .

[0293] In some embodiments, the output bit sequence e=[e 0 ,e 1 ,…,eE-1 ] is the polarization coded output bit sequence after H components are pre-transformed d (0) d (1) ,…,d (H-1) The cascade is as follows:

[0294]

[0295] In some embodiments, the output bit sequence e=[e 0 ,e 1 ,…,e E-1 ] is the polarization coded output bit sequence after H components are pre-transformed d (0) d (1) ,…,d (H-1) The cascade is as follows:

[0296]

[0297] Figure 4B A specific example of an output bit sequence e is given, where the output bit sequence e is the polarization coded output bit sequence d after H components are pre-transformed. (0) d (1) ,…,d (H-1) cascade.

[0298] Example 12

[0299] This section discloses examples involving polar coding after component pre-transformation.

[0300] Example 12 is based on the above example.

[0301] In some embodiments, for h=0, 1, ..., H-1, the length is N h The hth component is pre-transformed into the polar coded output bit sequence is the output of the polarization coding of the hth component after pre-transformation, where the polarization coding of the hth component after pre-transformation corresponds to the polarization matrix of the hth component The polar coding of the hth component after pre-transformation is determined by at least one of the following items:

[0302] 1) Size is K h The hth component data bit index set Q (h) ,

[0303] 2) The h-th component generating polynomial g on GF(2) (h) (D)

[0304] 3) The h-th component recursive feedback polynomial q on GF(2)(h) (D) or

[0305] 4) Size is N h The h-th component polarization matrix

[0306] Here, K h is the hth component repetition length, and N h is the size of the polarization matrix of the hth component.

[0307] like Figure 6 As shown, the polarization coding after component pre-transformation includes: obtaining a polarization coding input bit sequence c'=[c' 0 ,c' 1 ,…,c' K'-1 ]; and by the first node by using a component data bit index set Q'={Q' 0 ,Q' 1 ,…,Q' K'-1} rate configuration to determine the rate configuration output bit sequence v = [v 0 ,v 1 ,…,v N-1 ]; and determining, by the first node, a pre-transformation output bit sequence u=[u 0 ,u 1 ,…,u N-1 ]:The component generating polynomial g(D)=g on GF(2) 0+ g 1 ·D+...+g m ·D m , component recursive feedback polynomial q(D) = q 0+ q 1 ·D+...+q m ·D m ; and by the first node by using a component polarization matrix G of size N (N) Polarization transformation is performed to convert the component of length N into a polarization coded output bit sequence d = [d 0 ,d 1 ,…,d N-1 ] is determined as d = u·G (N) .

[0308] Here, polarization conversion is the pre-conversion output bit sequence u = [u 0 ,u 1 ,…,u N-1 ] and the component polarization matrix G on GF(2) (N) The vector matrix of is multiplied to obtain the component polar coding output bit sequence d, that is, d = u·G(N) ; K' is the component repetition length; K' is a non-negative integer less than N; N is the component polarization matrix G (N) The size of the polarization matrix.

[0309] Description of rate configuration

[0310] Rate configuration is the same operation as adding frozen bits, where the component polar coding input bit sequence is the polar coding output bit sequence c'=[c' 0 ,c' 1 ,…,c' K'-1 ]; add frozen bits; the output bit sequence is the rate configuration output bit sequence v = [v 0 ,v 1 ,…,v N-1 ].

[0311] Pre-transformation instructions

[0312] The pre-conversion in the polar coding after the component pre-conversion includes: obtaining a pre-conversion input bit sequence with a length of N by the first node, and determining the pre-conversion output bit sequence u=[u 0 ,u 1 ,…,u N-1 ]:The component generating polynomial g(D)=g on GF(2) 0+ g 1 ·D+...+g m ·D m , component recursive feedback polynomial q(D) = q 0+ q 1 ·D+...+q m ·D m .

[0313] Here, N is the component polarization matrix size; m is the component memory length; the pre-transformed input bit sequence is the rate-configured output bit sequence v = [v 0 ,v 1 ,…,v N-1 ]; among them Figure 6 A specific example is given in .

[0314] Pre-transformation using the generator polynomial g(D) or the generator bit sequence g

[0315] In some embodiments, the pre-transformation is based on a generating polynomial g(D)=g 0 +g 1 ·D+g 2 ·D+···+g m-1 ·D+g mD (or equivalently, generate the bit sequence g = [g 0 ,g 1 ,g 2 ,...,g m-1 ,g m ]), determine the pre-transformed input bit sequence v = [v 0 ,v 1 ,...,v N-1 ] corresponds to the pre-transformation output bit sequence u, where m is called the memory length of the generating polynomial g(D) (or the generating bit sequence g).

[0316] Generator polynomial g(D) = g 0 +g 1 ·D+...+g m-1 ·D m-1 +g m ·D m It can be any bivariate polynomial over GF(2), where m is the polynomial order or memory length. In the specific example of memory length m=6, the generating polynomial is g(D)=g 0 +g 1 ·D+g 2 ·D 2 +g 3 ·D 3 +g 4 ·D 4 +g 5 ·D 5 +g 6 ·D 6 =1+0·D+1·D 2 +1·D 3 +0·D 4 +1·D 5 +1·D 6 =1+D 2 +D 3 +D 5 +D 6 In another specific example where the memory length is m=3, the generating polynomial is g(D)=g 0 +g 1 ·D+g 2 ·D 2 +g 3 ·D 3 =1+1·D+0·D 2 +1·D 3 =1+D+D 3 . Generate a bit sequence g = [g 0 ,g 1 ,...,g mcan be any binary sequence of length m + 1, where m is referred to as the memory length. In a specific example where the memory length m = 6, the generated bit sequence is g = [g 0 , g 1 , g 2 , g 3 , g 4 , g 5 , g 6 = [1, 0, 1, 1, 0, 1, 1]. In another specific example where the memory length m = 3, the generated bit sequence is g = [g 0 , g 1 , g 2 , g 3 = [1, 1, 0, 1].

[0317] Figure 3 shows a specific schematic diagram of the pre - transformation performed using the generating polynomial g(D) = g 0 + g 1 ·D +... + g m-1 ·D m-1 + g m ·D m (or the generated bit sequence g = [g 0 , g 1 ,..., g m ), where the bit u i at index i in the pre - transformation output bit sequence u is determined by the m + 1 bits v i , v i-1 , v i-2 ,..., v i-m with consecutive indices i, i - 1, i - 2,..., i - m in the pre - transformation input bit sequence v and the generating polynomial g(D) = g 0 + g 1 ·D +... + g m-1 ·D m-1 + g m ·D m (or the generated bit sequence g = [g 0 , g 1 ,..., g m ) as:

[0318]

[0319] where the summation and multiplication are performed over GF(2); for i < k, the bit v i-k = 0; g k is the generating polynomial g(D) = g 0 + g 1 ·D + … + gm-1 ·D m-1 +g m ·D m The coefficient of the k-th term in (or equivalently, the generated bit sequence g = [g 0 ,g 1 ,…,g m ] is the bit indexed by k in ). The specific pseudo code is as follows.

[0320]

[0321] Pre-transformation using a recursive feedback polynomial q(D) or a recursive feedback sequence q

[0322] In some embodiments, the pre-transform is performed according to a recursive feedback polynomial (or equivalently, a recursive feedback bit sequence q=[q 0 ,q 1 ,q 2 ,…,q m-1 ,q m ]) to determine the pre-transformed output bit sequence u corresponding to the pre-transformed input bit sequence v, where m is called the memory length of the recursive feedback polynomial q(D) (or the recursive feedback bit sequence q).

[0323] Recursive feedback polynomial q(D) = q 0 +q 1 ·D+…+q m-1 ·D m-1 +q m ·D m is a two-variable polynomial, where the zero-order coefficient q 0 is 1 and the other coefficients q 1 ,…,q m is any binary value over GF(2), where m is the memory length.

[0324] In the specific example of memory length m=6, the recursive feedback polynomial is q(D)=q 0 +q 1 ·D+q 2 ·D 2 +q 3 ·D 3 +q 4 ·D 4 +q 5 ·D 5 +q 6 ·D 6 =1+0·D+1·D 2 +0·D 3 +1·D 4 +1·D 5 +1·D 6 =1+D 2 +D4 +D 5 +D 6 In another specific example where the memory length is m=3, the recursive feedback polynomial is q(D)=q 0 +q 1 ·D+q 2 ·D 2 +q 3 ·D 3 =1+0·D+1·D 2 +1·D 3 =1+D 2 +D 3 . Recursive feedback bit sequence q = [q 0 ,q 1 ,…,q m ] is a binary sequence of length m+1, where [q 1 ,...,q m ] can be of length m and q 0 = 1, where m is the memory length. In the specific example of memory length m = 3, the recursive feedback bit sequence is q = [q 0 ,q 1 ,q 2 ,q 3 ,q 4 ,q 5 ,q 6 ]=[1,0,1,0,1,1,1]. In another specific example where the memory length m=3, the recursive feedback bit sequence is q=[q 0 ,q 1 ,q 2 ,q 3 ]=[1,0,1,1].

[0325] Figure 7 shows the use of a recursive feedback polynomial q(D)=q with q0=1 and a memory length of m. 0 +q 1 ·D+…+q m-1 ·D m-1 +q m ·D m (Or equivalently, the recursive feedback bit sequence q = [q 0 ,q 1 ,q 2 ,…,q m-1 ,q m ]) is a specific schematic diagram of the pre-transformation performed, wherein the bit u indexed as i in the pre-transformation output bit sequence u is i Determined by:

[0326] 1) The bit v at index i in the pre-transform input bit sequence v i ,

[0327] 2) The first m bits u with consecutive indices i-1, i-2, …, i-m in the pre-transform output bit sequence u i-1 , u i-2 , …, u i-m , and / or

[0328] 3) Where q 0 = 1, the recursive feedback polynomial q(D) = q 0 + q 1 ·D + … + q m-1 ·D m-1 + q m ·D m (or the recursive feedback bit sequence q = [q 0 , q 1 , …, q m ),

[0329] Here, a specific example is where both the summation and multiplication are performed over GF(2); for i < k, the bit u i-k = 0; q k is the coefficient of the k-th term in the recursive feedback polynomial q(D) = q 0 + q 1 ·D + … + q m-1 ·D m-1 + q m ·D m (or equivalently, the bit at index k in the recursive feedback bit sequence q = [q 0 , q 1 , …, q m ). The specific pseudocode is as follows.

[0330]

[0331] Using both the generator polynomial g(D) and the recursive feedback polynomial q(D) (or generating the bit sequence g and the recursive feedback bit sequence q)

[0332] In some embodiments, the pre-transform is based on the generating polynomial g(D) = g 0 + g 1 ·D + … + g m-1 ·D + g m ·D and the recursive feedback polynomial q(D) = q 0 + q 1 ·D + … + q m-1 ·D m-1 + q m ·D mBoth (or equivalently, generate the bit sequence g = [g 0 ,g 1 ,g 2 ,…,g m-1 ,g m ] and the recursive feedback bit sequence q = [q 0 ,q 1 ,…,q m-1 ,q m ] both) to determine the pre-transformed output bit sequence u corresponding to the pre-transformed input bit sequence v, where m is called the memory length of both the generating polynomial g(D) and the recursive feedback polynomial q(D) (or equivalently, both the generating bit sequence g and the recursive feedback bit sequence q).

[0333] Generator polynomial g(D) = g 0 +g 1 ·D+…+g m-1 ·D m-1 +g m ·D m can be any bivariate polynomial over GF(2), where m is the polynomial order or memory length.

[0334] In a specific example with a memory length of m=6, the generating polynomial is g(D)=g 0 +g 1 ·D+g 2 ·D 2 +g 3 ·D 3 +g 4 ·D 4 +g 5 ·D 5 +g 6 ·D 6 =1+0·D+1·D 2 +1·D 3 +0·D 4 +1·D 5 +1·D 6 =1+D 2 +D 3 +D 5 +D 6 In another specific example where the memory length is m=3, the generating polynomial is g(D)=g 0 +g 1 ·D+g 2 ·D 2 +g 3 ·D 3 =1+1·D+0·D 2 +1·D 3 =1+D+D 3. Generate a bit sequence g = [g 0 ,g 1 ,...,g m ] can be any binary sequence of length m+1, where m is called the memory length. In the specific example of memory length m=6, the generated bit sequence is g=[g 0 ,g 1 ,g 2 ,g 3 ,g 4 ,g 5 ,g 6 ]=[1,0,1,1,0,1,1].

[0335] In another specific example where the memory length is m=3, the generated bit sequence is g=[g 0 ,g 1 ,g 2 ,g 3 ]=[1,1,0,1]. Recursive feedback polynomial q(D)=q 0 +q 1 ·D+...+q m-1 ·D m-1 +q m ·D m is a two-variable polynomial, where the zero-order coefficient q 0 is 1, and the other coefficients q 1 ,…,q m is any binary value on GF(2), where m is the memory length. In the specific example of memory length m=6, the recursive feedback polynomial is q(D)=q 0 +q 1 ·D+q 2 ·D 2 +q 3 ·D 3 +q 4 ·D 4 +q 5 ·D 5 +q 6 ·D 6 =1+0·D+1·D 2 +0·D 3 +1·D 4 +1·D 5 +1·D 6 =1+D 2 +D 4 +D 5 +D 6 In another specific example where the memory length is m=3, the recursive feedback polynomial is q(D)=q 0 +q 1 ·D+q 2·D 2 +q 3 ·D 3 =1+0·D+1·D 2 +1·D 3 =1+D 2 +D 3 . Recursive feedback bit sequence q = [q 0 ,q 1 ,...,q m ] is a binary sequence of length m+1, where [q 1 ,…,q m ] can be of length m and q 0 = 1, where m is the memory length. In the specific example of memory length m = 3, the recursive feedback bit sequence is q = [q 0 ,q 1 ,q 2 ,q 3 ,q 4 ,q 5 ,q 6 ]=[1,0,1,0,1,1,1]. In another specific example where the memory length m=3, the recursive feedback bit sequence is q=[q 0 ,q 1 ,q 2 ,q 3 ]=[1,0,1,1].

[0336] Figure 8 It shows that the use of the generating polynomial g(D) = g 0 +g 1 ·D+…+g m-1 ·D m-1 +g m ·D m Schematic diagram of pre-transformation performed on both and the recursive feedback polynomial q(D) (or equivalently, both the generated bit sequence g and the recursive feedback bit sequence q).

[0337] Here, the pre-transformation determines the bit u with index i in the pre-transformation output bit sequence u. i The first node converts the state bit sequence t=[t 0 ,t 1 ,t 2 ,...,t m ] bit t with index 0 in 0 Set the pre-transform input bit sequence v = [v 0 ,v 1 ,v 2 ,...,v N-1 ] bit v with index i i , that is, t0 =v i ; and the first node through the recursive feedback polynomial q(D) = q on GF(2) 0 +q 1 ·D+...+q m ·D m (or equivalently, the feedback bit sequence q = [q 0 ,q 1 ,...,q m ]) and the updated state bit sequence t=[t 0 ,t 1 ,t 2 ...,t m-1 ,t m ] to determine the sum bit s as The first node sets the state bit sequence t=[t 0 ,t 1 ,t 2 ...,t m-1 ,t m ] bit t with index 0 in 0 Set to sum bit s, ie t 0 =s; and from the first node through the generating polynomial g(D)=g on GF(2) 0 +g 1 ·D+…+g m ·D m (or equivalently, generate the bit sequence g = [g 0 ,g 1 ,…,g m ]) and the updated state bit sequence t=[t 0 ,t 1 ,t 2 ...,t m-1 ,t m ], the pre-transformed output bit sequence u = [u 0 ,u 1 ,u 2 ,...,u N-1 ] bit u with index i i Determined as And the first node performs the state bit sequence t=[t 0 ,t 1 ,...,t m-1 ,t m ] performs a right shift, where the state bit sequence t = [t 0 ,t 1 ,...,t m-1 ,t m ] bit t with index 0 in 0 is set to 0 as shown below.

[0338]

[0339] The specific pseudo code of the above steps is as follows.

[0340]

[0341]

[0342] Example 13

[0343] This section discloses examples of using a repeated output bit sequence as an input bit sequence for component polar coding.

[0344] Example 13 is based on the above example.

[0345] In some embodiments, for h=0, 1, ..., H-1, the length is K h The hth component polar coded input bit sequence is the h-th component repeated output bit sequence, where the h-th component polarization coded input bit sequence corresponds to the h-th component polarization matrix N h is the size of the h-th polarization matrix; K h is the hth component repetition length; H components are repeated to output the bit sequence c (0) 、c (1) ,…,c (H-1) is a repeated output.

[0346] Embodiment 14

[0347] This section discloses examples involving using a repeated output bit sequence as a polar coded input bit sequence after component pre-transformation.

[0348] Example 14 is based on Example 12.

[0349] In some embodiments, for h=0, 1, ..., H-1, the length is K h The h-th pre-transformed component polar coding input bit sequence is the h-th component repeated output bit sequence, where the h-th component pre-transformed polarization coded input bit sequence corresponds to the h-th component polarization matrix N h is the size of the h-th polarization matrix; K h is the hth component repetition length; H components are repeated to output the bit sequence c (0) 、c (1) ,…,c (H-1) is a repeated output.

[0350] Embodiment 15

[0351] This section discloses examples related to repeating blocks.

[0352] Example 15 is based on the above-mentioned related embodiments.

[0353] In some embodiments, the repetition includes: obtaining, by the first node, an input bit sequence c=[c 0 ,c 1 ,…,c K-1 ]; and the first node determines the H component repeated output bit sequence c by at least one of the following items: (0) 、c (1) ,…,c (H-1) :H components repetition length K 0 , K 1 , …, K H-1 , H components repeated index set R (0) , R (1) , …, R (H -1) .

[0354] Here, for h = 0, 1, ..., H-1, the hth component repeats the output bit sequence The length is K h

[0355] In some embodiments, for h=0, 1, ..., H-1, the bit sequence c is repeatedly output by repeatedly taking the hth component (h) The kth bit in Set as input bit sequence c = [c 0 ,c 1 ,...,c K-1 ] is indexed as bits to determine the hth component repeated output bit sequence c (h) ,Right now, The pseudo code is as follows.

[0356]

[0357] Where K = 6, the input bit sequence c = [c 0 ,c 1 ,c 2 ,c 3 ,c 4 ,c 5 ], H = 2 component repeated index set R (0) ={0,1,2,3,4,5}(where K 0 =6), and R (1)={0,1,2}(where K 1 =3), the 0th component repeatedly outputs the bit sequence The first component repeats the output bit sequence

[0358] Where K = 6, the input bit sequence c = [c 0 ,c 1 ,c 2 ,c 3 ,c 4 ,c 5 ], H = 3 component repeated index set R (0) ={0,1,2,3,4,5}(where K 0 =6) R (1) ={0,1,2}(where K 1 =3) and R (2) ={4}(where K 2 = 1), the 0th component repeatedly outputs the bit sequence

[0359] The first component repeats the output bit sequence The second component repeats the output bit sequence

[0360] Where K = 6, the input bit sequence c = [c 0 ,c 1 ,c 2 ,c 3 ,c 4 ,c 5 ], H = 3 component repeated index set R (0) ={0,1,2,4,3}(where K 0 =5) R (1) ={0,5}(where K 1 =2) and R (2) ={4}(where K 2 = 1), the 0th component repeatedly outputs the bit sequence The first component repeats the output bit sequence The second component repeats the output bit sequence

[0361] In some embodiments, the repetition includes: obtaining, by the first node, an input bit sequence c=[c 0 ,c 1 ,…,cK-1 ]; and the first node uses the first data bit index set Q to perform the input bit sequence c=[c 0 ,c 1 ,…,c K-1 ] performs the add frozen bit operation to obtain a repetition rate configuration output bit sequence v'=[v' 0 ,v' 1 ,…,v' N-1 ]; and the first node determines the H component repeated output bit sequence c by at least one of the following items: (0) 、c (1) ,…,c (H-1) : The first data bit index set Q = {Q 0 ,Q 1 ,…,Q K-1}, H components have a repetition length of K 0 , K 1 , …, K H-1 .

[0362]

[0363] Here, for h = 0, 1, ..., H-1, the hth component repeats the output bit sequence The length is K h .

[0364] In some embodiments, for h=0, 1, ..., H-1, the bit sequence c is repeatedly output by repeating the h components. (h) The kth bit in Set to repetition rate configuration output bit sequence v' = [v' 0 ,v' 1 ,...,v' N-1 ] index is Q k bits to determine the hth component repeated output bit sequence c (h) ,Right now The pseudo code is as follows.

[0365]

[0366] Where K = 6, the input bit sequence c = [c 0 ,c 1 ,c 2 ,c 3 ,c 4 ,c 5 ], H = 2 polarization matrix size N 0 =16 and N 1＝ 8. First data bit index set Q = {12, 7, 11, 13, 14, 15}, K0 =6, K 1 =3, we get a length of N=max(N 0 ,N 1 )=16 repetition rate configuration output bit sequence v'=[v' 0 ,v' 1 ,...,v' N-1 ]=[v' 0 ,v' 1 ,v' 2 ,v' 3 ,v' 4 ,v' 5 ,v' 6 ,v' 7 ,v' 8 ,v' 9 ,v' 10 ,v' 11 ,v' 12 ,v' 13 ,v' 14 ,v' 15 ], then we get the 0th component repeated output bit sequence

[0367] And the first component repeats the output bit sequence

[0368] In some embodiments, the H repeated output bit sequences c (0) 、c (1) ,…,c (H-1) The at least two repetitive output bit sequences include a repetitive rate configuration output bit sequence v'=[v' 0 ,v' 1 ,…,v' N-1 Q in ] k Bits Wherein k is a non-negative integer less than the size of the first data bit index set Q; Q k is the kth element in the first data bit index set Q.

[0369] A specific example is all the repeated output bit sequences c (0) 、c (1) 、c (H-1) The repetition rate configuration output bit sequence v'=[v' 0 ,v' 1 ,…,v' N-1 Q in ] 0 Bits One specific example is

[0370] In some embodiments, the H repeated output bit sequences c (0) 、c (1) ,…,c (H-1) The at least two repeated output bit sequences include an input bit sequence c=[c 0 ,c 1 ,…,c K-1 The kth bit c in ] k A specific example is all the repeated output bit sequences c (0) 、c (1) 、c (H-1) The output bit sequence c=[c 0 ,c 1 ,…,c K-1 ]'s 0th bit c 0 , a specific example of which is

[0371] In some embodiments, the H repeated output bit sequences c (0) 、c (1) ,…,c (H-1) At least two repeated output bit sequences have the same length, that is, there exists h≠k such that K h =K k , where for h = 0, 1, ..., H-1, K h is the hth repeated output bit sequence c (h) In the specific example where H=3, all repeated output bit sequences c (0) c (1) c (2) The length is K 0 =K 1 =K 2 =2.

[0372] In some embodiments, not all repeated output bit sequences c (0) 、c (1) ,…,c (H-1) have the same length, that is, there exists h≠k such that K h ≠K k , where K h Output bit sequence c for the hth repetition (h) The length of K k Output bit sequence c for the kth repetition (k) In the specific example where H=3, the 0th repetition outputs the bit sequence c (0) The length is K0 =6, and the first repeated output bit sequence c (1) The length is K 1 =3, where K 0 ≠K 1 .

[0373] In some embodiments, all repeated output bit sequences c (0) 、c (1) ,…,c (H-1) have different lengths, i.e., if h≠k, then K h ≠K k Among them, K h is the hth repeated output bit sequence c (h) The length of K k is the kth repeated output bit sequence c (k) In the specific example where H=3, the 0th repetition outputs the bit sequence c (0) The length is K 0 =6, the first repeated output bit sequence c (1) The length is K 1 =3, and the second repeated output bit sequence c (2) The length is K 2 =1, where K 0 ≠K 1 , K 0 ≠K 2 , and K 1 ≠K 2 .

[0374] Example 16

[0375] This section discloses examples involving output bit sequences including component interleaved output bit sequences and component polarization coded output bit sequences.

[0376] Example 16 is based on the above example.

[0377] In some embodiments, for h=0, 1, ..., W-1, the hth concatenated input bit sequence x (h) is of length N h The hth component of the interleaved output bit sequence For h = W, W+1, ..., H-1, the hth cascade input bit sequence x (h) is the hth component polar coding output bit sequence Among them, N h The hth component polarization matrix size; W is the number of component interleaving patterns or the number of component interleavings; H is the number of component polarization matrices. In some embodiments, the output bit sequence e = [e 0 ,e1 ,...,e E-1 ] includes a component interleaved output bit sequence d' for some h's (h) and the polar coded output bit sequence d for the remaining h's components (h) , where the hth component interleaved output bit sequence The length of is equal to the size of the polarization matrix N of the hth component h ; The hth component polarization coded output bit sequence The length of is equal to the size of the polarization matrix N of the hth component h In a specific example, the output bit sequence e = [e 0 ,e 1 ,…,e E-1 ] is the W component interleaved output bit sequence d' (1) , d' (2) ,…,d' (W-1) and HW component polarization coded output bit sequence d (W) d (W+1) ,…,d (H-1) The cascade is as follows:

[0378]

[0379] Figure 4E A specific example of an output bit sequence e is given, which is the concatenation of a component interleaved output bit sequence and a component polarization coded output bit sequence.

[0380] Embodiment 17

[0381] This section discloses examples involving output bit sequences that include both component interleaved output bit sequences and component pre-transformed polarization coded output bit sequences.

[0382] Example 17 is based on the above example.

[0383] In some embodiments, for h=0, 1, ..., W-1, the hth concatenated input bit sequence x (h) is of length N h The hth component of the interleaved output bit sequence For h = W, W+1, ..., H-1, the hth cascade input bit sequence x (h) is the polarization coded output bit sequence after pre-transformation of the hth component Where N h is the size of the hth component polarization matrix. In some embodiments, the output bit sequence e=[e 0 ,e 1 ,…,e E-1] includes a component interleaved output bit sequence d' for some h's (h) and the polar coded output bit sequence d after pre-transformation of the components for the remaining h's (h) , where the hth component interleaved output bit sequence The length of is equal to the size of the polarization matrix N of the hth component h ; Polarization coded output bit sequence after pre-transformation of the hth component The length of is equal to the size of the polarization matrix N of the hth component h In a specific example, the output bit sequence e = [e 0 ,e 1 ,…,e E-1 ] is the W component interleaved output bit sequence d' (0) , d' (1) ,…,d' (W-1) The polarization coded output bit sequence d after pre-transformation of HW components (W) d (W+1) ,…,d (H-1) The cascade is as follows:

[0384]

[0385]

[0386] Figure 4F A specific example of an output bit sequence e is given, which is the concatenation of a component interleaved output bit sequence and a component pre-transformed polarization coded output bit sequence.

[0387] Fig. 9 An exemplary block diagram of a hardware platform 900 is shown, which may be part of a network device (e.g., a base station) or a communication device (e.g., a user equipment (UE)). The hardware platform 900 includes at least one processor 910 and a memory 905 having instructions stored thereon. The instructions when executed by the processor 910 configure the hardware platform 900 to perform Figures 1 to 8 The operations in the embodiments described in the present patent application and the operations in the various embodiments described in the present patent application. Transmitter 915 transmits or sends information or data to another device. For example, a network device transmitter can send a message to a user device. Receiver 920 receives information or data transmitted or sent by another device. For example, a user device can receive a message from a network device.

[0388] The above-described embodiments will be applied to network communications. Fig.10An example of a communication system (e.g., a 5G or NR cellular network) is shown that includes a base station 1020 and one or more user equipment (UE) 1011, 1012, and 1013. In some embodiments, the UE accesses a BS (e.g., a network) using a communication link to the network (sometimes referred to as an uplink direction, as depicted by dashed arrows 1031, 1032, 1033), which then enables subsequent communication from the BS to the UE (e.g., shown in a direction from the network to the UE, sometimes referred to as a downlink direction, as depicted by arrows 1041, 1042, 1043). In some embodiments, the BS sends information to the UE (sometimes referred to as a downlink direction, as depicted by arrows 1041, 1042, 1043), which then enables subsequent communication from the UE to the BS (e.g., shown in a direction from the UE to the BS, sometimes referred to as an uplink direction, as depicted by dashed arrows 1031, 1032, 1033). The UE may be, for example, a smartphone, a tablet computer, a mobile computer, a machine-to-machine (M2M) device, an Internet of Things (IoT) device, etc.

[0389] Fig.11 An example flow chart representation of a method for digital communication according to one or more embodiments of the present technology is shown. Operation 1102 includes: determining, by a first node, an output bit sequence having E bits based on an input bit sequence having K bits, wherein the output bit sequence is determined by 1) performing a polarization transformation having H components and 2) not performing a pre-transformation operation or performing at least two pre-transformation operations; wherein the polarization transformation is based on H polarization matrices Where H, K and E are integers greater than 1, where the polarization matrix The size is N i Operation 1104 includes sending, by the first node to the second node, a signal including the output bit sequence.

[0390] Fig.12 Another example flow chart representation of a digital communication method according to one or more embodiments of the present technology is shown. Operation 1202 includes: receiving, by a second node, a signal including an output bit sequence having E bits from a first node. Operation 1204 includes: determining, by the second node, an input bit sequence having K bits based on the output bit sequence, wherein the output bit sequence is determined by 1) performing a polarization transformation having H components and 2) not performing a pre-transformation operation or performing at least two pre-transformation operations; wherein the polarization transformation is based on H polarization matrices Among them, H, K, E are integers greater than 1, and the polarization matrix The size is N i .

[0391] Fig.11and Fig.12 Various preferred embodiments and additional features of the above method are as follows. Further examples are described with reference to embodiments 1 to 17.

[0392] In some embodiments, at least two of the H polarization matrices have different sizes. In some embodiments, at least two of the H polarization matrices are different. In some embodiments, at least two of the H polarization matrices have a size greater than 2.

[0393] In some embodiments, N 0 、N 1 ,…,N H-1 And E satisfies N 0 +N- 1 +…+N H-1 = E. In some embodiments, N 0 、N 1 ,…,N H-1 An integer that is a power of 2.

[0394] In some embodiments, the output bit sequence is further determined by performing a repetition operation, wherein the input of the repetition operation is based on the input bit sequence. In some embodiments, the repetition operation includes: obtaining a repetitive input bit sequence by the first node; and determining, by the first node, H component repetitive output bit sequences c based on at least one of the following: (0) 、c (1) ,…,c (H-1) :1) Length list (K 0 ,K 1 ,…,K H-1 ), where K i Indication c (i) length, or 2) of the repeated index list (R (0) ,R (1) ,…,R (H-1) ),in And K i is a positive integer. In some embodiments, at least two of the H component repeated output bit sequences share at least one common element. In some embodiments, the H component repeated output bit sequences c (0) 、c (1) ,…,c (H-1) At least one component repetitive output bit sequence in the H component repetitive output bit sequences has a length equal to the length of the input bit sequence. In some embodiments, at least two component repetitive output bit sequences c of the H component repetitive output bit sequences are determined based on at least one identical bit in the input bit sequence. (i) and c (j)In some embodiments, at least two of the H component repeated output bit sequences are repeated output bit sequences c (i) and c (j) Include common subsequences in the input bit sequences.

[0395] In some embodiments, at least two of the H component repeated output bit sequences c (i) and c (j) Including matching subsequences generated based on the input bit sequence. In one example, the input bit sequence c=[c 0 ,c 1 ,c 2 ,c 3 ,c 4 ,c 5 ,c 6 ,c 7 ,c 8 ],c (i) =[c 0 ,c 1 ,c 7 ,c 3 ]and c (j) =[c 3 ,c 2 ,c 7 ,c 5 ]. Here, c (i) and c (j) Correspondingly has a matching subsequence [c 7 ,c 3 ] and [c 3 ,c 7 Both matching subsequences are generated based on the input sequence c, that is, element c 3 and c 7 In the input sequence c. In addition, the two subsequences [c 7 ,c 3 ] and [c 3 ,c 7 ] have a matching relationship, for example, c (i) The third and fourth elements in (c 7 and c 3 ) Determine c (j) The third and first elements in (c 7 and c 3 ). The two matching subsequences do not need to be in the same order as each other. Furthermore, the elements in the matching subsequences do not need to be in the same order as each other. (i) or c (j) consecutive positions in .

[0396] In some embodiments, the repeat index list (R (0) ,R(1) ,…,R (H-1) ) at least one element R (i) Equal to the set Z of integers of the first type K ={0,1,2,…,K-1}, where the first type integer set Z K ={0,1,2,…,K-1} includes all non-negative integers less than K.

[0397] In some embodiments, the output bit sequence is further determined by performing a rate configuration operation, wherein the input of the rate configuration operation is based on the input bit sequence. In some embodiments, a first data bit index set Q={Q 0 ,Q 1 ,…,Q K-1 For the input bit sequence c = [c 0 ,c 1 ,…,c K-1 ] performs a rate configuration operation to obtain a repetitive rate configuration output bit sequence v'=[v' 0 ,v' 1 ,…,v' N-1 ].

[0398] In some embodiments, the output bit sequence is further determined by performing a repetition operation, wherein the repetition operation includes: configuring the output bit sequence v'=[v' 0 ,v' 1 ,…,v' N-1 ] The H component repeated output bit sequences c are determined by at least one of the following (0) 、c (1) ,…,c (H-1) :1) Length list (K 0 ,K 1 ,…,K H-1 ), where K i Indication c (i) Length, or 2) the first data bit index set Q = {Q 0 ,Q 1 ,…,Q K-1},in In some embodiments, at least two of the H component repeated output bit sequences share at least one common element. (0) 、c (1) ,…,c (H-1) At least one component of the repetition output bit sequence has a length equal to the length of the input bit sequence. In some embodiments, the output bit sequence v'=[v' 0 ,v'1 ,…,v' N-1 ] to determine at least two component repeated output bit sequences c in the H component repeated output bit sequences (i) and c (j) , where N is an integer greater than 1. In some embodiments, at least two of the H component repeated output bit sequences c (i) and c (j) Including repetition rate configuration output bit sequence v'=[v' 0 ,v' 1 ,…,v' N-1 ], where N is an integer greater than 1.

[0399] In some embodiments, at least two of the H component repeated output bit sequences c (i) and c (j) The output bit sequence v'=[v' 0 ,v' 1 ,…,v' N-1 ], where N is an integer greater than 1. In one example, the repetition rate profile outputs a bit sequence v'=[v' 0 ,v' 1 ,v' 2 ,v' 3 ,v' 4 ,v' 5 ,v' 6 ,v' 7 ], c (i) =[v' 0 ,v' 1 ,v' 2 ] and c (j) =[v' 2 ,v' 1 ,v' 4 ]. Here, c (i) and c (j) Correspondingly has a matching subsequence [v' 1 ,v' 2 ] and [v' 2 ,v' 1 ]. Both matching subsequences are generated based on the repetition rate configuration output bit sequence v', i.e., element v' 1 and v' 2 is located in the repetition rate configuration output bit sequence v'. In addition, the two subsequences [v' 1 ,v' 2 ] and [v' 2 ,v' 1] have a matching relationship, for example, c (i) The second and third elements in (v' 1 and v' 2 ) is mapped to c (j) The second and first elements in (v' 1 and v' 2 ). The two matching subsequences need not be in the same order as each other. Furthermore, the elements in the matching subsequences need not be in consecutive positions in c(i) or c(j).

[0400] In some embodiments, the first data bit index set Q={Q 0 ,Q 1 ,…,Q K-1} to sort.

[0401] In some embodiments, the rate configuration operation is performed using H components. In some embodiments, based on the component data bit index set To perform the hth component of the rate configuration operation, where K h is the input length of the hth component of the rate configuration operation.

[0402] In some embodiments, the method further comprises performing a concatenation operation, wherein an input of the concatenation operation is based on the input sequence. In some embodiments, the concatenation operation generates an output sequence having E bits.

[0403] In some embodiments, the concatenation operation is performed on the first H component bit sequences generated based on the input sequence.In some embodiments, each of the at least two pre-transform operations generates an intermediate bit sequence.

[0404] In some embodiments, the bits of the intermediate bit sequence are determined by a convolution bit sequence or a convolution polynomial. In some embodiments, the convolution bit sequence comprises generating a bit sequence g=[g 0 ,g 1 ,…,g m ], or the recursive feedback bit sequence q = [q 0 ,q 1 ,…,q m ], where m is a positive integer. In some embodiments, the convolution polynomial includes a generating polynomial g(D)=g 0 +g 1 ·D+...+g m-1 ·D m-1 +g m ·D m , or the recursive feedback polynomial q(D) = q 0 +q 1 ·D+...+q m-1 ·Dm-1 +q m ·D m , where m is a positive integer.

[0405] In some embodiments, at least two pre-transform operations are performed using H components, and H intermediate bit sequences are generated. In some embodiments, the H intermediate bit sequences are determined by H convolution bit sequences or H convolution polynomials. In some embodiments, the H convolution bit sequences are H generated bit sequences g (0) ,g (1) ,...,g (H-1) , or H recursive feedback bit sequences q (0) ,q (1) ,...,q (H-1) ; where, for h = 0, 1, ..., H-1, g (h) =[g (h) 0 ,g (h) 1 ,...,g (h) m ] or q (h) =[q (h) 0 ,q (h) 1 ,...,q (h) m In some embodiments, the H convolution polynomials include H generator polynomials g (0) (D),g (1) (D),...,g (H-1) (D), or H recursive feedback polynomials q (0) (D),q (1) (D),...,q (H-1) (D); where for h = 0, 1, ..., H-1, g (h) (D) = g (h) 0 +g (h) 1 ·D+...+g (h) m-1 ·D m-1 +g (h) m ·D m or q (h) (D) = q (h) 0 +q (h) 1 ·D+...+q (h) m-1 ·D m-1 +q (h) m ·Dm .

[0406] In some embodiments, the output bit sequence is further determined by performing an interleaving operation, wherein the input to the interleaving operation is based on the input bit sequence. In some embodiments, the interleaving operation is performed using W components, wherein W is an integer less than or equal to H. In some embodiments, the interleaving operation of any W components is performed by a length N h Interwoven pattern To determine, where N h is an integer greater than 1.

[0407] It should be understood that the present application discloses methods and apparatus related to rate matching schemes applied to polar codes, PAC codes, or other pre-transformed polar codes. In the 3GPP 5G mobile communication standard, low-density parity-check (LDPC) codes are used for data transmission. However, compared with polar codes, LDPC has certain disadvantages in terms of short payload size (also known as transport block size (TBS)). Alternatively, PAC codes can achieve finite length boundaries at moderate decoding complexity. The code length of the PAC code is a power of 2 (N=2 n , where n is a positive integer), as a polar code. However, in order to effectively transmit the payload (or transport block (TB)) in different wireless channel environments, it is not always necessary to have N=2 in the time and frequency resources allocated by the base station (BS). n Therefore, the application of PAC codes in wireless communications requires a rate matching scheme.

[0408] The disclosed and other embodiments, modules and functional operations described in this application can be implemented in digital electronic circuits, or in computer software, firmware or hardware (including the structures disclosed in this application and their equivalents), or in a combination of one or more thereof. The disclosed embodiments and other embodiments can be implemented as one or more computer program products (i.e., modules of one or more computer program instructions encoded on a computer-readable medium) for execution or control of its operation by a data processing device. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a storage device, a composition of matter that affects a machine-readable propagation signal, or one or more combinations thereof. The term "data processing device" includes all devices, equipment and machines for processing data, including, for example, a programmable processor, a computer or multiple processors or multiple computers. In addition to hardware, the device can also include code that creates an execution environment for the computer program in question, for example, code that constitutes a processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more thereof. A propagation signal is an artificially generated signal, for example, a machine-generated electrical, optical or electromagnetic signal, which is generated to encode information for transmission to a suitable receiver device.

[0409] A computer program (also referred to as a program, software, software application, script, or code) can be written in any form of programming language (including compiled or interpreted languages), and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple collaborative files (e.g., files storing one or more modules, subroutines, or code portions). A computer program can be deployed to execute on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a communications network.

[0410] The processes and logic flows described in this application can be performed by one or more programmable processors that execute one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by special purpose logic circuits, and the apparatus can also be implemented as special purpose logic circuits, for example, FPGAs (field programmable gate arrays) or ASICs (application specific integrated circuits).

[0411] For example, processors suitable for executing computer programs include general and special purpose microprocessors, and any one or more processors of any type of digital computer. Typically, the processor will receive instructions and data from a read-only memory or a random access memory or both. The basic elements of a computer are a processor for executing instructions and one or more storage devices for storing instructions and data. Typically, a computer will also include or be operably coupled to one or more mass storage devices (such as magnetic disks, magneto-optical disks, or optical disks) for storing data to receive data from the mass storage device or to transfer data to it, or both. However, a computer is not required to have such a device. Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM optical disks. The processor and memory may be supplemented by or incorporated into a dedicated logic circuit.

[0412] Although the present application contains many details, these details should not be interpreted as limitations on the scope of the claimed invention or the content that can be claimed, but should be interpreted as an explanation of the specific features of a particular embodiment. Some of the features described herein in the context of a separate embodiment can also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment can also be implemented individually or in any suitable sub-combination in multiple embodiments. In addition, although the above-mentioned features may be described as working in the form of certain combinations, or even initially claimed as such, in some cases, one or more features in the claimed combination can be deleted from the combination, and the claimed combination can be for a sub-combination or a variant of a sub-combination. Similarly, although the operations are described in a specific order in the accompanying drawings, this should not be understood as requiring the operations to be performed in the specific order or sequential order shown, or requiring the execution of all illustrated operations to achieve the desired result.

[0413] Only a few examples and implementations are disclosed herein. Variations, modifications and enhancements may be made to the described examples and implementations and other implementations based on what is disclosed.

Claims

1. A digital communication method, comprising: The first node determines an output bit sequence having E bits based on an input bit sequence having K bits, wherein the output bit sequence is determined by 1) performing a polarization transformation having H components and 2) not performing a pre-transformation operation or performing at least two pre-transformation operations; wherein the polarization transformation is based on H polarization matrices Where H, K and E are integers greater than 1, where the polarization matrix The size is N i ;as well as A signal including the output bit sequence is sent by the first node to the second node.

2. A digital communication method, the digital communication method comprising: receiving, by the second node from the first node, a signal comprising an output bit sequence having E bits; as well as The second node determines an input bit sequence having K bits based on the signal, wherein the output bit sequence is determined by 1) performing a polarization transformation having H components and 2) not performing a pre-transformation operation or performing at least two pre-transformation operations; wherein the polarization transformation is based on H polarization matrices Where H, K and E are integers greater than 1, where the polarization matrix The size is N i。 3. The method according to claim 1 or 2, wherein: At least two of the H polarization matrices have different sizes.

4. The method according to claim 1 or 2, wherein: At least two polarization matrices among the H polarization matrices are different.

5. The method according to claim 1 or 2, wherein: At least two of the H polarization matrices have a size greater than 2.

6. The method according to claim 1 or 2, wherein: N0, N1, ..., N H-1 And E satisfies N0+N1+…+N H-1 =E.

7. The method according to claim 1 or 2, wherein: N0, N1, ..., N H-1 An integer that is a power of 2.

8. The method according to claim 1 or 2, wherein: The output bit sequence is also determined by performing a repetitive operation, wherein an input to the repetitive operation is based on the input bit sequence.

9. The method according to claim 8, wherein: The repeated operation includes: Obtaining, by the first node, a repeated input bit sequence; and The first node determines the H component repeated output bit sequences c by at least one of the following items: (0) 、c (1) ,…,c (H-1) :1) Length list (K0, K1, ..., K H-1 ), where K i Indication c (i) length, or 2) repeat the index list (R (0) ,R (1) ,…,R (H-1) ).

10. The method according to claim 9, wherein: At least two of the H component repeated output bit sequences share at least one common element.

11. The method according to claim 9, wherein: The H components repeatedly output the bit sequence c (0) 、c (1) ,…,c (H -1) At least one component of the repeated output bit sequence has a length equal to the length of the input bit sequence.

12. The method according to claim 9, wherein: At least two component repeated output bit sequences c of the H component repeated output bit sequences are determined based on at least one identical bit in the input bit sequence (i) and c (j) .

13. The method according to claim 9, wherein: At least two of the H component repeated output bit sequences are repeated output bit sequences c (i) and c (j) The method comprises generating a matching subsequence based on the input bit sequence.

14. The method according to claim 9, wherein: The repeat index list (R (0) ,R (1) ,…,R (H-1) ) at least one element R (i) Equal to the set Z of integers of the first type K ={0,1,2,…,K-1}, where the first type integer set Z K ={0,1,2,…,K-1} includes all non-negative integers less than K.

15. The method according to claim 1 or 2, wherein: The output bit sequence is also determined by performing a rate configuration operation, wherein an input to the rate configuration operation is based on the input bit sequence.

16. The method according to claim 15, wherein: Using the first data bit index set Q = {Q0, Q1, ..., Q K-1 For the input bit sequence c = [c0, c1, ..., c K-1 ] performs the rate configuration operation to obtain a repetitive rate configuration output bit sequence v'=[v'0, v'1, ..., v' N-1 ].

17. The method according to claim 16, wherein: The output bit sequence is also determined by performing a repetition operation, wherein the repetition operation comprises: configuring the output bit sequence v'=[v'0, v'1, ..., v' N-1 ] The H component repeated output bit sequences c are determined by at least one of the following (0) 、c (1) ,…,c (H-1) :1) Length list (K0, K1, ..., K H-1 ), where K i Indication c (i) or 2) the first data bit index set Q = {Q0, Q1, ..., Q K-1 },in 18. The method according to claim 17, wherein: At least two of the H component repeated output bit sequences share at least one common element.

19. The method according to claim 17, wherein: The H components repeatedly output the bit sequence c (0) 、c (1) ,…,c (H-1) At least one component of the repeated output bit sequence has a length equal to the length of the input bit sequence.

20. The method according to claim 17, wherein: The output bit sequence v'=[v'0, v'1, ..., v' N-1 ] to determine at least two component repeated output bit sequences c in the H component repeated output bit sequences (i) and c (j) , where N is an integer greater than 1.

21. The method according to claim 17, wherein: At least two of the H component repeated output bit sequences are repeated output bit sequences c (i) and c (j) comprising configuring an output bit sequence v'=[v'0, v'1, ..., v' N-1 ] where N is an integer greater than 1.

22. The method according to claim 17, wherein: The first data bit index set Q={Q0, Q1, ..., Q K-1 } to sort.

23. The method according to claim 15, wherein: The rate configuration operation is performed with H components.

24. The method according to claim 23, wherein: Component data bit index set to perform the hth component of the rate configuration operation, where K h is the input length of the hth component of the rate configuration operation.

25. The method according to claim 1 or 2, wherein the method further comprises performing a cascade operation, wherein: The input of the cascade operation is based on the input sequence.

26. The method according to claim 25, wherein: The concatenation operation generates an output sequence having E bits.

27. The method according to claim 25, wherein: The concatenation operation is performed on first H component bit sequences generated based on the input sequence.

28. The method according to claim 1 or 2, wherein: Each of the at least two pre-transform operations generates an intermediate bit sequence.

29. The method according to claim 28, wherein: The bits of the intermediate bit sequence are determined by a convolution bit sequence or a convolution polynomial.

30. The method of claim 29, wherein: The convolution bit sequence includes generating a bit sequence g=[g0, g1, ..., g m ], or the recursive feedback bit sequence q = [q0, q1, ..., q m ].

31. The method of claim 29, wherein: The convolution polynomial includes a generating polynomial g(D)=g0+g1·D+...+g m-1 ·D m-1 +g m ·D m , or the recursive feedback polynomial q(D) = q0 + q1·D + ... + q m-1 ·D m-1 +q m ·D m .

32. The method according to claim 1 or 2, wherein: The at least two pre-transform operations are performed using H components and generate H intermediate bit sequences.

33. The method according to claim 32, wherein: The H intermediate bit sequences are determined by H convolution bit sequences or H convolution polynomials.

34. The method of claim 33, wherein: The H convolution bit sequences are H generated bit sequences g (0) ,g (1) ,...,g (H-1) , or H recursive feedback bit sequences q (0) ,q (1) ,...,q (H-1) ; where, for h = 0, 1, ..., H-1, g (h) =[g (h) 0,g (h) 1,...,g (h) m ] or q (h) =[q (h) 0,q (h) 1,...,q (h) m ] 。 35. The method of claim 33, wherein: The H convolution polynomials include H generating polynomials g (0) (D),g (1) (D),...,g (H-1) (D), or H recursive feedback polynomials)q (0) (D),q (1) (D),...,q (H-1) (D); where for h = 0, 1, ..., H-1, g (h) (D) = g (h) 0+g (h) 1·D+...+g (h) m-1 ·D m-1 +g (h) m ·D m or (h) (D) = q (h) 0+q (h) 1·D+...+q (h) m-1 ·D m-1 +q (h) m ·D m .

36. The method according to claim 1 or 2, wherein: The output bit sequence is also determined by performing an interleaving operation, wherein an input to the interleaving operation is based on the input bit sequence.

37. The method of claim 36, wherein the interleaving operation is performed on W components, wherein: W is an integer less than or equal to H.

38. The method of claim 37, wherein: The interleaving operation of any one of the W components is performed by a length N h Interwoven pattern Determine, where N h is an integer greater than 1.

39. An apparatus for a communication network, the apparatus comprising: A processor configured to implement the method according to any one of claims 1 to 38.

40. A computer readable storage medium having stored thereon code which, when executed by a processor, causes the processor to implement the method according to any one of claims 1 to 38.

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