Voltage regulator, multi-phase controller and method thereof

Abstract

The invention provides a voltage regulator, a multiphase controller and a method thereof. The multi-phase controller includes an adder circuit configured to sense a plurality of phase currents generated by a plurality of power stages and generate a sum current value representative of a total current generated by the plurality of power stages; and a current limiting controller configurable in a current limiting mode or a non-current limiting mode based on the total current value, and configured to limit the total current to a predetermined value during the current limiting mode. The current limit controller includes a threshold selector circuit and a mode configuration circuit. The threshold selector circuit selects a first threshold or a second threshold as the selected threshold based on the configuration signal. The mode configuration circuit monitors a duration during which the comparison result indicates that the sum current value satisfies a selected threshold, and generates a configuration signal based on whether the duration satisfies a duration threshold.

Description

Technical Field

[0001] The present invention relates to a voltage regulator, a multi-phase controller and a method thereof. Background Art

[0002] A voltage regulator is an electronic device or circuit that maintains a constant output voltage regardless of changes in input voltage or load conditions. Its main function is to regulate or control the voltage level to a specific value within a desired range. Voltage regulators are often used in electronic systems to ensure that sensitive components receive a stable and reliable supply of power. They are found in a variety of applications, including power supplies, battery chargers, computer systems, automotive electronics, and many other devices. A voltage regulator works by comparing the output voltage to a reference voltage and adjusting its internal components to maintain a constant output voltage. When the input voltage or load changes, the voltage regulator automatically adjusts its output to compensate for those changes.

[0003] In certain applications, such as in power distribution systems or three-phase systems, voltage regulators may be used in conjunction with other components (such as transformers, power stages, or power electronics) to control phase currents. These systems may involve regulating the voltage supplied to the load to maintain a specific current level or power factor. In such cases, additional components or control systems may be used to monitor and adjust the phase currents based on the voltage regulation provided by the voltage regulator. In such scenarios, the role of the voltage regulator may be to maintain a stable voltage supply, which indirectly affects the phase currents through load characteristics and overall system design. Summary of the invention

[0004] In some implementations, a voltage regulator includes: a plurality of power stages configured to generate a plurality of phase currents, wherein a sum of the plurality of phase currents represents a total current, and wherein each of the plurality of power stages is configured to generate a corresponding phase current of the plurality of phase currents; an adder circuit configured to sense the plurality of phase currents and generate a summed current value representing a total current generated by the plurality of power stages; and a current limiting controller configurable to a current limiting mode or a non-current limiting mode and configured to limit the total current to a predetermined value during the current limiting mode, wherein the current limiting controller is configured to receive the summed current value, and wherein the current limiting controller includes: a threshold selector circuit configured to select a first threshold or a second threshold as a selected threshold based on a configuration signal, wherein the second threshold a first monitoring path including: a first comparator circuit configured with a dynamic threshold value set to a selected threshold value, wherein the first comparator circuit is configured to compare the total current value with the selected threshold value and generate a first comparison result indicating whether the total current value satisfies the selected threshold value; and a mode configuration circuit configured to monitor a first duration during which the first comparison result indicates that the total current value satisfies the selected threshold value, and generate a configuration signal based on whether the first duration satisfies the duration threshold value.

[0005] In some implementations, a multi-phase controller includes an adder circuit configured to sense a plurality of phase currents generated by a plurality of power stages and generate a summed current value representing a total current generated by the plurality of power stages; and a current limit controller configurable to a current limiting mode or a non-current limiting mode and configured to limit the total current to a predetermined value during the current limiting mode, wherein the current limiting controller is configured to receive the summed current value, and wherein the current limiting controller includes: a threshold selector circuit configured to select a first threshold or a second threshold as a selected threshold based on a configuration signal, wherein the second threshold is less than the first threshold, wherein when the current limiting controller is set to the non-current limiting mode, the threshold selector circuit A selector circuit is configured to select a first threshold as a selected threshold, and wherein, when the current limit controller is set to a current limit mode, the threshold selector circuit is configured to select a second threshold as the selected threshold; and a first monitoring path, comprising: a first comparator circuit, the first comparator circuit being configured with a dynamic threshold set to the selected threshold, wherein the first comparator circuit is configured to compare the total current value with the selected threshold and generate a first comparison result indicating whether the total current value satisfies the selected threshold; and a mode configuration circuit, the mode configuration circuit being configured to monitor a first duration, during which the first comparison result indicates that the total current value satisfies the selected threshold, and generate a configuration signal based on whether the first duration satisfies the duration threshold.

[0006] In some implementations, a method for limiting a total phase current generated by a plurality of power stages includes: sensing a plurality of phase currents generated by the plurality of power stages; generating a sum current value representing a total phase current of the plurality of phase currents; configuring a current limit controller to a current limiting mode or a non-current limiting mode, wherein the current limit controller is configured to limit the total phase current to a predetermined value during the current limiting mode; selecting a first threshold or a second threshold as a selected threshold based on a configuration signal, wherein the second threshold is less than the first threshold, wherein when the current limit controller is set to the non-current limiting mode, the first threshold is used as the selected threshold, and wherein when the current limit controller is set to the current limiting mode, the second threshold is used as the selected threshold; comparing the sum current value with the selected threshold; generating a first comparison result indicating whether the sum current value satisfies the selected threshold; monitoring a first duration during which the first comparison result indicates that the sum current value satisfies the selected threshold; and generating a configuration signal based on whether the first duration satisfies the duration threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Implementations are described herein with reference to the accompanying drawings.

[0008] Figure 1A voltage regulator according to one or more implementations is shown.

[0009] Figure 2 Voltage and current compensation loops of a voltage regulator are shown in accordance with one or more implementations. DETAILED DESCRIPTION

[0010] In the following, the details are set forth to provide a more comprehensive explanation of the example implementations. However, it will be clear to those skilled in the art that the implementations may be practiced without these specific details. In other cases, well-known structures and devices are shown in block diagram form or schematic form rather than in detail to avoid confusing the implementations. In addition, unless otherwise specifically stated, the features of the different implementations described below may be combined with each other.

[0011] In addition, identical or similar elements or elements having identical or similar functions are indicated by identical or similar reference numerals in the following description. Since identical elements or elements having identical functions are assigned identical reference numerals in the drawings, repeated descriptions of elements provided with identical reference numerals may be omitted. Therefore, descriptions provided for elements having identical or similar reference numerals are interchangeable.

[0012] The orientation of various elements in the figure is shown as an example, and the illustrated example can be rotated relative to the illustrated orientation. The description provided herein and the attached claims relate to any structure having the described relationship between various features, regardless of whether these structures are in the specific orientation of the accompanying drawings, or rotate relative to this orientation. Similarly, for ease of description, spatially relative terms such as "top", "bottom", "below", "below", "lower", "above", "upper", "middle", "left side" and "right side" are used herein to describe the relationship between an element and one or more other elements shown in the figures. Spatially relative terms are intended to include different orientations of elements, structures and / or assemblies in use or operation except the orientation depicted in the figures. Structures and / or assemblies can be oriented otherwise (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can be interpreted accordingly.

[0013] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" versus "directly between," "adjacent" versus "immediately adjacent," etc.).

[0014] In the implementations described herein or shown in the accompanying drawings, any direct electrical connection or coupling (e.g., any connection or coupling without additional intermediate elements) may also be implemented by an indirect connection or coupling (e.g., a connection or coupling with one or more additional intermediate elements, and vice versa), as long as the general purpose of the connection or coupling is essentially maintained (e.g., transmitting a certain signal or transmitting certain information). Features from different implementations may be combined to form additional implementations. For example, changes or modifications described with respect to one of the implementations may also apply to other implementations, unless otherwise stated.

[0015] As used herein, the terms "substantially" and "approximately" mean "within reasonable tolerances of manufacturing and measurement." For example, the terms "substantially" and "approximately" may be used herein to illustrate small manufacturing tolerances or other factors (e.g., within 5%) that are considered acceptable in the industry without departing from aspects of the implementations described herein. For example, a resistor having an approximate resistance value may actually have a resistance within 5% of the approximate resistance value. As another example, a signal having an approximate signal value may actually have a signal value within 5% of the approximate signal value.

[0016] In the present disclosure, expressions including ordinal numbers such as "first", "second", etc. can modify various elements. However, such elements are not limited by these expressions. For example, such expressions do not limit the order and / or importance of elements. On the contrary, such expressions are only used for the purpose of distinguishing one element from other elements. For example, the first box and the second box indicate different boxes, although they are both boxes. For another example, without departing from the scope of the present disclosure, the first element can be referred to as the second element, and similarly, the second element can also be referred to as the first element.

[0017] The voltage regulator may include a multiphase controller and a plurality of power stages controlled by the multiphase controller. The plurality of power stages may form a multiphase buck converter, each power stage providing a corresponding output voltage and a corresponding phase current. The power stage (e.g., a pulse width modulation (PWM) power stage) may function similarly to a power transformer. Therefore, the multiphase controller may be a digital PWM controller, and the power stage may be a power converter that converts input power into output power applied to a load. In some cases, the power stage may be referred to as a step-down DC-DC converter or a buck converter.

[0018] In some implementations, two or more corresponding output voltages from each power stage may be used (e.g., used in combination) to provide a total output voltage provided by the multiphase buck converter to a load such as a central processing unit (CPU). The multiphase buck converter may be configured with a plurality of synchronous rectification channels arranged in parallel, each channel including a corresponding power stage providing a corresponding output voltage and a corresponding phase current. In some cases, two or more corresponding output voltages of a first group of power stages may be used to provide a first total output voltage and a first total current to a first load, and two or more corresponding output voltages of a second group of power stages may be used to provide a second total output voltage and a second total current to a second load.

[0019] The phase current should be measured at the output of the power stage to determine the total current generated by the multi-phase buck converter. For example, an increase in CPU load current can be caused by normal CPU high-speed activity in turbo mode, or by abnormal activity such as caused by a virus, and the load current increase caused by abnormal activity usually lasts for a longer duration than the typical duration of the load current increase caused by normal CPU high-speed activity. High load currents that last for a long duration may cause additional stress on the input power supply (such as a 12V input power supply) and should be avoided. However, if the multi-phase controller that drives the power stage to deliver power to the CPU limits the total current based only on the load current amplitude to prevent the CPU from consuming high load currents caused by viruses, then the load current consumed during normal CPU activity (including turbo mode) will also be affected. Therefore, the CPU may perform poorly during normal CPU activity.

[0020] Some implementations disclosed herein relate to a voltage regulator that provides a first path and a second path to limit a total current. The two paths can be implemented in a current limit controller that is part of a multiphase controller. The current limit controller can dynamically switch from the first path to the second path based on the load current magnitude of the total current and the duration that the load current magnitude remains above one or more thresholds.

[0021] The first path can limit the peak current of the total current. For example, once the peak load current is higher than the peak overcurrent protection (OCP) threshold for a certain amount of time (e.g., a duration threshold), the current limit controller is configured to limit the target current of the total current to a lower threshold.

[0022] The second path can limit the DC load current. In this case, when the total current that has passed through the low-pass filter exceeds the lower threshold for a certain amount of time (e.g., a duration threshold), the current limit controller can clamp or limit the target current to a lower threshold. Therefore, the current limit controller not only considers the load current amplitude of the total current, but also considers the amount of time that the load current amplitude of the total current exceeds a certain threshold. Therefore, before limiting the total current supplied to the CPU, the current limit controller is able to distinguish between normal CPU high-speed activity and abnormal activity of longer duration, at least to some extent. As a result, poor CPU performance caused by limiting the total current supplied during normal CPU high-speed activity can be reduced or prevented.

[0023] Figure 1 A voltage regulator 100 according to one or more implementations is shown. The voltage regulator 100 includes a multi-phase controller 102 (e.g., a digital PWM controller) and a plurality of power stages 104-1, 104-2, ..., 104-N, collectively referred to as power stages 104, where N is an integer representing the total number of power stages. In some implementations, each power stage 104 may be a current synchronous buck gate driver integrated circuit (IC).

[0024] The multi-phase controller 102 can generate a plurality of PWM control signals for controlling the power stage 104. For example, each PWM control signal can be provided to a corresponding power stage 104 for controlling a phase current and an output voltage Vo provided by the corresponding power stage 104. The phase current can be limited via the PWM control signal. Each power stage 104 can be coupled to a corresponding inductor L through which the phase current of the power stage 104 flows. Therefore, each phase current can also be referred to as a phase inductor current. Therefore, the power stage 104 is configured to generate a plurality of phase currents, and each power stage is configured to generate a corresponding phase current in a plurality of phase currents. The sum of the plurality of phase currents represents the total current provided by the power stage 104. The phase current and the output voltage Vo of the power stage 104 can be supplied to a single load, such as a single CPU, or can be distributed between a plurality of loads, such as between a plurality of CPUs.

[0025] The voltage regulator 100 also includes a current limit controller 106. In some implementations, the current limit controller 106 can be integrated in the multi-phase controller 102 as a feedback control for limiting the total current. The voltage regulator 100 may include an adder circuit (e.g., a sensing circuit) configured to sense multiple phase currents and generate a sum current value Isum representing the total current generated by multiple power stages. In some implementations, the adder circuit may include sensing circuits 108-1, 108-2, ..., 108-N (collectively referred to as sensing circuits 108) for each power stage 104. For example, each sensing circuit 108 may include a probe and an analog-to-digital converter (ADC) coupled to the output of the corresponding power stage 104. Each ADC may be configured to generate a digital representation of the instantaneous phase current of the corresponding power stage 104. In other words, each ADC may generate a sensing current value Isen1, Isen2, ... or IsenN representing the instantaneous phase current of the power stage 104 coupled to the ADC. In some implementations, the sensed current values ​​Isen1, Isen2, ... or IsenN may be analog representations of the instantaneous phase currents. Thus, the sensing circuit 108 may be an analog circuit or a digital circuit.

[0026] In addition, the adder circuit may include an adder 110 configured to receive the sensed current values ​​Isen1, Isen2, ... or IsenN from the sense circuit 108 and sum the sensed current values ​​Isen1, Isen2, ... or IsenN to generate a summed current value Isum representing the total current. Therefore, the summed current value Isum represents the instantaneous amount of the total current generated by the plurality of power stages 104. In some implementations, the adder circuit may be integrated as part of the current limit controller 106. For example, the adder 110 may be integrated on the same chip as the current limit controller 106.

[0027] The current limit controller 106 can be configured in a current limit mode or a non-current limit mode, and the current limit controller 106 is configured to limit the total current to a predetermined value (e.g., a limit target value) during the current limit mode. The current limit controller 106 is configured to receive the sum current value Isum, and determine which mode to configure based on two monitoring paths for evaluating the sum current value Isum. The two monitoring paths include a first monitoring path P1 and a second monitoring path P2. The first monitoring path P1 and the second monitoring path P2 can share a mode configuration circuit 112.

[0028] The current limit controller 106 includes a threshold selector circuit 114, which is configured to select a first threshold value Th1 or a second threshold value Th2 as a selected threshold value 116 based on a configuration signal 118. The second threshold value Th2 is less than the first threshold value Th1. The threshold selector circuit 114 may be a multiplexer including two inputs and one output. The first threshold value Th1 and the second threshold value Th2 may be provided to the two inputs, respectively, and the threshold selector circuit 114 may selectively output one of the two threshold values ​​Th1 or Th2 based on the configuration signal 118. For example, when the current limit controller 106 is configured to a non-current limiting mode, the configuration signal 118 may be a logic "0" value, and when the current limit controller 106 is configured to a current limiting mode, the configuration signal 118 may be a logic "1" value. When the configuration signal 118 is at a logic "0" value, the threshold selector circuit 114 may output the first threshold value Th1, and when the configuration signal 118 is at a logic "1" value, the threshold selector circuit 114 may output the second threshold value Th2.

[0029] Therefore, when the current limit controller 106 is set to the non-current limiting mode, the threshold selector circuit 114 is configured to select the first threshold Th1 as the selected threshold 116, and when the current limit controller 106 is set to the current limiting mode, the threshold selector circuit 114 is configured to select the second threshold Th2 as the selected threshold 116.

[0030] The first monitoring path P1 includes a first comparator circuit 120 (e.g., a first comparator) configured with a dynamic threshold value set to a selected threshold value 116. In other words, the first comparator circuit 120 is configured to use the selected threshold value 116 (e.g., the first threshold value Th1 or the second threshold value Th2) selected by the threshold selector circuit 114 as a threshold value for performing comparison. Therefore, the threshold value for performing comparison is dynamically changed based on the configuration signal 118 that controls the output of the threshold selector circuit 114. The first comparator circuit 120 includes two inputs, input A and input B, and compares the signals received at the two inputs to generate a first comparison result 122. Input A can be configured to receive the selected threshold value 116, and input B can be configured to receive the sum current value Isum. The first comparator circuit 120 can be configured to compare the sum current value Isum with the selected threshold value 116, and generate a first comparison result 122 indicating whether the sum current value Isum meets the selected threshold value 116. For example, the first comparison result 122 can indicate whether the sum current value Isum is greater than the selected threshold value 116. For example, when the total current value Isum is greater than the selected threshold value 116 (for example, when the total current value Isum satisfies the selected threshold value 116), the first comparator circuit 120 can set the first comparison result 122 to a logic "1" value, and when the total current value Isum is not greater than the selected threshold value 116 (for example, when the total current value Isum does not satisfy the selected threshold value 116), the first comparator circuit 120 can set the first comparison result 122 to a logic "0" value.

[0031] The mode configuration circuit 112 may be configured to monitor a first duration during which the first comparison result 122 indicates that the sum current value Isum satisfies the selected threshold 116, and to generate a configuration signal 118 based on whether the first duration satisfies the duration threshold. That is, the mode configuration circuit 112 may detect when the first comparison result 122 is set to a logic “1” value, and may monitor the amount of time (e.g., the first duration) that the first comparison result 122 is set to a logic “1” value. If the first comparison result 122 is set to a logic “1” value long enough to satisfy the duration threshold, the mode configuration circuit 112 may be configured to change the configuration signal 118 from a logic “0” value to a logic “1” value to change the mode of the current limit controller from a non-current limiting mode to a current limiting mode. However, if the first comparison result 122 changes from a logic “1” value to a logic “0” value before the first duration satisfies the duration threshold, the mode configuration circuit 112 may maintain the configuration signal 118 at a logic “0” value, thereby not triggering the current limiting mode.

[0032] Thus, in some implementations, the first duration may satisfy the duration threshold if the first duration is greater than the duration threshold. Alternatively, in some implementations, the first duration may satisfy the duration threshold if the first duration is equal to or greater than the duration threshold. The threshold condition may be a matter of design choice. The mode configuration circuit 112 may be configured to generate a configuration signal 118 to set the current limit controller 106 to the current limit mode if the first duration satisfies the duration threshold.

[0033] By changing the configuration signal 118 from a logic "0" value to a logic "1" value, the mode configuration circuit 112 changes the selected threshold 116 from the first threshold Th1 to a lower second threshold Th2. As a result, in order for the first comparator circuit 120 to be able to set the first comparison result 122 to a logic "0" value again, the total current value Isum must be lower than (or equal to) the second threshold Th2. As long as the selected threshold 116 is set to the second threshold Th2 and the total current value Isum meets the second threshold Th2, the current limit controller 106 will remain set in the current limiting mode. Therefore, the second threshold Th2 behaves like a hysteresis threshold to ensure that the total current value Isum drops below the second threshold Th2 before the voltage regulator 100 can operate in the non-limited current mode again.

[0034] The mode configuration circuit 112 may include a time delay filter 124 (e.g., a deglitch filter) configured to monitor a first duration during which the first comparison result 122 indicates that the sum current value Isum satisfies the selected threshold 116. When the first duration satisfies the duration threshold, the time delay filter 124 may generate a current limit mode control signal 126 indicating that the first duration satisfies the duration threshold. The time delay filter 124 may change the current limit mode control signal 126 to indicate when the first duration does not satisfy the duration threshold.

[0035] The mode configuration circuit 112 may include a latch 128 (e.g., a set-reset latch) configured to receive the current limit mode control signal 126 and generate a configuration signal 118 to set the current limit controller 106 into the current limit mode. For example, when the current limit mode control signal 126 indicates that the first duration satisfies the duration threshold (e.g., the current limit mode control signal 126 is a logic "1" value), the output of the latch 128 (e.g., the configuration signal 118) may be set to a logic "1" value, which places the current limit controller 106 in the current limit mode.

[0036] The latch 128 may be configured to be reset based on the first comparison result 122 indicating that the sum current value Isum does not satisfy (e.g., no longer satisfies) the selected threshold value 116. For example, the latch 128 may be configured to be reset when the sum current value Isum becomes less than a second threshold value Th2, which is the selected threshold value 116 when the current limit controller 106 is set to the current limit mode (e.g., when the configuration signal 118 is set to a logic "1" value by the latch 128). Based on the latch 128 being reset, the latch 128 may be configured to generate the configuration signal 118 to set the current limit controller in the non-current limit mode (e.g., the configuration signal 118 is set to a logic "0" value by the latch 128).

[0037] The mode configuration circuit 112 may include a logic inverter 130 and an OR logic gate 132. The OR logic gate 132 may be coupled to both the first monitoring path P1 and the second monitoring path P2, and may generate an output based on two inputs provided via the first monitoring path P1 and the second monitoring path P2. The logic inverter 130 is configured to reset the latch 128 when both inputs of the OR logic gate 132 are logic "0" values. Therefore, when the first comparison result 122 indicates that the sum current value Isum does not satisfy (e.g., no longer satisfies) the selected threshold 116 (e.g., when the sum current value Isum becomes less than the second threshold Th2), the logic inverter 130 may reset the latch 128.

[0038] Latch 128 can be configured to provide a current limiter to the programmable current limiter ( Figure 1 100). The programmable current limiter may be configured to receive the configuration signal 118 and set the total control current (e.g., total target current) of the total current of the voltage regulator 100. When the current limit controller 106 is set to the current limit mode by the configuration signal (e.g., when the configuration signal 118 is set to a logic "1" value), the programmable current limiter may be configured to limit the total control current to the current limit value so that the total current is limited to a predetermined value (e.g., a limit target value). In other words, the programmable current limiter may prevent the total current of the power stage 104 from exceeding a predetermined value corresponding to the current limit value. As a result, the power stage 104 may be prevented from providing a total current that may stress the input power supply of the voltage regulator 100. In addition, the programmable current limiter may be configured to limit the total current only when the total load current magnitude exceeds a certain threshold for at least a certain duration. Therefore, normal CPU activities that may cause the total load current magnitude to increase beyond the desired limit for a short duration below the duration threshold may not be limited by the current limit controller 106.

[0039] In addition, the mode of the current limit controller 106 is adjusted by the second monitoring path P2. The second monitoring path P2 may include a low-pass filter 134, a second comparator circuit 136, and a mode configuration circuit 112. The low-pass filter 134 may be configured to receive the sum current value Isum from the adder 110 and output a filtered current value 138. The second comparator circuit 136 (e.g., a second comparator) may be configured with a third threshold Th3 (e.g., a fixed threshold), which may be less than the first threshold Th1. In some implementations, the third threshold Th3 may be set to a value between the second threshold Th2 and the first threshold Th1. That is, the third threshold Th3 may be greater than the second threshold Th2 and less than the first threshold Th1. The second comparator circuit 136 may be configured to compare the filtered current value 138 with the third threshold Th3, and generate a second comparison result 140 indicating whether the filtered current value 138 meets the third threshold Th3.

[0040] For example, the second comparator circuit 136 includes two inputs, input C and input D, and compares the signals received at the two inputs to generate a second comparison result 140. Input D may be configured to receive a third threshold value Th3, and input C may be configured to receive a filtered current value 138. The second comparator circuit 136 may be configured to compare the filtered current value 138 with the third threshold value Th3, and generate a second comparison result 140 indicating whether the filtered current value 138 satisfies the third threshold value Th3. For example, the second comparison result 140 may indicate whether the filtered current value 138 is greater than the third threshold value Th3. For example, when the filtered current value 138 is greater than the third threshold value Th3 (for example, when the filtered current value 138 satisfies the third threshold value Th3), the second comparator circuit 136 can set the second comparison result 140 to a logic "1" value, and when the filtered current value 138 is not greater than the third threshold value Th3 (for example, when the filtered current value 138 does not satisfy the third threshold value Th3), the second comparator circuit 136 can set the second comparison result 140 to a logic "0" value.

[0041] The OR logic gate 132 may be coupled to both the first monitoring path P1 and the second monitoring path P2, and may generate an output based on two inputs provided by the first monitoring path P1 and the second monitoring path P2. Therefore, when the first comparison result 122 or the second comparison result 140 indicates a logic "1" value, the OR logic gate 132 may output a logic "1" value, and when both the first comparison result 122 and the second comparison result 140 indicate a logic "0" value, the OR logic gate 132 may output a logic "0" value.

[0042] The mode configuration circuit 112 may be configured to monitor a second duration during which the second comparison result 140 indicates that the filtered current value 138 satisfies the third threshold value Th3, and to generate the configuration signal 118 based on whether the second duration satisfies the duration threshold. That is, the mode configuration circuit 112 may detect when the second comparison result 140 is set to a logic “1” value, and may monitor the amount of time (e.g., the second duration) that the second comparison result 140 is set to a logic “1” value. If the second comparison result 140 is set to a logic “1” value long enough to satisfy the duration threshold, the mode configuration circuit 112 may be configured to change the configuration signal 118 from a logic “0” value to a logic “1” value to change the mode of the current limit controller 106 from a non-current limiting mode to a current limiting mode.

[0043] However, if the configuration signal 118 is at a logic “0” value, and if the second comparison result 140 changes from a logic “1” value to a logic “0” value before the second duration satisfies the duration threshold, the mode configuration circuit 112 may maintain the configuration signal 118 at a logic “0” value, thereby not triggering the current limiting mode. Alternatively, if the configuration signal 118 has been set to a logic “1” value (e.g., because the sum current value Isum satisfies the first threshold Th1 for the duration threshold), the mode configuration circuit 112 may maintain the configuration signal 118 at a logic “1” value until the first comparison result 122 and the second comparison result 140 are simultaneously provided at a logic “0” value. This may occur when the sum current value Isum is less than (or equal to) the second threshold Th2 and the filtered current value 138 is less than (or equal to) the third threshold Th3.

[0044] Thus, in some implementations, the second duration may satisfy the duration threshold if the second duration is greater than the duration threshold. Alternatively, in some implementations, the second duration may satisfy the duration threshold if the second duration is equal to or greater than the duration threshold. The threshold condition may be a matter of design choice. The mode configuration circuit 112 may be configured to generate a configuration signal 118 to set or maintain the current limit controller 106 in the current limit mode if the second duration satisfies the duration threshold.

[0045] Since OR logic gate 132 receives both first comparison result 122 and second comparison result 140 , mode configuration circuit 112 may be configured to generate configuration signal 118 to set current limit controller 106 to current limit mode if the first duration satisfies the duration threshold or if the second duration satisfies the duration threshold.

[0046] The mode configuration circuit 112 sets the current limit controller 106 to the current limit mode by changing the configuration signal 118 from a logic "0" value to a logic "1" value, or by maintaining the configuration signal 118 at a logic "1" value. When in the current limit mode, the selected threshold 116 is also set to the second threshold Th2. As a result, the filtered current value 138 must be lower than (or equal to) the third threshold Th3 so that the second comparator circuit 136 can again set the second comparison result 140 to a logic "0" value. As long as the filtered current value 138 meets the third threshold Th3, the current limit controller 106 will remain set in the current limit mode. In order for the current limit controller 106 to return to the non-current limit mode, the sum current value Isum must be less than (or equal to) the second threshold Th2, and the filtered current value 138 must be less than (or equal to) the third threshold Th3.

[0047] The time delay filter 124 (e.g., a deglitch filter) may be configured to monitor a second duration during which the second comparison result 140 indicates that the filtered current value 138 satisfies the third threshold Th3. When the second duration satisfies the duration threshold, the time delay filter 124 may generate a current limit mode control signal 126 indicating that the second duration satisfies the duration threshold. The time delay filter 124 may change the current limit mode control signal 126 to indicate when the second duration does not satisfy the duration threshold.

[0048] The latch 128 (e.g., a set-reset latch) can be configured to receive the current limit mode control signal 126 and generate the configuration signal 118 to set the current limit controller 106 into the current limit mode. For example, when the current limit mode control signal 126 indicates that the second duration satisfies the duration threshold (e.g., the current limit mode control signal 126 is a logic "1" value), the output of the latch 128 (e.g., the configuration signal 118) can be set to a logic "1" value, which places the current limit controller 106 in the current limit mode.

[0049] As long as the sum current value Isum also does not satisfy the second threshold value Th2, the latch 128 can be configured to be reset based on the second comparison result 140 indicating that the filtered current value 138 does not satisfy (e.g., no longer satisfies) the third threshold value Th3. For example, as long as the sum current value Isum also does not satisfy the second threshold value Th2, the latch 128 can be configured to be reset when the filtered current value 138 becomes less than the third threshold value Th3. Based on the latch 128 being reset, the latch 128 can be configured to generate a configuration signal 118 to set the current limit controller in a non-current limiting mode (e.g., the configuration signal 118 is set to a logic "0" value by the latch 128).

[0050] As long as the total current value Isum also does not satisfy the second threshold value Th2, when the second comparison result 140 indicates that the filtered current value 138 does not satisfy (e.g., no longer satisfies) the third threshold value Th3 (e.g., when the filtered current value 138 becomes less than the third threshold value Th3), the logic inverter 130 can reset the latch 128.

[0051] The programmable current limiter may be configured to receive the configuration signal 118 and a total control current (eg, a total target current) that sets the total current of the voltage regulator 100 , and operate as described above based on the configuration signal 118 .

[0052] As indicated above, Figure 1 Provided as an example. Other examples may differ from Figure 1 Examples described. Figure 1 The number and arrangement of devices and components shown are provided as examples. Figure 1 There may be more devices or components, fewer devices or components, different devices or components, or differently arranged devices or components than those shown.

[0053] Figure 2 FIG. 2 shows a voltage and current compensation loop of a voltage regulator 200 according to one or more implementations. The voltage regulator 200 may be similar to a combination of Figure 1 The voltage regulator 100 is described. The voltage and current compensation loops may be part of a multi-phase controller 102 , which may also include a current limit controller 106 .

[0054] The multiphase controller 102 uses digital voltage and current feedback loops to maintain a tightly regulated output voltage with inherent phase current balance. During operation, the output voltage Vo can be sensed and digitized by an ADC 202 arranged in a voltage feedback loop 204. The digitized voltage 206 is provided to an error generator 208. The error generator 208 can also receive a target voltage V for the output voltage Vo. target The error generator 208 may be configured to compare the target voltage V target and digitized voltage 206, and generates a voltage representing the target voltage V target The error signal 210 is a difference between the digitized voltage 206 and the digitized voltage 206. The error signal 210 can be provided to a digital compensator 212 (e.g., a proportional-integral-derivative (PID) controller) that uses PID parameters, such as a proportional coefficient Kp, an integral coefficient Ki, and a derivative coefficient Kd, to generate a total control current 214 (e.g., a total target current) that sets the total current of the voltage regulator 200.

[0055] The total control current 214 may be provided to a programmable current limiter 216, which may also receive the configuration signal 118. The programmable current limiter 216 may be similar to a combination of Figure 1 1. In some implementations, the programmable current limiter 216 can be part of the current limit controller 106. When the configuration signal 118 is set to a logic "0" value by the current limit controller 106 indicating a non-current limiting mode, the programmable current limiter 216 can be configured to not limit the total control current 214. Therefore, the total control current 214 received by the programmable current limiter 216 passes through the programmable current limiter 216. However, if the configuration signal 118 is set to a logic "1" value by the current limit controller 106, the programmable current limiter 216 is set to the current limiting mode.

[0056] When the current limit controller 106 and the programmable current limiter 216 are set to the current limit mode, the programmable current limiter 216 is configured to limit the total control current 214 to the current limit value LIM, so that the total current of the voltage regulator 200 (e.g., the power stage 104) is limited to a predetermined value corresponding to the current limit value LIM. The current limit value LIM can be a programmable current limit value configured by programming a desired value at the input of the programmable current limiter 216 that receives the current limit value LIM. If the total control current 214 is equal to or greater than the current limit value LIM, the output of the programmable current limiter 216 can be clamped to the current limit value LIM. If the total control current 214 is less than the current limit value LIM, the output of the programmable current limiter 216 can be the same as the total control current 214.

[0057] Thus, the programmable current limiter 216 can prevent the total control current 214 from exceeding the current limit value LIM during the current limit mode, which can prevent the total current (e.g., the total phase current of the power stage 104) from exceeding a predetermined value corresponding to the current limit value LIM. As a result, the power stage 104 can be prevented from providing a total current that may stress the input power supply of the voltage regulator 100 (e.g., during abnormal activity or behavior of the load). In addition, the programmable current limiter 216 can be configured to limit the total current only when the total load current magnitude exceeds a certain threshold for at least a certain duration. Therefore, normal CPU activity that may cause the total load current magnitude to increase beyond the desired limit for a short duration below the duration threshold may not be limited by the current limit controller 106.

[0058] The output of the programmable current limiter 216 (e.g., the total control current 214 or the current limit value LIM) can be provided to a divider 218, which can divide the output of the programmable current limiter 216 into equal control currents 220 at 1 / N. Thus, each active phase of the voltage regulator 200 receives a control current 220. The power stage 104 can be configured to generate their respective phase currents based on the control current 220. Each phase current can be sensed and used as feedback in an internal phase current feedback loop. Each internal phase current feedback loop can include a gain of 1 / kapc, which can be used to convert the sensed phase current into a digital code.

[0059] Each sensed phase current (or digital code) may be compared to the control current 220 by a corresponding error generator 222. Each corresponding error generator 222 may be configured to compare the control current 220 and the corresponding sensed phase current (or the corresponding digital code) and generate an error signal 224 representing the difference between the control current 220 and the corresponding sensed phase current. Each error signal 224 may be provided to a corresponding digital compensator 226 (e.g., a proportional-integral (PI) controller) that uses PI parameters, such as a proportional coefficient Kp and an integral coefficient Ki, for generating a PWM control signal for a corresponding power stage 104.

[0060] The current limit controller 106 enables the voltage and current compensation loop of the voltage regulator 200 to temporarily provide sufficient output current exceeding the current limit setting without stressing the 12V input power supply, and when the current limit controller 106 enters the current limit mode, the target current can be limited to a lower level. During the current limit mode, the voltage regulator can perform in a constant current mode (e.g., when the output of the programmable current limiter 216 can be clamped to the current limit value LIM), and the output voltage is allowed to fold back to protect the 12V input power supply.

[0061] As indicated above, Figure 2 Provided as an example. Other examples may differ from Figure 2 Examples described. Figure 2 The number and arrangement of devices and components shown are provided as examples. Figure 2 There may be more devices or components, fewer devices or components, different devices or components, or differently arranged devices or components than those shown.

[0062] The following provides an overview of some aspects of the disclosure:

[0063] Aspect 1: A voltage regulator, comprising: a plurality of power stages configured to generate a plurality of phase currents, wherein the sum of the plurality of phase currents represents a total current, and wherein each of the plurality of power stages is configured to generate a corresponding phase current among the plurality of phase currents; an adder circuit configured to sense the plurality of phase currents and generate a summed current value representing the total current generated by the plurality of power stages; and a current limiting controller configurable to a current limiting mode or a non-current limiting mode, and configured to limit the total current to a predetermined value during the current limiting mode, wherein the current limiting controller is configured to receive the summed current value, and wherein the current limiting controller comprises: a threshold selector circuit configured to select a first threshold or a second threshold as a selected threshold based on a configuration signal, wherein the second threshold is smaller than at the first threshold, when the current limit controller is set to a non-current limiting mode, the threshold selector circuit is configured to select the first threshold as the selected threshold, and wherein, when the current limit controller is set to a current limiting mode, the threshold selector circuit is configured to select the second threshold as the selected threshold; and a first monitoring path, comprising: a first comparator circuit, the first comparator circuit being configured with a dynamic threshold set to the selected threshold, wherein the first comparator circuit is configured to compare the total current value with the selected threshold and generate a first comparison result indicating whether the total current value satisfies the selected threshold; and a mode configuration circuit, the mode configuration circuit being configured to monitor a first duration, during which the first comparison result indicates that the total current value satisfies the selected threshold, and to generate a configuration signal based on whether the first duration satisfies the duration threshold.

[0064] Aspect 2: A voltage regulator according to Aspect 1, wherein the total current value satisfies the selected threshold if the total current value is greater than the selected threshold, wherein the first duration satisfies the duration threshold if the first duration is greater than the duration threshold, or the first duration satisfies the duration threshold if the first duration is equal to or greater than the duration threshold, and wherein the mode configuration circuit is configured to generate a configuration signal to set the current limiting controller to a current limiting mode if the first duration satisfies the duration threshold.

[0065] Aspect 3: A voltage regulator according to any one of Aspects 1 to 2, wherein the mode configuration circuit includes: a time delay filter, which is configured to monitor a first duration, during which a first comparison result indicates that the total current value satisfies a selected threshold, and when the first duration satisfies the duration threshold, generates a current limiting mode control signal indicating that the first duration satisfies the duration threshold; and a latch, which is configured to receive the current limiting mode control signal and generate a configuration signal to set the current limiting controller to a current limiting mode.

[0066] Aspect 4: A voltage regulator according to aspect 3, wherein the latch is configured to be reset based on the first comparison result indicating that the total current value does not meet the selected threshold, and wherein, based on the latch being reset, the latch is configured to generate a configuration signal to set the current limit controller to a non-current limiting mode.

[0067] Aspect 5: A voltage regulator according to any one of Aspects 1 to 4, wherein the current limiting controller also includes a programmable current limiter, which is configured to receive a configuration signal and set a total control current of the total current of the voltage regulator, and wherein, when the current limiting controller is set to a current limiting mode by the configuration signal, the programmable current limiter is configured to limit the total control current to a current limiting value, so that the total current is limited to a predetermined value, wherein the predetermined value corresponds to the current limiting value.

[0068] Aspect 6: A voltage regulator according to any one of Aspects 1 to 5, wherein the current limiting controller includes: a second monitoring path, including: a low-pass filter, which is configured to receive a total current value and output a filtered current value; a second comparator circuit, which is configured with a third threshold value less than the first threshold value, wherein the second comparator circuit is configured to compare the filtered current value with the third threshold value and generate a second comparison result indicating whether the filtered current value meets the third threshold value; and a mode configuration circuit, which is configured to monitor a second duration, during which the second comparison result indicates that the filtered current value meets the third threshold value, and generate a configuration signal based on whether the second duration meets the duration threshold.

[0069] Aspect 7: A voltage regulator according to Aspect 6, wherein if the filtered current value is greater than a third threshold, the filtered current value satisfies the third threshold, wherein if the second duration is greater than the duration threshold, the second duration satisfies the duration threshold, or if the second duration is equal to or greater than the duration threshold, the second duration satisfies the duration threshold, and wherein the mode configuration circuit is configured to generate a configuration signal to set the current limiting controller to a current limiting mode if the second duration satisfies the duration threshold.

[0070] Aspect 8: A voltage regulator according to Aspect 6, wherein the mode configuration circuit includes: a time delay filter configured to monitor a second duration, during which a second comparison result indicates that the filtered current value satisfies a third threshold, and when the second duration satisfies the duration threshold, a current limiting mode control signal is generated indicating that the second duration satisfies the duration threshold; and a latch configured to receive the current limiting mode control signal and generate a configuration signal to set the current limiting controller to a current limiting mode.

[0071] Aspect 9: A voltage regulator according to Aspect 8, wherein the latch is configured to be reset based on the second comparison result indicating that the filtered current value does not meet the third threshold, and wherein, based on the latch being reset, the latch is configured to generate a configuration signal to set the current limiting controller to a non-current limiting mode.

[0072] Aspect 10: A voltage regulator according to Aspect 6, wherein the current limiting controller also includes a programmable current limiter, which is configured to receive a configuration signal and set a total control current of the total current of the voltage regulator, and wherein, when the current limiting controller is set to a current limiting mode through the configuration signal, the programmable current limiter is configured to limit the total control current to a current limiting value, so that the total current is limited to a predetermined value, wherein the predetermined value corresponds to the current limiting value.

[0073] Aspect 11: The voltage regulator according to Aspect 6, wherein the third threshold is greater than the second threshold.

[0074] Aspect 12: A voltage regulator according to Aspect 6, wherein the current limit controller includes an OR logic gate, which is coupled to the first monitoring path to receive the first comparison result and coupled to the second monitoring path to receive the second comparison result, wherein the output of the OR logic gate is coupled to the input of the mode configuration circuit.

[0075] Aspect 13: A voltage regulator according to Aspect 6, wherein if the total current value is greater than a selected threshold, the total current value satisfies the selected threshold, wherein if the first duration is greater than the duration threshold, the first duration satisfies the duration threshold, or if the first duration is equal to or greater than the duration threshold, the first duration satisfies the duration threshold, wherein if the filtered current value is greater than a third threshold, the filtered current value satisfies the third threshold, wherein if the second duration is greater than the duration threshold, the second duration satisfies the duration threshold, or if the second duration is equal to or greater than the duration threshold, the second duration satisfies the duration threshold, and wherein the mode configuration circuit is configured to generate a configuration signal to set the current limiting controller to a current limiting mode if the first duration satisfies the duration threshold or if the second duration satisfies the duration threshold.

[0076] Aspect 14: A voltage regulator according to Aspect 13, wherein the current limiting controller also includes a programmable current limiter, which is configured to receive a configuration signal and set a total control current of the total current of the voltage regulator, and wherein, when the current limiting controller is set to a current limiting mode by the configuration signal, the programmable current limiter is configured to limit the total control current to a current limiting value so that the total current is limited to a predetermined value, wherein the predetermined value corresponds to the current limiting value.

[0077] Aspect 15: A voltage regulator according to any one of Aspects 1 to 14, wherein each of the plurality of power stages comprises a corresponding gate driver and a corresponding transistor half-bridge, the corresponding transistor half-bridge being configured to be driven by the corresponding gate driver to generate a corresponding phase current.

[0078] Aspect 16: A multi-phase controller comprising: an adder circuit configured to sense multiple phase currents generated by multiple power stages and generate a sum current value representing a total current generated by the multiple power stages; and a current limiting controller configurable to a current limiting mode or a non-current limiting mode and configured to limit the total current to a predetermined value during the current limiting mode, wherein the current limiting controller is configured to receive the sum current value, and wherein the current limiting controller comprises: a threshold selector circuit configured to select a first threshold or a second threshold as a selected threshold based on a configuration signal, wherein the second threshold is less than the first threshold, wherein when the current limiting controller is set to the non-current limiting mode, the threshold selector circuit The threshold selector circuit is configured to select a first threshold as a selected threshold, and wherein, when the current limit controller is set to the current limit mode, the threshold selector circuit is configured to select a second threshold as the selected threshold; and a first monitoring path, comprising: a first comparator circuit, the first comparator circuit being configured with a dynamic threshold set to the selected threshold, wherein the first comparator circuit is configured to compare the total current value with the selected threshold and generate a first comparison result indicating whether the total current value satisfies the selected threshold; and a mode configuration circuit, the mode configuration circuit being configured to monitor a first duration, during which the first comparison result indicates that the total current value satisfies the selected threshold, and generate a configuration signal based on whether the first duration satisfies the duration threshold.

[0079] Aspect 17: A multi-phase controller according to Aspect 16, wherein the total current value satisfies the selected threshold if the total current value is greater than the selected threshold, wherein the first duration satisfies the duration threshold if the first duration is greater than the duration threshold, or the first duration satisfies the duration threshold if the first duration is equal to or greater than the duration threshold, and wherein the mode configuration circuit is configured to generate a configuration signal to set the current limiting controller to a current limiting mode if the first duration satisfies the duration threshold.

[0080] Aspect 18: A multi-phase controller according to any one of Aspects 16 to 17, wherein the current limiting controller includes: a second monitoring path, comprising: a low-pass filter, which is configured to receive a total current value and output a filtered current value; a second comparator circuit, which is configured with a third threshold value less than the first threshold value, wherein the second comparator circuit is configured to compare the filtered current value with the third threshold value and generate a second comparison result indicating whether the filtered current value meets the third threshold value; and a mode configuration circuit, which is configured to monitor a second duration, during which the second comparison result indicates that the filtered current value meets the third threshold value, and generate a configuration signal based on whether the second duration meets the duration threshold.

[0081] Aspect 19: A multi-phase controller according to Aspect 18, wherein the filtered current value satisfies the third threshold if the filtered current value is greater than a third threshold, wherein the second duration satisfies the duration threshold if the second duration is greater than the duration threshold, or the second duration satisfies the duration threshold if the second duration is equal to or greater than the duration threshold, and wherein the mode configuration circuit is configured to generate a configuration signal to set the current limiting controller to a current limiting mode if the second duration satisfies the duration threshold.

[0082] Aspect 20: A method for limiting a total phase current generated by multiple power stages, the method comprising: sensing multiple phase currents generated by multiple power stages; generating a sum current value representing a total phase current of the multiple phase currents; configuring a current limiting controller to a current limiting mode or a non-current limiting mode, wherein the current limiting controller is configured to limit the total phase current to a predetermined value during the current limiting mode; selecting a first threshold or a second threshold as a selected threshold based on a configuration signal, wherein the second threshold is less than the first threshold, wherein when the current limiting controller is set to the non-current limiting mode, the first threshold is used as the selected threshold, and wherein when the current limiting controller is set to the current limiting mode, the second threshold is used as the selected threshold; comparing the sum current value with the selected threshold; generating a first comparison result, the first comparison result indicating whether the sum current value satisfies the selected threshold; monitoring a first duration, during which the first comparison result indicates that the sum current value satisfies the selected threshold; and generating a configuration signal based on whether the first duration satisfies the duration threshold.

[0083] Aspect 21: The method according to Aspect 20 also includes: low-pass filtering the total current value to generate a filtered current value; comparing the filtered current value with a third threshold value that is less than the first threshold value; generating a second comparison result indicating whether the filtered current value meets the third threshold value; monitoring a second duration, during which the second comparison result indicates that the filtered current value meets the third threshold value; and generating a configuration signal based on whether the second duration meets the duration threshold.

[0084] Aspect 22: A system configured to perform one or more operations described in one or more of Aspects 1 to 21.

[0085] Aspect 23: An apparatus comprising means for performing one or more operations described in one or more of Aspects 1 to 21.

[0086] Aspect 24: A non-transitory computer-readable medium storing a set of instructions, the set of instructions comprising one or more instructions, which when executed by a device, causes the device to perform one or more operations described in one or more of aspects 1 to 21.

[0087] Aspect 25: A computer program product comprising instructions or codes for performing one or more operations described in one or more of Aspects 1 to 21.

[0088] The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the implementations to the precise forms disclosed. Modifications and variations may be made in light of the above disclosure or may be acquired from practice of the implementations.

[0089] Some implementations may be described herein in conjunction with a threshold value. As used herein, satisfying a threshold value may refer to a value being greater than a threshold value, more than a threshold value, above a threshold value, greater than or equal to a threshold value, less than a threshold value, less than a threshold value, below a threshold value, less than or equal to a threshold value, equal to a threshold value, etc.

[0090] As used herein, the term "component" is intended to be broadly interpreted as hardware, firmware, or a combination of hardware and software. The systems and / or methods described herein can be implemented in different forms of hardware, firmware, or a combination of hardware and software. The actual dedicated control hardware or software code used to implement these systems and / or methods does not limit the implementation. Therefore, the operation and behavior of the systems and / or methods are described herein without reference to specific software codes, and it should be understood that software and hardware can be designed to implement the systems and / or methods based on the description herein.

[0091] Any of the processing components can be implemented as a central processing unit (CPU) or other processor that reads and executes a software program from a non-transient computer-readable recording medium such as a hard disk or a semiconductor memory device. For example, instructions can be executed by one or more processors, such as one or more CPUs, digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field programmable logic arrays (FPLAs), programmable logic controllers (PLCs), or other equivalent integrated or discrete logic circuit systems. Therefore, the term "processor" used in this article refers to any of the aforementioned structures or any other structure suitable for implementing the technology described herein. The software can be stored on a non-transient computer-readable medium, so that the non-transient computer-readable medium includes a program code or a program algorithm stored thereon, which causes the processor to perform the steps of the method by a computer program when executed.

[0092] A controller including hardware may also perform one or more of the techniques of the present disclosure. A controller including one or more processors may use electrical signals and digital algorithms to perform its receiving, analyzing, and controlling functions, which may also include correction functions. Such hardware, software, and firmware may be implemented in the same device or in different devices to support the various techniques described in the present disclosure.

[0093] Signal processing circuitry and / or signal conditioning circuitry may receive one or more signals (e.g., measurement signals) from one or more components in the form of raw measurement data, and may derive additional information from the measurement signals. As used herein, "signal conditioning" refers to manipulating an analog signal so that the signal meets further processing requirements at the next stage. Signal conditioning may include conversion from analog to digital (e.g., via an analog-to-digital converter), amplification, filtering, conversion, biasing, range matching, isolation, and any other processing required to make the signal suitable for processing after conditioning.

[0094] Even if a particular feature combination is listed in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the implementation described herein. Many of these features can be combined in a manner not specifically listed in the claims and / or not disclosed in the specification. For example, the present disclosure includes each dependent claim in the claim group combined with each other individual claim in the claim group and each combination of multiple claims in the claim group. As used herein, the phrase "at least one" mentioned in the project list refers to any combination of these projects, including single members. For example, "at least one of a, b or c" is intended to cover a, b, c, a and b, a and c, b and c and a, b and c, and any combination with multiple identical elements (for example, a+a, a+a+a, a+a+b, a+a+c, a+b+b, a+c+c, b+b, b+b+b, b+b+c, c+c and c+c+c or any other order of a, b and c).

[0095] In addition, it should be understood that the disclosure of multiple actions or functions disclosed in the specification or claims may not be interpreted as being in a specified order. Therefore, the disclosure of multiple actions or functions will not limit these actions or functions to a specific order unless these actions or functions are not interchangeable for technical reasons. In addition, in some implementations, a single action may include multiple sub-actions, or may be decomposed into multiple sub-actions. Unless explicitly excluded, such sub-actions may be included and are part of the disclosure of the single action.

[0096] When "a component" or "one or more components" (or another element, such as a "controller" or "one or more controllers") is described or claimed (either within a single claim or across multiple claims) to perform or be configured to perform multiple operations, the language is intended to broadly cover a variety of architectures and environments. For example, unless otherwise expressly required (e.g., via the use of "a first component" and "a second component" or other language that distinguishes components in a claim), the language is intended to cover a single component that performs or is configured to perform all operations, a group of components that collectively perform or are configured to perform all operations, a first component that performs or is configured to perform a first operation and a second component that performs or is configured to perform a second operation, or any combination of components that perform or are configured to perform operations. For example, when a claim has the form "one or more components are configured to: perform X; perform Y; and perform Z," the claim should be interpreted as "one or more components are configured to perform X; one or more (possibly different) components are configured to perform Y; and one or more (possibly different) components are configured to perform Z."

[0097] Unless explicitly stated, the elements, actions or instructions used in this article should not be interpreted as key or necessary elements, actions or instructions. In addition, as used in this article, the articles "one" and "an" are intended to include one or more projects, and can be used interchangeably with "one or more". In addition, as used in the text, the article "the" is intended to include one or more projects quoted in combination with the article "the", and can be used interchangeably with "one or more". If only intended for a project, the phrases "only one", "single" or similar language are used. In addition, as used in this article, the terms "have", "have", "contain" etc. are intended to be open terms (for example, "having" A elements may also have B) that do not limit the elements modified. In addition, unless explicitly stated otherwise, the phrase "based on" means "at least partially based on". As used in this article, the term "multiple" can be replaced by "plurality", and vice versa. In addition, as used in this article, the term "or" is intended to be inclusive when used continuously, and can be used interchangeably with "and / or", unless explicitly stated otherwise (for example, if used in combination with "any one" or "only one").

Claims

1. A voltage regulator, comprising: a plurality of power stages configured to generate a plurality of phase currents, wherein a sum of the plurality of phase currents represents a total current, and wherein each power stage of the plurality of power stages is configured to generate a respective phase current of the plurality of phase currents; an adder circuit configured to sense the plurality of phase currents and generate a summed current value representative of the total current generated by the plurality of power stages; and a current limiting controller configurable in a current limiting mode or a non-current limiting mode and configured to limit the total current to a predetermined value during the current limiting mode, wherein the current limiting controller is configured to receive the total current value, and wherein the current limiting controller comprises: a threshold selector circuit configured to select the first threshold or the second threshold as a selected threshold based on a configuration signal, wherein the second threshold is smaller than the first threshold, wherein, when the current limit controller is set to the non-current limit mode, the threshold selector circuit is configured to select the first threshold as the selected threshold, and wherein, when the current limit controller is set to the current limit mode, the threshold selector circuit is configured to select the second threshold as the selected threshold; and The first monitoring path includes: a first comparator circuit configured with a dynamic threshold value set to the selected threshold value, wherein the first comparator circuit is configured to compare the summed current value with the selected threshold value and generate a first comparison result indicating whether the summed current value satisfies the selected threshold value; and A mode configuration circuit is configured to monitor a first duration during which the first comparison result indicates that the summed current value satisfies the selected threshold, and to generate the configuration signal based on whether the first duration satisfies a duration threshold.

2. The voltage regulator according to claim 1, wherein: If the sum current value is greater than the selected threshold, then the sum current value satisfies the selected threshold, wherein the first duration satisfies the duration threshold if the first duration is greater than the duration threshold, or the first duration satisfies the duration threshold if the first duration is equal to or greater than the duration threshold, and The mode configuration circuit is configured to generate the configuration signal to set the current limit controller to the current limit mode if the first duration satisfies the duration threshold.

3. The voltage regulator according to claim 1, wherein: The mode configuration circuit comprises: a time delay filter configured to monitor the first duration during which the first comparison result indicates that the sum current value satisfies the selected threshold, and when the first duration satisfies the duration threshold, generate a current limit mode control signal indicating that the first duration satisfies the duration threshold; and A latch is configured to receive the current limit mode control signal and generate the configuration signal to set the current limit controller to the current limit mode.

4. The voltage regulator according to claim 3, wherein: The latch is configured to be reset based on the first comparison result indicating that the summed current value does not satisfy the selected threshold, and Wherein, based on the latch being reset, the latch is configured to generate the configuration signal to set the current limit controller to the non-current limit mode.

5. The voltage regulator according to claim 1, wherein: The current limit controller further includes a programmable current limiter configured to receive the configuration signal and set a total control current of the total current of the voltage regulator, and When the current limiting controller is set to the current limiting mode through the configuration signal, the programmable current limiter is configured to limit the total control current to a current limiting value so that the total current is limited to the predetermined value, wherein the predetermined value corresponds to the current limiting value.

6. The voltage regulator according to claim 1, wherein: The current limiting controller comprises: The second monitoring path includes: a low pass filter configured to receive the summed current value and output a filtered current value; a second comparator circuit configured with a third threshold value that is less than the first threshold value, wherein the second comparator circuit is configured to compare the filtered current value with the third threshold value and generate a second comparison result indicating whether the filtered current value satisfies the third threshold value; and The mode configuration circuit is configured to monitor a second duration during which the second comparison result indicates that the filtered current value meets the third threshold, and generate the configuration signal based on whether the second duration meets the duration threshold.

7. The voltage regulator according to claim 6, wherein: If the filtered current value is greater than the third threshold, then the filtered current value satisfies the third threshold, wherein the second duration satisfies the duration threshold if the second duration is greater than the duration threshold, or the second duration satisfies the duration threshold if the second duration is equal to or greater than the duration threshold, and The mode configuration circuit is configured to generate the configuration signal to set the current limit controller to the current limit mode if the second duration satisfies the duration threshold.

8. The voltage regulator according to claim 6, wherein: The mode configuration circuit comprises: a time delay filter configured to monitor the second duration, during which the second comparison result indicates that the filtered current value satisfies the third threshold, and, when the second duration satisfies the duration threshold, generate a current limit mode control signal indicating that the second duration satisfies the duration threshold; and A latch is configured to receive the current limit mode control signal and generate the configuration signal to set the current limit controller to the current limit mode.

9. The voltage regulator according to claim 8, wherein: The latch is configured to be reset based on the second comparison result indicating that the filtered current value does not meet the third threshold, and Wherein, based on the latch being reset, the latch is configured to generate the configuration signal to set the current limit controller to the non-current limit mode.

10. The voltage regulator according to claim 6, wherein: The current limit controller further includes a programmable current limiter configured to receive the configuration signal and set a total control current of the total current of the voltage regulator, and When the current limiting controller is set to the current limiting mode through the configuration signal, the programmable current limiter is configured to limit the total control current to a current limiting value so that the total current is limited to the predetermined value, wherein the predetermined value corresponds to the current limiting value.

11. The voltage regulator according to claim 6, wherein: The third threshold is greater than the second threshold.

12. The voltage regulator according to claim 6, wherein: The current limit controller includes an OR logic gate coupled to the first monitoring path to receive the first comparison result and coupled to the second monitoring path to receive the second comparison result, wherein an output of the OR logic gate is coupled to an input of the mode configuration circuit.

13. The voltage regulator according to claim 6, wherein: If the sum current value is greater than the selected threshold, then the sum current value satisfies the selected threshold, wherein if the first duration is greater than the duration threshold, the first duration satisfies the duration threshold, or if the first duration is equal to or greater than the duration threshold, the first duration satisfies the duration threshold, If the filtered current value is greater than the third threshold, then the filtered current value satisfies the third threshold. wherein the second duration satisfies the duration threshold if the second duration is greater than the duration threshold, or the second duration satisfies the duration threshold if the second duration is equal to or greater than the duration threshold, and The mode configuration circuit is configured to generate the configuration signal to set the current limit controller to the current limit mode if the first duration satisfies the duration threshold or if the second duration satisfies the duration threshold.

14. The voltage regulator according to claim 13, wherein: The current limit controller further includes a programmable current limiter configured to receive the configuration signal and set a total control current of the total current of the voltage regulator, and When the current limiting controller is set to the current limiting mode through the configuration signal, the programmable current limiter is configured to limit the total control current to a current limiting value so that the total current is limited to the predetermined value, wherein the predetermined value corresponds to the current limiting value.

15. The voltage regulator according to claim 1, wherein: Each power stage of the plurality of power stages includes a corresponding gate driver and a corresponding transistor half-bridge, the corresponding transistor half-bridge being configured to be driven by the corresponding gate driver to generate the corresponding phase current.

16. A multi-phase controller comprising: an adder circuit configured to sense a plurality of phase currents generated by a plurality of power stages and to generate a summed current value representative of a total current generated by the plurality of power stages; as well as a current limiting controller configurable in a current limiting mode or a non-current limiting mode and configured to limit the total current to a predetermined value during the current limiting mode, wherein the current limiting controller is configured to receive the total current value, and wherein the current limiting controller comprises: a threshold selector circuit configured to select the first threshold or the second threshold as a selected threshold based on a configuration signal, wherein the second threshold is smaller than the first threshold, wherein, when the current limit controller is set to the non-current limit mode, the threshold selector circuit is configured to select the first threshold as the selected threshold, and wherein, when the current limit controller is set to the current limit mode, the threshold selector circuit is configured to select the second threshold as the selected threshold; and The first monitoring path includes: a first comparator circuit configured with a dynamic threshold value set to the selected threshold value, wherein the first comparator circuit is configured to compare the summed current value with the selected threshold value and generate a first comparison result indicating whether the summed current value satisfies the selected threshold value; and A mode configuration circuit is configured to monitor a first duration during which the first comparison result indicates that the summed current value satisfies the selected threshold, and to generate the configuration signal based on whether the first duration satisfies a duration threshold.

17. The multi-phase controller according to claim 16, wherein: If the sum current value is greater than the selected threshold, then the sum current value satisfies the selected threshold, wherein the first duration satisfies the duration threshold if the first duration is greater than the duration threshold, or the first duration satisfies the duration threshold if the first duration is equal to or greater than the duration threshold, and The mode configuration circuit is configured to generate the configuration signal to set the current limit controller to the current limit mode if the first duration satisfies the duration threshold.

18. The multi-phase controller according to claim 16, wherein: The current limiting controller comprises: The second monitoring path includes: a low pass filter configured to receive the summed current value and output a filtered current value; a second comparator circuit configured with a third threshold value that is less than the first threshold value, wherein the second comparator circuit is configured to compare the filtered current value with the third threshold value and generate a second comparison result indicating whether the filtered current value satisfies the third threshold value; and The mode configuration circuit is configured to monitor a second duration during which the second comparison result indicates that the filtered current value meets the third threshold, and generate the configuration signal based on whether the second duration meets the duration threshold.

19. The multi-phase controller according to claim 18, wherein: If the filtered current value is greater than the third threshold, then the filtered current value satisfies the third threshold, wherein the second duration satisfies the duration threshold if the second duration is greater than the duration threshold, or the second duration satisfies the duration threshold if the second duration is equal to or greater than the duration threshold, and The mode configuration circuit is configured to generate the configuration signal to set the current limit controller to the current limit mode if the second duration satisfies the duration threshold.

20. A method of limiting a total phase current generated by a plurality of power stages, the method comprising: sensing a plurality of phase currents generated by the plurality of power stages; generating a sum current value representing a total phase current of the plurality of phase currents; configuring a current limiting controller to a current limiting mode or a non-current limiting mode, wherein the current limiting controller is configured to limit the total phase current to a predetermined value during the current limiting mode; selecting the first threshold or the second threshold as the selected threshold based on the configuration signal, wherein the second threshold is smaller than the first threshold, wherein when the current limiting controller is set to the non-current limiting mode, the first threshold is used as the selected threshold, and wherein, when the current limiting controller is set to the current limiting mode, the second threshold is used as the selected threshold; comparing the summed current value to the selected threshold; generating a first comparison result indicating whether the summed current value satisfies the selected threshold; monitoring a first duration during which the first comparison result indicates that the summed current value satisfies the selected threshold; and The configuration signal is generated based on whether the first duration satisfies a duration threshold.

21. The method according to claim 20, further comprising: low pass filtering the summed current value to generate a filtered current value; comparing the filtered current value to a third threshold value that is less than the first threshold value; generating a second comparison result indicating whether the filtered current value satisfies the third threshold; monitoring a second duration, during which the second comparison result indicates that the filtered current value satisfies the third threshold; and The configuration signal is generated based on whether the second duration satisfies the duration threshold.

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