Storage method for simulating EEPROM

Abstract

The invention discloses a storage method for simulating an EEPROM (Electrically Erasable Programmable Read-Only Memory), which comprises the following steps of: performing storage region division operation on a FLASH storage unit to obtain a first region and a second region, writing data into the first region, entering an erasing working state after the first region is full of the data, starting to enter a writing state by the second region, and starting to write the data into the second region; after the second area is full of data, the first area enters the write-in state again, and the second area starts to enter the erasing state; the ineffective time after the first area and the second area return to the empty state from the to-be-cleaned state is greatly shortened; according to the method, all the marked units are storage units which are not filled with effective data, and the states of the storage units in the two areas are clear, so that the complexity of data management is reduced, and the problems of low space utilization rate and incomplete states of an existing storage method for simulating EEPROM by FLASH are solved.

Description

Technical Field

[0001] The invention relates to the technical field of embedded development, and in particular to a storage method for simulating EEPROM. Background Art

[0002] FLASH is a storage device that can save data when power is off. The data stored in this device is not easy to lose and the cost is relatively low. It is usually used to save codes and data that need to be saved for a long time. Due to the circuit characteristics of FLASH storage devices, when rewriting the internal data of FLASH, the internal area of ​​FLASH must be erased first, and the erasure must be done in units of sectors, blocks or the entire FLASH. This process is complex and time-consuming, and is not suitable for modifying scattered data.

[0003] EEPROM is a storage device that can save data when power is off. This storage device can modify any data in the storage space at will, and the number of erasures is higher than FLASH, and the stored data is also not easily lost. Compared with the FLASH storage method, the EEPROM storage method seems to have better performance in all aspects, but it is accompanied by higher circuit complexity and lower storage density of EEPROM storage devices, which makes the cost of EEPROM storage devices much higher than that of FLASH storage devices, which makes the EEPROM storage method more used to store data rather than code.

[0004] In order to make up for the shortcomings of FLASH storage devices and EEPROM storage devices, some solutions that use FLASH storage devices to simulate the characteristics of EEPROM storage devices have emerged.

[0005] In the prior art, after the FLASH storage device is divided into two storage areas, data is first written into the first FLASH storage area. After the first FLASH storage area is full, part of the data is transferred to the second area. Subsequent data will continue to be written into the second area, while the first area is cleared. After the second area is full, part of the data is transferred to the first area in the same way to continue writing. This is repeated back and forth to realize the storage method of FLASH storage device simulating EEPROM. However, this FLASH simulating EEPROM solution has problems such as low space utilization and imperfect state, that is, after the first area in the FLASH simulating EEPROM is erased until the second area is full, the first area is invalid; there is an unclear storage space state in the entire simulation process; in the reciprocating alternation between the two areas, data needs to be repeatedly marked, transferred, stored and other complex operations. Summary of the invention

[0006] In order to improve and solve the deficiencies in the prior art, a storage method for simulating EEPROM is provided to solve the problems of low space utilization and imperfect state of the storage method for simulating EEPROM in the prior art.

[0007] In order to achieve the above technical effects, the technical solution adopted by the present invention is:

[0008] A storage method for simulating EEPROM, comprising the steps of:

[0009] S1: performing a storage area division operation on the FLASH storage unit to obtain a first area and a second area, and determining that a working state of the first area is different from a working state of the second area at the same time;

[0010] S2: making the first area enter a first writing state to write data into the first area in sequence, until the first area is full of data, making the first area enter a first erasing working state, and the second area enter a second writing state;

[0011] S3: after the first area enters the first erasing working state, traverse the data states of all erasing units in the first area to obtain the size of invalid data, mark all erasing units in the first area whose invalid data size is greater than half of the minimum erasing unit as first marking units, and perform an erasing operation on the first marking units to store valid data in the first marking units;

[0012] After the second area enters the second writing state, data is written into the second area until the second area is full of data, so that the second area enters the second erasing working state, and the first area re-enters the first writing state;

[0013] S4: looping step S2 to step S3 until it is determined that both the first area and the second area are filled with valid data.

[0014] Optionally, the storage method of simulating EEPROM further comprises step S0: determining the size of the storage space of the EEPROM to be simulated, so that the size of the storage space of the EEPROM to be simulated is N times the minimum erasing unit in the FLASH storage device, wherein N is a positive integer.

[0015] Optionally, in step S2, the step of causing the first area to enter a first writing state to sequentially write data into the first area includes:

[0016] continuously writing data into the first area, and when writing data that needs to be rewritten, continuing to write new data with a first mark into the first area;

[0017] The data to be rewritten is marked as invalid data, and the new data with the first mark is marked as valid data.

[0018] Optionally, in step S3, the step of performing an erasing operation on the first marking unit to store valid data in the first marking unit includes:

[0019] Traversing all data in the first marking unit and marking all data to obtain valid data and invalid data in the first marking unit;

[0020] Writing all valid data in the first marking unit into a RAM storage unit;

[0021] Erasing all data in the first marking unit;

[0022] The valid data in the RAM storage unit is written back to the first marking unit.

[0023] Optionally, in step S3, the step of the second area entering the second erasing working state includes:

[0024] Traverse the data status of all erase units in the second area to obtain the size of invalid data, mark all erase units in the second area whose invalid data size is greater than half of the minimum erase unit as second marking units, and perform an erase operation on the second marking unit to store valid data in the second marking unit.

[0025] Optionally, in step S4, the step of performing an erasing operation on the second marking unit to store valid data in the second marking unit includes:

[0026] Traversing all data in the second marking unit and marking all data to obtain valid data and invalid data in the second marking unit;

[0027] Writing all valid data in the second marking unit into a RAM storage unit;

[0028] Erasing all data in the second marking unit;

[0029] The valid data in the RAM storage unit is written back to the second marking unit.

[0030] Optionally, in step S4, the step of looping step S2 to step S3 until it is determined that both the first area and the second area are filled with valid data includes:

[0031] The first area and the second area are traversed, and when it is determined that the number of the first marking unit and the number of the second marking unit are both 0, it is determined that the first area and the second area are both filled with valid data.

[0032] Due to the adoption of the above technical solution, the present application has the following beneficial effects:

[0033] The present application first performs a storage area division operation on the FLASH storage unit to obtain a first area and a second area, first writes data into the first area, and after the first area is filled with data and enters the erase working state, the second area starts to enter the write state, and after the second area is filled with data, the first area re-enters the write state, and the second area starts to enter the erase state; the invalid time of the first area and the second area after returning from the to-be-cleaned state to the empty state is greatly reduced;

[0034] After the first area of ​​the present application enters the first erasing working state, the data states of all erasing units in the first area are traversed to obtain the size of invalid data, and all erasing units in the first area whose invalid data size is greater than half of the minimum erasing unit are marked as first marking units, and the first marking units are erased and written to store valid data in the first marking units; the marked units are all storage units that are not filled with valid data, and the states of the storage units in the two areas are clear, which reduces the complexity of data management and solves the problems of low space utilization and imperfect state of the existing FLASH emulation EEPROM storage method. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 The figure is a flow chart of a storage method of simulating EEPROM according to an embodiment of the present invention.

[0037] Figure 2 The flowchart of the storage method of simulating EEPROM in some other embodiments of the present invention. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] The present invention mainly provides a storage method for simulating EEPROM to solve the problems of low space utilization and imperfect state of the storage method for simulating EEPROM in the prior art.

[0040] See also Figure 1 The specific operation steps of the storage method of simulating EEPROM of the present invention are as follows:

[0041] S1: performing a storage area division operation on the FLASH storage unit to obtain a first area and a second area, and determining that a working state of the first area is different from a working state of the second area at the same time.

[0042] In some embodiments, the storage space of the first region and the storage space of the second region are equal in size.

[0043] In some embodiments, the FLASH storage unit is powered on, initialized and divided into two areas to obtain a first area and a second area, and all minimum units in the first area and the second area that are allowed to be erased are marked, that is, all erasable minimum storage units in the two areas are marked. At this time, all marked erasable minimum storage units in the first area and the second area are in an empty state.

[0044] S2: The first area is put into a first writing state to write data into the first area in sequence until the first area is fully written with data, and then the first area is put into a first erasing working state, and the second area is put into a second writing state.

[0045] As an optional implementation manner of the present invention, in step S2, the step of making the first area enter the first writing state to write data into the first area in sequence includes:

[0046] S21: continuously writing data into the first area, and when writing data that needs to be rewritten, continuing to write new data with a first mark into the first area;

[0047] S22: Mark the data to be rewritten as invalid data, and mark the new data with the first mark as valid data.

[0048] In some embodiments, the data to be rewritten may be positionally marked by the writing position of the index data, so as to accurately mark the data to be rewritten, thereby facilitating marking the data to be rewritten as invalid data.

[0049] In some embodiments, data is continuously written into the first area. When data that needs to be rewritten is encountered, the data already written into the first area is not modified. Instead, the latest data is continuously written. Then, by changing the index method, the original data that needs to be rewritten is marked as invalid data, and the replaced data is set as valid data to complete the data modification and replacement. For example, when the data written into the first area is 11, 22, 33, 44, and 55, after the storage device receives the request instruction to rewrite the second data 22, it transmits the sixth data 66 to replace 22, marks the data 22 as invalid data, and marks the new data carrying the first mark as valid data. At this time, the data 22 becomes invalid data, and the area storing the data 22 also becomes an invalid area. The invalid area will be cleared and then rewritten with new data until the area is filled with valid data.

[0050] S3: After the first area enters the first erasing working state, the data states of all erasing units in the first area are traversed to obtain the size of invalid data, all erasing units in the first area whose invalid data size is greater than half of the minimum erasing unit are marked as first marking units, and the first marking units are erased to store valid data in the first marking units;

[0051] After the second area enters the second writing state, data is written into the second area until the second area is fully written with data, so that the second area enters the second erasing working state, and the first area re-enters the first writing state.

[0052] Preferably, after the first area is full of data, data is immediately written to the second area, and the first area enters the erase operation, thereby avoiding the process in which a single storage area of ​​a traditional FLASH storage unit can only be written first, then erased, and then written and erased again, reducing the invalid time of the two storage areas, and effectively utilizing the gap time between the time when the first area is full of data and the time when the stored data is erased to write data to the second area; and after the second area is full of data, while the second area enters the erase state, the first area has stored valid data and enters the vacant state, and can re-enter the data writing state at this time, that is, the gap time between the time when the second area is full of data and the time when the stored data is erased is effectively utilized to write data to the first area, thus greatly shortening the data writing interval, improving storage efficiency, and reducing redundant erase operations caused by repeated marking and transfer of data in the two areas, so as to reduce the complexity of data management and increase the service life of FLASH storage devices.

[0053] In some embodiments, all erase units, data states and minimum erase units in the first area of ​​the FLASH storage unit are traversed, and the memory occupied by invalid data is calculated in each minimum erase unit. When the memory occupied by invalid data in the minimum erase unit is greater than half of the memory of the minimum erase unit, the minimum erase unit is marked as a first marking unit, and the first marking unit will be erased and written later.

[0054] As an optional implementation of the present invention, in step S3, the step of performing an erase operation on the first marking unit to store valid data in the first marking unit includes:

[0055] S31: traverse all data in the first marking unit and mark all data to obtain valid data and invalid data in the first marking unit;

[0056] S32: writing all valid data in the first marking unit into the RAM storage unit;

[0057] S33: Erasing all data in the first marking unit;

[0058] S34: Write the valid data in the RAM storage unit back to the first marking unit.

[0059] In some specific embodiments, ten data are stored in the first marking unit, and the data are 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9 respectively. After marking, 1 and 9 are determined to be valid data, and the rest of the data are invalid data. The valid data 1 and 9 are written into the RAM storage unit and temporarily stored in the RAM storage unit; then all the data in the first marking unit are erased, and finally the valid data temporarily stored in the RAM storage unit is written back to the first marking unit in order of arrangement. At this time, the content of the data space in the first marking unit is: 1, 9, no data, no data, no data, no data, no data, no data, no data, no data, and these storage spaces with no data can continue to write data and store data subsequently, that is, after the first area re-enters the first write state, the data will be written into these storage spaces with no data, and new valid data can be saved subsequently.

[0060] In some embodiments, after step S34 is completed, that is, after the erase operation is completed on all the first marking units in the first area, valid data is stored in the first area and there is no invalid data. At this time, the state of the first area is updated to an empty state, and a new round of writing and erasing operations is performed after the second area is full of data.

[0061] In some embodiments, in step S3, after the second area enters the second writing state, the step of writing data to the second area includes:

[0062] continuously writing data into the second area, and when writing data that needs to be rewritten, continuing to write new data with a second mark into the second area;

[0063] The data to be rewritten is marked as invalid data, and the new data with the second mark is marked as valid data. That is, the data to be rewritten is processed in the same way in the first area and the second area, and both realize the modification and replacement of the data to be rewritten, so that the original data to be rewritten can be erased later, and the new data with the second mark can be stored as valid data.

[0064] As an optional implementation of the present invention, in step S3, the step of the second area entering the second erasing working state includes:

[0065] Traverse the data status of all erase units in the second area to obtain the size of invalid data, mark all erase units in the second area whose invalid data size is greater than half of the minimum erase unit as second marking units, and perform erase operations on the second marking units to store valid data in the second marking units.

[0066] In some embodiments, all erase units, data states and minimum erase units in the second area of ​​the FLASH storage unit are traversed, and the memory occupied by invalid data is calculated in each minimum erase unit. When the memory occupied by invalid data in the minimum erase unit is greater than half of the memory of the minimum erase unit, the minimum erase unit is marked as a second marking unit, and the second marking unit will be erased and written later.

[0067] As an optional implementation of the present invention, in step S3, the step of performing an erase operation on the second marking unit to store valid data in the second marking unit includes:

[0068] Traversing all data in the second marking unit and marking all data to obtain valid data and invalid data in the second marking unit;

[0069] Writing all valid data in the second marking unit into the RAM storage unit;

[0070] Erasing all data in the second marking unit;

[0071] The valid data in the RAM storage unit is written back to the second marking unit.

[0072] In some embodiments, the specific steps of performing an erasing operation on the second marking unit to store valid data in the second marking unit are similar to the above-mentioned steps S31 to S34, which are all to mark the marked unit with valid data and invalid data, and write the valid data into the RAM storage unit for temporary storage, and then erase all the data in the marking unit, and then write the valid data temporarily stored in the RAM storage unit back to the marking unit in arrangement, so as to achieve the purpose of storing the valid data in the marking unit.

[0073] S4: looping step S2 to step S3 until it is determined that both the first area and the second area are filled with valid data.

[0074] As an optional implementation of the present invention, in step S4, the step of looping step S2 to step S3 until it is determined that both the first area and the second area are filled with valid data includes:

[0075] S41: traverse the first area and the second area, and when it is determined that the numbers of the first marking unit and the second marking unit are both 0, it is determined that the first area and the second area are both filled with valid data, and all operations are terminated.

[0076] In some embodiments, when the number of marking units in any area is 0, data can only be written to the area where the marking units are not 0. For example, when only the number of first marking units is 0, the first area is in a full storage state, and data can only be written to the second area at this time; when only the number of second marking units is 0, the second area is in a full storage state, and data can only be written to the first area at this time; when and only when the numbers of first marking units and second marking units are both 0, the first area and the second area are both in a full storage state; at this time, the amount of stored data in the first area and the second area is greater than the EEPROM storage space to be simulated, thereby achieving the purpose of the FLASH storage unit simulating the EEPROM storage unit.

[0077] See also Figure 2 In some other embodiments of the present application, the storage method of simulating EEPROM of the present application further performs step S0 before performing step S1:

[0078] The size of the storage space of the EEPROM to be simulated is determined so that the size of the storage space is N times the minimum erasing unit in the FLASH storage device, where N is a positive integer. Preferably, the size of the storage space of the EEPROM to be simulated is determined to be a positive integer multiple of the minimum erasing unit in the FLASH storage device, so as to ensure that when the subsequent erasing and writing operations are performed on the marking units of the first area and the second area, the erasing and writing operations are smoothly performed, and the stability of the erasing and writing operations is ensured. It can be explained that the minimum erasing unit in the present application refers to the smallest erasable unit when performing an erasing operation, which can be a sector or block in the FLASH storage space. The specific size is determined according to the model of the FLASH chip, which will not be repeated here.

[0079] In summary, the storage method of simulating EEPROM of the present application has the following advantages:

[0080] (1) The present application first performs a storage area division operation on the FLASH storage unit to obtain a first area and a second area, first writes data into the first area, and after the first area is filled with data and enters the erase working state, the second area starts to enter the write state, and after the second area is filled with data, the first area re-enters the write state, and the second area starts to enter the erase state; the invalid time of the first area and the second area after returning from the to-be-cleaned state to the empty state is greatly reduced;

[0081] (2) After the first area of ​​the present application enters the first erasing working state, the data states of all erasing units in the first area are traversed to obtain the size of invalid data, and all erasing units in the first area whose invalid data size is greater than half of the minimum erasing unit are marked as first marked units, and the first marked units are erased and written to store valid data in the first marked units; the marked units are all storage units that are not filled with valid data, and the states of the storage units in the two areas are clear, which reduces the complexity of data management and solves the problems of low space utilization and imperfect state of the existing FLASH emulation EEPROM storage method.

[0082] It should be noted that, in this article, terms such as "comprises", "includes" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0083] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A storage method for simulating EEPROM, characterized in that: Includes steps: S1: performing a storage area division operation on the FLASH storage unit to obtain a first area and a second area, and determining that a working state of the first area is different from a working state of the second area at the same time; S2: making the first area enter a first writing state to write data into the first area in sequence, until the first area is full of data, making the first area enter a first erasing working state, and the second area enter a second writing state; S3: after the first area enters the first erasing working state, traverse the data states of all erasing units in the first area to obtain the size of invalid data, mark all erasing units in the first area whose invalid data size is greater than half of the minimum erasing unit as first marking units, and perform an erasing operation on the first marking units to store valid data in the first marking units; After the second area enters the second writing state, data is written into the second area until the second area is full of data, so that the second area enters the second erasing working state, and the first area re-enters the first writing state; S4: looping step S2 to step S3 until it is determined that both the first area and the second area are filled with valid data.

2. The storage method of emulating EEPROM as claimed in claim 1, characterized in that: The method further comprises step S0: determining the size of the storage space of the EEPROM to be simulated, so that the size of the storage space of the EEPROM to be simulated is N times the minimum erasing unit in the FLASH storage device, wherein N is a positive integer.

3. The storage method of emulating EEPROM as claimed in claim 1, characterized in that: In step S2, the step of making the first area enter a first writing state to sequentially write data into the first area includes: continuously writing data into the first area, and when writing data that needs to be rewritten, continuing to write new data with a first mark into the first area; The data to be rewritten is marked as invalid data, and the new data with the first mark is marked as valid data.

4. The storage method of emulating EEPROM as claimed in claim 3, characterized in that: In step S4, the step of performing an erasing operation on the first marking unit to store valid data in the first marking unit includes: Traversing all data in the first marking unit and marking all data to obtain valid data and invalid data in the first marking unit; Writing all valid data in the first marking unit into a RAM storage unit; Erasing all data in the first marking unit; The valid data in the RAM storage unit is written back to the first marking unit.

5. The storage method of emulating EEPROM as claimed in claim 4, characterized in that: In step S4, the step of the second area entering the second erasing working state includes: Traverse the data status of all erase units in the second area to obtain the size of invalid data, mark all erase units in the second area whose invalid data size is greater than half of the minimum erase unit as second marking units, and perform an erase operation on the second marking unit to store valid data in the second marking unit.

6. The storage method of emulating EEPROM as claimed in claim 5, characterized in that: In step S3, the step of performing an erase operation on the second marking unit to store valid data in the second marking unit includes: Traversing all data in the second marking unit and marking all data to obtain valid data and invalid data in the second marking unit; Writing all valid data in the second marking unit into a RAM storage unit; Erasing all data in the second marking unit; The valid data in the RAM storage unit is written back to the second marking unit.

7. The storage method of emulating EEPROM as claimed in claim 6, characterized in that: In step S4, the step of looping step S2 to step S3 until it is determined that both the first area and the second area are filled with valid data includes: The first area and the second area are traversed, and when it is determined that the number of the first marking unit and the number of the second marking unit are both 0, it is determined that the first area and the second area are both filled with valid data.

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