Memory device and memory management method of memory device

Abstract

A memory device and a memory management method of the memory device are provided. The memory device includes a memory and a near memory processing unit. The memory includes a normal memory region for storing uncompressed data and a compressed memory region for storing compressed data. The near memory processing unit is configured to: receive a first command for prechanging and storing a large page stored in the normal memory region in a compressed memory region; identifying an address of a sub-page of the large page based on the address of the large page; compressing the sub-page using the address of the sub-page to generate a compressed sub-page; and storing the compressed sub-pages in a compressed memory region. The large page is larger than the conventional page.

Description

[0001] This patent application claims the priority benefit of Korean Patent Application No. 10-2023-0089788 filed on July 11, 2023 in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0002] Embodiments of the present disclosure are directed to a memory management method based on a compressed memory and a device using the memory management method. Background Art

[0003] Swapping is a memory management technique that prevents memory shortage by moving part of the memory allocated to an application to a secondary storage device with a relatively large capacity (e.g., a solid-state drive (SSD) or a hard disk drive (HDD)) when a main memory area to be allocated to an application is insufficient.

[0004] When the main memory area is insufficient, the operating system may move data in the memory area that has been allocated to the application program to a swap area of ​​a nonvolatile memory used as an auxiliary storage device to alleviate the memory shortage.

[0005] However, the cost of moving data to the secondary storage device is considerable. Compared with the main memory, the data needs to be sent through a relatively slow system bus, and if necessary, the stored data needs to be retrieved to be output to the main memory. In this case, the performance of the application can be reduced. Summary of the invention

[0006] In one embodiment, a memory device includes a memory and a near memory processing unit. The memory includes: a normal memory area for storing uncompressed data and a compressed memory area for storing compressed data. The near memory processing unit is configured to: receive a first command for pre-storing a large page stored in the normal memory area in the compressed memory area; identify an address of a subpage of the large page based on the address of the large page; compress the subpage using the address of the subpage to generate a compressed subpage; and store the compressed subpage in the compressed memory area. The size of the large page is larger than that of a regular page,

[0007] In one embodiment, a memory includes a memory, a first processing unit, and a second processing unit. The memory includes: a first memory channel and a second memory channel, the first memory channel includes a first normal memory area and a first compressed memory area, and the second memory channel includes a second normal memory area and a second compressed memory area. The first processing unit is configured to communicate with the first memory channel. The second processing unit is configured to communicate with the second memory channel. Subpages of a large page having a size greater than a page are distributed across the first normal memory area and the second normal memory area. In response to a first command for pre-swapping the large page to be stored in the compressed memory area, the first processing unit and the second processing unit are configured to compress the subpages by processing the subpages in parallel.

[0008] In one embodiment, a memory management method of a memory device includes: receiving a first command for pre-storing a large page stored in a normal memory area of ​​the memory in a compressed memory area of ​​the memory; identifying an address of a subpage of the large page based on an address of the large page; compressing the subpage using the address of the subpage to generate a compressed subpage; and storing the compressed subpage in the compressed memory area. The size of the large page is larger than a regular page. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram schematically showing a configuration of a host device and a memory device according to an embodiment;

[0011] Figure 2 is a block diagram of an example of a detailed configuration of a host central processing unit (CPU) and a memory device;

[0012] Figure 3A An example of address data based on multi-level paging and page table traversal for the address data is shown;

[0013] Figure 3B An example of conversion processing of large pages and subpages according to an embodiment is shown;

[0014] Figure 3C shows a block diagram illustrating a multi-channel configuration of a memory device according to an embodiment;

[0015] Figure 4 is a block diagram showing an example of the operation of a memory device based on a forward memory command according to an embodiment;

[0016] Figure 5 is a flowchart illustrating an example of operations for performing forward storage according to an embodiment;

[0017] Figure 6 is a block diagram showing an example of the operation of a memory device based on a forward swap load command according to an embodiment;

[0018] Figure 7 A flowchart illustrating an example of operations for performing a forward swap load according to an embodiment;

[0019] Figure 8 An example of a CPU-based zSwap dual in-line memory module (DIMM) acceleration structure is shown according to an embodiment;

[0020] Fig. 9 A multi-rank structure based on DIMM according to an embodiment is shown;

[0021] Figures 10 to 12 An example of a zSwap structure in a heterogeneous memory according to an embodiment is shown;

[0022] Fig.13 shows an example of a multi-stage switching backend configuration according to an embodiment;

[0023] Fig.14 shows an example of a plane switching backend configuration according to an embodiment; and

[0024] Fig.15 is a flowchart illustrating a memory management method of a memory device according to an embodiment. DETAILED DESCRIPTION

[0025] Hereinafter, example embodiments of the present disclosure will be described with reference to the accompanying drawings. However, the present disclosure can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. Throughout the present application, the same reference numerals represent the same elements.

[0026] It should be noted that if one component is described as being “connected,” “coupled” or “engaged” to another component, although the first component may be directly connected, coupled or engaged to the second component, the third component may also be “connected,” “coupled” or “engaged” between the first and second components.

[0027] Unless the context clearly indicates otherwise, singular forms are intended to include plural forms as well.

[0028] As used herein, "at least one of A and B", "at least one of A, B, or C", etc., each of which may include any one of the items listed together in a corresponding phrase, or all possible combinations thereof.

[0029] Figure 1 is a block diagram schematically showing a configuration of a host device and a memory device according to an embodiment.

[0030] Reference Figure 1 , the host device 110 may include a processor 111 and a memory controller 112 (eg, a controller circuit). The processor 111 may send instructions used by the memory device 120 while executing an operating system and applications. The memory controller 112 may perform memory management associated with the execution of the operating system and applications.

[0031] The memory device 120 may include a near memory processing (NMP) unit 121 and a memory 122. The memory device 120 may operate based on an instruction of the host device 110. The memory device 120 may provide data to the host device 110 as needed.

[0032] The memory 122 may store instructions (or programs) executable by the processor 111. For example, the instructions include instructions for performing an operation of the processor 111 and / or an operation of each component of the processor 111.

[0033] The memory 122 may be implemented as a volatile memory device or a nonvolatile memory device.

[0034] The volatile memory device may be implemented as a dynamic random access memory (DRAM), a static random access memory (SRAM), a thyristor RAM (T-RAM), a zero capacitor RAM (Z-RAM), or a two-transistor RAM (TTRAM).

[0035] The non-volatile memory device may be implemented as an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic RAM (MRAM), a spin transfer torque (STT)-MRAM, a conductive bridging RAM (CBRAM), a ferroelectric RAM (FeRAM), a phase change RAM (PRAM), a resistive RAM (RRAM), a nanotube RRAM, a polymer RAM (PoRAM), a nano floating gate memory (NFGM), a holographic memory, a molecular electronic memory device, or an insulator resistive change memory.

[0036] The host device 110 may manage the memory of the memory device 120 by performing swapping. Swapping may refer to a memory management method that prevents memory shortage by moving a portion of the memory allocated to the application program to a secondary storage device (e.g., a solid state drive (SSD) or a hard disk drive (HDD)) having a relatively large capacity when a main memory area to be allocated to the application program is insufficient in the computing system.

[0037] The host device 110 may manage memory by performing zSwap. zSwap is an example of compressed memory swapping. The description of zSwap provided below may be applied to a compressed memory swapping method. zSwap may represent a method of compressing and storing swap data in a predetermined area of ​​a main memory when a memory area is insufficient. For example, the compressed swap data may be stored in a predetermined area of ​​a random access memory (RAM). In the zSwap method, the host device 110 compresses data and stores the compressed data to be moved to a swap area in a zSwap pool area of ​​the main memory; and when the data is needed, the host device 110 decompresses the compressed data and reuses the data from the main memory.

[0038] In the zSwap process, host device 110 may compress data and process operations for managing memory to store the compressed data located outside host device 110 in memory or near memory, thereby increasing the overall processing rate of the application.

[0039] The NMP unit 121 may be spaced apart from the host device 110. The NMP unit 121 may be implemented in or near the memory device 120. Being implemented near the memory device 120 may indicate that the NMP unit 121 is implemented at a location that allows access to data stored in the memory 122 without passing through the main data bus between the host device 110 and the memory 122. When the NMP unit 121 is implemented near the memory 122, data may be quickly processed by processing the data without processing the data through the data bus between the host device 110 and the memory 122. For example, the NMP unit 121 may be located outside the memory device 120 and communicate with the memory 122 through a signal line different from the data bus.

[0040] The host device 110 may be a main management agent of a computer system. The host device 110 may be implemented as a personal computer or a server. The NMP unit 121 may process data of the memory 122 by interoperating or communicating with the host device 110. The NMP unit 121 may control the memory 122 in response to a command from the host device 110.

[0041] The NMP unit 121 may include a processing unit configured to process data. The processing unit may execute computer-readable code (eg, software) stored in a memory and instructions triggered by a processor.

[0042] The processing unit may be a data processing device implemented by hardware having a circuit physically constructed to perform the desired operation. For example, the desired operation may include codes or instructions included in a program.

[0043] The data processing device implemented in hardware may include, for example, a microprocessor, a central processing unit (CPU), a processor core, a multi-core processor, a multiprocessor, an application specific integrated circuit (ASIC), and a field programmable gate array (FPGA).

[0044] The NMP unit 121 may receive a command from the host device 110. The command may be a swap_in command or a swap_out command regarding data stored in the memory 122 or compressed data. Commands related to compression and decompression may include information indicating frontswap_store or frontswap_load. A detailed description of the swap command is provided below.

[0045] The NMP unit 121 may compress or decompress data in response to a command. The NMP unit 121 may manage entries of compressed data.

[0046] The NMP unit 121 may generate an entry tree configured in a tree structure or a hash structure based on the compressed data. The NMP unit 121 may manage entries based on the entry tree.

[0047] The NMP unit 121 may include a buffer. The buffer may include at least one of an input buffer and an output buffer. The NMP unit 121 may receive information about data stored in the input buffer from the host device 110, and may read the input buffer. The NMP unit 121 may write data to the output buffer, and output information about the written data to a predetermined memory area. For example, the predetermined memory area may include a main memory area of ​​the host device 110, a second memory area (such as a computing fast link (CXL)), or a memory area for near data processing (NDP).

[0048] In response to a swap out command being received from the host device 110, the NMP unit 121 may set a swap out parameter based on the swap out command. The swap out parameter may include the type of data, the offset of the data, and indicate whether to compress the data. The offset may be address information including page information.

[0049] The NMP unit 121 may determine whether to compress the data based on the swap-out parameter. The NMP unit 121 may allocate an area for storing the compressed data.

[0050] The NMP unit 121 may update the entry based on the swap-out parameter and the area for storing compressed data. The NMP unit 121 may generate the entry based on the address of the area for storing compressed data, the type of data, and the offset of the data. The NMP unit 121 may update the entry by inserting the entry into the entry tree.

[0051] In response to a swap-in command being received from the host device 110, the NMP unit 121 may set a swap-in parameter based on the swap-in command. The NMP unit 121 may retrieve the compressed data based on the swap-in parameter. The NMP unit 121 may retrieve the compressed data based on the type of the compressed data and the offset of the compressed data.

[0052] The NMP unit 121 may decompress the compressed data. The NMP unit 121 may decompress the compressed data based on a decompression option of the compressed data included in the swap-in parameter.

[0053] The NMP unit 121 may output the decompressed data to the host device 110 .

[0054] The NMP unit 121 may delete the entry corresponding to the decompressed data from the entry tree. For example, the NMP unit 121 may delete the entry corresponding to the decompressed data after the decompressed data has been output to the host device 110.

[0055] The NMP unit 121 may store data or compressed data in a buffer on an entry basis.

[0056] The NMP unit 121 may store the data or the decompressed data in the near memory area. The near memory area may refer to a storage space accessible by the NMP unit 121 instead of through a main data bus between the host device 110 and the memory.

[0057] Figure 2 is a block diagram of an example of a detailed configuration of a host central processing unit (CPU) and a memory device.

[0058] Reference Figure 2 , the host CPU 210 may execute a plurality of application programs (or applications) 211 and 213. The host CPU 210 may manage data in the memory device 270 to execute the plurality of application programs 211 and 213. The processor 111 may be implemented by the host CPU 210, and the memory device 120 may be implemented by the memory device 270.

[0059] The host CPU 210 may include a zSwap front-end interface 230 (e.g., a zSwap front-end or first interface circuit), and the zSwap front-end interface 230 may include a zSwap back-end interface 250 (e.g., a zSwap back-end or second interface circuit). The zSwap back-end interface 250 may include a zSwap memory 251, a zSwap loader 253, a zSwap compressor 255, a zSwap decompressor 257, and an entry node manager 259. The zSwap memory 251, the zSwap loader 253, the zSwap compressor 255, the zSwap decompressor 257, and the entry node manager 259 may be logic circuits or programs executed by the host CPU 210. When the zSwap unit 291 is dedicated to zSwap related operations, the zSwap compressor 255 and the zSwap decompressor 257 of the zSwap back-end interface 250 may be omitted.

[0060] Memory device 270 may include NMP unit 290, normal memory area 271, and compressed memory area 273. NMP unit 290 may include zSwap unit 291. zSwap unit 291 may include a zSwap near data processing (NDP) backend. The zSwapNDP backend may include a zSwap compressor 293 and a zSwap decompressor 295. The zSwap NDP backend may optionally include a zSwap memory that is the same as zSwap memory 251, a zSwap loader that is the same as zSwap loader 253, and an entry node manager that is the same as entry node manager 259. For example, the zSwap NDP backend may include at least one of zSwap compressor 293, zSwap decompressor 295, zSwap memory, zSwap loader, and entry node manager.

[0061] The NMP unit 290 can be used with Figure 1 The NMP unit 121 operates in the same manner.

[0062] The data of the plurality of applications 211 and 213 may be stored in the main memory (e.g., the memory device 270) on a page basis (e.g., on a 4-KB basis). When a portion of these pages is moved to the swap area, the data may be processed through the zSwap front-end interface 230. The host CPU 210 may process the data by compressing and storing the data in the compressed memory area 273 of the main memory before the data is moved to the secondary storage device (e.g., SSD).

[0063] The NMP unit 290 may compress the data using the zSwap compressor 293 in response to a zswap_offload_store command and store the compressed data in a memory (e.g., in the compressed memory area 273). The NMP unit 290 may allocate a compressed memory area to store the data using the entry node manager 259. The entry node manager 259 may include a zswap_alloc / tree module.

[0064] In the event of a high memory load due to continuous memory demands from other devices, the NMP unit 290 may secure a main memory area for the application by moving data stored in the compressed memory area 273 to a secondary swap area such as an SSD.

[0065] NMP unit 290 may read the compressed data stored in compressed memory area 273 in response to the zswap_offload_load command and decompress the compressed data using zSwap decompressor 295 to generate decompressed data. NMP unit 290 may move the decompressed data to the swap area of ​​the auxiliary storage device according to the swap process of the operating system.

[0066] The NMP unit 290 may perform memory region management, compression and decompression functions that require large memory bandwidth during the exchange process. The NMP unit 290 may be located inside or near the memory device 270 to perform compression, decompression and memory region management functions to efficiently process data.

[0067] For example, the NMP unit 290 may be implemented in a memory buffer of a dual in-line memory module (DIMM) to process data. In this case, the NMP unit 290 may process data while efficiently using the internal bandwidth of the DIMM.

[0068] The NMP unit 290 can distribute the execution of the computing function so that multiple DIMMs can process data in parallel for each rank (e.g., memory rank). Thus, the NMP unit 290 can prevent data access delays with respect to the compressed memory area 273 and effectively reduce external bus traffic.

[0069] The switch front-end interface 230 may use the zSwap back-end interface 250 to use the zSwap acceleration function of the NMP unit 290. The zSwap back-end interface 250 may provide an interface for zSwap acceleration to be compatible with an operating system.

[0070] The zSwap backend interface 250 may use a command set (eg, a zswap_frontswap_ops support command set) to provide zSwap acceleration functionality.

[0071] The command set may include commands such as zswap_offload_store, zswap_offload_load, zswap_offload_invalidate_page, zswap_offload_invalidate_area, and zswap_offload_init.

[0072] The NMP unit 290 may perform an operation of compressing the data of the page to be swapped out in response to the zswap_offload_store command and storing the compressed data in the compressed memory area 273. The NMP unit 290 may use the zSwap compressor 293 to compress the data of the page to be swapped out from the main memory. The NMP unit 290 may use the entry node manager 259 to allocate a space corresponding to the compressed size to the compressed memory and store the compressed data in the allocated space. The NMP unit 290 may update the meta information of the compressed page through the zSwap tree module of the entry node manager 259.

[0073] The NMP unit 290 may decompress the data of the page to be swapped in response to the zswap_offload_load command and store the decompressed data in the main memory. The NMP unit 290 may use the zSwap-tree module to search the storage location of the compressed data to be swapped in the compressed memory area 273. The NMP unit 290 may use the zSwap decompressor 295 to decompress the compressed data and store the data in the main memory again. The NMP unit 290 may use the entry node manager 297 to release the space corresponding to the compressed size from the compressed memory area 273 and initialize the meta information of the page to be swapped in.

[0074] The NMP unit 290 may delete the meta information of the swapped out page in response to the zswap_offload_invalidate_page command. The NMP unit 290 may search for a swap area designated as a specific type, delete the meta information of the page designated as a specific offset using the entry node manager 259, and release the allocated memory space.

[0075] The NMP unit 290 may generate a swap area in response to the zswap_offload_init command. The NMP unit 290 may use the entry node manager 259 to release all memory space allocated to a swap area designated as a particular type.

[0076] Figure 3A An example of address data based on multi-level paging and a page table walk for the address data is shown. Virtual memory can be managed based on multi-level paging. Virtual memory can be a memory management technique that allocates a memory area for a process to a virtual address space instead of directly allocating the memory area to a physical memory. The virtual address space can be an abstract memory area provided to the process, and the process can use the virtual address space to read and write data as if the process actually uses physical memory. Multi-level paging can be a virtual memory management technique that converts a virtual memory address (hereinafter, referred to as a virtual address) into a physical memory address (hereinafter, referred to as a physical address) using a hierarchical structure.

[0077] Reference Figure 3A , the virtual address 301 can be converted into a physical address 302 by performing a page table traversal based on multi-level paging. Figure 3A An example using a hierarchical structure having 4 levels is shown, but the disclosed embodiments are not limited thereto.

[0078] Each operation of the processing can be performed in units of pages. The number of pages can be determined based on the page size and the number of representable bits supported by the processor. For example, when the number of representable bits of the virtual address 301 is 48 bits, as 2 48 A virtual memory area of ​​256 terabytes (TB) of 4 kilobytes (KB) can be represented by a virtual address 301. When the page size is 4 kilobytes (KB), 64 billion pages of 256 TB / 4 KB can be obtained. Since the page table supports as many indexes as the number of pages, 64 billion indexes can be included, and the virtual address 301 can occupy an address space in the range of 0x000000000_00000000 to 0x0000ffff_ffffffff.

[0079] As described above, when using a virtual address 301 without a hierarchical structure, too much address space may be required. Therefore, the virtual address 301 may be managed using multi-level paging based on a page table with multiple levels. When using multi-level paging, a page table traversal may be performed for each level of the hierarchical structure.

[0080] Reference Figure 3A, the high bits of the virtual address 301 except the page offset can be respectively assigned to the levels of the hierarchical structure. For example, the number of representable bits of the virtual address 301 can be 48 bits, and 9 bits can be assigned to each of the L1 to L4 indexes. In this case, by using a total of 36-bit indexes, a page table in a hierarchical structure with 4 levels can be operated. When the virtual page number is specified based on a 4-level page table traversal using a 36-bit index of the virtual address 301, a page table entry (PTE) in the page table can be specified based on the virtual page number using the remaining 12-bit page offset of the virtual address 301. In this case, the page offset can be 4KB, and the memory coverage of the L1 to L4 indexes can be 2 megabytes (MB), 1 gigabyte (GB), 512GB, and 256TB, respectively.

[0081] When the entries of a data set (e.g., a table) of a level are specified based on the index of the level, the entries can be used as pointers indicating data sets of subsequent levels. For example, a first data set 310 can be constructed based on the L4 index of the first level, and each entry of the first data set 310 can be used as a pointer indicating a second data set 320 of the second level.

[0082] The first base address of the first data set 310 may be stored in the CR3 register (or CR3). The sum of the first base address and the L4 index may specify the first entry 311. The first entry 311 may specify the second base address of the second data set 320. Using the method described above, the third entry 331 of the third data set 330 and the fourth entry 341 of the fourth data set 340 may be specified based on the L2 index and the L1 index. The third data set 330 may correspond to a page directory table, and the fourth data set 340 may correspond to a page table. The third entry 331 may correspond to a page directory entry (PDE), and the fourth entry 341 may correspond to a PTE. When a page is specified by the fourth entry 341, the physical address 302 in the page may be determined using a page offset.

[0083] In the LINUX operating system, a virtual address 301 may be converted to a physical address 302 through a first-level page global directory (PGD), a second-level page upper directory (PUD), a third-level page middle directory (PMD), and a fourth-level PTE. When multi-level paging is used, access to a memory (or a device storing a page table) may be required in each operation. When the page size is 4KB, a cache buffer miss may result in a memory access cost of 4 accesses.

[0084] Figure 3BAn example of conversion processing of large pages and subpages according to the disclosed embodiment is shown. Large page 351 may have a size larger than the size of a regular page. For example, a regular page may have a size of 4KB, and large page 351 may have a size of 2MB, however, the disclosed embodiment is not limited thereto. With the trend of increasing workload and memory capacity, memory management efficiency can be improved by using large page 351. For example, by using large page 351, address conversion processing can be simplified, and cache buffer hit rate can be increased. However, because large page 351 has a size larger than the size of a regular page, memory efficiency can be reduced when only a portion of large page 351 is used to store data.

[0085] According to an embodiment, the host device (eg, 110) performs address translation on a stage for managing large pages 351, and the memory device (eg, 120) performs address translation on the remaining stages. Figure 3A The number of representable bits of the virtual address 301 is 48 bits, the L1 to L4 indexes use 9 bits respectively, and the page offset uses 12 bits. In this case, the host device can use the L4 index to perform the first level page table traversal, use the L3 index to perform the second level page table traversal, and use the L2 index to perform the third level page table traversal. As a result, the address conversion result of the host device can indicate a 2Mb large page 351. The memory device can find the PTE by performing the fourth level page table traversal using the L1 index, and can obtain the physical address by adding the page offset to the address value of the PTE. Therefore, due to the use of the large page 351, the memory device can prevent the memory efficiency from deteriorating and provide management convenience.

[0086] The large page 351 may be stored in a linear space with continuous addresses. When the large page 351 is split (e.g., split into subpages), the subpages 352 of the large page 351 may be stored in a non-linear space with non-continuous addresses. The subpage 352 may collapse and may be converted to the large page 351 in the linear space.

[0087] When the large page 351 exists in the linear space, the data of the large page 351 can be accessed through the physical address of the large page 351. For example, the memory device may receive a request for the large page 351 using a virtual address specifying the large page 351 from the host device. The memory device may determine the page frame number from the virtual address, and may use the offset value of the virtual address in the physical address of the large page 351 of the page frame number to determine the physical address of the large page 351. The memory device may access the data of the large page 351 using the physical address of the large page 351.

[0088] When the large page 351 is segmented and exists as a subpage 352 in a nonlinear space, the corresponding physical address of the subpage 352 may need to be calculated. When the virtual address of the designated large page 351 is received from the host device, the memory device may identify the page frame number of the virtual address. When the segmentation state of the large page 351 is identified based on the page frame number, the memory device may use the page frame number to obtain the PTE and offset value of the subpage 352, and may obtain the physical address of the subpage 352 by adding the offset value to the address of the PTE.

[0089] Figure 3C A block diagram showing a multi-channel configuration of a memory device according to a disclosed embodiment is shown. Figure 3C , the host device 360 ​​may include a processor 361 and a memory controller 362, and the memory device 370 may include an NMP unit 371 and a memory 372.

[0090] In one embodiment, host device 360 ​​and memory device 370 perform zSwap in large page units. Host device 360 ​​may instruct memory device 370 to perform zSwap in large page units. Memory device 370 may reduce the overhead of host device 360 ​​by offloading operations for performing zSwap in large page units.

[0091] In one embodiment, memory 372 includes a normal memory area for storing uncompressed data and a compressed memory area for storing compressed data. Execution of zSwap may include performing a swap store to compress data (e.g., a page) in the normal memory area and store the compressed data in the compressed memory area, and performing a swap load to decompress data (e.g., a compressed page) in the compressed memory area and store the decompressed data in the normal memory area.

[0092] When receiving a command for pre-storing a large page stored in the normal memory area in the compressed memory area, the NMP unit 371 may perform address management and compression on the large page for pre-storage. In one embodiment, in response to receiving a command for pre-storing a large page, the NMP unit 371 identifies the address of a subpage of the large page, compresses the subpage using the identified address of the subpage, and stores the compressed subpage in the compressed memory area.

[0093] When the virtual address of the large page is specified in response to the forward storage command, an address conversion operation of converting the virtual address into a physical address may be performed. The virtual address may be based on multi-level paging. One level of the hierarchical structure of the multi-level paging may be performed by the host device 360, and the remaining levels of the hierarchical structure of the multi-level paging may be performed by the memory device 370. The host device 360 ​​may perform address conversion on the level indicating the large page. The NMP unit 371 may perform address conversion on the remaining levels to generate a conversion result, and may obtain a physical address corresponding to the conversion result.

[0094] The NMP unit 371 may identify the address of a subpage based on whether the addresses of the subpages of the large page are continuous. When the subpages are stored in a continuous address space, the NMP unit 371 may determine the address of a subsequent subpage in the subpage by adding the subpage size to the address of the current subpage in the subpage. The subpage size may be 4kB, but is not limited thereto.

[0095] For example, the physical address of the large page may correspond to the start address. The physical address of the first subpage of the large page may correspond to the start address. The physical address of the second subpage may be obtained by adding the subpage size to the start address. The physical address of the third subpage may be obtained by adding the subpage size to the physical address of the second subpage. The second subpage may correspond to a subsequent page of the first subpage, and the third subpage may correspond to a subsequent page of the second subpage.

[0096] When subpages are stored in a non-contiguous address space, the NMP unit 371 can obtain the page frame number of the subsequent subpage among the subpages by performing a page table traversal, and can determine the address of the subsequent subpage by adding the page offset of the subsequent subpage to the page frame number of the subsequent subpage. When subpages are stored in a non-contiguous address space, the continuous address of the subpage cannot be obtained using the subpage size, and a separate address conversion may be required for each of the subpages. A page table traversal of each subpage of a large page can be performed, and therefore, a physical address corresponding to the virtual address of each subpage can be obtained.

[0097] As described above, in both cases where subpages are stored in a continuous address space and where subpages are stored in a non-contiguous address space, the host device 360 ​​may need to perform address translation on a large page level, and the remaining address translation may be performed by the NMP unit 371. Therefore, due to the offloading of the NMP unit 371, the overhead of the host device 360 ​​associated with address management may be reduced.

[0098] The NMP unit 371 can reduce the compression-related overhead of the host device 360 ​​by performing data compression for forward storage. Data compression can be performed in parallel using multiple memory channels, and thus compression speed can be increased.

[0099] More specifically, the memory 372 may include a first memory channel 372a and a second memory channel 372b. Subpages of a large page may be distributed and stored in the first memory channel 372a and the second memory channel 372b, and the NMP unit 371 may process the subpages distributed and stored in the first memory channel 372a and the second memory channel 372b in parallel, and may compress the subpages. For example, the subpages of a large page may be distributed across the first memory channel 372a and the second memory channel 372b.

[0100] In one embodiment, the NMP unit includes a first processing unit 371a configured to communicate with a first memory channel 372a and a second processing unit 371b configured to communicate with a second memory channel 372b. When a subpage among subpages is included in the first memory channel 372a, the subpage may be compressed by the first processing unit 371a, and when the subpage is included in the second memory channel 372b, the subpage may be compressed by the second processing unit 371b.

[0101] The first processing unit 371a may compress some of the subpages stored in the first memory channel 372a, and the second processing unit 371b may compress other subpages stored in the second memory channel 372b. The compression operation of some subpages by the first processing unit 371a may be performed in parallel with the compression operation of other subpages by the second processing unit 371b.

[0102] When receiving a command for forward loading a compressed large page stored in the compressed memory area to the compressed memory area, the NMP unit 371 can perform address management and compression on the large page for forward loading. After the large page is forwarded and stored in the compressed memory area, when the target subpage of the large page is requested, a forward load command can be generated.

[0103] When a forward load command for a subpage of a large page (also referred to as a target subpage) or a request for a target subpage is received, the NMP unit 371 may provide the target subpage to the host device with a higher priority than other subpages. For example, decompression of the compressed target subpage may be performed before decompression of the remaining compressed subpages of the large page.

[0104] The NMP unit 371 may determine a target frame number based on a difference between the address of the large page and the address of the target subpage, may determine an address of a compressed target subpage in the compressed memory area based on the target frame number, may decompress the compressed target subpage using the address of the compressed target subpage, and may store the decompressed target subpage in the normal memory area. For example, the NMP unit 371 may perform the above operations upon receiving a forward load command for a subpage of a large page.

[0105] When the target subpage of the large page is provided preferentially, the delay of the host device accessing the target subpage can be reduced compared to the case where the target subpage is accessible only after all subpages of the large page have been decompressed. For example, providing the target subpage of the large page preferentially may mean that the portion of the compressed large page associated with the target subpage is decompressed before the rest of the large page is decompressed, so that the portion of the compressed large page associated with the target subpage can be quickly provided to the host device. In this case, when the NMP unit 371 decompresses adjacent subpages adjacent to, around or adjacent to the target subpage, and the adjacent subpages can be processed in parallel, the delay of accessing the adjacent subpage can be reduced. In addition, as with the duplication process of zSwap, the compressed memory area and compression value corresponding to the decompressed page can be maintained without being removed, and when the swap-in is performed without updating the decompressed page in the future, the update of the compressed page can be omitted.

[0106] Figure 4 is a block diagram illustrating an example of the operation of a memory device based on a forward memory command according to an embodiment of the disclosure. Figure 4 , the memory device 401 may include a first processing unit 431, a first memory channel 441, a second processing unit 432, and a second memory channel 442. The memory device 401 may be connected to the host CPU 410 through a CXL interface 420 (e.g., an interface circuit). The host CPU 410 may be an example of a processor of a host device. For example, the host CPU 410 may correspond to the processor 111 or the processor 361.

[0107] The first processing unit 431 and the second processing unit 432 may be included in the NMP unit. In one embodiment, the first memory channel 441 includes a first normal memory area 441a and a first compressed memory area 441b, and the second memory channel 442 includes a second normal memory area 442a and a second compressed memory area 442b.

[0108] Subpages sp1 to sp8 of the large page 402 may be stored in normal memory areas 441a and 442a. Subpages sp1 to sp8 may be stored in normal memory areas 441a and 442a in an interleaved manner. Processing units 431 and 432 may identify the physical addresses of subpages sp1 to sp8 based on the address of the large page 402, may use the physical addresses of subpages sp1 to sp8 to compress subpages sp1 to sp8, and may store compressed subpages csp1 to csp8 of the compressed large page 405 in compressed memory areas 441b and 442b. For example, compressed subpages csp1 to csp8 may be stored in compressed memory areas 441b and 442b in an interleaved manner.

[0109] The host CPU 410 may perform some operations for specifying the large page 402 to perform the address translation operation of the multi-level paging, and the remaining operations may be performed by the CXL interface 420 and / or the memory device 401. In addition, the CXL interface 420 and / or the memory device 401 may perform task allocation to the memory channels 441 and 442 based on the physical addresses of the sub-pages sp1 to sp8. When the address translation and / or the task allocation are performed by the memory device 401, the address translation may be performed by an NMP unit (e.g., an additional processing unit other than the processing units 431 and 432 may exist) and / or a separate controller (e.g., a buffer chip (e.g., a dual in-line memory module (DIMM) buffer chip)). On the other hand, in the absence of a separate task allocation agent, the task allocation may be performed based on a predetermined rule (e.g., an interleaved manner). The processing units 431 and 432 may identify the physical addresses of the sub-pages sp1 to sp8 based on the address translation results, and may compress the sub-pages sp1 to sp8 using the physical addresses of the sub-pages sp1 to sp8.

[0110] The memory device 401 may determine the physical addresses of the subpages sp1 to sp8 based on the physical address of the large page 402 specified by the forward storage command 400. The memory device 401 may determine the physical address of the large page 402 by address conversion (e.g., page table traversal) of the virtual address of the large page 402. For example, the forward storage command 400 may specify the virtual address of the large page 402. The address conversion may correspond to a portion of the address conversion operation of the multi-level paging. The first address 403 of the large page 402 may correspond to the physical address of the large page 402. The first address 403 may be referred to as the starting address. When the large page 402 exists in a continuous memory address space, the second address 404 of the large page 402 may be determined based on the sum of the first address 403 and the subpage size. When the large page 402 does not exist in a continuous memory address space, a separate address conversion operation may be used to determine the second address 404. The second address 404 may be derived by performing address conversion on the virtual address of the second subpage of the large page 402.

[0111] When the compressed large page 405 exists in the continuous memory address space, the address conversion of the large page 402 is similar, and the second address 407 of the compressed large page 405 can be derived based on the first address 406 of the compressed large page 405. In this case, the corresponding sizes of the compressed sub-pages csp1 to csp8 can be used. For example, the second address 407 of the compressed large page 405 can be determined based on the sum of the first address 406 and the size of the compressed sub-page.

[0112] Figure 5 is a flow chart illustrating an example of operations for performing forward storage according to the disclosed embodiment. Figure 7In operation 510, a compression command of a starting subpage may be sent to a corresponding processing unit based on a starting address of the large page. For example, when a starting subpage of a large page is stored in a first memory channel, the starting subpage may be compressed by a first processing unit configured to communicate with the first memory channel.

[0113] In operation 520, it is determined whether the large page exists in the continuous address space. When the large page exists in the continuous address space, in operation 530, the address of the subsequent subpage is determined based on the address of the current subpage and the subpage size. For example, the address of the subsequent subpage may correspond to the sum of the address of the current subpage and the subpage size. The address of the current subpage may correspond to the starting address or be determined from the starting address. In operation 540, a compression command for the subsequent subpage may be sent to the corresponding processing unit based on the address of the subsequent subpage.

[0114] When the large page does not exist in the continuous address space, in operation 550, the page frame number of the subsequent subpage is obtained by performing a page table traversal. In operation 560, the address of the subsequent subpage is determined based on the page table entry and the page offset. The page table entry and the page offset can be determined using the page frame number. In operation 540, a compression command for the subsequent subpage can be sent to the corresponding processing unit based on the address of the subsequent subpage. In one embodiment, if it is necessary to perform zSwap on a regular page based on a forward swap storage command, it is not the NMP unit (e.g., 371) that processes zSwap, but the host CPU 210 that processes zSwap. For example, the host CPU 210 can use its zSwap compressor 255 to compress the regular page for storage in the compressed memory area 273. In one embodiment, if it is necessary to perform zSwap on a regular page based on a forward swap load command, it is not the NMP unit (e.g., 371) that processes zSwap, but the host CPU 210 that processes zSwap. For example, host CPU 210 may use its zSwap decompressor 257 to decompress compressed regular pages stored in normal memory area 271 .

[0115] Figure 6 is a block diagram illustrating an example of the operation of a memory device based on a forward memory command according to an embodiment of the disclosure. Figure 6 , the memory device 601 may include a first processing unit 631, a first memory channel 641, a second processing unit 632, and a second memory channel 642. The memory device 601 may be connected to the host CPU 610 through the CXL interface 620. The host CPU 610 may be an example of a processor of a host device. For example, the host CPU 610 may correspond to the processor 111 or the processor 361.

[0116] The first processing unit 631 and the second processing unit 632 may be included in the NMP unit. In one embodiment, the first memory channel 641 includes a first normal memory area 641a and a first compressed memory area 641b, and the second memory channel 642 includes a second normal memory area 642a and a second compressed memory area 642b.

[0117] Subpages sp1 to sp8 of the large page 602 may be stored in the normal memory areas 641a and 642a. After the large page 602 is pre-swapped and stored in the compressed memory areas 641b and 642b, the NMP unit may receive a pre-swapped load command 600 requesting a target subpage (e.g., subpage sp3) of the large page 602. The NMP unit may determine a target frame number based on the starting physical address of the large page 602 and the physical address of the target subpage, and may determine the physical address of the compressed target subpage (e.g., compressed subpage scp3) of the compressed memory areas 641b and 642b based on the target frame number. The second processing unit 632 may decompress the compressed target subpage using the physical address of the compressed target subpage (e.g., compressed subpage scp3), and may store the decompressed target subpage (e.g., subpage sp3) in the normal memory area (e.g., the second normal memory area 642a). The compressed large page pool 605 may store information about compressed sub-pages, and a physical address of a compressed target sub-page, such as a third compressed pool entry address 606 , may be ensured from the compressed large page pool 605 .

[0118] Figure 7 A flow chart showing an example of operations for performing a forward load according to the disclosed embodiments. Figure 7 , in operation 710, a target frame number is determined based on a difference between a start address of a large page and an address of a target subpage. For example, the difference may be determined based on a difference between a physical address of a target subpage and a start physical address of a large page, and the target frame number may be determined based on a result obtained by dividing the difference by a subpage size. In operation 720, a physical address of a compressed target subpage in a compressed memory space is determined based on the target frame number. A compressed large page pool for storing information about compressed subpages may exist, and a physical address of a compressed target subpage corresponding to a target frame number may be extracted from the compressed large page pool. In operation 730, a decompressed target subpage is provided preferentially. For example, a compressed target subpage using a physical address of a compressed target subpage may be decompressed before other compressed subpages. For example, a target subpage of a large page may be decompressed and output to the host CPU 610 before other subpages of the same large page are decompressed.

[0119] Figure 8An example of a CPU-based zSwap DIMM acceleration structure according to the disclosed embodiment is shown, and Fig. 9 An example of a DIMM-based multi-rank structure according to the disclosed embodiment is shown.

[0120] Reference Figure 8 and Fig. 9 , the host may be implemented as a CPU 810. The CPU 810 may include a plurality of memory controllers 811 and 813 (eg, controller circuits). The CPU 810 may process data stored in a plurality of memory modules 830 through the plurality of memory controllers 811 and 813.

[0121] When the main memory includes a plurality of memory modules 830 capable of performing accelerated DIMM (AXDIMM) zSwap acceleration, zSwap acceleration performance may be enhanced in proportion to the number of memory modules 830 .

[0122] exist Figure 8 In the example of , two memory controllers 811 and 813 may be provided with two DIMMs (or AXDIMMs) per channel, so that the CPU 810 may set a zSwap region for each DIMM, thereby performing zSwap acceleration in up to four DIMMs.

[0123] exist Fig. 9 In the example of FIG. 1 , the CPU 910 may include one memory controller 911 (eg, a controller circuit). The CPU 910 may process data in the plurality of memory modules 930 through the one memory controller 911 .

[0124] Depending on the CPU 810 or 910 and the board configuration, the topology of installable DIMMs may vary.

[0125] Data processing equipment (e.g. Figure 1 The data processing device 10) can be configured inside or near the memory module to perform scalable AXDIMM zSwap acceleration in various configurations.

[0126] For scalable zSwap acceleration performed in various configurations, a zSwap back-end interface of the host may individually generate commands for each DIMM accelerator unit mapped to the system memory and input the generated commands to the corresponding DIMM accelerator unit to operate the DIMM accelerator unit.

[0127] Figures 10 to 12 An example of a zSwap structure in a heterogeneous memory according to the disclosed embodiment is shown. Figures 10 to 12 ,The zSwap structure in heterogeneous memory can include a planar structure, a multi-level structure, and a hybrid structure.

[0128] The flat structure may be a structure in which DRAM 1010, zSwap 1030, CXL memory switch 1050, and SSD switch 1070 are arranged in a single layer. The flat structure may directly perform offloading to a predetermined backend. For example, DRAM 1010 may perform offloading of each of zSwap 1030, CXL memory switch 1050, and SSD switch 1070.

[0129] The multi-level structure may be a structure in which the offload backend is arranged in several layers according to performance. For example, the zSwap 1130 may be set on a lower layer of the DRAM 1110, the CXL memory switch 1150 may be set on a lower layer of the zSwap 1130, and the SSD switch 1170 may be set on a lower layer of the CXL memory switch 1150. In this case, offloading may be performed sequentially according to the layers. Fig.11 In the example of , offloading may be performed in the order of DRAM 1110 , zSwap 1130 , CXL memory swap 1150 , and SSD swap 1170 .

[0130] like Fig.12 As shown in , the hybrid structure may be a structure in which a flat structure and a multi-level structure are mixed. In this case, zSwap 1230 and CXL memory switch 1250 may be configured in a flat structure, and CXL memory switch 1250 and SSD switch 1270 may be configured in a multi-level structure.

[0131] Data processing equipment (e.g. Figure 1 The NMP unit 121) can offload all or part of the functions used for zSwap acceleration to multiple near memory acceleration units through various types of hierarchical structures, thereby accelerating zSwap.

[0132] Fig.13 An example of a multi-stage switching backend configuration according to the disclosed embodiment is shown. Fig.13 , the host CPU may execute application 1310 and operating system 1330. The host CPU may perform zSwap acceleration through multiple memory modules (e.g., memory modules 1350, 1370, and 1390) having a multi-level backend structure. For example, operating system 1330 may include a swap frontend and a zSwap backend interface (I / F).

[0133] The memory module 1350 may be implemented as a DIMM memory. The memory module 1350 may include a DIMM controller 1351, a zSwap area 1353 (or zSwap 1353), and a memory 1355. The DIMM memory module 1370 may be implemented as a CXL memory. The memory module 1370 may include a CXL memory controller 1371 and a CXL memory exchange area 1373 (or CXL memory exchange 1373). The memory module 1390 may be implemented as a CXL / SSD memory. The memory module 1390 may include a CXL / SSD controller 1391 and an SSD exchange area 1393 (or SSD exchange 1393).

[0134] Fig.13 An example of a multi-stage switching backend configuration utilizing CXL can be used. Fig.13 In the example of , DIMMs may be used as main memory, CXL memory may be used as secondary main memory, and CXL / SSD may be used as storage devices.

[0135] The zSwap area 1353, which is a compressed memory area, can be used as a partial area of ​​the DIMM. The DIMM controller 1351 can use a dedicated accelerator unit (e.g., Figure 1 The NMP unit 121 of the DIMM is used for zSwap acceleration. In the pages of the memory, the pages to be swapped out can be first compressed in the NMP zSwap of the DIMM through zSwap 1353 and stored in the zpool as a compressed memory area.

[0136] When the compressed memory area is insufficient due to an increase in memory load, DIMM controller 1351 may select the least accessed pages from among the pages allocated to the compressed memory and evict the selected pages to CXL memory swap area 1373. In this case, DIMM controller 1351 may reduce memory bandwidth by sending compressed pages from zSwap area 1353 to CXL memory.

[0137] The compressed data may be decompressed by the NMP of the CXL controller 1371 and then stored in the CXL memory swap area 1373. The CXL controller 1371 may send the compressed page to the CXL memory, and the CXL memory may decompress and store the page. Thus, the CXL controller 1371 may prevent the corresponding memory from decompressing the data when the memory is swapped in for future use in the application, thereby reducing degradation of the performance of the application. The swap-in process may affect the performance of the application. The swap-out process may be performed asynchronously with the execution of the application in the background.

[0138] When the capacity is insufficient as the memory load of the swap space of the CXL memory increases, the CXL controller 1371 may evict less frequently accessed pages to the swap area 1393 of the CXL / SSD and secure free space of the CXL memory, thereby maintaining performance.

[0139] Fig.14 An example of a plane switching backend configuration according to the disclosed embodiment is shown. Fig.14 , the host CPU may execute application 1410 and operating system 1430. The host CPU may perform zSwap acceleration through a plurality of memory modules (eg, memory modules 1450, 1470, and 1490) having a multi-level backend structure.

[0140] Memory module 1450 may be implemented as a DIMM memory. Memory module 1450 may include a DIMM controller 1451, a zSwap area 1453 (or zSwap 1453), and a memory 1455. DIMM memory module 1470 may be implemented as a CXL memory. Memory module 1470 may include a CXL memory controller 1471 and a CXL memory swap area 1473 (or CXL memory swap 1473). Memory module 1490 may be implemented as a CXL / SSD memory. Memory module 1490 may include a CXL / SSD controller 1491 and an SSD swap area 1493 (or SSD swap 1493).

[0141] like Fig.14 As shown in the example of , the flat switch backend structure can be implemented using CXL memory. In this case, DIMM memory, CXL memory and CXL / SSD memory can be used as the same level of switching devices.

[0142] DIMM memory, CXL memory, and CXL / SSD memory may have access latency differences according to the characteristics of the respective devices and interfaces connected to them, such as double data rate (DDR) bus and peripheral component interconnect express (PCIe). The DIMM closest to the host CPU may have the shortest access latency, and then the CXL memory and CXL / SSD may have shorter access latency in order.

[0143] In order to minimize the impact of differences in the performance of swap devices on the performance of the application, offloads may be assigned to appropriate swap devices taking into account access characteristics of pages to be swapped out.

[0144] For example, pages may be divided into as many three parts as swap devices according to the access frequency of the swapped pages, and pages with the highest access frequency (e.g., hot pages) may be assigned to the zSwap region 1453 of the fastest DIMM. Pages with the lowest access frequency (e.g., cold pages) may be stored in the slowest SSD swap region 1493.

[0145] Hot pages having access frequencies between those of hot pages and cold pages may be stored in the intermediate CXL memory swap area 1473. By assigning pages to swap devices respectively according to their access frequencies, degradation of application performance due to access to slow devices may be minimized.

[0146] In a flat swap backend configuration, the compression function may be applied differently depending on the probability of the swapped out pages being accessed again. For example, hot pages stored in the zSwap region 1453 of the fastest DIMM have a high probability of being accessed again, and thus may be stored without compression, whereby access latency may be minimized. In contrast, warm or cold pages with a low probability of being accessed again may be compressed and stored in the corresponding swap region.

[0147] Fig.15 is a flowchart illustrating a memory management method of a memory device according to a disclosed embodiment. Fig.15 In operation 1510, the memory device receives a first command to perform forward storage on a large page stored in a normal memory area of ​​the memory. In a compressed memory area of ​​the memory, the large page may have a size larger than a page. In operation 1520, the memory device identifies an address of a subpage of the large page based on the address of the large page. In operation 1530, the memory device compresses the subpage using the address of the subpage. In operation 1540, the memory device stores the compressed subpage in the compressed memory area.

[0148] Operation 1520 may include an operation of determining an address of a subsequent subpage in the subpages by adding a subpage size to an address of a current subpage in the subpages when the subpages are stored in a continuous address space.

[0149] Operation 1520 may include an operation of obtaining a page frame number of a subsequent subpage in a subpage by performing a page table traversal when the subpage is stored in a non-contiguous address space, and an operation of determining an address of the subsequent subpage by adding a page offset of the subsequent subpage to the page frame number of the subsequent subpage.

[0150] The memory device may also perform operations of receiving a second command requesting a target subpage of a large page after the large page is forward-swapped and stored in the compressed memory area, determining a target frame number based on a difference between the address of the large page and the address of the target subpage, determining an address of a compressed target subpage in the compressed memory area based on the target frame number, decompressing the compressed target subpage using the address of the compressed target subpage, and storing the decompressed target subpage in the normal memory area.

[0151] The memory may include a first memory channel and a second memory channel, and subpages of the large page may be distributed and stored in the first memory channel and the second memory channel. Operation 1530 may include parallel processing of the subpages distributed and stored in the first memory channel and the second memory channel and compressing the subpages.

[0152] The memory device may also perform operations of identifying a memory channel including a subpage based on an address of the subpage, compressing the subpage using a first processing unit configured to communicate with the first memory channel when the subpage is included in the first memory channel, and compressing the subpage using a second processing unit configured to communicate with the second memory channel when the subpage is included in the second memory channel.

[0153] In addition, refer to Figures 1 to 14 The description provided can be applied to Fig.15 Memory management method.

[0154] The units described herein can be implemented using hardware components, software components, and / or combinations thereof. The processing device can be implemented using one or more general or special computers (such as, for example, a processor, a controller and an arithmetic logic unit (ALU), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA), a programmable logic unit (PLU), a microprocessor, or any other device capable of responding and executing instructions in a defined manner). The processing device can run an operating system (OS) and one or more software applications running on the OS. The processing device can also access, store, manipulate, process, and create data in response to the execution of the software. For simplicity, the description of the processing device is used as a singular form; however, the processing device may include multiple processing elements and multiple types of processing elements. For example, the processing device may include multiple processors, or a single processor and a single controller. In addition, different processing configurations (such as parallel processors) are feasible.

[0155] Software may include computer programs, snippets of code, instructions, or some combination thereof, to independently or collectively instruct or configure a processing device to operate as desired. Software and data may be stored in any type of machine, component, physical or virtual device, or computer storage medium or device that can provide instructions or data to or be interpreted by a processing device. Software may also be distributed on networked computer systems so that the software is stored and executed in a distributed manner. Software and data may be stored by one or more non-transitory computer-readable recording media.

[0156] The method according to the above example may be recorded in a non-transitory computer-readable medium including program instructions for implementing various operations of the above example. The medium may also include data files, data structures, etc., either alone or in combination with program instructions. The program instructions recorded on the medium may be program instructions specially designed and constructed to implement the above embodiments. Examples of non-transitory computer-readable media include magnetic media (such as hard disks, floppy disks, and tapes); optical media (such as CD-ROM disks, DVDs, and / or Blu-ray discs); magneto-optical media (such as optical discs); and hardware devices (such as read-only memory (ROM), random access memory (RAM), flash memory (e.g., universal serial bus (USB) flash drive, memory card, memory stick, etc.)) specially configured to store and execute program instructions. Examples of program instructions include both machine code (such as generated by a compiler) and files containing higher-level codes that can be executed by a computer using an interpreter.

[0157] The above-mentioned apparatuses may be configured to act as one or more software modules in order to perform the operations of the above-mentioned examples, and vice versa.

[0158] The foregoing is an illustration of an example embodiment and should not be construed as limiting thereof. Although several example embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications may be made in the example embodiments without departing substantially from the teachings of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure.

Claims

1. A memory device, comprising: a memory including a normal memory area for storing uncompressed data and a compressed memory area for storing compressed data; as well as A near memory processing unit configured to: receiving a first command for pre-storing a large page stored in a normal memory area in a compressed memory area, wherein the large page has a size greater than a size of a regular page, Based on the address of the large page, the addresses of multiple subpages of the large page are identified. compressing the plurality of sub-pages using the addresses of the plurality of sub-pages to generate compressed sub-pages, and The compressed sub-pages are stored in the compressed memory area.

2. The memory device according to claim 1, wherein: The near memory processing unit is configured to identify addresses of the plurality of sub-pages based on whether the addresses of the plurality of sub-pages are continuous.

3. The memory device according to claim 1, wherein: The near memory processing unit is configured to determine an address of a subsequent subpage of the plurality of subpages by adding a subpage size to an address of a current subpage of the plurality of subpages when the plurality of subpages are stored in a continuous address space.

4. The memory device according to claim 1, wherein: The near memory processing unit is configured to: When the plurality of sub-pages are stored in a non-contiguous address space, a page frame number of a subsequent sub-page in the plurality of sub-pages is obtained by performing a page table traversal, and The address of the subsequent sub-page is determined by adding the page offset of the subsequent sub-page to the page frame number of the subsequent sub-page.

5. The memory device according to claim 1, wherein: The near memory processing unit is further configured to: After the large page is forwarded and stored in the compressed memory area, receiving a second command for requesting a target subpage of the large page, The target frame number is determined based on the difference between the address of the large page and the address of the target subpage. determining an address of a compressed target subpage in the compressed memory area based on the target frame number, decompressing the compressed target subpage using the address of the compressed target subpage to generate a decompressed target subpage, and The decompressed target sub-page is stored in the normal memory area.

6. The memory device according to claim 5, wherein: Decompression of the compressed target sub-page is performed before decompression of the remaining compressed sub-pages of the large page.

7. The memory device according to any one of claims 1 to 6, wherein: The memory includes a first memory channel and a second memory channel.

8. The memory device according to claim 7, wherein: The plurality of sub-pages of the large page are distributed across the first memory channel and the second memory channel, and The near memory processing unit is configured to compress the plurality of sub-pages by processing the plurality of sub-pages distributed across the first memory channel and the second memory channel in parallel.

9. The memory device according to claim 7, wherein: The near memory processing unit includes a first processing unit configured to communicate with the first memory channel and a second processing unit configured to communicate with the second memory channel.

10. The memory device according to claim 9, wherein: When a subpage of the plurality of subpages is included in a first memory channel, the subpage is compressed by a first processing unit, and When a subpage of the plurality of subpages is included in a second memory channel, the subpage is compressed by a second processing unit.

11. The memory device according to claim 9, wherein: The first processing unit is configured to: compress a portion of the plurality of subpages stored in the first memory channel, The second processing unit is configured to: compress other portions of the plurality of sub-pages stored in the second memory channel, and The compression operation on the portion of the plurality of sub-pages by the first processing unit is performed in parallel with the compression operation on the other portion of the plurality of sub-pages by the second processing unit.

12. A memory device comprising: A memory, comprising a first memory channel and a second memory channel, the first memory channel comprising a first normal memory area and a first compressed memory area, the second memory channel comprising a second normal memory area and a second compressed memory area; a first processing unit configured to communicate with a first memory channel; as well as a second processing unit configured to communicate with a second memory channel, wherein a plurality of sub-pages of a large page having a size greater than a size of a regular page are distributed across a first normal memory region and a second normal memory region, and In response to a first command for storing a large page forward in a compressed memory area, the first processing unit and the second processing unit are configured to compress the sub-pages by processing the plurality of sub-pages in parallel.

13. The memory device according to claim 12, wherein: Based on addresses of the plurality of subpages, when a subpage of the plurality of subpages is included in a first memory channel, the subpage is compressed by a first processing unit, and When a subpage of the plurality of subpages is included in a second memory channel, the subpage is compressed by a second processing unit.

14. The memory device according to claim 12, wherein: The first processing unit is further configured to: compress the portion of the plurality of subpages stored in the first memory channel, The second processing unit is configured to: compress other portions of the plurality of sub-pages stored in the second memory channel, and The compression operation on the portion of the plurality of sub-pages by the first processing unit is performed in parallel with the compression operation on the other portion of the plurality of sub-pages by the second processing unit.

15. A memory management method for a memory device, the memory management method comprising: receiving a first command for forwarding a large page stored in a normal memory area of ​​the memory to a compressed memory area of ​​the memory, wherein the large page has a size greater than a size of a regular page; Identifying addresses of multiple subpages of the large page based on the address of the large page; compressing the plurality of sub-pages using the addresses of the plurality of sub-pages to generate compressed sub-pages; and The compressed sub-pages are stored in the compressed memory area.

16. The memory management method according to claim 15, wherein: The step of identifying addresses of the plurality of subpages includes determining addresses of subsequent subpages of the plurality of subpages by adding a subpage size to an address of a current subpage of the plurality of subpages when the plurality of subpages are stored in a continuous address space.

17. The memory management method according to claim 15, wherein: The step of identifying the addresses of the plurality of sub-pages comprises: When the plurality of sub-pages are stored in a non-contiguous address space, obtaining a page frame number of a subsequent sub-page among the plurality of sub-pages by performing a page table traversal; and The address of the subsequent sub-page is determined by adding the page offset of the subsequent sub-page to the page frame number of the subsequent sub-page.

18. The memory management method according to claim 15, further comprising: After the large page is forwarded and stored in the compressed memory area, receiving a second command for requesting a target subpage of the large page; determining a target frame number based on a difference between an address of the large page and an address of the target subpage; determining an address of a compressed target subpage in the compressed memory area based on the target frame number; decompressing the compressed target subpage using the address of the compressed target subpage to generate a decompressed target subpage; as well as The decompressed target sub-page is stored in the normal memory area.

19. The memory management method according to claim 15, wherein: The memory includes a first memory channel and a second memory channel, The plurality of sub-pages of the large page are distributed across the first memory channel and the second memory channel, and The step of compressing the plurality of sub-pages includes compressing the plurality of sub-pages by processing the plurality of sub-pages distributed across the first memory channel and the second memory channel in parallel.

20. The memory management method according to any one of claims 15 to 19, further comprising: identifying a memory channel including the plurality of subpages based on addresses of the plurality of subpages; When a subpage of the plurality of subpages is included in a first memory channel, compressing the subpage using a first processing unit configured to communicate with the first memory channel; as well as When the sub-page is included in a second memory channel, the sub-page is compressed using a second processing unit configured to communicate with the second memory channel.

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