Data transmission system and method based on SoC bus

Abstract

The invention discloses a data transmission system and method based on an SoC bus, the data transmission system based on the SoC bus comprises a write control unit, a read control unit and an arbiter, and the write control unit and the read control unit are connected in parallel and then are arranged between the arbiter and slave equipment in series. According to the invention, the writing control unit and the reading control unit are arranged between the arbiter and the slave device, so that data operation is carried out in the data transmission process; specifically, when a write control unit receives a write enable signal sent by an arbiter, the write control unit performs caching and data calculation on a write address and write data, and writes cached calculation data into slave equipment; when the read control unit receives the read enable signal sent by the arbiter, the read control unit selects the bus read-back data according to the cache write address and the read address so as to reduce the storage access of the data processing module, thereby improving the data transmission efficiency and reducing the power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and in particular to a data transmission system and method based on a SoC bus. Background Art

[0002] With the development of chip design and manufacturing technology, the storage read and write efficiency based on von Neumann's storage and computing separation architecture in the post-Moore era has restricted the computing efficiency of the chip. The traditional data processing method requires reading the memory data first, and then writing it to the memory after data processing, but this will increase the load on the bus and memory, resulting in increased power consumption of the chip during data access and transmission, and reducing the efficiency of data transmission. Summary of the invention

[0003] The purpose of the present invention is to design a data transmission system based on SoC bus in order to solve the above problems.

[0004] The present invention achieves the above-mentioned purpose through the following technical solutions: Data transmission system based on SoC bus, including: A write control unit, a read control unit and an arbiter, wherein the write control unit and the read control unit are connected in parallel and arranged in series between the arbiter and the slave device; The write control unit is used to cache and calculate the write address and write data when receiving the write enable signal sent by the arbitrator, and write the cached calculation data into the slave device; The read control unit is used to select a bus to read back data according to a cache write address and a read address when receiving a read enable signal sent by the arbitrator.

[0005] The present invention further proposes a data transmission method based on a SoC bus, which is applied to the above-mentioned data transmission system based on a SoC bus. The data transmission method based on a SoC bus comprises the following steps: Cache write address and write data, calculate data and write the calculation result to the slave device; The bus is selected to read back data based on the cache write address and read address.

[0006] The beneficial effects of the present invention are: The data transmission system based on the SoC bus realizes data calculation during the data transmission process by setting a write control unit and a read control unit between the arbitrator and the slave device; specifically, when the write control unit receives the write enable signal sent by the arbitrator, it caches and calculates the write address and write data, and writes the cached calculated data to the slave device; when the read control unit receives the read enable signal sent by the arbitrator, it selects the bus to read back the data according to the cached write address and read address, so as to reduce the storage access of the data processing module, thereby improving the data transmission efficiency and reducing the power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is an overall block diagram of the data transmission system based on SoC bus of the present invention; Figure 2 It is a flow chart of an embodiment of a data transmission method based on SoC bus of the present invention; Figure 3 The figure is a flow chart of another embodiment of the data transmission method based on SoC bus of the present invention. DETAILED DESCRIPTION

[0008] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0009] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0010] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0011] In the description of the present invention, it should be understood that the terms "upper", "lower", "inside", "outside", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, or are directions or positional relationships in which the product of the invention is usually placed when in use, or are directions or positional relationships commonly understood by those skilled in the art. These directions or positional relationships are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0012] Furthermore, the terms “first”, “second”, etc. are merely used for distinguishing descriptions and should not be understood as indicating or implying relative importance.

[0013] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms such as "setting" and "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0014] The specific implementation modes of the present invention are described in detail below in conjunction with the accompanying drawings.

[0015] like Figure 1-3 As shown, the data transmission system based on SoC bus includes: A write control unit, a read control unit and an arbiter, wherein the write control unit and the read control unit are connected in parallel and arranged in series between the arbiter and the slave device; The write control unit is used to cache and calculate the write address and write data when receiving the write enable signal sent by the arbitrator, and write the cached calculation data into the slave device; The read control unit is used to select a bus to read back data according to a cache write address and a read address when receiving a read enable signal sent by the arbitrator.

[0016] In this embodiment, the arbitrator is connected to the master device. During the data transmission process, the write control unit stores the write address and write data, divides it into a two-stage pipeline to optimize the write data timing, performs data calculation, and writes the cached calculation data to the slave device; the read control unit judges the write cache write address and read address to select the bus to read back the data, thereby solving the problem of data delay.

[0017] The data transmission system based on the SoC bus of the present invention realizes data operation simultaneously during data transmission by setting a write control unit and a read control unit between an arbitrator and a slave device; specifically, when the write control unit receives a write enable signal sent by the arbitrator, it caches and calculates the write address and the write data, and writes the cached calculated data into the slave device; when the read control unit receives a read enable signal sent by the arbitrator, it selects the bus to read back the data according to the cached write address and the read address, so as to reduce the storage access of the data processing module, thereby improving the data transmission efficiency and reducing the power consumption.

[0018] In one embodiment, the write control unit includes a write cache unit and a calculation unit, the write cache unit is used to cache the write address and the write data, and the calculation unit is used to perform data calculation on the write data and write the cached calculation data to the slave device.

[0019] Among them, the write cache unit can be implemented using any write cache unit that can cache write addresses and write data; in this embodiment, the write cache unit can be optionally a register, and the register is used to cache the write address and the write data; it can be understood that since the register is tightly coupled with the arbitrator, the access speed is very fast, which can reduce access power consumption to improve data transmission efficiency.

[0020] In this embodiment, the write cache unit stores the write address and write data, and is divided into a two-level pipeline to optimize the write data timing; the calculation unit performs data calculation on the write data, and writes the cached calculation data to the slave device, so as to realize data calculation at the same time during the data transmission process, so as to improve the data transmission efficiency.

[0021] In one embodiment, the read control unit includes an address judgment unit and a data selection unit, the address judgment unit is used to judge the cache write address and the read address and output a corresponding judgment result, and the data selection unit selects bus readback data according to the judgment result.

[0022] In this embodiment, the address judgment unit judges whether the cache write address is consistent with the read address, and selects the bus readback data according to the judgment result; specifically, when the cache write address is consistent with the read address, the arbitrator reads the cache calculation data in the write control unit, and the data selection unit selects the cache calculation data as the bus readback data; when the cache write address and the read address are inconsistent, the read data from the device is selected as the bus readback data to solve the read data delay problem.

[0023] The present invention further proposes a data transmission method based on a SoC bus, which is applied to the above-mentioned data transmission system based on a SoC bus. The data transmission method based on a SoC bus comprises the following steps: Cache write address and write data, calculate data and write the calculation result to the slave device; The bus is selected to read back data based on the cache write address and read address.

[0024] In this embodiment, the bus write process is divided into two levels of pipelines. The first level of the pipeline is responsible for caching the write data and address, and the second level of the pipeline is responsible for writing the data calculation results to the slave device. Specifically, in the first level of the pipeline, when the arbitrator sends a write enable signal, the write data and write address are cached in the corresponding registers, respectively identified as wdata_cache and waddr_cache, and the write cache flag signal wen_flag is set to indicate whether there is data in the write cache unit that needs to be written to the slave device. In the second level of the pipeline, the write cache unit outputs the cache calculation data wdata_cal after the data is calculated in the calculation unit; at this time, it is necessary to determine whether the arbitrator has a read / write enable signal sent, and the arbitrator will only send one read / write enable signal in the same clock cycle. According to whether there is a read / write enable signal, it is divided into the following three cases: Case 1, there is no read enable signal and write enable signal, that is, the cache calculation data wdata_cal is written to the slave device, and the cache flag signal wen_flag is set to 0, indicating that the write cache is cleared and the calculation is completed; Case 2, there is no read enable signal, but there is a write enable signal, that is, the cache calculation data wdata_cal is written to the slave device, and the cache flag signal wen_flag needs to be kept at 1 at this time, indicating that the write cache is valid and the calculation is completed; Case 3, there is a read enable signal, but no write enable signal, that is, a read request is sent to the slave device first, and the cache calculation data wdata_cal is temporarily written out, and the write cache flag signal wen_flag continues to be set to 1. At this time, the read data path needs to be controlled by the read data module; The bus write process is alternately carried out through the above two-level pipeline to realize data transmission and data calculation at the same time, reduce the storage access of the data processing module, and improve data transmission efficiency. The bus read process selects the bus readback data according to the cache write address and read address to solve the data delay problem.

[0025] In one embodiment, the step of selecting a bus to read back data according to the cache write address and the read address is specifically: When the cache write address is consistent with the read address, the cache calculation data in the write control unit is read, and the cache calculation data is selected as the bus readback data; When the cache write address is inconsistent with the read address, the read data from the device is selected as the bus read-back data.

[0026] In this embodiment, after receiving the read enable signal sent by the arbitrator, the read control unit first determines whether the read address and the cache write address waddr_cache are consistent through the address judgment unit. If the current read address is consistent with the cache write address waddr_cache, the arbitrator reads the cache calculation data wdata_cal from the calculation unit, and selects the data as the bus read back data in the next clock cycle; if the current read address is inconsistent with the cache write address waddr_cache, the arbitrator sends a read request to the slave device, and selects the slave device read data as the bus read back data in the next clock cycle, thereby reducing the timing cost of operations in the data transmission process to solve the data read delay problem.

[0027] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A data transmission system based on SoC bus, characterized in that: The data transmission system based on the SoC bus includes a write control unit, a read control unit and an arbiter, wherein the write control unit and the read control unit are connected in parallel and arranged in series between the arbiter and the slave device; The write control unit is used to cache and calculate the write address and write data when receiving the write enable signal sent by the arbitrator, and write the cached calculation data into the slave device; The read control unit is used to select a bus to read back data according to a cache write address and a read address when receiving a read enable signal sent by the arbitrator.

2. The data transmission system based on SoC bus according to claim 1, characterized in that: The write control unit includes a write cache unit and a calculation unit. The write cache unit is used to cache the write address and the write data. The calculation unit is used to perform data calculation on the write data and write the cached calculation data into the slave device.

3. The data transmission system based on SoC bus according to claim 2, characterized in that: The write cache unit is a register, and the register is used to cache the write address and the write data.

4. The data transmission system based on SoC bus according to claim 1, characterized in that: The read control unit includes an address judgment unit and a data selection unit. The address judgment unit is used to judge the cache write address and the read address and output a corresponding judgment result. The data selection unit selects bus readback data according to the judgment result.

5. A data transmission method based on SoC bus, characterized in that: Applied to the data transmission system based on SoC bus as claimed in any one of claims 1 to 4, characterized in that the data transmission method based on SoC bus comprises the following steps: Cache write address and write data, calculate data and write the calculation result to the slave device; The bus is selected to read back data based on the cache write address and read address.

6. The data transmission method based on SoC bus according to claim 5, characterized in that: The step of selecting the bus to read back data according to the cache write address and read address is specifically: When the cache write address and the read address are consistent, the cache calculation data in the write control unit is read, and the cache calculation data is selected as the bus readback data; When the cache write address and read address are inconsistent, the read data from the device is selected as the bus readback data.

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