Logic gate equivalence judgment method based on graph neural network

Abstract

The invention belongs to the field of electronic design automation (EDA), and particularly provides a logic gate equivalence judgment method based on a graph neural network, which is used for improving the speed improvement effect of GNN on SAT solving. The invention provides a logic gate equivalence judgment method based on a graph neural network, and the method comprises the steps: constructing logic gate feature values through a truth table, effectively representing the function information of a logic gate, carrying out the sorting of the feature values on this basis, taking a feature sequence number as a training target of a graph neural network model, reducing the number of nodes of a full connection layer, and improving the equivalence of the logic gate. Therefore, the circuit representation capability of the graph neural network model is improved, the model parameters are reduced, the training speed is improved, and in the aspect of logic gate equivalence judgment, the graph neural network model is utilized to predict the similarity between logic gates, the variable search strategy is improved, and the SAT solving speed is improved.

Description

Technical Field

[0001] The present invention belongs to the field of Electronic Design Automation (EDA), and specifically provides a logic gate equivalence determination method based on a graph neural network. Background Art

[0002] Logic gate equivalence refers to the equivalence of two logic gates in logical function. Logic gate equivalence determination is the main step in equivalent circuit checking and plays an important role in electronic design automation.

[0003] There are many methods to determine the equivalence of logic gates, including truth table comparison, logic expression comparison, and Boolean Satisfiability Problem (SAT) solution. Among them, the truth table comparison method determines whether two logic gates are equivalent by comparing the truth tables output by two logic gates; the logic expression comparison method uses Boolean algebra simplification and then compares the simplified logic expressions to determine equivalence; the Boolean Satisfiability Problem solution method converts the logic equivalence problem into a Boolean Satisfiability Problem and completes the determination through the SAT solver. This method is currently an effective method for solving the logic equivalence problem. The mainstream SAT solver is based on the Conflict-Driven Clause Learning (CDCL) algorithm. The advantage of the CDCL algorithm is that it can solve a large number of problems, but its disadvantage is that it depends significantly on the difficulty of the problem and has a high computational complexity for solving difficult clauses. In recent years, Graph Neural Networks (GNNs) have been introduced into SAT solvers to improve the time efficiency of solving, such as by using GNNs to preprocess logical formulas, identify potential conflicts and structural features to guide the search process, or use node features obtained by GNNs to generate or improve heuristic search strategies.

[0004] Although GNN has improved the speed of SAT solving, due to the complex and changeable circuit structure, the current graph neural network model is still insufficient in its ability to represent the logical functions of the circuit, resulting in the effect of GNN on improving the speed of SAT solving needs to be improved. Summary of the invention

[0005] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and provide a logic gate equivalence determination method based on graph neural network, so as to improve the speed improvement effect of GNN on SAT solving.

[0006] In order to achieve the above object, the technical solution adopted by the present invention is:

[0007] A method for determining logic gate equivalence based on a graph neural network, characterized by comprising the following steps:

[0008] A1. Generate feature number:

[0009] A1-1. Obtain the truth table of each logic gate of the circuit through analog input;

[0010] A1-2. For each logic gate, calculate the characteristic value of the logic gate;

[0011] A1-3. Sort the logic gates in descending order according to the eigenvalues ​​of the logic gates. Logic gates with the same eigenvalues ​​have the same serial number. The serial number obtained after sorting is used as the characteristic serial number of the logic gate.

[0012] A2. Build and train graph neural network models:

[0013] A2-1. Build a graph neural network model, including graph convolution layer and fully connected layer;

[0014] The graph convolution layer includes nodes and edges of the graph network, and its construction process is as follows: for each logic gate in the circuit, a logic gate node is created, and the initial value of the data vector of the logic gate node is a random number; for each connection between a pair of logic gates in the circuit, an edge is created from the input logic gate node to the output logic gate node;

[0015] The fully connected layer includes the same number of nodes as the logic gate nodes, and the nodes are connected to the logic gate nodes of the graph convolutional layer in a fully connected manner;

[0016] A2-2. Training the graph neural network model: Set the loss function and use the back propagation algorithm to complete the training of the graph neural network model to obtain the data vector of each logic gate node;

[0017] A3. Construct SAT: Define a Boolean variable for each logic gate in the circuit. Let the variables corresponding to the two logic gates to be determined be u 1 and u 2 , corresponding to the output logic expressions of the two logic gates and Then define SAT: logical expression Is it satisfying, among which, Represents a logical expression AND logical expressions XOR; the logical expression Add all variables in to the initially empty set V, and set the initial value of the benchmark variable to 1;

[0018] A4. Quickly solve SAT:

[0019] A4-1. Define a backup Boolean variable t and back up the value of the reference variable to t;

[0020] A4-2. Determine whether the set V is empty: If it is empty, end the current SAT solution;

[0021] A4-3. Select variable v from set V, and update the benchmark variable to variable v, and delete variable v from set V; if the current selection is the first selection, select it randomly; otherwise, calculate the graph representation distance between each variable in set V and the current benchmark variable, and select the variable with the smallest graph representation distance;

[0022] A4-4. Let the value of variable v be the logical inversion of the backup Boolean variable t, and perform a simplified recursive solution;

[0023] A4-5. Let the value of variable v be the logical value of the backup Boolean variable t, and perform a simplified recursive solution;

[0024] A4-6. Return result: The current SAT is unsatisfactory;

[0025] A5. Logic gate equivalence determination: For SAT: logical expression Whether it is satisfied, if not, the output is that the two logic gates to be determined are equivalent, otherwise, the output is that the two logic gates to be determined are not equivalent.

[0026] Furthermore, in step A1-2, the characteristic value calculation process is: for the i-th logic gate, let the output value sequence of its truth table be {z i,1 ,z i,2 ,z i,3 …z i,M}, calculate the eigenvalue f of the i-th logic gate i :

[0027]

[0028] Where i = 1, 2, ..., I, I is the number of logic gates, M is the number of rows in the truth table, z i,j Represents the jth output value of the i-th logic gate.

[0029] Furthermore, in step A2-2, the loss function is expressed as:

[0030]

[0031] in, is the predicted value of the characteristic number of the i-th logic gate, N i is the characteristic number of the i-th logic gate.

[0032] Furthermore, in step 4-3, the graph represents the distance as the Euclidean distance between the data vectors of the logic gate nodes of the graph convolution layer corresponding to the two variables.

[0033] Furthermore, in step A4-4 and step A4-5, the recursive solution process is simplified as follows:

[0034] According to variable assignment and logical constraints, simplify the current SAT logical expression to the simplest expression or logical value Y;

[0035] If the current SAT logical expression is simplified to the simplest expression, it is recorded as Then solve the new SAT according to step A4: logical expression Is it satisfyable?

[0036] If the current SAT logical expression is simplified to logical value Y, determine the logical value Y: if Y = 0, then end the current SAT solution; if Y = 1, then end the entire SAT solution and return the result: Logical expression Can be satisfied.

[0037] Based on the above technical solution, the beneficial effects of the present invention are:

[0038] The present invention provides a logic gate equivalence determination method based on graph neural network. The method constructs logic gate eigenvalues ​​through a truth table to effectively characterize the functional information of the logic gate, and on this basis, sorts the eigenvalues, and uses the feature sequence numbers as the training targets of the graph neural network model, thereby reducing the number of nodes in the fully connected layer, thereby improving the circuit representation capability of the graph neural network model while reducing model parameters and increasing the training speed. In terms of logic gate equivalence determination, the graph neural network model is used to predict the similarity between logic gates, thereby improving the variable search strategy and increasing the SAT solution speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a flowchart of the logic gate equivalence determination method based on graph neural network in the present invention. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and beneficial effects of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0041] This embodiment provides a method for determining the equivalence of logic gates based on a graph neural network, and the process is as follows: Figure 1 As shown, the goal is to determine the equivalence of the first and second logic gates of a given digital circuit, which is given in the form of a circuit netlist.

[0042] The specific steps of the logic gate equivalence determination method are as follows:

[0043] A1. Generate feature number:

[0044] A1-1. Obtain the truth table of each logic gate of the circuit through analog input;

[0045] A1-2. For each logic gate, calculate the characteristic value of the logic gate respectively; specifically: for the i-th logic gate, let the output value sequence of its truth table be {z i,1 ,z i,2 ,z i,3 …z i,M}, calculate the eigenvalue f of the i-th logic gate i :

[0046]

[0047] Where i = 1, 2, ..., I, I is the number of logic gates, M is the number of rows in the truth table, z i,j represents the jth output value of the i-th logic gate;

[0048] In this embodiment, the number of logic gates is I=36, the number of rows of the truth table is M=32, and the characteristic values ​​of each logic gate are calculated. Taking the first and second logic gates as examples, the characteristic value f of the first logic gate is 1 =792058851, the eigenvalue f of the second logic gate 2 =894254013;

[0049] A1-3. Sort the logic gates according to their eigenvalues ​​from large to small. Logic gates with the same eigenvalues ​​have the same serial number. The serial number obtained after sorting is used as the characteristic serial number of the logic gate. The characteristic serial number of the i-th logic gate is recorded as N i ;

[0050] In this embodiment, taking the first and second logic gates as examples, the feature number N of the first logic gate is 1 =10, the characteristic number N of the second logic gate 2 =19;

[0051] A2. Build and train graph neural network models:

[0052] A2-1. Build a graph neural network model, including graph convolution layer and fully connected layer;

[0053] The graph convolution layer contains nodes and edges of the graph network, and its construction process is as follows: for each logic gate in the circuit, a logic gate node is created, and the data of the logic gate node is a vector with a dimension of w, and its initial value is a random number; for each connection between a pair of logic gates in the circuit, an edge is created from the input logic gate node to the output logic gate node;

[0054] In this embodiment, the graph convolution layer contains 36 logic gate nodes and 45 edges, and the initial data of each node is a 64-dimensional vector (w=64);

[0055] The fully connected layer includes I=36 nodes, and the 36 nodes are connected to the logic gate nodes of the graph convolutional layer in a fully connected manner;

[0056] A2-2. Training the graph neural network model: Perform graph convolution on the graph convolution layer, forward propagate the obtained logic gate node data to the fully connected layer, calculate the loss, and use the backpropagation algorithm to update the model parameters, iterating until the training is completed;

[0057] The loss function is:

[0058]

[0059] in, is the data of the i-th node of the fully connected layer, that is, the predicted feature number;

[0060] In this embodiment, taking the first and second logic gates as an example, the feature serial number of the first logic gate is The characteristic number of the second logic gate Then the loss corresponding to the first and second logic gates is and The final calculated loss of the entire network is L = 306;

[0061] A3. Construct SAT: Define a Boolean variable for each logic gate in the circuit. Let the variables corresponding to the first and second logic gates to be determined be u and 1 and u 2 , construct logic gate u 1 The output logic expression of Construct logic gate u 2 The output logic expression of Define SAT as: logical expression Is it satisfying, among which, Represents a logical expression AND logical expressions XOR; the logical expression Add all variables in to an initially empty set V, and set the benchmark variable to a Boolean variable with an initial value of 1;

[0062] In this embodiment, u is defined 1 ,u 2 ,u 3 ···,u 36 There are 36 variables, corresponding to 36 logic gates, and the resulting logical expression is SAT is defined as: logical expression Whether it can be satisfied, u 3 ,u 4 ,u 8 The other three variables are added to the set V, that is, V = {u 3 ,u 4 ,u 8}, define a new Boolean variable q, set q = 1, and set q as the initial reference variable;

[0063] A4. Quickly solve SAT:

[0064] A4-1. Define a backup Boolean variable t and back up the value of the baseline variable to t;

[0065] In this embodiment, let t = q, that is, t = 1;

[0066] A4-2. Determine whether the set V is empty: if it is empty, end the current SAT solution; otherwise, continue to execute the subsequent steps of the current SAT solution;

[0067] In this example, to solve SAT: the logical expression Taking the first round of iteration as an example, since the set V is not empty, the subsequent steps of the current SAT solution are continued;

[0068] A4-3. Select variable v from set V, and update the benchmark variable to variable v, and delete variable v from set V; if the current selection is the first selection, select it randomly; otherwise, calculate the graph representation distance between each variable in set V and the current benchmark variable, and select the variable with the smallest graph representation distance; the graph representation distance is the Euclidean distance between the data vectors of the graph convolutional layer logic gate nodes corresponding to the two variables;

[0069] In this embodiment, in the first selection, the variable u is randomly selected 8 , and update the benchmark variable to variable u 8 , and delete it from V, and get V = {u 3 ,u 4};

[0070] A4-4. Let the value of v be the logical inverse of t and perform a simplified recursive solution;

[0071] In this example, to solve SAT: the logical expression Take the first round of iteration as an example, let u 8 The logical inversion value of t, that is, u 8 =0;

[0072] Simplified recursive solution specifically includes:

[0073] Simplify logical expressions based on existing variable assignments and logical constraints Get the simplest expression Solve the new SAT according to step A4: logical expression whether it is satisfyable;

[0074] Further, to solve SAT: the logical expression Take a round of iteration as an example to illustrate whether it can be satisfied:

[0075] According to step A4-1, define a backup Boolean variable t', let t' = u 8 , that is, t′=0;

[0076] According to step A4-2, determine whether the set V is empty. Since the set V is not empty, continue to execute the subsequent steps of the current SAT solution;

[0077] Select the variable according to step A4-3. Since this is not the first selection, calculate u in V 3 ,u 4 with u 8 The graph represents the distance, and the variable u with the smallest distance is selected 4 , will u 4 Set it as the benchmark variable and delete it from V, and get V = {u 3};

[0078] Follow step A4-4. Let u 4 is the logical negation of t′, i.e. u 4 =1;

[0079] Simplified recursive solution specifically includes:

[0080] Simplify logical expressions based on existing variable assignments and logical constraints If the logical value Y=1 is obtained, the entire SAT solution is terminated and the result is returned: Logical expression Satisfiable;

[0081] A5. Logic gate equivalence determination: For SAT: logical expression Whether it is satisfyable, if not, then the output is that the two logic gates are equivalent, otherwise, the output is that the two logic gates are not equivalent;

[0082] In this embodiment, since the logical expression is satisfiable, then it is determined that the first logic gate is not equivalent to the second logic gate;

[0083] From the above process, we can see that in the SAT solution, the graph representation information obtained by the graph neural network is used to calculate the graph representation distance between the variable to be selected and the benchmark variable, and the variable with the smallest distance is preferentially selected, and the logical value opposite to the benchmark variable is preferentially assigned to it, which speeds up the SAT solution process.

[0084] The above description is only a specific implementation mode of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other alternative features that are equivalent or have similar purposes; all the disclosed features, or all the steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A logic gate equivalence determination method based on graph neural network, characterized in that: The following steps are involved: A1. Generate feature number: A1-1. Obtain the truth table of each logic gate of the circuit through analog input; A1-2. For each logic gate, calculate the characteristic value of the logic gate; A1-3. Sort the logic gates in descending order according to the eigenvalues ​​of the logic gates. Logic gates with the same eigenvalues ​​have the same serial number. The serial number obtained after sorting is used as the characteristic serial number of the logic gate. A2. Build and train graph neural network models: A2-1. Build a graph neural network model, including graph convolution layer and fully connected layer; The graph convolution layer includes nodes and edges of the graph network, and its construction process is as follows: for each logic gate in the circuit, a logic gate node is created, and the initial value of the data vector of the logic gate node is a random number; for each connection between a pair of logic gates in the circuit, an edge is created from the input logic gate node to the output logic gate node; The fully connected layer includes the same number of nodes as the logic gate nodes, and the nodes are connected to the logic gate nodes of the graph convolutional layer in a fully connected manner; A2-2. Training the graph neural network model: Set the loss function and use the back propagation algorithm to complete the training of the graph neural network model to obtain the data vector of each logic gate node; A3. Construct SAT: Define a Boolean variable for each logic gate in the circuit. Let the variables corresponding to the two logic gates to be determined be u1 and u2 respectively. Construct the output logic expressions of the two logic gates accordingly. and Then define SAT: logical expression Is it satisfying, among which, Represents a logical expression AND logical expressions XOR; the logical expression Add all variables in to the initially empty set V, and set the initial value of the benchmark variable to 1; A4. Quickly solve SAT: A4-1. Define a backup Boolean variable t and back up the value of the reference variable to t; A4-2. Determine whether the set V is empty: If it is empty, end the current SAT solution; A4-3. Select variable v from set V, and update the benchmark variable to variable v, and delete variable v from set V; if the current selection is the first selection, select it randomly; otherwise, calculate the graph representation distance between each variable in set V and the current benchmark variable, and select the variable with the smallest graph representation distance; A4-4. Let the value of variable v be the logical inversion of the backup Boolean variable t, and perform a simplified recursive solution; A4-5. Let the value of variable v be the logical value of the backup Boolean variable t, and perform a simplified recursive solution; A4-6. Return result: The current SAT is unsatisfactory; A5. Logic gate equivalence determination: For SAT: logical expression Whether it is satisfied, if not, the output is that the two logic gates to be determined are equivalent, otherwise, the output is that the two logic gates to be determined are not equivalent.

2. The logic gate equivalence determination method based on graph neural network according to claim 1 is characterized in that: In step A1-2, the characteristic value calculation process is: for the i-th logic gate, let the output value sequence of its truth table be {z i,1 ,z i,2 ,z i,3 …z i,M }, calculate the eigenvalue f of the i-th logic gate i : Where i = 1, 2, ..., I, I is the number of logic gates, M is the number of rows in the truth table, z i,j Represents the jth output value of the i-th logic gate.

3. The logic gate equivalence determination method based on graph neural network according to claim 1 is characterized in that: In step A2-2, the loss function is expressed as: in, is the predicted value of the characteristic number of the i-th logic gate, N i is the characteristic number of the i-th logic gate.

4. The logic gate equivalence determination method based on graph neural network according to claim 1 is characterized in that: In step 4-3, the graph represents the distance as the Euclidean distance between the data vectors of the logic gate nodes of the graph convolutional layer corresponding to the two variables.

5. The logic gate equivalence determination method based on graph neural network according to claim 1 is characterized in that: In step A4-4 and step A4-5, the simplified recursive solution process is: According to variable assignment and logical constraints, simplify the current SAT logical expression to the simplest expression or logical value Y; If the current SAT logical expression is simplified to the simplest expression, it is recorded as Then solve the new SAT according to step A4: the logical expression Is it satisfyable? If the current SAT logical expression is simplified to logical value Y, determine the logical value Y: if Y = 0, then end the current SAT solution; If Y=1, the entire SAT solution is terminated and the result is returned: logical expression Can be satisfied.

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