Verification method and storage medium

Abstract

The invention discloses a verification method and a storage medium, and relates to the technical field of scanning dump, and the verification method comprises the steps: obtaining an actual observation value of a scanning dump circuit in a simulation circuit operation process of the scanning dump circuit, comparing the actual observation value with a target observation value, and obtaining a circuit verification result; in the simulation transfer process of the scanning dump circuit, after a first report value of each register in the scanning dump circuit is recorded, transfer data transferred by the scanning dump circuit and a second report value mapped to each register are obtained, the first report value and the second report value corresponding to each register are compared, and a simulation result is obtained. Therefore, full verification of the scanning dump circuit is realized, and defects existing in later use are avoided.

Description

Technical Field

[0001] The present application relates to the field of scanning dump technology, and in particular to a verification method and a storage medium. Background Art

[0002] When the system encounters a stuck case, we cannot debug through the normal processor read register operation, but there will be a need to obtain the internal register status of the chip to obtain clues for chip debugging. At this time, the chip will be configured to scan dump mode through the scan dump circuit, so as to transfer each register inside the chip based on the scan chain and obtain the value of each register inside the chip.

[0003] However, conventional scan dump circuits generally verify whether they can work properly, but do not verify whether there are problems with their circuit design and whether the values ​​of registers dumped based on the circuit are credible, which results in dump errors caused by circuit design during the operation of the scan dump circuit and data analysis errors caused by the dumped values ​​during the debugging process. Summary of the invention

[0004] The main purpose of the present application is to provide a verification method and a storage medium, aiming to solve the technical problem of defects in later use caused by insufficient early verification of a scan dump circuit.

[0005] To achieve the above purpose, the present application proposes a verification method, which includes:

[0006] During the simulation circuit operation of the scan dump circuit, actual observation values ​​of the scan dump circuit are obtained, and the actual observation values ​​are compared with target observation values ​​to obtain circuit verification results;

[0007] During the simulation transfer process of the scan dump circuit, after recording the first report value of each register in the scan dump circuit, the transfer data transferred through the scan dump circuit is obtained, and the second report value when mapped to each register is obtained. The first report value and the second report value corresponding to each register are compared to obtain the data dump result.

[0008] In one embodiment, the scan dump circuit is composed of a plurality of partition circuits, the partition circuits include a reset signal switching circuit, and in the case of being in a partition circuit operation phase of a simulation circuit operation process, in the simulation circuit operation process of the scan dump circuit, before the step of obtaining the actual observation value of the scan dump circuit, the steps include:

[0009] Controlling the scan dump circuit to enter a single chain mode, tracing the scan chain in the scan dump circuit, and obtaining a first scan path report of each partition circuit, wherein each first scan path report includes first register information of each register on each scan chain on the corresponding partition circuit, and first inverter information between each electronic component on each scan chain;

[0010] Tracking the reset signal switching circuit using a first preset script to obtain switching information of the reset signal in the reset signal switching circuit, wherein the switching information includes first switching information that the reset signal implements a switching operation based on a multi-way reset device, and a functional reset source of the multi-way reset device is connected to a combinational logic, and second switching information that the reset signal implements a switching operation based on the multi-way reset device, and a functional reset source of the multi-way reset device is connected to a register;

[0011] A partition circuit verification script is generated according to the first scan path report and the switching information.

[0012] In one embodiment, the step of generating a partition circuit verification script according to the first scan path report and the switching information includes:

[0013] Generate a first circuit verification script for executing a reset invalid value for the combinational logic according to the first switching information;

[0014] According to the first register information and the second switching information, if the register reflected by the first register information is the register reflected by the second switching information, a second circuit verification script for executing placing a reset invalid value in the register is generated;

[0015] According to the first register information and the second switching information, if the register reflected by the first register information is not the register reflected by the second switching information, generating a third circuit verification script for executing placing a random value in the register;

[0016] A fourth circuit verification script is generated based on the first register information and the first inverter information for executing the capture of the actual observation value of the register and the calculation of the target observation value of the register.

[0017] In one embodiment, the steps of obtaining an actual observation value of a scan dump circuit, comparing the actual observation value with a target observation value, and obtaining a circuit verification result include:

[0018] After executing the second circuit verification script and / or the third circuit verification script, and the first circuit verification script, sequentially configuring the partition circuit;

[0019] Execute the fourth circuit verification script, configure a plurality of clocks for the scan clock port in the partition circuit based on the fourth circuit verification script, extract the register value of each register according to the clock pulse of each clock, and obtain the actual observation value;

[0020] Calculate the target observation value according to the reset invalid value configured when executing the second circuit verification script and / or the random value configured when executing the third circuit verification script, and the first scan path report corresponding to the partition circuit;

[0021] Determine whether the actual observation value is equal to the target observation value;

[0022] If the actual observed value is equal to the target observed value, a circuit verification result indicating that the partitioned circuit has passed verification is output.

[0023] In one embodiment, the scan dump circuit includes a reset signal switching circuit, and in a case where the overall circuit operation stage of the simulation circuit operation process is in progress, in the simulation circuit operation process of the scan dump circuit, before the step of obtaining the actual observation value of the scan dump circuit, the steps include:

[0024] Controlling the scan dump circuit to enter a single chain mode, tracing the scan chain in the scan dump circuit, and obtaining a second scan path report of the scan dump circuit, wherein the second scan path report includes second register information of each register on each scan chain in the scan dump circuit, and second inverter information between each electronic component on each scan chain;

[0025] Track the reset signal switching circuit using a second preset script to obtain switching information of the reset signal in the reset signal switching circuit, wherein the switching information includes third switching information that the reset signal implements a switching operation based on a multi-way reset device, and a functional reset source of the multi-way reset device is connected to a combinational logic, and fourth switching information that the reset signal implements a switching operation based on the multi-way reset device, and a functional reset source of the multi-way reset device is connected to a register;

[0026] An overall circuit verification script is generated according to the second scan path report and the switching information.

[0027] In one embodiment, the step of generating an overall circuit verification script according to the second scan path report and the switching information includes:

[0028] Generate a fifth circuit verification script for executing a reset invalid value for the combinational logic according to the third switching information;

[0029] According to the second register information and the fourth switching information, if the register reflected by the second register information is the register reflected by the fourth switching information, a sixth circuit verification script for executing placing a reset invalid value in the register is generated;

[0030] According to the second register information and the fourth switching information, if the register reflected by the second register information is not the register reflected by the fourth switching information, generating a seventh circuit verification script for executing placing a random value in the register;

[0031] An eighth circuit verification script is generated based on the second register information and the second inverter information, for executing the capture of the actual observed value of the register and the calculation of the target observed value of the register.

[0032] In one embodiment, the steps of obtaining an actual observation value of a scan dump circuit, comparing the actual observation value with a target observation value, and obtaining a circuit verification result include:

[0033] After executing the sixth circuit verification script and / or the seventh circuit verification script, and the fifth circuit verification script, sequence configuration is performed on the scan dump circuit;

[0034] Execute the eighth circuit verification script, configure a plurality of clocks for the scan clock port in the scan dump circuit based on the eighth circuit verification script, extract the register value of each register according to the clock pulse of each clock, and obtain the actual observation value;

[0035] According to the reset invalid value placed when executing the sixth circuit verification script and / or the random value placed when executing the seventh circuit verification script, combined with the second inverter information, a transfer value of the random value on the register transferred to the data output port is calculated, and the transfer value is determined as the target observation value;

[0036] Determine whether the actual observation value is equal to the target observation value;

[0037] If the actual observed value is equal to the target observed value, a circuit verification result indicating that the scan dump circuit verification has passed is output.

[0038] In one embodiment, during the simulated transfer process of the scan dump circuit, after recording the first report value of each register in the scan dump circuit and before the step of acquiring the transfer data transferred by the scan dump circuit, the step includes:

[0039] Tracking the scan chain in the scan dump circuit to obtain a third scan path report of the scan dump circuit, and obtaining, according to the third scan path report, a first transfer script for executing random value placement for each register on each scan path in the third scan path report, a second transfer script for collecting register values ​​on each register, and a third transfer script for executing generation of a read command according to the length of the third scan path report;

[0040] The third transfer script is executed to generate a first operation file for collecting the transfer data transferred to the data output port, and a second operation file for closing the clock source.

[0041] In one embodiment, after recording the first report value of each register in the scan dump circuit, obtaining the second report value of the transfer data transferred by the scan dump circuit when mapped to each register, and comparing the first report value and the second report value corresponding to each register to obtain the data dump result, the step includes:

[0042] Execute the first transfer script, place a random value on each register based on the first transfer script, run the second operation file, turn off the clock source based on the second operation file, execute the second transfer script, obtain the register value on each register based on the second transfer script, and obtain the first report value;

[0043] Run the first run file to enter the scan dump mode, in the scan dump mode, record the transfer data transferred to the data output port, and map the transfer data to the corresponding register according to the third scan path report, calculate the pre-transfer data of the register, and determine the pre-transfer data as the second report value;

[0044] determining whether the first reported value is equal to the second reported value;

[0045] If the first report value is equal to the second report value, a transfer verification result indicating that the scan dump circuit verification has passed is output.

[0046] In addition, to achieve the above objectives, the present application also proposes a verification device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the verification method described above.

[0047] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the verification method described above are implemented.

[0048] One or more technical solutions proposed in this application have at least the following technical effects:

[0049] A verification method for verifying a scan dump circuit is proposed, the verification method comprising:

[0050] During the simulation circuit operation of the scan dump circuit, the actual observation value of the scan dump circuit is obtained, and the actual observation value is compared with the target observation value to obtain a circuit verification result, thereby determining the circuit design verification result of the scan dump circuit based on the circuit verification result, and obtaining a result of whether the circuit design of the scan dump circuit will have a dump error; and during the simulation transfer process of the scan dump circuit, after recording the first report value of each register in the scan dump circuit, the transfer data transferred by the scan dump circuit is obtained, and the second report value when mapped to each register is obtained, and the first report value and the second report value corresponding to each register are compared to obtain a data dump result, thereby determining the credibility result of the value of the register transferred based on the scan dump circuit based on the data dump result, and obtaining a phenomenon of whether the value of the register transferred based on the scan dump circuit will cause an error in the subsequent debugging result, thereby achieving full verification of the scan dump circuit and avoiding defects in subsequent use. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0052] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0053] Figure 1 A flowchart of the first embodiment of the verification method of this application is provided;

[0054] Figure 2 A flowchart of the second embodiment of the verification method of this application is provided;

[0055] Figure 3 A flowchart of the third embodiment of the verification method of this application is provided;

[0056] Figure 4 A flowchart of the fourth embodiment of the verification method of this application is provided;

[0057] Figure 5 A schematic diagram of the device structure of the hardware operating environment involved in the verification method in the embodiment of the present application.

[0058] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0059] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0060] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0061] The main solution of the embodiment of the present application is: during the simulation circuit operation of the scan dump circuit, the actual observation value of the scan dump circuit is obtained, and the actual observation value is compared with the target observation value to obtain a circuit verification result; during the simulation transfer process of the scan dump circuit, after recording the first report value of each register in the scan dump circuit, the transfer data transferred by the scan dump circuit is obtained, and the second report value when mapped to each register is obtained, and the first report value and the second report value corresponding to each register are compared to obtain a data dump result.

[0062] Since conventional scan dump circuits generally verify whether they can work normally, but do not verify whether there are problems with their circuit design and whether the values ​​of registers dumped based on the circuit are credible, there are dump errors caused by circuit design during the operation of the scan dump circuit, and data analysis errors caused by the dumped values ​​during the debugging process.

[0063] The present application provides a solution to achieve full verification of the scan dump circuit and avoid defects in subsequent use.

[0064] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or an electronic device capable of realizing the above functions, a verification device, etc. The following takes the verification device as an example to illustrate this embodiment and the following embodiments.

[0065] Based on this, the present application embodiment provides a verification method, referring to Figure 1 , Figure 1 This is a flowchart of the first embodiment of the verification method of the present application.

[0066] In this embodiment, the verification method includes steps S10 to S20:

[0067] Step S10, during the simulation circuit operation of the scan dump circuit, obtaining the actual observation value of the scan dump circuit, comparing the actual observation value with the target observation value, and obtaining a circuit verification result.

[0068] It should be noted that the scan dump circuit is a circuit based on a DFT (Design for Test) scan chain designed for circuit debugging. Therefore, the accuracy of the scan dump circuit will affect the subsequent debugging process, and the accuracy of the scan dump circuit is directly related to the circuit design of the scan dump circuit.

[0069] Therefore, in order to ensure the accuracy of the subsequent debugging process, this embodiment proposes to simulate the circuit operation process of the scan dump circuit, obtain the actual observation value of the circuit operation during the simulation circuit operation process, and obtain the target observation value of the circuit operation, compare the actual observation value with the target observation value, and obtain the circuit verification result according to the comparison result. Among them, if the actual observation value is consistent with the target observation value, it means that the actual operation state of the scan dump circuit is consistent with the target operation state, that is, the circuit design of the scan dump circuit will not cause the register value dump failure phenomenon.

[0070] The simulation circuit operation process can be realized by the Paladin simulator, based on which the function verification of the scan dump circuit can be quickly performed. In the actual verification process, other types of simulators can also be used.

[0071] Step S20, during the simulation transfer process of the scan dump circuit, after recording the first report value of each register in the scan dump circuit, obtain the transfer data transferred by the scan dump circuit, and the second report value when mapped to each register, compare the first report value and the second report value corresponding to each register to obtain the data dump result.

[0072] In addition, the accuracy of the scan dump circuit is also directly related to the dump process (i.e., the transfer process) of the scan dump circuit. Therefore, in order to ensure the accuracy of the subsequent debugging process, the present embodiment proposes to simulate the transfer process of the scan dump circuit, obtain the first report value transferred to the register in the actual data transfer process during the simulated transfer process, and obtain the second report value transferred to the register in the ideal data transfer process, compare the first report value with the second report value, and obtain the data dump result according to the comparison result. If the first report value is consistent with the second report value, it means that the actual data transfer accuracy of the scan dump circuit is consistent with the target data transfer accuracy, that is, the data dump operation of the scan dump circuit can ensure the accuracy of the data dump and will not cause data dump errors or omissions.

[0073] In this embodiment, during the simulation circuit operation of the scan dump circuit, the actual observation value of the scan dump circuit is obtained, and the actual observation value is compared with the target observation value to obtain a circuit verification result, thereby determining the circuit design verification result of the scan dump circuit based on the circuit verification result, and obtaining the result of whether the circuit design of the scan dump circuit will have a dump error; and during the simulation transfer process of the scan dump circuit, after recording the first report value of each register in the scan dump circuit, obtaining the transfer data transferred by the scan dump circuit, and mapping it to each register when the second report value is obtained, and comparing the first report value and the second report value corresponding to each register to obtain a data dump result, thereby determining the credibility result of the value of the register transferred based on the scan dump circuit based on the data dump result, and obtaining the phenomenon of whether the value of the register transferred based on the scan dump circuit will cause an error in the subsequent debugging result, thereby achieving full verification of the scan dump circuit and avoiding defects in subsequent use.

[0074] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the above-mentioned embodiment 1 can be referred to the above introduction, and will not be repeated in the following. Figure 2 Before step S10, the verification method further includes steps A11 to A13:

[0075] Step A11, controlling the scan dump circuit to enter the single chain mode, tracing the scan chain in the scan dump circuit, and obtaining a first scan path report of each partition circuit, wherein each first scan path report includes first register information of each register on each scan chain on the corresponding partition circuit, and first inverter information between each electronic component on each scan chain.

[0076] It should be noted that in order to ensure the accuracy of the circuit design verification results of the scan dump circuit, it is proposed to conduct circuit design verification in stages. The first stage of verification is the present embodiment, which is to verify several partition circuits that constitute the scan dump circuit to verify whether there are problems with the circuit design of a single partition circuit, so as to avoid the incomplete verification of the circuit design of the entire scan dump circuit. Circuit design verification is performed separately for each partition circuit included in the scan dump circuit, which is conducive to comprehensive verification of the functions corresponding to each partition circuit and improves the verification accuracy of the underlying design of the scan dump circuit.

[0077] First, the scan chain structure in the partitioned circuit is traced using the Tessent ATPG tool, an automated test vector generation tool.

[0078] Because the scan dump circuit is based on the single chain mode, when tracing the scan chains in each partition circuit, the partition circuit is first configured to enter the single chain mode, and then each scan chain in the partition circuit is traced to obtain a first scan path report that can reflect the scan chain structure. The first scan path report corresponding to each partition circuit includes the hierarchical information of each register on each scan chain (i.e., the first register information), and the information of whether an inverter is included between each electronic component on the scan chain (i.e., the first inverter information).

[0079] Among them, in the actual verification process, other types of atpg tools can also be used to track the scan chain structure.

[0080] Step A12, use the first preset script to track the reset signal switching circuit to obtain the switching information of the reset signal in the reset signal switching circuit, wherein the switching information includes the first switching information that the reset signal is based on a multi-way reset device to implement the switching operation, and the functional reset source of the multi-way reset device is connected to the combinational logic, and the second switching information that the reset signal is based on the multi-way reset device to implement the switching operation, and the functional reset source of the multi-way reset device is connected to the register.

[0081] After the scan chain on the partition circuit is traced using the tessent atpg tool through step A11 and the first scan path report is obtained, the structure of the reset signal switching circuit in the partition circuit is traced using the first preset script and the relevant information is saved. The first preset script is any tracing script that can be used to trace the structure of the reset signal switching circuit in the partition circuit.

[0082] Specifically, there are two sources for the reset signal of the register in the partition circuit, one is the function control and the other is the DFT control. The reset signal output by the function control and the reset signal output by the DFT control are both output switched through the configuration of the DFT control control register. Therefore, in this step, it is necessary to start from the reset control TDR (Test Data Register) and track where the control register is connected.

[0083] ① If it is tracked that a reset control TDR is connected to a non-multi-way reset device, it means that the switching of the reset signal output by the function control or DFT control is realized by a non-multi-way reset device. The switching of the reset signal based on the non-multi-way reset device will generate glitches during the switching of the reset signal, which will have a negative impact on the circuit operation of the partition circuit. Therefore, after the information is tracked, the non-multi-way reset device obtained will be collected and reported, so that the circuit design can be modified after the verification is completed to avoid the defect of the reset control TDR being connected to the non-multi-way reset device. Among them, the non-multi-way reset device in this embodiment refers to a combination device with a multiplexer function composed of some simple logic gates such as AND gates, OR gates, and NOT gates. This combination device will generate glitches during operation.

[0084] ② If it is traced that a reset control TDR is connected to a multi-channel reset device, it means that the switching of the reset signal output by the functional control or DFT control is realized by the multi-channel reset device, then continue to track the functional control one channel (i.e., the functional reset source) of the output reset signal corresponding to the multi-channel reset device. If it is traced that the functional control one channel is connected to the combinational logic, then record the combinational logic to obtain the first switching information.

[0085] ③ If it is traced that a reset control TDR is connected to a multi-channel reset device, continue to trace the functional control one channel of the output reset signal corresponding to the multi-channel reset device. If it is traced that the functional control one channel is connected to a register, record the register to obtain the second switching information.

[0086] Step A13: Generate a partition circuit verification script according to the first scan path report and the switching information.

[0087] After obtaining the first scan path report and the corresponding switching information through step A11 and step A12, it is necessary to generate a corresponding partition circuit verification script for verifying the partition circuit according to the first scan path report and the corresponding switching information, as described in detail as follows:

[0088] In a feasible implementation, step A13 may include steps A14 to A17:

[0089] Step A14: generating a first circuit verification script for configuring a reset invalid value for the combinational logic according to the first switching information.

[0090] Step A15, based on the first register information and the second switching information, if the register reflected by the first register information is the register reflected by the second switching information, a second circuit verification script for executing placing a reset invalid value in the register is generated.

[0091] Step A16: based on the first register information and the second switching information, if the register reflected by the first register information is not the register reflected by the second switching information, a third circuit verification script for executing placing a random value in the register is generated.

[0092] In order to put the register driven by the multiplexed device in a reset invalid state before switching to the reset source controlled by the DFT, so as to place a random value in the register driven by the multiplexed device and avoid the placed random value being reset to 0, a first circuit verification script for executing a reset invalid value for configuring the combinational logic will be generated.

[0093] At this time, based on the first register information and the second switching information, it is determined whether the register to which the first register information belongs and the register connected to the functional reset source in the second switching information are the same register. If so, a second circuit verification script is generated to execute a reset invalid value for the register. If not, a third circuit verification script is generated to execute a random value for the register.

[0094] Step A17, generating a fourth circuit verification script for executing the capture of the actual observed value of the register and the calculation of the target observed value of the register according to the first register information and the first inverter information.

[0095] Furthermore, after generating the first circuit verification script, the second circuit verification script and / or the third circuit verification script, a fourth circuit verification script for executing the simulation circuit operation process of the partitioned circuit will be generated. When running the fourth circuit verification script, the step flow of capturing the actual observation value of the register and calculating the target observation value of the register can be realized.

[0096] In a feasible implementation, step S10 includes steps S11 to S15:

[0097] Step S11, after executing the second circuit verification script and / or the third circuit verification script, and the first circuit verification script, sequentially configure the partition circuit.

[0098] Step S12, executing the fourth circuit verification script, based on the fourth circuit verification script, configuring a number of clocks for the scan clock port in the partition circuit, extracting the register value of each register according to the clock pulse of each clock, and obtaining the actual observed value.

[0099] Step S13, calculating the target observation value according to the reset invalid value configured when executing the second circuit verification script and / or the random value configured when executing the third circuit verification script, and the first scan path report corresponding to the partition circuit.

[0100] When entering the simulation circuit operation process, first execute the second circuit verification script and / or the third circuit verification script, as well as the first circuit verification script, to configure a reset invalid value on the combinational logic corresponding to the multiplexer device, and place a reset invalid value or a random value on the register corresponding to the multiplexer device. Then, use the tessentijtag tool to make an ijtag pattern (graph) for simulation circuit operation. In the ijtag pattern, it is necessary to configure a sequence required for scan dump for the current partition circuit. For example, the sequence is configured to be the source of the reset signal of the DFT control in the partition circuit. First, configure the reset signal switching multiplexer in the partition circuit. After switching it to the DFT control branch, configure the partition circuit to pull up the scan test mode, and then control the partition circuit to enter the scan dump mode.

[0101] After configuring the sequence, the fourth circuit verification script is executed. Based on the fourth circuit verification script, after N clocks are configured for the scan clock port on the partition circuit, the registers included in the partition circuit are observed before the clock pulse corresponding to each clock in each cycle to obtain the actual observation value on each register.

[0102] The target observation value requires the register to be calculated in each cycle according to the reset invalid value configured in the second circuit verification script or the random value configured in the third circuit verification script, combined with the first scan path report. For example, a 0 value is placed in a certain register A. After N cycles of transfer, this 0 value will be transferred to the Nth register downstream of register A, that is, transferred to register B. Therefore, in the Nth cycle, the observation value of register B is the value of the 0 value of register A transferred to register B. According to the first inverter information in the first scan path report, it is determined whether there is an inverter between register A and register B. If there is an inverter between register A and register B, it is considered that the target observation value of register B is 1. If not, it is considered that the target observation value on register B is 0. And so on, the target observation value of each register in each transfer cycle is obtained.

[0103] Step S14, determining whether the actual observed value is equal to the target observed value.

[0104] Step S15: if the actual observed value is equal to the target observed value, a circuit verification result indicating that the partitioned circuit has passed the verification is output.

[0105] After obtaining the actual observation value and target observation value corresponding to each register, the actual observation value and the target observation value belonging to the same register are compared to determine whether the actual observation value is equal to the target observation value. If so, it means that the circuit design of the partition circuit is correct and there is no failure in register value dumping. Therefore, the circuit verification result indicating that the partition circuit has passed the verification will be output at this time.

[0106] If the actual observed value is not equal to the target observed value, it means that there is a design error in the circuit design of the corresponding partition circuit. At this time, a circuit verification result indicating that the partition circuit has failed the verification will be output so that the designer can correct the partition circuit.

[0107] In this embodiment, each partition circuit included in the scan dump circuit is verified to verify whether there is a problem in the circuit design of each partition circuit, thereby ensuring whether the function of each partition circuit can be performed normally.

[0108] Based on the first embodiment of the present application, in the third embodiment of the present application, the same or similar contents as those in the above-mentioned embodiment 1 can be referred to the above introduction, and will not be repeated in the following. Figure 3 Before step S10, the verification method further includes steps B11 to B13:

[0109] Step B11, controlling the scan dump circuit to enter the single chain mode, tracing the scan chain in the scan dump circuit, and obtaining a second scan path report of the scan dump circuit, wherein the second scan path report includes second register information of each register on each scan chain in the scan dump circuit, and second inverter information between each electronic component on each scan chain.

[0110] This embodiment is the second stage verification of the circuit design, which is to verify the overall scan dump circuit to verify whether there are problems in the circuit design of the overall scan dump circuit, that is, to verify whether there are errors in the circuit design of the scan dump circuit, which is conducive to comprehensively verifying the data dump function that can be achieved by the entire scan dump circuit and improving the verification accuracy of the upper-level design of the scan dump circuit.

[0111] First, use the tessent atpg tool to trace the scan chain structure in the entire scan dump circuit.

[0112] Because the scan dump circuit is based on the single chain mode, when tracing the scan chain in the scan dump circuit, the scan dump circuit is first configured to enter the single chain mode, and then each scan chain in the scan dump circuit is traced to obtain a second scan path report that can reflect the scan chain structure. The second scan path report includes the hierarchical information of each register on each scan chain (i.e., the second register information), and the information of whether an inverter is included between each electronic component on the scan chain (i.e., the second inverter information).

[0113] Step B12, use the second preset script to track the reset signal switching circuit to obtain the switching information of the reset signal in the reset signal switching circuit, wherein the switching information includes the third switching information that the reset signal is based on a multi-way reset device to implement the switching operation, and the functional reset source of the multi-way reset device is connected to the combinational logic, and the fourth switching information that the reset signal is based on the multi-way reset device to implement the switching operation, and the functional reset source of the multi-way reset device is connected to the register.

[0114] After the scan chain on the scan dump circuit is traced using the tessent atpg tool in step B11 and the second scan path report is obtained, the second preset script is used to trace the structure of the reset signal switching circuit in the scan dump circuit and save the relevant information. The second preset script is any tracing script that can be used to trace the structure of the reset signal switching circuit in the scan dump circuit.

[0115] Specifically, the reset signal source of the register in the scan dump circuit is the same as the reset signal source of the register in the entire scan dump circuit. There are two sources, one is function control and the other is DFT control. In this step, it is also necessary to start from the reset control TDR and track where the control register is connected.

[0116] ① If it is traced that a reset control TDR is connected to a non-multi-way reset device, it means that the switching of the reset signal output by the function control or DFT control is realized by a non-multi-way reset device. The switching of the reset signal based on the non-multi-way reset device will generate glitches during the switching of the reset signal, which will have a negative impact on the circuit operation of the scan dump circuit. Therefore, after the information is obtained through tracing, the non-multi-way reset devices obtained through tracing will be collected and reported so that the circuit design can be modified after the verification is completed to avoid the defect of the reset control TDR being connected to the non-multi-way reset device. Among them, the non-multi-way reset device in this embodiment refers to a combination device with a multiplexer function composed of some simple logic gates such as AND gates, OR gates, and NOT gates. This combination device will generate glitches during operation.

[0117] ② If it is traced that a reset control TDR is connected to a multi-channel reset device, it means that the switching of the reset signal output by the functional control or DFT control is realized by the multi-channel reset device, then continue to trace the functional control one channel (i.e., the functional reset source) of the output reset signal corresponding to the multi-channel reset device. If it is traced that the functional control one channel is connected to the combinational logic, then record the combinational logic to obtain the third switching information.

[0118] ③ If it is traced that a reset control TDR is connected to a multi-channel reset device, continue to trace the functional control one channel of the output reset signal corresponding to the multi-channel reset device. If it is traced that the functional control one channel is connected to a register, record the register to obtain the fourth switching information.

[0119] Step B13, generating an overall circuit verification script according to the second scan path report and the switching information.

[0120] After obtaining the second scan path report and the corresponding switching information through step B11 and step B12, it is necessary to generate a corresponding overall circuit verification script for verifying the scan dump circuit according to the second scan path report and the corresponding switching information, as described in detail as follows:

[0121] In a feasible implementation manner, step B13 includes steps B14 to B17:

[0122] Step B14: generating a fifth circuit verification script for configuring a reset invalid value for the combinational logic according to the third switching information.

[0123] Step B15, based on the second register information and the fourth switching information, if the register reflected by the second register information is the register reflected by the fourth switching information, a sixth circuit verification script for executing placing a reset invalid value in the register is generated.

[0124] Step B16, based on the second register information and the fourth switching information, if the register reflected by the second register information is not the register reflected by the fourth switching information, generate a seventh circuit verification script for executing placing a random value in the register.

[0125] The script contents of the fifth circuit verification script, the sixth voltage verification script and the seventh circuit verification script in this embodiment are consistent with the script contents of the first circuit verification script, the second circuit verification script and the third circuit verification script, and are all script contents used to configure a reset invalid value for the combinational logic and to place a reset invalid value or a random value in the register.

[0126] Step B17, generating an eighth circuit verification script for executing the capture of the actual observed value of the register and the calculation of the target observed value of the register according to the second register information and the second inverter information.

[0127] Furthermore, after generating the fifth circuit verification script and / or the sixth circuit verification script, and the seventh circuit verification script, an eighth circuit verification script for executing the simulation circuit operation process of the scan dump circuit will be generated. When running the eighth circuit verification script, the step flow of capturing the actual observation value of the register and calculating the target observation value of the register can be realized.

[0128] In a feasible implementation, step S10 includes steps S16 to S110:

[0129] Step S16, after executing the sixth circuit verification script and / or the seventh circuit verification script, and the fifth circuit verification script, sequence configuration is performed on the scan dump circuit.

[0130] Step S17, executing the eighth circuit verification script. Based on the eighth circuit verification script, a number of clocks are configured for the scan clock port in the scan dump circuit. According to the clock pulses of each clock, the register value of each register is extracted to obtain the actual observed value.

[0131] Step S18, based on the reset invalid value placed when executing the sixth circuit verification script and / or the random value placed when executing the seventh circuit verification script, combined with the second inverter information, calculate the transfer value of the random value on the register to the data output port, and determine the transfer value as the target observation value.

[0132] When entering the simulation circuit operation process, first execute the sixth circuit verification script and / or the seventh circuit verification script, as well as the fifth circuit verification script, to configure a reset invalid value on the combinational logic corresponding to the multiplexer device, and place a reset invalid value or a random value on the register corresponding to the multiplexer device. Then, use the tessentijtag tool to make an ijtag pattern for the simulation circuit operation. In the ijtag pattern, it is necessary to configure a sequence required for scan dumping for the scan dump circuit. For example, the sequence is configured to configure the source of the reset signal controlled by DFT in the entire scan dump circuit. First, configure the reset signal switching multiplexer device in the entire scan dump circuit. After switching it to the DFT control branch, configure the entire scan dump circuit to pull up the scan test mode, and then control the entire scan dump circuit to enter the scan dump mode.

[0133] After configuring the sequence, the eighth circuit verification script is executed. Based on the eighth circuit verification script, after configuring N clocks for the scan clock port on the scan dump circuit, before the clock pulse corresponding to each clock of each cycle, the registers included in the scan dump circuit are observed to obtain the actual observation values ​​on each register.

[0134] And because there is a total scan dump interface in the upper layer, the scan dump structure will connect the scan dump link to the upper-layer JTAG TAP controller (a state machine for parsing the JTAG protocol), so the data in the upper layer will be output from the JTAG data output port after the transfer. Therefore, the specific content of the script execution of the eighth circuit verification script is: according to the random value or reset invalid value placed on each register, combined with the second inverter information in the second scan path report, calculate the target observation value of the random value of each register transferred to the data output port during the scan dump transfer process.

[0135] The process of scanning dump transfer is realized by reading commands when Tessent (an EDA tool that can generate Verilog testbench for simulation and verification) does IJTAG pattern, and the comparison between actual observation value and target observation value is also realized by reading commands. Write a series of transfer values ​​calculated into the read command, and Tessent IJTAG pattern simulation will automatically compare these values ​​to realize the comparison between actual observation value and target observation value.

[0136] Step S19, determine whether the actual observation value is equal to the target observation value.

[0137] Step S110 : if the actual observed value is equal to the target observed value, then outputting a circuit verification result indicating that the scan dump circuit verification has passed.

[0138] In this embodiment, the entire scan dump circuit is verified to verify whether there are any problems in the circuit design of the entire scan dump circuit, thereby ensuring the accuracy of the circuit design of the entire scan dump circuit.

[0139] Based on the first embodiment of the present application, in the fourth embodiment of the present application, the same or similar contents as those in the first embodiment can be referred to the above description, and will not be described in detail later. Figure 4 Before step S20, the verification method further includes steps C11 to C12:

[0140] Step C11, tracing the scan chain in the scan dump circuit to obtain a third scan path report of the scan dump circuit, and based on the third scan path report, obtaining a first transfer script for executing random value placement for each register on each scan path in the third scan path report, a second transfer script for collecting register values ​​on each register, and a third transfer script for executing generation of a read command based on the length of the third scan path report.

[0141] In this embodiment, the Paladin emulator can be combined with the Lauterbach (a general embedded debugging tool) trace32 debugger to prepare and verify the correctness of the scan dump sequence required on the evaluation board in advance. The details are as follows:

[0142] Determine the module that needs to be scan dumped on the scan dump circuit, use the Tessent ATPG tool to trace the module, and after obtaining the third scan path report, generate a corresponding transfer script according to the third scan path report, that is, generate a first transfer script for use on the simulator to execute random value placement on the registers on the scan path, generate a second transfer script for use on the simulator to execute the acquisition of register values ​​on each register on the scan path, and a third transfer script that needs to be read in when the Tessent tool makes an IJTAG pattern, and the third transfer script is written as a read command according to the length of the third scan path report.

[0143] Step C12, executing the third transfer script to generate a first operation file for collecting the transfer data transferred to the data output port, and generating a second operation file for shutting down the clock source.

[0144] Before executing the third transfer script, the ijtag network is configured to work in scanning mode, and the working status is consistent with the working status when the third scanning path report is tracked. At this time, the third transfer script is executed to generate a first running file for collecting the transfer data transferred to the data output port, and a second running file for shutting down the clock source is generated.

[0145] In a feasible implementation manner, step S20 includes steps S21 to S24:

[0146] Step S21, execute the first transfer script, based on the first transfer script, place a random value on each register, run the second operation file, based on the second operation file, turn off the clock source, execute the second transfer script, based on the second transfer script, obtain the register value on each register, and obtain the first report value.

[0147] You need to start the emulator first, wait until the system startup of the emulator is completed, and all resets are released. Then execute the first transfer script. Based on the first transfer script, place a random value on each register, run the second run file on trace32, and based on the second run file, stop all clock sources, suspend the system, and then execute the second transfer script. Based on the second transfer script, obtain the register value on each register, and record the register value on each register as the first report value.

[0148] Step S22, run the first running file and enter the scan dump mode. In the scan dump mode, record the transfer data transferred to the data output port, and map the transfer data to the corresponding register according to the third scan path report, calculate the pre-transfer data of the register, and determine the pre-transfer data as the second report value.

[0149] Run the first running file on trace32, configure the jtag network through the JTAG interface to make it enter the scan dump mode, based on the first running file, in the transfer process of the scan dump, trace32 will print the transferred data, at this time it is necessary to record the register value (i.e., transfer data) transferred to the data output port, and map the transfer data on the data output port to the corresponding register according to the third scan path report and the second inverter information in the third scan path report, so as to deduce the pre-transfer data on each register before the scan dump transfer, and determine each calculated pre-transfer data as the second report value.

[0150] Step S23, determining whether the first report value is equal to the second report value.

[0151] Step S24: if the first report value is equal to the second report value, outputting a transfer verification result indicating that the scan dump circuit verification has passed.

[0152] After obtaining the first report value and the second report value corresponding to each register respectively, the first report value and the second report value belonging to the same register are compared to determine whether the first report value is equal to the second report value. If equal, it means that the data dump process based on the scan dump circuit is correct, and there is no phenomenon of register value dump failure. Therefore, the transfer verification result indicating that the scan dump circuit verification has passed will be output at this time.

[0153] If the first report value is not equal to the second report value, it means that the data dump process of the scan dump circuit is wrong. At this time, a circuit verification result indicating that the scan dump circuit has failed verification will be output to avoid debugging failure when the scan dump circuit is put into actual application.

[0154] In this embodiment, the data transfer process of the scan dump circuit is simulated and verified to verify the correctness of the first operation file and the second operation file, ensuring that the value of the transferred register is credible when the data transfer process is simulated and verified on the evaluation board.

[0155] The present application provides a verification device, which includes: at least one processor; and a memory that is communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the verification method in the above-mentioned embodiment one.

[0156] Reference below Figure 5 , which shows a schematic diagram of the structure of a verification device suitable for implementing the embodiment of the present application. The verification device in the embodiment of the present application may include but is not limited to mobile terminals such as laptop computers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 5 The verification device shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0157] like Figure 5As shown, the verification device may include a processing device 1001 (e.g., a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM: Read Only Memory) 1002 or a program loaded from a storage device 1003 to a random access memory (RAM: Random Access Memory) 1004. In RAM1004, various programs and data required for the operation of the verification device are also stored. The processing device 1001, ROM1002, and RAM1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems can be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD: Liquid Crystal Display), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the verification device to communicate with other devices wirelessly or by wire to exchange data. Although the figure shows a verification device with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems can be implemented or have alternatively.

[0158] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0159] The verification device provided by the present application adopts the verification method in the above embodiment, which can solve the technical problem of insufficient early verification of the scan dump circuit and defects in later use. Compared with the prior art, the beneficial effects of the verification device provided by the present application are the same as the beneficial effects of the verification method provided by the above embodiment, and the other technical features in the verification device are the same as the features disclosed in the method of the previous embodiment, which will not be repeated here.

[0160] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0161] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0162] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, computer programs) stored thereon, and the computer-readable program instructions are used to execute the verification method in the above-mentioned embodiment.

[0163] The computer-readable storage medium provided in the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination of the above.

[0164] The computer-readable storage medium may be included in the verification device; or may exist independently without being assembled into the verification device.

[0165] The above-mentioned computer-readable storage medium carries one or more programs. When the above-mentioned one or more programs are executed by the verification device, the verification device: during the simulation circuit operation of the scan dump circuit, obtains the actual observation value of the scan dump circuit, compares the actual observation value with the target observation value, and obtains the circuit verification result; during the simulation transfer process of the scan dump circuit, after recording the first report value of each register in the scan dump circuit, obtains the transfer data transferred through the scan dump circuit, and the second report value when mapped to each register, compares the first report value and the second report value corresponding to each register, and obtains the data dump result.

[0166] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0167] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0168] The modules involved in the embodiments described in this application may be implemented by software or hardware, wherein the name of the module does not constitute a limitation on the unit itself in some cases.

[0169] The readable storage medium provided by the present application is a computer-readable storage medium, which stores computer-readable program instructions (i.e., computer programs) for executing the above-mentioned verification method, and can solve the technical problem of defects in later use caused by insufficient early verification of the scan dump circuit. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided by the present application are the same as the beneficial effects of the verification method provided by the above-mentioned embodiment, and will not be repeated here.

[0170] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A verification method, characterized in that: The verification method is used to verify the scan dump circuit, and the verification method includes: During the simulation circuit operation of the scan dump circuit, obtaining an actual observation value of the scan dump circuit, comparing the actual observation value with a target observation value, and obtaining a circuit verification result; During the simulation transfer process of the scan dump circuit, after recording the first report value of each register in the scan dump circuit, the transfer data transferred through the scan dump circuit is obtained, and the second report value when mapped to each register is obtained, and the first report value and the second report value corresponding to each register are compared to obtain a data dump result.

2. The verification method according to claim 1, characterized in that: The scan dump circuit is composed of a plurality of partition circuits, and the partition circuit includes a reset signal switching circuit. In the case of being in a partition circuit operation stage of the simulation circuit operation process, before the step of obtaining the actual observation value of the scan dump circuit during the simulation circuit operation process of the scan dump circuit, the method includes: Controlling the scan dump circuit to enter a single chain mode, tracing the scan chains in the scan dump circuit, and obtaining a first scan path report of each partition circuit, wherein each first scan path report includes first register information of each register on each scan chain on the partition circuit, and first inverter information between each electronic component on each scan chain; Tracking the reset signal switching circuit using a first preset script to obtain switching information of the reset signal in the reset signal switching circuit, wherein the switching information includes first switching information that the reset signal implements a switching operation based on a multi-way reset device, and a functional reset source of the multi-way reset device is connected to a combinational logic, and second switching information that the reset signal implements a switching operation based on the multi-way reset device, and a functional reset source of the multi-way reset device is connected to the register; A partition circuit verification script is generated according to the first scan path report and the switching information.

3. The verification method according to claim 2, characterized in that: The step of generating a partition circuit verification script according to the first scan path report and the switching information comprises: Generate a first circuit verification script for executing a reset invalid value for configuring the combinational logic according to the first switching information; According to the first register information and the second switching information, if the register reflected by the first register information is the register reflected by the second switching information, generating a second circuit verification script for executing placing a reset invalid value in the register; According to the first register information and the second switching information, if the register reflected by the first register information is not the register reflected by the second switching information, generating a third circuit verification script for executing placing a random value in the register; A fourth circuit verification script is generated based on the first register information and the first inverter information for executing the capture of the actual observed value of the register and the calculation of the target observed value of the register.

4. The verification method according to claim 3, characterized in that: The step of obtaining the actual observed value of the scan dump circuit, comparing the actual observed value with the target observed value, and obtaining the circuit verification result comprises: After executing the second circuit verification script and / or the third circuit verification script, and the first circuit verification script, sequentially configuring the partition circuit; Execute the fourth circuit verification script, configure a plurality of clocks for the scan clock port in the partition circuit based on the fourth circuit verification script, extract the register value of each register according to the clock pulse of each clock, and obtain the actual observation value; The target observation value is calculated according to the reset invalid value configured when executing the second circuit verification script and / or the random value configured when executing the third circuit verification script, and the first scan path report corresponding to the partition circuit; Determine whether the actual observed value is equal to the target observed value; If the actual observed value is equal to the target observed value, a circuit verification result indicating that the partitioned circuit has passed verification is output.

5. The verification method according to claim 1, characterized in that: The scan dump circuit includes a reset signal switching circuit. In the case of being in the overall circuit operation stage of the simulation circuit operation process, before the step of obtaining the actual observation value of the scan dump circuit during the simulation circuit operation process of the scan dump circuit, the method includes: Controlling the scan dump circuit to enter a single chain mode, tracing the scan chains in the scan dump circuit, and obtaining a second scan path report of the scan dump circuit, wherein the second scan path report includes second register information of each register on each scan chain in the scan dump circuit, and second inverter information between each electronic component on each scan chain; Tracking the reset signal switching circuit using a second preset script to obtain switching information of the reset signal in the reset signal switching circuit, wherein the switching information includes third switching information that the reset signal implements a switching operation based on a multi-way reset device, and a functional reset source of the multi-way reset device is connected to a combinational logic, and fourth switching information that the reset signal implements a switching operation based on the multi-way reset device, and a functional reset source of the multi-way reset device is connected to the register; An overall circuit verification script is generated according to the second scan path report and the switching information.

6. The verification method according to claim 5, characterized in that: The step of generating an overall circuit verification script according to the second scan path report and the switching information comprises: generating, according to the third switching information, a fifth circuit verification script for executing configuration of a reset invalid value for the combinational logic; According to the second register information and the fourth switching information, if the register reflected by the second register information is the register reflected by the fourth switching information, a sixth circuit verification script for executing placing a reset invalid value in the register is generated; According to the second register information and the fourth switching information, if the register reflected by the second register information is not the register reflected by the fourth switching information, generating a seventh circuit verification script for executing placing a random value in the register; An eighth circuit verification script is generated based on the second register information and the second inverter information, for executing the capture of the actual observed value of the register and the calculation of the target observed value of the register.

7. The verification method according to claim 6, characterized in that: The step of obtaining the actual observed value of the scan dump circuit, comparing the actual observed value with the target observed value, and obtaining the circuit verification result comprises: After executing the sixth circuit verification script and / or the seventh circuit verification script, and the fifth circuit verification script, sequence configuration is performed on the scan dump circuit; Execute the eighth circuit verification script, configure a plurality of clocks for the scan clock port in the scan dump circuit based on the eighth circuit verification script, extract the register value of each register according to the clock pulse of each clock, and obtain the actual observed value; According to the reset invalid value placed when executing the sixth circuit verification script and / or the random value placed when executing the seventh circuit verification script, combined with the second inverter information, a transfer value of the random value on the register transferred to the data output port is calculated, and the transfer value is determined as the target observation value; Determine whether the actual observed value is equal to the target observed value; If the actual observed value is equal to the target observed value, a circuit verification result indicating that the scan dump circuit verification has passed is output.

8. The verification method according to claim 1, characterized in that: In the simulation transfer process of the scan dump circuit, after recording the first report value of each register in the scan dump circuit and before the step of acquiring the transfer data transferred by the scan dump circuit, the method includes: Tracking the scan chain in the scan dump circuit to obtain a third scan path report of the scan dump circuit, and obtaining, according to the third scan path report, a first transfer script for executing random value placement for each register on each scan path in the third scan path report, a second transfer script for collecting register values ​​on each of the registers, and a third transfer script for executing generation of a read command according to the length of the third scan path report; The third transfer script is executed to generate a first operation file for collecting the transfer data transferred to the data output port, and a second operation file for shutting down the clock source.

9. The verification method according to claim 8, characterized in that: After recording the first report value of each register in the scan dump circuit, obtaining the transfer data transferred by the scan dump circuit, and mapping the second report value to each register, and comparing the first report value and the second report value corresponding to each register to obtain the data dump result, the step includes: Executing the first transfer script, placing the random value on each of the registers based on the first transfer script, executing the second operation file, turning off the clock source based on the second operation file, executing the second transfer script, obtaining the register value on each of the registers based on the second transfer script, and obtaining the first report value; Run the first operation file to enter a scan dump mode, record the transfer data transferred to the data output port in the scan dump mode, map the transfer data to a corresponding register according to the third scan path report, calculate and obtain pre-transfer data of the register, and determine the pre-transfer data as the second report value; determining whether the first reported value is equal to the second reported value; If the first report value is equal to the second report value, a transfer verification result indicating that the scan dump circuit verification has passed is output.

10. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the verification method according to any one of claims 1 to 9 are implemented.

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