Verification method and storage medium

Abstract

The application discloses a verification method and a storage medium, relates to the technical field of scan dump, and discloses a verification method, which comprises the following steps: in the running process of a simulation circuit of a scan dump circuit, acquiring actual observation values of the scan dump circuit, comparing the actual observation values with target observation values, and obtaining a circuit verification result; in the simulation transfer process of the scan dump circuit, recording first report values of all registers in the scan dump circuit, acquiring transfer data transferred out of the scan dump circuit, mapping second report values of the registers when the transfer data is mapped onto the registers, comparing the first report values and the second report values corresponding to the registers, and obtaining a data dump result, so that sufficient verification of the scan dump circuit is realized, and defects existing in later use are avoided.

Description

Technical Field

[0001] This application relates to the field of scanning and dumping technology, and in particular to a verification method and storage medium. Background Technology

[0002] When a system encounters a freeze, we cannot debug it by reading the processor registers normally. However, there is a need to obtain the state of the chip's internal registers to obtain clues for chip debugging. At this time, a scan dump circuit is used to configure the chip to scan dump mode, so that each register inside the chip can be transferred out based on the scan chain to obtain the value of each register inside the chip.

[0003] However, conventional scan dump circuits typically verify whether they can function properly, but do not verify whether there are problems with their circuit design, or whether the values ​​of the registers dumped based on the circuit are reliable. This can lead to dumping errors caused by circuit design during the operation of the scan dump circuit, and data analysis errors caused by using the dumped values ​​during the debugging process. Summary of the Invention

[0004] The main purpose of this application is to provide a verification method and storage medium, which aims to solve the technical problem of insufficient verification in the early stage of scanning and dumping circuits, resulting in defects in later use.

[0005] To achieve the above objectives, this application proposes a verification method, which includes:

[0006] During the simulation circuit operation of the scan dump circuit, the actual observation values ​​of the scan dump circuit are obtained, and the actual observation values ​​are compared with the target observation values ​​to obtain the circuit verification results.

[0007] During the simulation transfer process of the scan-dump circuit, after recording the first report value of each register in the scan-dump circuit, the second report value of the transferred data transferred through the scan-dump circuit and mapped onto each register is obtained. The first report value and the second report value corresponding to each register are compared to obtain the data dump result.

[0008] In one embodiment, the scan dump circuit consists of several partition circuits, each partition circuit including a reset signal switching circuit. When the partition circuit is in the simulation circuit operation phase, prior to the step of acquiring the actual observation value of the scan dump circuit during the simulation circuit operation of the scan dump circuit, the following steps are included:

[0009] The control scan dump circuit enters single-chain mode, and the scan chain in the scan dump circuit is traced to obtain the first scan path report of each partition circuit. Each first scan path report includes the first register information of each register on each scan chain on the corresponding partition circuit, and the first inverter information between each electronic component on each scan chain.

[0010] The first preset script is used to trace the reset signal switching circuit to obtain the switching information of the reset signal in the reset signal switching circuit. The switching information includes the first switching information where the reset signal is switched based on a multi-channel reset device and the functional reset source of the multi-channel reset device is connected to the combinational logic, and the second switching information where the reset signal is switched based on a multi-channel reset device and the functional reset source of the multi-channel reset device is connected to the register.

[0011] Based on the first scan path report and switching information, generate a partition circuit verification script.

[0012] In one embodiment, the step of generating a partition circuit verification script based on a first scan path report and switching information includes:

[0013] Based on the first switching information, generate a first circuit verification script for executing a reset invalid value configured for combinational logic;

[0014] Based on the first register information and the second switching information, if the register reflected by the first register information is the same as the register reflected by the second switching information, then a second circuit verification script is generated to execute the function of placing a reset invalid value in the register.

[0015] Based on the first register information and the second switching information, if the register reflected by the first register information is not the register reflected by the second switching information, a third circuit verification script is generated to execute the function of placing a random value in the register.

[0016] Based on the information from the first register and the first inverter, a fourth circuit verification script is generated to perform the capture of the actual observations of the register and the calculation of the target observations of the register.

[0017] In one embodiment, the steps of obtaining the actual observations of the scan dump circuit and comparing the actual observations with the target observations to obtain the circuit verification results include:

[0018] After executing the second circuit verification script and / or the third circuit verification script, as well as the first circuit verification script, the partition circuit is configured sequentially.

[0019] The fourth circuit verification script is executed. Based on the fourth circuit verification script, several clocks are configured for the scanning clock port in the partition circuit. According to the clock pulse of each clock, the register value of each register is extracted to obtain the actual observation value.

[0020] The target observation value is calculated based on the reset invalid value configured when executing the second circuit verification script and / or the random value configured when executing the third circuit verification script, as well as the first scan path report corresponding to the partition circuit.

[0021] Determine whether the actual observed value is equal to the target observed value;

[0022] If the actual observed value equals the target observed value, then the output represents the circuit verification result indicating that the partition circuit verification has passed.

[0023] In one embodiment, the scan dump circuit includes a reset signal switching circuit. During the overall circuit operation phase of the simulation circuit, prior to the step of acquiring the actual observations of the scan dump circuit during the simulation circuit operation of the scan dump circuit, the following steps are included:

[0024] The control scan dump circuit enters single-chain mode, and the scan chain in the scan dump circuit is traced to obtain the second scan path report of the scan dump circuit. The second scan path report includes the second register information of each register on each scan chain in the scan dump circuit, and the second inverter information between each electronic component on each scan chain.

[0025] The second preset script is used to trace the reset signal switching circuit to obtain the switching information of the reset signal in the reset signal switching circuit. The switching information includes the third switching information where the reset signal is switched based on a multi-channel reset device and the functional reset source of the multi-channel reset device is connected to the combinational logic, and the fourth switching information where the reset signal is switched based on a multi-channel reset device and the functional reset source of the multi-channel reset device is connected to the register.

[0026] Based on the second scan path report and switching information, generate the overall circuit verification script.

[0027] In one embodiment, the step of generating an overall circuit verification script based on the second scan path report and switching information includes:

[0028] Based on the third switching information, a fifth circuit verification script is generated to execute the configuration of a reset invalid value for the combinational logic;

[0029] Based on the second register information and the fourth switching information, if the register reflected by the second register information is the same as the register reflected by the fourth switching information, then a sixth circuit verification script is generated to execute the function of placing an invalid reset value in the register.

[0030] Based on the second register information and the fourth switching information, if the register reflected by the second register information is not the register reflected by the fourth switching information, then a seventh circuit verification script is generated to execute the function of placing a random value in the register.

[0031] Based on the information from the second register and the second inverter, an eighth circuit verification script is generated to perform the capture of the actual observations of the register and the calculation of the target observations of the register.

[0032] In one embodiment, the steps of obtaining the actual observations of the scan dump circuit and comparing the actual observations with the target observations to obtain the circuit verification results include:

[0033] After executing the sixth circuit verification script and / or the seventh circuit verification script, as well as the fifth circuit verification script, the scan dump circuit is sequentially configured.

[0034] The eighth circuit verification script is executed. Based on the eighth circuit verification script, several clocks are configured for the scan clock port in the scan dump circuit. According to the clock pulse of each clock, the register values ​​of each register are extracted to obtain the actual observation values.

[0035] Based on the invalid reset value placed when executing the sixth circuit verification script and / or the random value placed when executing the seventh circuit verification script, combined with the second inverter information, the transfer value from the random value on the register to the data output port is calculated, and the transfer value is determined as the target observation value.

[0036] Determine whether the actual observed value is equal to the target observed value;

[0037] If the actual observed value equals the target observed value, the output indicates that the circuit verification result represents the successful verification of the scan dump circuit.

[0038] In one embodiment, before the step of obtaining the transfer data transferred through the scan dump circuit after recording the first report value of each register in the scan dump circuit during the simulation transfer process of the scan dump circuit, the following steps are included:

[0039] The scan chain in the scan dump circuit is traced to obtain the third scan path report of the scan dump circuit. Based on the third scan path report, a first transfer script is obtained to randomly place a value in each register on each scan path in the third scan path report, a second transfer script is obtained to collect the register value on each register, and a third transfer script is obtained to generate a read command based on the length of the third scan path report.

[0040] Execute the third transfer script to generate a first run file for acquiring the transferred data on the data output port, and a second run file for shutting down the clock source.

[0041] In one embodiment, the steps of recording the first report value of each register in the scan dump circuit, obtaining the second report value of the transferred data mapped to each register after passing through the scan dump circuit, and comparing the first report value and the second report value corresponding to each register to obtain the data dump result include:

[0042] Execute the first transfer script, and based on the first transfer script, place random values ​​in each register, then run the second run file, and based on the second run file, turn off the clock source, execute the second transfer script, and based on the second transfer script, obtain the register values ​​in each register to get the first report value;

[0043] Run the first executable file to enter the scan dump mode. In the scan dump mode, record the transfer data transferred to the data output port, and map the transfer data to the corresponding register according to the third scan path report. Calculate the data of the register before transfer and determine the data before transfer as the second report value.

[0044] Determine if the first report value is equal to the second report value;

[0045] If the first report value equals the second report value, then the transfer verification result indicating that the scan dump circuit has passed verification is output.

[0046] In addition, to achieve the above objectives, this application also proposes a verification device, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the verification method as described above.

[0047] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and which, when executed by a processor, implements the steps of the verification method described above.

[0048] One or more technical solutions proposed in this application have at least the following technical effects:

[0049] A verification method for verifying scan dump circuits is proposed, the verification method comprising:

[0050] During the simulation operation of the scan dump circuit, the actual observation values ​​of the scan dump circuit are acquired. The actual observation values ​​are compared with the target observation values ​​to obtain the circuit verification results. Based on the circuit verification results, the circuit design verification results of the scan dump circuit are determined, and the result of whether the circuit design of the scan dump circuit will result in a dumping error is obtained. In addition, during the simulation transfer process of the scan dump circuit, after recording the first report value of each register in the scan dump circuit, the second report value when the transferred data transferred through the scan dump circuit is mapped to each register is obtained. The first report value and the second report value corresponding to each register are compared to obtain the data dump result. Based on the data dump result, the credibility result of the register values ​​transferred from the scan dump circuit is determined, and the phenomenon of whether the register values ​​transferred from the scan dump circuit will cause errors in the later debugging results is obtained. This achieves full verification of the scan dump circuit and avoids defects in later use. Attached Figure Description

[0051] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0052] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 This is a flowchart illustrating the verification method of this application in Embodiment 1.

[0054] Figure 2 This is a flowchart illustrating Embodiment 2 of the verification method of this application;

[0055] Figure 3 This is a flowchart illustrating Embodiment 3 of the verification method of this application;

[0056] Figure 4 This is a flowchart illustrating Embodiment 4 of the verification method of this application;

[0057] Figure 5 This is a schematic diagram of the device structure of the hardware operating environment involved in the verification method in this application embodiment.

[0058] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0059] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0060] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0061] The main solution of this application embodiment is as follows: during the simulation circuit operation of the scan dump circuit, the actual observation value of the scan dump circuit is obtained, and the actual observation value is compared with the target observation value to obtain the circuit verification result; during the simulation transfer process of the scan dump circuit, after recording the first report value of each register in the scan dump circuit, the transfer data transferred through the scan dump circuit is obtained, and the second report value is mapped to each register. The first report value and the second report value corresponding to each register are compared to obtain the data dump result.

[0062] Because conventional scan dump circuits are generally verified to function properly, but not to have problems with their circuit design or the reliability of the values ​​of the registers dumped based on the circuit, there are dumping errors caused by circuit design during the operation of the scan dump circuit, and data analysis errors caused by the dumped values ​​being used in the debugging process.

[0063] This application provides a solution to achieve full verification of the scan dump circuit and avoid defects that may exist in later use.

[0064] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device or verification device capable of performing the above functions. The following description uses a verification device as an example to illustrate this embodiment and the subsequent embodiments.

[0065] Based on this, the embodiments of this application provide a verification method, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the verification method of this application.

[0066] In this embodiment, the verification method includes steps S10 to S20:

[0067] Step S10: During the simulation circuit operation of the scan dump circuit, the actual observation value of the scan dump circuit is obtained, and the actual observation value is compared with the target observation value to obtain the circuit verification result.

[0068] It should be noted that the scan dump circuit is a DFT (Design for Test) scan chain designed for circuit debugging. Therefore, the accuracy of the scan dump circuit affects the subsequent debugging process, and the accuracy of the scan dump circuit is directly related to its circuit design.

[0069] Therefore, to ensure the accuracy of subsequent debugging procedures, this embodiment proposes to simulate the circuit operation of the scan-dump circuit, obtain the actual observed values ​​during the simulated circuit operation, and obtain the target observed values ​​during the circuit operation. The actual observed values ​​are compared with the target observed values, and the circuit verification results are obtained based on the comparison results. If the actual observed values ​​are consistent with the target observed values, it indicates that the actual operating state of the scan-dump circuit is consistent with the target operating state, meaning that the circuit design of the scan-dump circuit will not cause the register value dumping failure phenomenon.

[0070] The simulation circuit operation can be implemented using the Paladin simulator, which enables rapid functional verification of the circuit through scanning and dumping. In actual verification processes, other types of simulators can also be used.

[0071] Step S20: During the simulation transfer process of the scan dump circuit, after recording the first report value of each register in the scan dump circuit, obtain the second report value of the transfer data transferred through the scan dump circuit and mapped to each register, compare the first report value and the second report value corresponding to each register, and obtain the data dump result.

[0072] Furthermore, the accuracy of the scan dump circuit is directly related to the dump process (i.e., the transfer process) of the scan dump circuit. Therefore, in order to ensure the accuracy of the subsequent debugging process, this embodiment proposes to simulate the transfer process of the scan dump circuit, obtain the first report value transferred to the register during the actual data transfer process, and obtain the second report value transferred to the register during the ideal data transfer process. The first report value and the second report value are compared, and the data dump result is obtained according to the comparison result. If the first report value and the second report value are consistent, it means that the actual data transfer accuracy of the scan dump circuit is consistent with the target data transfer accuracy. That is, the data dump operation of the scan dump circuit can guarantee the accuracy of data dump and will not cause data dump errors or omissions.

[0073] In this embodiment, during the simulation circuit operation of the scan dump circuit, the actual observation values ​​of the scan dump circuit are obtained. The actual observation values ​​are compared with the target observation values ​​to obtain the circuit verification results. Based on the circuit verification results, the circuit design verification results of the scan dump circuit are determined, and the result of whether the circuit design of the scan dump circuit will result in a dumping error is obtained. In addition, during the simulation transfer process of the scan dump circuit, after recording the first report value of each register in the scan dump circuit, the second report value when the transfer data transferred through the scan dump circuit is mapped to each register is obtained. The first report value and the second report value corresponding to each register are compared to obtain the data dumping result. Based on the data dumping result, the credibility result of the register values ​​transferred from the scan dump circuit is determined, and the phenomenon of whether the register values ​​transferred from the scan dump circuit will cause errors in the later debugging results is obtained. This achieves full verification of the scan dump circuit and avoids defects in later use.

[0074] Based on the first embodiment of this application, in the second embodiment of this application, the content that is the same as or similar to that in the first embodiment described above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 2 Before step S10, the verification method further includes steps A11 to A13:

[0075] Step A11: Control the scan dump circuit to enter single-chain mode, track the scan chain in the scan dump circuit, and obtain the first scan path report of each partition circuit. Each first scan path report includes the first register information of each register on each scan chain of the corresponding partition circuit, and the first inverter information between each electronic component on each scan chain.

[0076] It should be noted that, in order to ensure the accuracy of the circuit design verification results of the scan dump circuit, a phased verification of the circuit design is proposed. The first phase of verification is the one in this embodiment, which involves verifying several partition circuits that make up the scan dump circuit. This verifies whether there are any problems with the circuit design of a single partition circuit, avoiding the incomplete verification that can occur when only the entire scan dump circuit is verified. Verifying the circuit design of each partition circuit included in the scan dump circuit separately is beneficial for comprehensively verifying the functions of each partition circuit and improving the verification accuracy of the underlying design of the scan dump circuit.

[0077] First, the scan chain structure in the partitioned circuit is traced using the tessent atpg tool (an automated test vector generation tool).

[0078] Because the scan dump circuit is based on single-chain mode, when tracing the scan chains in each partition circuit, the partition circuit is first configured to enter single-chain mode before tracing each scan chain in the partition circuit to obtain a first scan path report that reflects the scan chain structure. The first scan path report corresponding to each partition circuit includes the hierarchical information of each register on each scan chain (i.e., first register information) and information on whether there is an inverter between each electronic component on the scan chain (i.e., first inverter information).

[0079] In the actual verification process, other types of ATPG tools can also be used to trace the scan chain structure.

[0080] Step A12: Use the first preset script to trace the reset signal switching circuit and obtain the switching information of the reset signal in the reset signal switching circuit. The switching information includes the first switching information where the reset signal is switched based on a multi-channel reset device and the functional reset source of the multi-channel reset device is connected to the combinational logic, and the second switching information where the reset signal is switched based on a multi-channel reset device and the functional reset source of the multi-channel reset device is connected to the register.

[0081] After tracing the scan chain on the partition circuit using the tessent atpg tool in step A11 and obtaining the first scan path report, the structure of the reset signal switching circuit in the partition circuit is then traced using a first preset script, and relevant information is saved. The first preset script can be any tracing script that can be used to trace the structure of the reset signal switching circuit in the partition circuit.

[0082] Specifically, the reset signal of the register in the partition circuit has two sources: one is the function control and the other is the DFT control. The reset signal output by the function control and the reset signal output by the DFT control are switched by manipulating the configuration of the control register through the DFT control. Therefore, in this step, it is necessary to start from the reset control TDR (Test Data Register) and trace where the control register is connected.

[0083] ① If a reset control TDR is found to be connected to a non-multiplexed reset device, it indicates that the switching of the reset signal output by the function control or DFT control is implemented through a non-multiplexed reset device. Switching of the reset signal based on a non-multiplexed reset device will generate glitches during the reset signal switching process, negatively impacting the operation of the partition circuit. Therefore, after this information is obtained, the traced non-multiplexed reset devices will be collected and reported so that the circuit design can be modified after verification to avoid the defects of the reset control TDR being connected to a non-multiplexed reset device. In this embodiment, the non-multiplexed reset device refers to a combination device with multiplexer function composed of simple logic gates such as AND gates, OR gates, and NOT gates. This type of combination device will generate glitches during operation.

[0084] ② If it is found that a certain reset control TDR is connected to a multi-channel reset device, it means that the switching of the reset signal output by the function control or DFT control is realized through the multi-channel reset device. Then continue to trace the function control channel (i.e., function reset source) of the output reset signal corresponding to the multi-channel reset device. If it is found that the function control channel is connected to the combinational logic, then record the combinational logic and obtain the first switching information.

[0085] ③ If it is found that a certain reset control TDR is connected to a multi-channel reset device, then continue to trace the function control channel of the output reset signal corresponding to the multi-channel reset device. If it is found that the function control channel is connected to a register, then record the register and obtain the second switching information.

[0086] Step A13: Generate a partition circuit verification script based on the first scan path report and switching information.

[0087] After obtaining the first scan path report and corresponding switching information through steps A11 and A12, it is now necessary to generate a corresponding partition circuit verification script to verify the partition circuit based on the first scan path report and corresponding switching information, as detailed below:

[0088] In one feasible implementation, step A13 may include steps A14 to A17:

[0089] Step A14: Based on the first switching information, generate a first circuit verification script for executing a reset invalid value configured for combinational logic.

[0090] Step A15: Based on the first register information and the second switching information, if the register reflected by the first register information is the same as the register reflected by the second switching information, then generate a second circuit verification script for executing the function of placing a reset invalid value in the register.

[0091] Step A16: Based on the first register information and the second switching information, if the register reflected by the first register information is not the same as the register reflected by the second switching information, then generate a third circuit verification script for executing the function of placing a random value in the register.

[0092] In order to ensure that the registers driven by the multiplexed device are in a reset invalid state before switching to the reset source controlled by the DFT, so that random values ​​can be placed in the registers driven by the multiplexed device and the placed random values ​​are not reset to 0, a first circuit verification script is generated to execute the configuration of a reset invalid value for the combinational logic.

[0093] At this point, based on the first register information and the second switching information, it is determined whether the register to which the first register information belongs is the same register as the register to which the function reset source in the second switching information is connected. If so, a second circuit verification script is generated to execute the function of placing an invalid reset value in the register. If not, a third circuit verification script is generated to execute the function of placing a random value in the register.

[0094] Step A17: Based on the first register information and the first inverter information, generate a fourth circuit verification script for performing the capture of the actual observation value of the register and the calculation of the target observation value of the register.

[0095] Furthermore, after generating the first circuit verification script, the second circuit verification script, and / or the third circuit verification script, a fourth circuit verification script will be generated to execute the simulation circuit operation process of the partitioned circuit. When running the fourth circuit verification script, the steps of capturing the actual observation value of the register and calculating the target observation value of the register can be realized.

[0096] In one feasible implementation, step S10 includes steps S11 to S15:

[0097] Step S11: After executing the second circuit verification script and / or the third circuit verification script, as well as the first circuit verification script, perform sequence configuration of the partitioned circuits.

[0098] Step S12: Execute the fourth circuit verification script. Based on the fourth circuit verification script, configure several clocks for the scanning clock port in the partition circuit. According to the clock pulse of each clock, extract the register value of each register to obtain the actual observation value.

[0099] Step S13: Calculate the target observation value based on the reset invalid value configured when executing the second circuit verification script and / or the random value configured when executing the third circuit verification script, as well as the first scan path report corresponding to the partition circuit.

[0100] When entering the simulation circuit operation process, the second circuit verification script and / or the third circuit verification script, as well as the first circuit verification script, are executed first to configure an invalid reset value on the combinational logic corresponding to the multiplexer and to place an invalid reset value or a random value on the register corresponding to the multiplexer. Then, the tessentijtag tool is used to create an ijtag pattern for the simulation circuit operation. In the ijtag pattern, a sequence required for scanning and dumping needs to be configured for the current partition circuit. For example, the sequence is configured to be the source of the reset signal controlled by DFT in the partition circuit. First, the reset signal in the partition circuit is configured to switch the multiplexer to the DFT control branch. Then, the partition circuit is configured to pull up the scan test mode and then the partition circuit is controlled to enter the scan dump mode.

[0101] After configuring the sequence, the fourth circuit verification script is executed. Based on the fourth circuit verification script, N clocks are configured for the scan clock port on the partition circuit. Before the clock pulse corresponding to each clock in each cycle, the registers included in the partition circuit are observed to obtain the actual observed values ​​on each register.

[0102] The target observation value needs to be calculated in each cycle based on the reset invalid value configured in the second circuit verification script or the random value configured in the third circuit verification script, combined with the first scan path report. For example, if a value of 0 is placed in a register A, this 0 value will be transferred to the Nth register downstream of register A after N cycles, i.e., to register B. Therefore, in the Nth cycle, the observation value of register B is the value of the 0 value in register A transferred to register B. Based on the first inverter information in the first scan path report, it is determined whether there is an inverter between register A and register B. If there is an inverter between register A and register B, the target observation value of register B is considered to be 1; if not, the target observation value of register B is considered to be 0. This process is repeated to obtain the target observation value of each register in each transfer cycle.

[0103] Step S14: Determine whether the actual observed value is equal to the target observed value.

[0104] Step S15: If the actual observed value is equal to the target observed value, output the circuit verification result indicating that the partition circuit verification has passed.

[0105] After obtaining the actual and target observation values ​​corresponding to each register, the actual and target observation values ​​belonging to the same register are compared to determine whether the actual observation value is equal to the target observation value. If they are equal, it means that the circuit design of the partition circuit is correct and there is no failure to dump the register value. Therefore, the circuit verification result indicating that the partition circuit has passed the verification will be output at this time.

[0106] If the actual observed value is not equal to the target observed value, it indicates that there is a design error in the circuit design of the corresponding partition circuit. In this case, a circuit verification result indicating that the partition circuit has failed verification will be output so that the designer can correct the partition circuit.

[0107] In this embodiment, the circuit design of each partition circuit is verified by verifying the circuit of each partition circuit, thereby ensuring that the function of each partition circuit can be performed normally.

[0108] Based on the first embodiment of this application, in the third embodiment of this application, the content that is the same as or similar to that in the first embodiment described above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 3 Before step S10, the verification method further includes steps B11 to B13:

[0109] Step B11: Control the scan dump circuit to enter single-chain mode, trace the scan chain in the scan dump circuit, and obtain the second scan path report of the scan dump circuit. The second scan path report includes the second register information of each register on each scan chain of the scan dump circuit, and the second inverter information between each electronic component on each scan chain.

[0110] This embodiment is the second stage of verification for the circuit design, which verifies the overall scan and dump circuit to check for problems in the overall circuit design, i.e., to check for errors in the circuit design of the scan and dump circuit. This is beneficial for comprehensively verifying the data dumping function that the entire scan and dump circuit can achieve, and improving the verification accuracy of the upper-level design of the scan and dump circuit.

[0111] First, the scan chain structure in the entire scan dump circuit was traced using the tessent atpg tool.

[0112] Because the scan dump circuit is based on single-chain mode, when tracing the scan chains in the scan dump circuit, the scan dump circuit is first configured to enter single-chain mode before tracing each scan chain in the scan dump circuit to obtain a second scan path report that reflects the scan chain structure. This second scan path report includes the hierarchical information of each register on each scan chain (i.e., second register information) and information on whether there is an inverter between each electronic component on the scan chain (i.e., second inverter information).

[0113] Step B12: Use the second preset script to trace the reset signal switching circuit and obtain the switching information of the reset signal in the reset signal switching circuit. The switching information includes the third switching information where the reset signal is switched based on a multi-channel reset device and the functional reset source of the multi-channel reset device is connected to the combinational logic, and the fourth switching information where the reset signal is switched based on a multi-channel reset device and the functional reset source of the multi-channel reset device is connected to the register.

[0114] After tracing the scan chain on the scan dump circuit using the tessent atpg tool in step B11 and obtaining the second scan path report, the second preset script is then used to trace the structure of the reset signal switching circuit in the scan dump circuit and save the relevant information. The second preset script can be any tracing script that can be used to trace the structure of the reset signal switching circuit in the scan dump circuit.

[0115] Specifically, the reset signal source for the registers in the scan dump circuit is the same as the reset signal source for the registers in the entire scan dump circuit, both having two sources: one is function control and the other is DFT control. In this step, it is also necessary to start from the reset control TDR and trace where the control register is connected.

[0116] ① If a reset control TDR is found to be connected to a non-multiplexed reset device, it indicates that the switching of the reset signal output by the function control or DFT control is implemented through a non-multiplexed reset device. Switching of the reset signal based on a non-multiplexed reset device will generate glitches during the reset signal switching process, negatively impacting the operation of the scan dump circuit. Therefore, after this information is obtained, the traced non-multiplexed reset devices will be collected and reported so that the circuit design can be modified after verification to avoid the defects of the reset control TDR being connected to a non-multiplexed reset device. In this embodiment, the non-multiplexed reset device refers to a combination device with multiplexer function composed of simple logic gates such as AND gates, OR gates, and NOT gates. This type of combination device will generate glitches during operation.

[0117] ② If it is found that a certain reset control TDR is connected to a multi-channel reset device, it means that the switching of the reset signal output by the function control or DFT control is realized through the multi-channel reset device. Then continue to trace the function control channel (i.e., function reset source) of the output reset signal corresponding to the multi-channel reset device. If it is found that the function control channel is connected to the combinational logic, then record the combinational logic and obtain the third switching information.

[0118] ③ If it is found that a certain reset control TDR is connected to a multi-channel reset device, then continue to trace the function control channel of the output reset signal corresponding to the multi-channel reset device. If it is found that the function control channel is connected to a register, then record the register and obtain the fourth switching information.

[0119] Step B13: Generate the overall circuit verification script based on the second scan path report and switching information.

[0120] After obtaining the second scan path report and corresponding switching information through steps B11 and B12, it is necessary to generate a corresponding overall circuit verification script for verifying the scan dump circuit based on the second scan path report and corresponding switching information, as detailed below:

[0121] In one feasible implementation, step B13 includes steps B14 to B17:

[0122] Step B14: Based on the third switching information, generate a fifth circuit verification script for executing a reset invalid value configured for combinational logic.

[0123] Step B15: Based on the second register information and the fourth switching information, if the register reflected by the second register information is the same as the register reflected by the fourth switching information, then generate a sixth circuit verification script to execute the function of placing a reset invalid value in the register.

[0124] Step B16: Based on the second register information and the fourth switching information, if the register reflected by the second register information is not the same as the register reflected by the fourth switching information, then generate a seventh circuit verification script for executing the function of placing a random value in the register.

[0125] The script content of the fifth circuit verification script, the sixth voltage verification script, and the seventh circuit verification script in this embodiment is the same as the script content of the first circuit verification script, the second circuit verification script, and the third circuit verification script. They are all used to execute script content to configure a reset invalid value for combinational logic and to place a reset invalid value or a random value in the register.

[0126] Step B17: Based on the second register information and the second inverter information, generate an eighth circuit verification script for performing the capture of the actual observation value of the register and the calculation of the target observation value of the register.

[0127] Furthermore, after generating the fifth and / or sixth circuit verification scripts, as well as the seventh circuit verification script, an eighth circuit verification script will be generated to execute the simulation circuit operation process of the scan dump circuit. When the eighth circuit verification script is run, the steps of capturing the actual observation value of the register and calculating the target observation value of the register can be realized.

[0128] In one feasible implementation, step S10 includes steps S16 to S110:

[0129] Step S16: After executing the sixth circuit verification script and / or the seventh circuit verification script, as well as the fifth circuit verification script, perform sequence configuration on the scan dump circuit.

[0130] Step S17: Execute the eighth circuit verification script. Based on the eighth circuit verification script, configure several clocks for the scan clock port in the scan dump circuit. According to the clock pulse of each clock, extract the register value of each register to obtain the actual observation value.

[0131] Step S18: Based on the invalid reset value placed when executing the sixth circuit verification script and / or the random value placed when executing the seventh circuit verification script, and combined with the information of the second inverter, calculate the transfer value from the random value on the register to the data output port, and determine the transfer value as the target observation value.

[0132] When entering the simulation circuit operation process, the sixth circuit verification script and / or the seventh circuit verification script, as well as the fifth circuit verification script, are executed first to configure an invalid reset value on the combinational logic corresponding to the multiplexer and to place an invalid reset value or a random value on the register corresponding to the multiplexer. Then, the tessentijtag tool is used to create an ijtag pattern for the simulation circuit operation. In the ijtag pattern, a sequence required for scanning and dumping needs to be configured for the scan dump circuit. For example, the sequence is configured to configure the source of the reset signal controlled by DFT in the entire scan dump circuit. First, the reset signal in the entire scan dump circuit is configured to switch the multiplexer to the DFT control branch. Then, the entire scan dump circuit is configured to pull up the scan test mode and then the entire scan dump circuit is controlled to enter the scan dump mode.

[0133] After configuring the sequence, the eighth circuit verification script is executed. Based on the eighth circuit verification script, N clocks are configured for the scan clock port on the scan dump circuit. Before the clock pulse corresponding to each clock in each cycle, the registers included in the scan dump circuit are observed to obtain the actual observed values ​​on each register.

[0134] Because there is a general scan dump interface in the upper layer, the scan dump structure will link the scan dump to the upper-layer JTAG TAP controller (a state machine used to parse the JTAG protocol). Therefore, the data in the upper layer will be output from the JTAG data output port after the transfer. Thus, the specific content of the script execution of the eighth circuit verification script is as follows: based on the random value or reset invalid value placed on each register, combined with the second inverter information in the second scan path report, calculate the target observation value transferred from the random value of each register to the data output port during the scan dump transfer process.

[0135] The process of scanning and dumping is implemented through read commands when performing ijtag patterning using Tessent (an EDA tool that generates Verilog Testbench for simulation verification). The comparison between actual and target observations is also achieved through read commands. A series of calculated transition values ​​are written to the read command, and during the Tessent ijtag pattern simulation, these values ​​are automatically compared to achieve the comparison between actual and target observations.

[0136] Step S19: Determine whether the actual observed value is equal to the target observed value.

[0137] Step S110: If the actual observed value is equal to the target observed value, output the circuit verification result indicating that the scan dump circuit has passed verification.

[0138] In this embodiment, the overall scan and dump circuit is verified to check whether there are any problems with the circuit design of the overall scan and dump circuit, thereby ensuring the accuracy of the overall scan and dump circuit design.

[0139] Based on the first embodiment of this application, in the fourth embodiment of this application, the content that is the same as or similar to that in the first embodiment described above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 4 Before step S20, the verification method further includes steps C11 to C12:

[0140] Step C11: Trace the scan chain in the scan dump circuit to obtain the third scan path report of the scan dump circuit. Based on the third scan path report, obtain the first transfer script for randomly placing a value in each register on each scan path in the third scan path report, the second transfer script for collecting the register value in each register, and the third transfer script for generating a read command based on the length of the third scan path report.

[0141] In this embodiment, the Paladin emulator, combined with the Lauterbach (a general-purpose embedded debugging tool) and Trace32 debugger, can be used to prepare and verify the correctness of the scan dump sequence required for the evaluation board in advance. Specifically, as follows:

[0142] Identify the modules on the scan dump circuit that require scan dumping. Use the tessent atpg tool to trace these modules and obtain the third scan path report. Based on the third scan path report, generate the corresponding transfer scripts. Specifically, generate a first transfer script for use on the simulator to randomly place values ​​in the registers along the scan path, a second transfer script for use on the simulator to collect the register values ​​of each register along the scan path, and a third transfer script that needs to be read when the tessent tool performs ijtag patterning. This third transfer script is written as a read command based on the length of the third scan path report.

[0143] Step C12: Execute the third transfer script to generate a first run file for acquiring the transferred data on the data output port and a second run file for shutting down the clock source.

[0144] Before executing the third transfer script, the ijtag network is configured to work in scan mode, with the working state consistent with the working state when the third scan path report is obtained. At this time, the third transfer script is executed, generating a first run file for collecting the transferred data on the data output port and a second run file for shutting down the clock source.

[0145] In one feasible implementation, step S20 includes steps S21 to S24:

[0146] Step S21: Execute the first transfer script. Based on the first transfer script, place random values ​​in each register and run the second run file. Based on the second run file, turn off the clock source and execute the second transfer script. Based on the second transfer script, obtain the register values ​​in each register and obtain the first report value.

[0147] The emulator must be started first. After the emulator system has finished booting and all resets have been released, the first transfer script is executed. Based on the first transfer script, a random value is placed in each register. Then, the second run file is run on trace32. Based on the second run file, all clock sources are stopped, and the system is paused. Then, the second transfer script is executed. Based on the second transfer script, the register value in each register is obtained, and the register value in each register is recorded as the first report value.

[0148] Step S22: Run the first running file and enter the scan dump mode. In the scan dump mode, record the transfer data transferred to the data output port, and map the transfer data to the corresponding register according to the third scan path report. Calculate the data before transfer in the register and determine the data before transfer as the second report value.

[0149] Run the first executable file on trace32 and configure the JTAG network through the JTAG interface to enter scan dump mode. Based on the first executable file, during the scan dump transfer process, trace32 will print the transferred data. At this time, it is necessary to record the register values ​​(i.e., the transferred data) on the data output port. According to the third scan path report and the second inverter information in the third scan path report, the transferred data on the data output port is mapped to the corresponding register. In this way, the data before the transfer in each register before the scan dump transfer is calculated, and each calculated data before the transfer is determined as the second report value.

[0150] Step S23: Determine whether the first report value is equal to the second report value.

[0151] Step S24: If the first report value is equal to the second report value, output the transfer verification result indicating that the scan dump circuit has passed verification.

[0152] After obtaining the first report value and the second report value corresponding to each register, the first report value and the second report value belonging to the same register are compared to determine whether the first report value is equal to the second report value. If they are equal, it means that the data dumping process based on the scan dump circuit is correct and there is no failure to dump the register value. Therefore, at this time, the transfer verification result indicating that the scan dump circuit has passed the verification will be output.

[0153] If the first report value is not equal to the second report value, it indicates that the data dumping process of the scan dump circuit is incorrect. At this time, a circuit verification result indicating that the scan dump circuit verification has failed will be output to avoid the debugging failure that may occur when the scan dump circuit is put into actual application.

[0154] In this embodiment, the data transfer process of the scan dump circuit is simulated and verified to verify the correctness of the first and second running files, ensuring that the transferred register values ​​are reliable when the data transfer process is simulated and verified on the evaluation board.

[0155] This application provides a verification device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, which are executed by the at least one processor to enable the at least one processor to perform the verification method in Embodiment 1 above.

[0156] The following is for reference. Figure 5 The diagram illustrates a structural schematic of a verification device suitable for implementing embodiments of this application. The verification device in these embodiments may include, but is not limited to, mobile terminals such as laptops, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), and in-vehicle terminals (e.g., in-vehicle navigation terminals), as well as fixed terminals such as digital TVs and desktop computers. Figure 5 The verification device shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0157] like Figure 5As shown, the verification device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the verification device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, a touchscreen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 1003 including, for example, magnetic tape, hard disk, etc.; and communication devices 1009. Communication device 1009 allows the verification device to communicate wirelessly or wiredly with other devices to exchange data. While the figures show verification devices with various systems, it should be understood that implementation or possession of all the systems shown is not required. More or fewer systems may be implemented alternatively.

[0158] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0159] The verification device provided in this application, employing the verification method described in the above embodiments, can solve the technical problem of insufficient early-stage verification of the scan and dump circuit, leading to defects in later use. Compared with the prior art, the beneficial effects of the verification device provided in this application are the same as those of the verification method provided in the above embodiments, and other technical features of this verification device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0160] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0161] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0162] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the verification method in the above embodiments.

[0163] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0164] The aforementioned computer-readable storage medium may be included in the verification device or may exist independently without being assembled into the verification device.

[0165] The aforementioned computer-readable storage medium carries one or more programs. When the aforementioned one or more programs are executed by the verification device, the verification device: during the simulation circuit operation of the scan-dump circuit, acquires the actual observation value of the scan-dump circuit, compares the actual observation value with the target observation value, and obtains the circuit verification result; during the simulation transfer process of the scan-dump circuit, after recording the first report value of each register in the scan-dump circuit, acquires the second report value when the transfer data transferred through the scan-dump circuit is mapped onto each register, compares the first report value and the second report value corresponding to each register, and obtains the data dump result.

[0166] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0167] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0168] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0169] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described verification method. This solves the technical problem of insufficient early-stage verification of the scan dump circuit, leading to defects in later use. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the verification method provided in the above embodiments, and will not be repeated here.

[0170] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A method of verification, characterized by, The verification method is used for verifying a scan dump circuit, and the verification method comprises: During a simulation circuit running process of the scan dump circuit, an actual observation value of the scan dump circuit is acquired, the actual observation value is compared with a target observation value, and a circuit verification result is obtained; During a simulation transfer process of the scan dump circuit, after a first report value of each register in the scan dump circuit is recorded, a second report value of each register when transfer data transferred out through the scan dump circuit is mapped onto the register is acquired, the first report value and the second report value of each register are compared, and a data dump result is obtained; Before the step of acquiring the second report value of each register when the transfer data transferred out through the scan dump circuit is mapped onto the register after the first report value of each register in the scan dump circuit is recorded during the simulation transfer process of the scan dump circuit, the step comprises: A scan chain in the scan dump circuit is tracked, a third scan path report of the scan dump circuit is obtained, and according to the third scan path report, a first transfer script for performing random value placement on each register on each scan path in the third scan path report, a second transfer script for collecting register values on each register, and a third transfer script for generating a read command according to a length of the third scan path report are obtained; The third transfer script is executed, a first running file for running collection of transfer data on a data output port is generated, and a second running file for running closing of a clock source is generated.

2. The authentication method of claim 1, wherein, The scan dump circuit is composed of a plurality of partition circuits, the partition circuit comprises a reset signal switching circuit, before the step of acquiring the actual observation value of the scan dump circuit during the simulation circuit running process of the scan dump circuit in a case where the partition circuit is in a partition circuit running stage of the simulation circuit running process, the step comprises: The scan dump circuit is controlled to enter a single-chain mode, a scan chain in the scan dump circuit is tracked, and a first scan path report of each partition circuit is obtained, wherein each first scan path report comprises first register information of each register on each scan chain on the partition circuit and first inverter information between each electronic element on each scan chain; The reset signal switching circuit is tracked using a first preset script to obtain switching information of a reset signal in the reset signal switching circuit, wherein the switching information comprises first switching information that the reset signal is switched based on a multiplex reset device and a function reset source of the multiplex reset device is connected to a combinational logic, and second switching information that the reset signal is switched based on the multiplex reset device and the function reset source of the multiplex reset device is connected to the register; According to the first scan path report and the switching information, a partition circuit verification script is generated.

3. The authentication method of claim 2, wherein, The step of generating the partition circuit verification script according to the first scan path report and the switching information comprises: generating, according to the first switch information, a first circuit verification script for performing a configuration of a reset invalid value to the combinational logic; generating, according to the first register information and the second switch information, a second circuit verification script for performing a configuration of a reset invalid value to the register, if the register reflected by the first register information is the register reflected by the second switch information; generating, according to the first register information and the second switch information, a third circuit verification script for performing a configuration of a random value to the register, if the register reflected by the first register information is not the register reflected by the second switch information; generating, according to the first register information and the first inverter information, a fourth circuit verification script for performing a capture of an actual observation value of the register and a calculation of a target observation value of the register.

4. The authentication method of claim 3, wherein, The step of obtaining the actual observation value of the scan dump circuit, comparing the actual observation value with the target observation value, and obtaining a circuit verification result comprises: performing a sequence configuration to the partitioned circuit after execution of the second circuit verification script and / or the third circuit verification script and the first circuit verification script; performing the fourth circuit verification script, and based on the fourth circuit verification script, configuring a plurality of clocks to a scan clock port in the partitioned circuit, and extracting a register value of each register according to a clock pulse of each clock to obtain the actual observation value; calculating the target observation value according to the reset invalid value configured during execution of the second circuit verification script and / or the random value configured during execution of the third circuit verification script, and the first scan path report corresponding to the partitioned circuit; judging whether the actual observation value is equal to the target observation value; if the actual observation value is equal to the target observation value, outputting a circuit verification result representing that the partitioned circuit passes the verification.

5. The authentication method of claim 1, wherein, The scan dump circuit comprises a reset signal switch circuit, and before the step of obtaining the actual observation value of the scan dump circuit in the simulation circuit running process of the scan dump circuit, in a case that the whole circuit is in a running stage during the simulation circuit running process of the scan dump circuit, the step comprises: controlling the scan dump circuit to enter a single-chain mode, tracking a scan chain in the scan dump circuit to obtain a second scan path report of the scan dump circuit, wherein the second scan path report comprises second register information of each register on each scan chain on the scan dump circuit, and second inverter information between each electronic element on each scan chain. acquiring switching information of the reset signal in the reset signal switching circuit by using a second preset script, wherein the switching information comprises first switching information that the reset signal is switched based on a multiplexing reset device, second switching information that a function reset source of the multiplexing reset device is connected to third switching information of a combinational logic, and third switching information that the reset signal is switched based on the multiplexing reset device, and a function reset source of the multiplexing reset device is connected to fourth switching information of the register; generating an overall circuit verification script according to the second scan path report and the switching information.

6. The authentication method of claim 5, wherein, The step of generating the overall circuit verification script according to the second scan path report and the switching information comprises: generating a fifth circuit verification script for executing a reset invalid value configured to the combinational logic according to the third switching information; generating a sixth circuit verification script for executing a reset invalid value placed to the register according to the second register information and the fourth switching information, if the register reflected by the second register information is the register reflected by the fourth switching information; generating a seventh circuit verification script for executing a random value placed to the register according to the second register information and the fourth switching information, if the register reflected by the second register information is not the register reflected by the fourth switching information; generating an eighth circuit verification script for executing actual observation values of the register captured and target observation values of the register calculated according to the second register information and the second inverter information.

7. The authentication method of claim 6, wherein, The step of acquiring the actual observation values of the scan dump circuit, comparing the actual observation values with the target observation values, and obtaining a circuit verification result comprises: performing sequence configuration on the scan dump circuit after the sixth circuit verification script and / or the seventh circuit verification script and the fifth circuit verification script are executed; performing the eighth circuit verification script, configuring a plurality of clocks in a scan clock port of the scan dump circuit based on the eighth circuit verification script, extracting register values of each register according to clock pulses of each clock, and obtaining the actual observation values; calculating a transfer value of a random value on the register transferred to a data output port according to the reset invalid value placed when the sixth circuit verification script is executed and / or the random value placed when the seventh circuit verification script is executed, combining the second inverter information, and determining the transfer value as the target observation value; determining whether the actual observation values are equal to the target observation values; if the actual observation values are equal to the target observation values, outputting a circuit verification result representing that the scan dump circuit passes verification.

8. The authentication method of claim 1, wherein, The step of acquiring transfer data transferred out of the scan dump circuit, mapping the transfer data to second report values of each register, comparing the first report values and the second report values corresponding to each register, and obtaining a data dump result after the first report values of each register in the scan dump circuit are recorded comprises: executing the first transfer script, based on the first transfer script, running the second running file, based on the second running file, closing the clock source, executing the second transfer script, based on the second transfer script, obtaining the register value on each of the registers, and obtaining the first report value; running the first running file, entering a scan dump mode, in the scan dump mode, recording the transfer data transferred to the data output port, and mapping the transfer data to the corresponding register according to the third scan path report, calculating the pre-transfer data of the register, and determining the pre-transfer data as the second report value; determining whether the first report value is equal to the second report value; if the first report value is equal to the second report value, outputting a transfer verification result representing that the scan dump circuit passes the verification.

9. A storage medium, characterized by The storage medium is a computer readable storage medium, and the storage medium stores a computer program. When the computer program is executed by a processor, the steps of the verification method in any one of claims 1 to 8 are implemented.

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