STDP learning circuit based on differential amplification circuit in saturation state

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to an STDP learning circuit based on a differential amplification circuit in a saturation state, which comprises a time decay voltage generator module and a differential amplification circuit module in a saturation state, the time decay voltage generator module is electrically connected with the differential amplification circuit module in the saturated state; the time decay voltage generator module is suitable for receiving front and rear neuron pulses of the current synapse to obtain two time decay voltage signals and sending the two time decay voltage signals to the differential amplification circuit module in the saturated state; the differential amplification circuit module in the saturated state is suitable for calculating and amplifying the difference between the two time decay voltage signals, outputting current, and integrating the current to obtain a change value of weight voltage; the STDP algorithm is realized by a smaller-scale circuit.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to an STDP learning circuit based on a differential amplifier circuit in a saturated state. Background Art

[0002] Spiking neural network is a machine learning method based on biological neural system, which aims to improve the performance and energy efficiency of machine learning. In biological neural system, synapse is a special part for signal transmission between neurons or between neurons and non-neuronal cells. Synaptic weight is used to adjust the connection strength between neurons. The larger the value, the stronger the connection strength, and vice versa. Learning in the brain can be understood as the process of change of synaptic connection strength over time, which is called synaptic plasticity. At present, the widely used learning rule is the spike-timing-dependent plasticity (STDP) learning rule. The STDP learning rule simulates synaptic plasticity, so that the synaptic weight can be changed according to the time difference of neuronal pulse firing. The relative timing of pre- and post-synaptic pulse firing will lead to different synaptic change processes. The result of synaptic weight change can be expressed as a function of the pre- and post-synaptic pulse time difference, which is called the learning window.

[0003] The design of synaptic circuits in traditional neural networks involves a synaptic weight dependency mechanism, which usually requires the synaptic weights to be stored in static random access memory. This method adds additional circuits and is not conducive to application in large-scale neural network circuits.

[0004] Therefore, based on the above technical problems, it is necessary to design a new STDP learning circuit based on the saturation state of the differential amplifier circuit. Summary of the invention

[0005] The disclosed embodiments at least provide a STDP learning circuit based on a differential amplifier circuit in a saturated state.

[0006] In a first aspect, an embodiment of the present disclosure provides an STDP learning circuit based on a differential amplifier circuit in a saturated state, comprising:

[0007] A time-decay voltage generator module and a differential amplifier circuit module in a saturated state;

[0008] The time-attenuated voltage generator module is electrically connected to the differential amplifier circuit module in the saturation state;

[0009] The time-decayed voltage generator module is adapted to receive the pre-synaptic and post-synaptic neuron pulses of the current synapse to obtain two time-decayed voltage signals, and send the two time-decayed voltage signals to the differential amplifier circuit module in the saturated state;

[0010] The differential amplifier circuit module in the saturated state is suitable for calculating and amplifying the difference between the two time-decayed voltage signals, outputting a current, and integrating the current to obtain a change value of the weighted voltage.

[0011] In an optional embodiment, when the presynaptic neuron pulse arrives earlier than the postsynaptic neuron pulse, the differential amplifier circuit module in a saturated state generates an enhanced signal;

[0012] When the presynaptic neuron pulse arrives later than the postsynaptic neuron pulse, the differential amplifier circuit module in the saturation state generates an inhibition signal.

[0013] In an optional implementation, the time decay voltage generator module includes: a PMOS transistor P1, an NMOS transistor N1 and a capacitor C1;

[0014] The gate of the PMOS tube P1 and the gate of the NMOS tube N1 are connected to an external input pulse signal;

[0015] One end of the capacitor C1 is connected to the drain of the PMOS transistor P1 and the drain of the PMOS transistor P1 to serve as the output of the time decay voltage generator module.

[0016] In an optional implementation, the aspect ratio of the PMOS tube P1 is 2;

[0017] The aspect ratio of the NMOS tube N1 is 20.

[0018] In an optional implementation, when the external pulse signal Input arrives, the capacitor C1 is charged to +3V, and when the external pulse signal Input ends, the capacitor C1 is discharged, and the voltage across the capacitor C1 decays exponentially.

[0019] In an optional implementation, the differential amplifier circuit module in the saturation state includes: a PMOS tube P2, a PMOS tube P3, an NMOS tube N2, an NMOS tube N3, an NMOS tube N4, an NMOS tube N5 and a capacitor C2;

[0020] The output signal Vin1 of the time decay voltage generator module is connected to the gate of the NMOS tube N2;

[0021] The output signal Vin2 of the time decay voltage generator module is connected to the gate of the NMOS tube N3;

[0022] The source of the NMOS tube N2, the source of the NMOS tube N3 and the drain of the NMOS tube N4 are connected;

[0023] The gate of the PMOS tube P2, the gate of the PMOS tube P3, the drain of the PMOS tube P2 and the drain of the NMOS tube N2 are connected;

[0024] The drain of the PMOS tube P3 and the drain of the NMOS tube N3 are connected to one end of the capacitor C2;

[0025] The gate of the NMOS tube N4, the gate of the NMOS tube N5, and the drain of the NMOS tube N5 are connected to one end of the external current source, and the other end of the external current source is connected to the external voltage VDD.

[0026] In an optional implementation manner, the NMOS transistor N2 and the NMOS transistor N3 have consistent parameters and constitute an input device;

[0027] The PMOS transistor P2 and the PMOS transistor P3 have consistent parameters and form a current mirror.

[0028] In an optional implementation manner, the aspect ratio of the NMOS transistor N4 is twice the aspect ratio of the NMOS transistor N5.

[0029] In an optional implementation, the differential amplifier circuit operates in a saturation state, and the difference between the input signals Vin1 and Vin2 is output as a current signal Istdp. The output current signal Istdp is integrated by the capacitor C2.

[0030] On the other hand, the present invention further provides a working method using the above-mentioned STDP learning circuit based on the saturation state of the differential amplifier circuit, comprising:

[0031] The time-decayed voltage generator module is adapted to receive the pre-synaptic and post-synaptic neuron pulses of the current synapse to obtain two time-decayed voltage signals, and send the two time-decayed voltage signals to the differential amplifier circuit module in a saturated state;

[0032] The differential amplifier circuit module in the saturated state is suitable for calculating and amplifying the difference between two time-decayed voltage signals, outputting a current, and integrating the current to obtain a change value of the weighted voltage.

[0033] In an optional implementation, the time decay voltage generator module includes: a PMOS transistor P1, an NMOS transistor N1 and a capacitor C1;

[0034] The gate of the PMOS tube P1 and the gate of the NMOS tube N1 are connected to an external input pulse signal;

[0035] One end of the capacitor C1 is connected to the drain of the PMOS transistor P1 and the drain of the PMOS transistor P1 to serve as the output of the time decay voltage generator module.

[0036] In an optional implementation, the differential amplifier circuit module in the saturation state includes: a PMOS tube P2, a PMOS tube P3, an NMOS tube N2, an NMOS tube N3, an NMOS tube N4, an NMOS tube N5 and a capacitor C2;

[0037] The output signal Vin1 of the time decay voltage generator module is connected to the gate of the NMOS tube N2;

[0038] The output signal Vin2 of the time decay voltage generator module is connected to the gate of the NMOS tube N3;

[0039] The source of the NMOS tube N2, the source of the NMOS tube N3 and the drain of the NMOS tube N4 are connected;

[0040] The gate of the PMOS tube P2, the gate of the PMOS tube P3, the drain of the PMOS tube P2 and the drain of the NMOS tube N2 are connected;

[0041] The drain of the PMOS tube P3 and the drain of the NMOS tube N3 are connected to one end of the capacitor C2;

[0042] The gate of the NMOS tube N4, the gate of the NMOS tube N5, and the drain of the NMOS tube N5 are connected to one end of the external current source, and the other end of the external current source is connected to the external voltage VDD.

[0043] The beneficial effect of the present invention is that the STDP learning circuit based on the differential amplifier circuit in the saturated state includes: a time-attenuated voltage generator module and a differential amplifier circuit module in the saturated state; the time-attenuated voltage generator module is electrically connected to the differential amplifier circuit module in the saturated state; the time-attenuated voltage generator module is suitable for receiving the pre- and post-neuron pulses of the current synapse to obtain two time-attenuated voltage signals, and sending the two time-attenuated voltage signals to the differential amplifier circuit module in the saturated state; the differential amplifier circuit module in the saturated state is suitable for calculating and amplifying the difference between the two time-attenuated voltage signals, outputting current, and integrating the current to obtain the change value of the weight voltage; the STDP algorithm is realized with a smaller-scale circuit.

[0044] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0045] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, this article specifically cites preferred embodiments and provides detailed descriptions as follows in conjunction with the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0047] Figure 1 A principle block diagram of a STDP learning circuit based on a differential amplifier circuit in a saturated state provided in an embodiment of the present disclosure;

[0048] Figure 2 A circuit diagram of a time-attenuated voltage generator module provided by an embodiment of the present disclosure;

[0049] Figure 3 A circuit diagram of a differential amplifier circuit module in a saturated state provided by an embodiment of the present disclosure;

[0050] Figure 4 A time window simulation diagram of synaptic weight voltage changes provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0052] As used herein, the phrases "in one embodiment," "according to one embodiment," "in some embodiments," and the like generally refer to the fact that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure. Therefore, a particular feature, structure, or characteristic may be included in more than one embodiment of the present disclosure, so that these phrases do not necessarily refer to the same embodiment. As used herein, the terms "example," "exemplary," and the like are used to "serve as an example, instance, or illustration." Any implementation, aspect, or design described herein as "example" or "exemplary" is not necessarily to be construed as preferred or superior to other implementations, aspects, or designs. On the contrary, the use of the terms "example," "exemplary," and the like is intended to present concepts in a concrete manner.

[0053] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0054] like Figures 1 to 3 As shown, an embodiment of the present disclosure provides an STDP learning circuit based on a differential amplifier circuit in a saturated state, comprising: a time-attenuated voltage generator module and a differential amplifier circuit module in a saturated state; the time-attenuated voltage generator module is electrically connected to the differential amplifier circuit module in a saturated state; the time-attenuated voltage generator module is suitable for receiving the pre- and post-neuron pulses of the current synapse to obtain two time-attenuated voltage signals, and sending the two time-attenuated voltage signals to the differential amplifier circuit module in a saturated state; the differential amplifier circuit module in a saturated state is suitable for calculating and amplifying the difference between the two time-attenuated voltage signals, outputting current, and integrating the current to obtain the change value of the weight voltage; the STDP algorithm is realized with a smaller-scale circuit.

[0055] In an optional embodiment, when the presynaptic neuron pulse arrives earlier than the postsynaptic neuron pulse, the differential amplifier circuit module in the saturation state generates an enhancement signal; when the presynaptic neuron pulse arrives later than the postsynaptic neuron pulse, the differential amplifier circuit module in the saturation state generates an inhibition signal.

[0056] In an optional embodiment, the time attenuation voltage generator module includes: a PMOS tube P1, an NMOS tube N1 and a capacitor C1; the gate of the PMOS tube P1 and the gate of the NMOS tube N1 are connected to an external input pulse signal; the source of the PMOS tube P1 is connected to a +3V power supply; the source of the NMOS tube N1 is connected to a +1V power supply; one end of the capacitor C1 is connected to the drain of the PMOS tube P1 and the drain of the PMOS tube P1, and the other end is connected to an external ground wire GND.

[0057] In an optional implementation, when the external pulse signal Input arrives, the capacitor C1 is charged to +3V. When the external pulse signal Input ends, the capacitor C1 is discharged, and the voltage across the capacitor C1 decays exponentially, thereby converting the pulse signal into a time-decayed voltage signal.

[0058] In an optional implementation, the differential amplifier circuit module in the saturation state includes: a PMOS tube P2, a PMOS tube P3, an NMOS tube N2, an NMOS tube N3, an NMOS tube N4, an NMOS tube N5 and a capacitor C2; the output signal Vin1 of the time decay voltage generator module is connected to the gate of the NMOS tube N2; the output signal Vin2 of the time decay voltage generator module is connected to the gate of the NMOS tube N3; the source of the NMOS tube N2, the source of the NMOS tube N3 and the drain of the NMOS tube N4 are connected; the gate of the PMOS tube P2, the gate of the PMOS tube P3, The drain of the PMOS tube P2 is connected to the drain of the NMOS tube N2; the drain of the PMOS tube P3 and the drain of the NMOS tube N3 are connected to one end of the capacitor C2; the other end of the capacitor C2 is grounded; the source of the PMOS tube P2 is connected to an external voltage VDD; the source of the PMOS tube P3 is connected to the external voltage VDD; the gate of the NMOS tube N4, the gate of the NMOS tube N5, and the drain of the NMOS tube N5 are connected to one end of the external current source, and the other end of the external current source is connected to the external voltage VDD; the source of the NMOS tube N4 is grounded; the source of the NMOS tube N5 is grounded.

[0059] In an optional implementation manner, the NMOS transistor N2 and the NMOS transistor N3 have consistent parameters and form an input device; the PMOS transistor P2 and the PMOS transistor P3 have consistent parameters and form a current mirror.

[0060] In an optional embodiment, the differential amplifier circuit operates in a saturation state, and the difference between the input signals Vin1 and Vin2 is output as a current signal Istdp. The output current signal Istdp is integrated by capacitor C2, and the change in current value can represent the change in synaptic weight.

[0061] like Figure 4 As shown, the horizontal axis represents the time difference between the presynaptic signal and the postsynaptic signal (ie, the input signals Vin1 and Vin2), and the vertical axis represents the value of the current signal Istdp, which is the change in the synaptic weight.

[0062] In at least one other embodiment, a working method using the above-mentioned STDP learning circuit based on the differential amplifier circuit in a saturated state is also provided, including: a time-decayed voltage generator module is suitable for receiving the pre- and post-neuron pulses of the current synapse to obtain two time-decayed voltage signals, and sending the two time-decayed voltage signals to the differential amplifier circuit module in a saturated state; the differential amplifier circuit module in a saturated state is suitable for calculating and amplifying the difference between the two time-decayed voltage signals, outputting current, and integrating the current to obtain a change value of the weight voltage.

[0063] In summary, the STDP learning circuit based on the differential amplifier circuit in the saturated state includes: a time-attenuated voltage generator module and a differential amplifier circuit module in the saturated state; the time-attenuated voltage generator module is electrically connected to the differential amplifier circuit module in the saturated state; the time-attenuated voltage generator module is suitable for receiving the pre- and post-neuron pulses of the current synapse to obtain two time-attenuated voltage signals, and sending the two time-attenuated voltage signals to the differential amplifier circuit module in the saturated state; the differential amplifier circuit module in the saturated state is suitable for calculating and amplifying the difference between the two time-attenuated voltage signals, outputting current, and integrating the current to obtain the change value of the weight voltage; the STDP algorithm is realized with a smaller-scale circuit.

[0064] Based on the above ideal embodiments of the present invention, the relevant staff can make various changes and modifications without departing from the technical concept of the present invention through the above description. The technical scope of the present invention is not limited to the contents of the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A STDP learning circuit based on a differential amplifier circuit in a saturated state, characterized in that: include: A time-decay voltage generator module and a differential amplifier circuit module in a saturated state; The time-attenuated voltage generator module is electrically connected to the differential amplifier circuit module in the saturation state; The time-decayed voltage generator module is adapted to receive the pre-synaptic and post-synaptic neuron pulses of the current synapse to obtain two time-decayed voltage signals, and send the two time-decayed voltage signals to the differential amplifier circuit module in the saturated state; The differential amplifier circuit module in the saturated state is suitable for calculating and amplifying the difference between the two time-decayed voltage signals, outputting a current, and integrating the current to obtain a change value of the weighted voltage.

2. The STDP learning circuit based on the saturation state of the differential amplifier circuit as claimed in claim 1, characterized in that: When the presynaptic neuron pulse arrives earlier than the postsynaptic neuron pulse, the differential amplifier circuit module in the saturated state generates an enhanced signal; When the presynaptic neuron pulse arrives later than the postsynaptic neuron pulse, the differential amplifier circuit module in the saturation state generates an inhibition signal.

3. The STDP learning circuit based on the saturation state of the differential amplifier circuit as claimed in claim 1, characterized in that: The time decay voltage generator module includes: a PMOS tube P1, an NMOS tube N1 and a capacitor C1; The gate of the PMOS tube P1 and the gate of the NMOS tube N1 are connected to an external input pulse signal; One end of the capacitor C1 is connected to the drain of the PMOS transistor P1 and the drain of the PMOS transistor P1 to serve as the output of the time decay voltage generator module.

4. The STDP learning circuit based on the saturation state of the differential amplifier circuit as claimed in claim 3, characterized in that: When the external pulse signal Input arrives, the capacitor C1 is charged to +3V. When the external pulse signal Input ends, the capacitor C1 is discharged, and the voltage across the capacitor C1 decays exponentially.

5. The STDP learning circuit based on the saturation state of the differential amplifier circuit as claimed in claim 3, characterized in that: The differential amplifier circuit module in the saturation state includes: a PMOS tube P2, a PMOS tube P3, an NMOS tube N2, an NMOS tube N3, an NMOS tube N4, an NMOS tube N5 and a capacitor C2; The output signal Vin1 of the time decay voltage generator module is connected to the gate of the NMOS tube N2; The output signal Vin2 of the time decay voltage generator module is connected to the gate of the NMOS tube N3; The source of the NMOS tube N2, the source of the NMOS tube N3 and the drain of the NMOS tube N4 are connected; The gate of the PMOS tube P2, the gate of the PMOS tube P3, the drain of the PMOS tube P2 and the drain of the NMOS tube N2 are connected; The drain of the PMOS tube P3 and the drain of the NMOS tube N3 are connected to one end of the capacitor C2; The gate of the NMOS tube N4, the gate of the NMOS tube N5, and the drain of the NMOS tube N5 are connected to one end of the external current source, and the other end of the external current source is connected to the external voltage VDD.

6. The STDP learning circuit based on the saturation state of the differential amplifier circuit as claimed in claim 5, characterized in that: The NMOS tube N2 and the NMOS tube N3 have the same parameters and constitute an input device; The PMOS transistor P2 and the PMOS transistor P3 have consistent parameters and form a current mirror.

7. The STDP learning circuit based on the saturation state of the differential amplifier circuit as claimed in claim 6, characterized in that: The differential amplifier circuit operates in a saturation state, and the difference between the input signals Vin1 and Vin2 is output as a current signal Istdp. The output current signal Istdp is integrated by the capacitor C2.

8. A working method using the STDP learning circuit based on the differential amplifier circuit in saturation state as claimed in claim 1, characterized in that: include: The time-decayed voltage generator module is adapted to receive the pre-synaptic and post-synaptic neuron pulses of the current synapse to obtain two time-decayed voltage signals, and send the two time-decayed voltage signals to the differential amplifier circuit module in a saturated state; The differential amplifier circuit module in the saturated state is suitable for calculating and amplifying the difference between two time-decayed voltage signals, outputting a current, and integrating the current to obtain a change value of the weighted voltage.

9. The working method according to claim 8, characterized in that: The time decay voltage generator module includes: a PMOS tube P1, an NMOS tube N1 and a capacitor C1; The gate of the PMOS tube P1 and the gate of the NMOS tube N1 are connected to an external input pulse signal; One end of the capacitor C1 is connected to the drain of the PMOS transistor P1 and the drain of the PMOS transistor P1 to serve as the output of the time decay voltage generator module.

10. The working method according to claim 9, characterized in that: The differential amplifier circuit module in the saturation state includes: a PMOS tube P2, a PMOS tube P3, an NMOS tube N2, an NMOS tube N3, an NMOS tube N4, an NMOS tube N5 and a capacitor C2; The output signal Vin1 of the time decay voltage generator module is connected to the gate of the NMOS tube N2; The output signal Vin2 of the time decay voltage generator module is connected to the gate of the NMOS tube N3; The source of the NMOS tube N2, the source of the NMOS tube N3 and the drain of the NMOS tube N4 are connected; The gate of the PMOS tube P2, the gate of the PMOS tube P3, the drain of the PMOS tube P2 and the drain of the NMOS tube N2 are connected; The drain of the PMOS tube P3 and the drain of the NMOS tube N3 are connected to one end of the capacitor C2; The gate of the NMOS tube N4, the gate of the NMOS tube N5, and the drain of the NMOS tube N5 are connected to one end of the external current source, and the other end of the external current source is connected to the external voltage VDD.

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