Method for preparing semiconductor device and semiconductor device

Abstract

The present application provides a method for preparing a semiconductor device and a semiconductor device. The method includes: providing a semiconductor initial structure, wherein the semiconductor initial structure includes a substrate and a plurality of initial structures arranged at intervals on one side of the substrate; forming a first sacrificial structure, the first sacrificial structure being formed on the circumferential surface of the initial structure; forming a second sacrificial layer and a third sacrificial layer in sequence on the side of the first sacrificial structure away from the substrate, in the thickness direction of the substrate, the size of the portion of the second sacrificial layer formed on the circumferential surface of the initial structure is a first size, and the size of the second sacrificial layer formed on the side of the substrate between adjacent initial structures is a second size, and the first size is greater than the second size; removing a portion of the third sacrificial layer and a portion of the second sacrificial layer to obtain a second sacrificial structure and a third sacrificial structure; removing the third sacrificial structure by a wet etching process. The present method can maintain the integrity of the surface morphology of the mask structure and improve the preparation quality of the subsequent preparation process.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a method for preparing a semiconductor device and a semiconductor device. Background Art

[0002] With the development and progress of semiconductor device manufacturing technology, the stress-increasing method used in the traditional CMOS (Complementary Metal Oxide Semiconductor) manufacturing technology can no longer meet the CMOS device's requirements for PMOS (Positive Channel Metal Oxide Semiconductor) driving current. When the critical size of semiconductor devices reaches 28nm and below, epitaxial technology is needed to increase the compressive stress of PMOS, thereby improving the overall response speed of CMOS.

[0003] However, in the existing epitaxial growth technology, three sidewalls are usually formed on the sidewalls of the gate structure to adjust the size of the recess required for epitaxial growth. However, the first sidewall, the third sidewall and the mask structure on the surface of the gate structure are usually formed of the same material. Therefore, when the second sidewall has an opening that exposes the first sidewall, the etching solution used for wet removal of the third sidewall will corrode the first sidewall and the mask structure through the opening of the second sidewall, thereby affecting the morphology of the mask structure, further affecting the preparation quality of the subsequent preparation process, and affecting the reliability of the semiconductor device. Summary of the invention

[0004] Based on this, the embodiments of the present application provide a method for preparing a semiconductor device and a semiconductor device, which can improve the protection capability of the first side wall to the mask structure, maintain the integrity of the surface morphology of the mask structure, and improve the preparation quality of subsequent preparation processes.

[0005] According to a first aspect of an embodiment of the present application, a method for preparing a semiconductor device is provided, comprising:

[0006] A semiconductor initial structure is provided, wherein the semiconductor initial structure comprises a substrate and a plurality of initial substructures spaced apart on one side of the substrate, the initial substructure comprises a gate, a mask structure and a protection structure, the mask structure is located on a side of the gate away from the substrate, and the protection structure is located on a side of the mask structure away from the substrate;

[0007] forming a first sacrificial structure on a side of the initial substructure away from the substrate, wherein the first sacrificial structure is formed on a circumferential surface of the initial substructure;

[0008] A second sacrificial layer and a third sacrificial layer are sequentially formed on a side of the first sacrificial structure away from the substrate, wherein a portion of the second sacrificial layer formed on a side of the first sacrificial structure away from the substrate has a first size in the thickness direction of the substrate, and a portion of the second sacrificial layer formed on a side of the substrate between adjacent initial substructures has a second size in the thickness direction of the substrate, and the first size is greater than the second size;

[0009] removing a portion of the third sacrificial layer and a portion of the second sacrificial layer in sequence to obtain a second sacrificial structure and a third sacrificial structure, wherein the second sacrificial structure is located between the first sacrificial structure and the third sacrificial structure;

[0010] The third sacrificial structure is removed by a wet etching process.

[0011] In one embodiment, forming a first sacrificial structure on a side of the initial substructure away from the substrate includes:

[0012] forming a first sacrificial layer on a side of the initial substructure away from the substrate;

[0013] Simultaneously etching the first sacrificial layer on the substrate side between adjacent initial substructures and a portion of the first sacrificial layer on a side of the initial substructure away from the substrate to obtain an initial sacrificial structure;

[0014] forming a fourth sacrificial layer between adjacent initial substructures;

[0015] Etching the fourth sacrificial layer so that the distance between the surface of the fourth sacrificial layer away from the substrate after etching and the substrate is equal to the first distance;

[0016] Etching the initial sacrificial structure to obtain the first sacrificial structure, wherein the distance between the surface of the first sacrificial structure away from the substrate and the substrate is a first distance;

[0017] The fourth sacrificial layer is removed.

[0018] In one embodiment, the distance between the surface of the first sacrificial structure away from the substrate and the substrate is a first distance, and the distance between the surface of the mask structure away from the substrate and the substrate is a second distance;

[0019] An absolute value of a difference between the first distance and the second distance is smaller than a preset threshold.

[0020] In one embodiment, the first distance is greater than or equal to the second distance.

[0021] In one of the embodiments, the preset threshold is smaller than a dimension of the protection structure in a thickness direction of the substrate.

[0022] In one embodiment, the sequentially removing a portion of the third sacrificial layer and a portion of the second sacrificial layer includes:

[0023] removing the third sacrificial layer on one side of the substrate between adjacent initial substructures and a portion of the third sacrificial layer on a side of the initial substructure away from the substrate;

[0024] The second sacrificial layer on the substrate side between adjacent initial substructures and a portion of the second sacrificial layer on a side of the initial substructure away from the substrate are removed by a SiCoNi etching process.

[0025] In one embodiment, before the step of removing the third sacrificial structure by a wet etching process, the method further includes:

[0026] etching the substrate between adjacent initial substructures to obtain grooves;

[0027] An epitaxial structure is formed inside the trench.

[0028] A second aspect of an embodiment of the present application provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method as described in any one of the first aspects above.

[0029] In one embodiment, when the semiconductor device includes an epitaxial structure,

[0030] The epitaxial structure includes a germanium-silicon alloy.

[0031] In one embodiment, the materials of the mask structure, the first sacrificial structure and the third sacrificial layer include silicon nitride; and / or,

[0032] The protection structure and the second sacrificial layer are made of silicon oxide.

[0033] The unexpected effect of the present application is that by forming a protective structure on the surface of the mask structure away from the substrate, the mask structure can be prevented from contacting the external water and oxygen environment. By adjusting the first size of the second sacrificial layer to be larger than the second size, the second sacrificial layer on the substrate surface between adjacent initial substructures can be removed in one etching process to facilitate etching of the substrate to form the recesses required for epitaxial growth. At the same time, it can be avoided that the second sacrificial structure on the circumferential surface of the initial substructure is completely etched away, resulting in the exposure of the first sacrificial structure. In the process of wet removal of the third sacrificial structure, the first sacrificial structure and the initial substructure can be protected by the second sacrificial structure to avoid corrosion of the first sacrificial structure and the mask structure by the etching solution. Therefore, the mask quality of the mask structure can be improved, the preparation quality of the subsequent preparation process can be improved, and then the reliability and yield rate of the semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 A schematic flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0036] Figure 2 A schematic structural diagram of a semiconductor initial substructure provided in an embodiment of the present application;

[0037] Figure 3 A schematic structural diagram of a structure obtained by forming a second sacrificial layer on a side of a first sacrificial structure away from a substrate in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0038] Figure 4 A schematic structural diagram of a second sacrificial structure and a third sacrificial structure prepared by a method for preparing a semiconductor device provided in an embodiment of the present application;

[0039] Figure 5 A scanning electron microscope schematic diagram of a second sacrificial structure prepared by an existing semiconductor device preparation method;

[0040] Figure 6 A schematic diagram of a scanning electron microscope showing a semiconductor device prepared by an existing method for preparing a semiconductor device;

[0041] Figure 7A schematic flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application, showing a step of forming a first sacrificial structure on a side of an initial substructure away from a substrate;

[0042] Figure 8 A schematic structural diagram of a step of forming a first sacrificial layer on a side of an initial substructure away from a substrate in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0043] Fig. 9 A schematic structural diagram of the steps of obtaining an initial sacrificial structure in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0044] Fig.10 A schematic structural diagram of a step of obtaining a fourth sacrificial layer in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0045] Fig.11 A schematic structural diagram of a fourth sacrificial layer after etching obtained in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0046] Fig.12 A schematic structural diagram of a first sacrificial structure obtained by a method for preparing a semiconductor device provided in an embodiment of the present application;

[0047] Fig.13 A schematic structural diagram of a fourth sacrificial layer obtained by a method for preparing a semiconductor device provided in an embodiment of the present application;

[0048] Fig.14 A schematic flow chart of the steps of sequentially removing a portion of the third sacrificial layer and a portion of the second sacrificial layer in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0049] Fig.15 A schematic structural diagram of a third sacrificial layer obtained by a method for preparing a semiconductor device provided in an embodiment of the present application;

[0050] Fig.16 A schematic structural diagram of a third sacrificial structure obtained by a method for preparing a semiconductor device provided in an embodiment of the present application;

[0051] Fig.17 A schematic structural diagram of a second sacrificial structure obtained by a method for preparing a semiconductor device provided in an embodiment of the present application;

[0052] Fig.18 A schematic flow chart of the steps of sequentially removing a portion of the third sacrificial layer and a portion of the second sacrificial layer in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0053] Fig.19A schematic structural diagram of a cavity obtained by a method for preparing a semiconductor device provided in an embodiment of the present application;

[0054] Fig. 20 A schematic structural diagram of a trench obtained by a method for preparing a semiconductor device provided in an embodiment of the present application;

[0055] Fig.21 A schematic structural diagram of an epitaxial structure obtained by a method for preparing a semiconductor device provided in an embodiment of the present application;

[0056] Fig. 22 A schematic structural diagram of a semiconductor device provided in an embodiment of the present application.

[0057] Description of reference numerals:

[0058] 100-semiconductor initial structure, 110-substrate, 111-initial substrate structure, 112-target substrate structure, 120-initial substructure, 121-gate, 122-mask structure, 123-protection structure, 200-first sacrificial structure, 201-first sacrificial layer, 202-initial sacrificial structure, 203-fourth sacrificial layer, 204-fourth sacrificial layer after etching, 300-second sacrificial layer, 310-second sacrificial structure, 400-third sacrificial layer, 410-third sacrificial structure, 500-epitaxial structure. DETAILED DESCRIPTION

[0059] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0061] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0062] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0063] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0064] It should be noted that in the existing method for preparing semiconductor devices, a first sacrificial layer is usually first formed on the side of the initial substructure away from the substrate, so as to form a sacrificial layer on the surface of the initial substructure and the surface of the substrate. Then, the first sacrificial layer of silicon nitride on the surface of the substrate between adjacent initial substructures is removed by an etching process, and at the same time, the first sacrificial layer on the surface of the side of the initial substructure away from the substrate can be synchronously etched, and then a first sidewall is formed on the circumferential surface of the initial substructure. At this time, the thickness of the first sidewall is less than the thickness of the initial substructure, and greater than the sum of the thicknesses of the gate and the mask structure. Then, a second sacrificial layer is formed on the surface of the side of the first sidewall away from the substrate layer, resulting in a thinner thickness of the second sacrificial layer on the surface of the side of the first sidewall away from the substrate. In the process of removing the second sacrificial layer on the surface of the substrate, the second sacrificial layer on the surface of the side of the first sidewall away from the substrate will be synchronously removed, resulting in the exposure of the surface of the first sidewall. However, the second sacrificial layer after etching constitutes a second sidewall, and a third sidewall is also formed on the side of the second sidewall away from the initial substructure. In the existing preparation method, the third sidewall is usually removed by a wet etching process, and the third sidewall, the first sidewall and the mask structure in the initial substructure are all made of the same material, which will cause the first sidewall to be corroded synchronously in this process section, and even cause the mask structure to be corroded synchronously. Therefore, the existing preparation method of semiconductor devices will cause the surface morphology of the mask structure to be damaged, affecting the accuracy of the subsequent mask process, thereby reducing the yield of the semiconductor device and affecting the preparation efficiency and preparation quality of the preparation method of the semiconductor device.

[0065] Figure 1 A schematic flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application. Figure 1 As shown, in a first aspect of an embodiment of the present application, a method for preparing a semiconductor device is provided, comprising:

[0066] Step S110, providing an initial semiconductor structure.

[0067] Figure 2 A schematic structural diagram of a semiconductor initial structure provided in an embodiment of the present application. Figure 2 As shown, the semiconductor initial structure 100 includes a substrate 110 and a plurality of initial substructures 120, wherein the initial substructure 120 includes a gate 121, a mask structure 122 and a protection structure 123, wherein the mask structure 122 is located between the gate 121 and the protection structure 123. The material of the mask structure 122 includes silicon nitride, and the material of the protection structure 123 includes silicon oxide.

[0068] Step S120 , forming a first sacrificial structure on a side of the initial structure away from the substrate, wherein the first sacrificial structure is formed on a circumferential surface of the initial structure.

[0069] Exemplarily, a first sacrificial layer may be formed on the side of the initial substructure 120 away from the substrate 110, and the first sacrificial layer on the surface of the substrate 110 between adjacent initial substructures 120 and part of the first sacrificial layer on the surface of the side of the initial substructure 120 away from the substrate 110 may be removed by an etching process to obtain a first sacrificial structure. The etching of the first sacrificial layer in the above two regions may be completed synchronously, that is, the etching depths of the two regions are the same, or may be completed in steps, that is, the etching depths in the above two regions may be adjusted separately, and the etching depths in different regions may be different.

[0070] Step S130, forming a second sacrificial layer and a third sacrificial layer in sequence on the side of the first sacrificial structure away from the substrate, wherein the size of the portion of the second sacrificial layer formed on the side of the first sacrificial structure away from the substrate in the thickness direction of the substrate is a first size, and the size of the second sacrificial layer formed on the side of the substrate between adjacent initial structures in the thickness direction of the substrate is a second size, and the first size is larger than the second size.

[0071] Figure 3 A method for preparing a semiconductor device provided in an embodiment of the present application is a schematic structural diagram of a structure obtained by forming a second sacrificial layer on a side of a first sacrificial structure away from a substrate. Figure 3 As shown, the second sacrificial layer 300 is formed on the side of the first sacrificial structure 200 away from the substrate 110, the size of the portion of the second sacrificial layer 300 formed on the side of the first sacrificial structure 200 away from the substrate 110 in the thickness direction of the substrate 110 is a first size L1, and the size of the second sacrificial layer 300 formed on the side of the substrate 110 between adjacent initial substructures 120 in the thickness direction of the substrate 110 is a second size L2.

[0072] For example, in the thickness direction of the substrate 110, when the distance between the surface of the first sacrificial structure 200 away from the substrate 110 and the surface of the protective structure 123 away from the substrate 110 is greater than or equal to the second size L2, the second sacrificial layer 300 can be formed simultaneously through a growth process. When the distance between the surface of the first sacrificial structure 200 away from the substrate 110 and the surface of the protective structure 123 away from the substrate 110 is less than the second size L2, the second sacrificial layer 300 in different regions can be grown step by step through multiple processes.

[0073] It is understandable that, in the process of etching the second sacrificial layer 300, while the second sacrificial layer 300 on the surface of the substrate 110 between the adjacent initial substructures 120 is removed by etching, part of the second sacrificial layer 300 located on the side of the initial substructure 120 away from the substrate 110 will be etched synchronously. By adjusting the first dimension L1 to be larger than the second dimension L2, the second sacrificial layer 300 located on the side of the initial substructure 120 away from the substrate 110 can be prevented from being completely etched, and the second sacrificial structure can protect the first sacrificial structure 200 and the initial substructure 120 inside it, thereby preventing subsequent processes from causing damage to the gate 121 and the mask structure 122, and further improving the reliability of the method for preparing the semiconductor device, and improving the preparation quality and yield rate of the semiconductor device.

[0074] Step S140 , removing a portion of the third sacrificial layer and a portion of the second sacrificial layer in sequence to obtain a second sacrificial structure and a third sacrificial structure, wherein the second sacrificial structure is located between the first sacrificial structure and the third sacrificial structure.

[0075] Figure 4 A schematic structural diagram of a second sacrificial structure and a third sacrificial structure prepared by a method for preparing a semiconductor device provided in an embodiment of the present application. Figure 4 As shown, the second sacrificial structure 310 is located between the first sacrificial structure and the third sacrificial structure 410. It can be seen that when a semiconductor device is manufactured by the method for manufacturing a semiconductor device provided by the embodiment of the present application, the interior of the second sacrificial structure is a closed space.

[0076] Figure 5 FIG. 1 is a schematic diagram of a second sacrificial structure prepared by an existing method for preparing a semiconductor device using a scanning electron microscope. Figure 5 As shown, the area indicated by the solid line is the area where the surface of the first sacrificial structure 200 is exposed during the etching of the second sacrificial layer in the conventional method for preparing a semiconductor device. Figure 6 FIG. 1 is a schematic diagram of a scanning electron microscope of a semiconductor device prepared by an existing semiconductor device preparation method. Figure 6 As shown, the area indicated by the dotted line is the area where the etching solution produces a corrosion effect on the first sacrificial structure 200 and the mask structure 122 during the wet etching of the third sacrificial structure in the existing method for preparing a semiconductor device. Therefore, it can be understood that when the first sacrificial structure 200 is exposed, the etching solution will corrode the mask structure 122, thereby affecting the mask quality of the mask structure 122, resulting in a decrease in the accuracy of the subsequent mask process, and further affecting the yield rate of the semiconductor device.

[0077] Step S150: removing the third sacrificial structure by a wet etching process.

[0078] The method for preparing a semiconductor device provided by an embodiment of the present application can prevent the mask structure 122 from contacting with an external water and oxygen environment by forming a protective structure 123 on the surface of the mask structure 122 away from the substrate 110. By adjusting the first size L1 of the second sacrificial layer 300 to be larger than the second size L2, the second sacrificial layer 300 on the surface of the substrate 110 between adjacent initial substructures 120 can be removed in one etching process, so as to facilitate etching the substrate 110 to form the recess required for epitaxial growth. At the same time, it can be avoided that the second sacrificial structure 310 on the circumferential surface of the initial substructure 120 is completely etched away, resulting in the exposure of the first sacrificial structure 200. In the process of wet removal of the third sacrificial structure 410, the first sacrificial structure 200 and the initial substructure 120 can be protected by the second sacrificial structure 310 to prevent the etching solution from corroding the first sacrificial structure 200 and the mask structure 122. Therefore, the mask quality of the mask structure 122 can be improved, the preparation quality of the subsequent preparation process can be improved, and then the reliability and yield rate of the semiconductor device can be improved.

[0079] Figure 7 A schematic flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application, showing the step of forming a first sacrificial structure on a side of an initial structure away from a substrate. Figure 7 As shown, the step of forming a first sacrificial structure 200 on a side of the initial structure away from the substrate includes:

[0080] like Figure 8 As shown, in step S210, a first sacrificial layer is formed on a side of the initial structure away from the substrate.

[0081] Exemplarily, the first sacrificial layer 201 may be formed by a chemical vapor deposition process, wherein the material of the first sacrificial layer 201 may include silicon nitride.

[0082] like Fig. 9 As shown, in step S220, the first sacrificial layer on one side of the substrate between adjacent initial structures and a portion of the first sacrificial layer on a side of the initial structure away from the substrate are simultaneously etched to obtain an initial sacrificial structure.

[0083] Exemplarily, a portion of the first sacrificial layer 201 may be etched by a dry etching process.

[0084] like Fig.10 As shown, in step S230, a fourth sacrificial layer is formed between adjacent initial structures.

[0085] Exemplarily, the material of the fourth sacrificial layer 203 may include amorphous carbon.

[0086] like Fig.11As shown, in step S240, the fourth sacrificial layer is etched so that the distance between the surface of the etched fourth sacrificial layer 204 away from the substrate and the substrate is equal to the first distance H1.

[0087] Exemplarily, a portion of the fourth sacrificial layer may be etched by a dry etching process to obtain the etched fourth sacrificial layer 204 .

[0088] like Fig.12 As shown, in step S250, the initial sacrificial structure is etched to obtain a first sacrificial structure, wherein the distance between the surface of the first sacrificial structure away from the substrate and the substrate is a first distance H1.

[0089] For example, the initial sacrificial structure 202 may be etched by a wet etching process or the like.

[0090] like Fig.13 As shown, in step S260, the fourth sacrificial layer is removed.

[0091] Exemplarily, the remaining fourth sacrificial layer 203 may be removed by a dry etching process.

[0092] The method for preparing a semiconductor device provided in an embodiment of the present application can expose a portion of the first sacrificial layer 201 by etching the fourth sacrificial layer 203, so as to facilitate the regulation of the etching of the first sacrificial layer 201, so that the distance between the surface of the first sacrificial structure 200 obtained by etching and the substrate 110 is the first distance H1, so that the size of the second sacrificial layer 300 formed on the surface of the first sacrificial structure 200 on the side away from the substrate 110 in the thickness direction of the substrate 110 can be regulated by regulating the size of the first sacrificial structure 200 in the thickness direction of the substrate 110, and thus the first size L1 can be made larger than the second size L2, thereby saving the regulation steps of the second sacrificial layer 300, reducing the difficulty of preparing the semiconductor device, reducing the preparation process, and improving the preparation efficiency of the method for preparing the semiconductor device.

[0093] See also Figure 8 In some feasible embodiments, the distance between the surface of the first sacrificial structure 200 away from the substrate 110 and the substrate 110 is a first distance H1, and the distance between the surface of the mask structure 122 away from the substrate 110 and the substrate 110 is a second distance H2; the absolute value of the difference between the first distance H1 and the second distance H2 is less than a preset threshold.

[0094] Exemplarily, the first distance H1 may be smaller than the second distance H2. The preset threshold value may range from 0 to 20 angstroms, for example, 0 angstroms, 5 angstroms, 10 angstroms, 15 angstroms, and 20 angstroms.

[0095] The method for preparing a semiconductor device provided in an embodiment of the present application can make the first size L1 of the second sacrificial layer 300 larger than the second size L2 by adjusting the absolute value of the difference between the first distance H1 and the second distance H2 to be smaller than a preset threshold value, while forming the second sacrificial layer 300 through a single growth process. This can save the step of adjusting the second sacrificial layer 300, reduce the difficulty of preparing the semiconductor device, reduce the preparation process, and improve the preparation efficiency of the method for preparing the semiconductor device.

[0096] In some feasible implementations, the first distance H1 is greater than or equal to the second distance H2.

[0097] The method for preparing a semiconductor device provided in the embodiment of the present application can protect the mask structure 122 through the first sacrificial structure 200 by adjusting the first distance H1 to be greater than or equal to the second distance H2, thereby preventing the circumferential surface of the mask structure 122 from contacting the external water and oxygen environment. At the same time, when the etching solution reaches the surface of the first sacrificial structure 200, the first sacrificial structure 200 can be corroded first, thereby further ensuring the integrity of the mask structure 122, improving the mask quality of the mask structure 122, and improving the yield rate of the semiconductor device.

[0098] In some feasible implementations, the preset threshold is smaller than a dimension of the protection structure 123 in a thickness direction of the substrate 110 .

[0099] It should be noted that when the preset threshold is equal to the dimension of the protective structure 123 in the thickness direction of the substrate 110, and the first distance H1 is greater than or equal to the second distance H2, it will result in that when the second sacrificial layer 300 is formed through a thin film growth process, it will be difficult to control the first dimension L1 of the second sacrificial layer 300 to be greater than the second dimension L2, which will increase the preparation steps of the semiconductor device preparation method and reduce the preparation efficiency.

[0100] The method for preparing a semiconductor device provided in an embodiment of the present application can save the step of forming the second sacrificial layer 300 by adjusting the preset threshold to be smaller than the size of the protection structure 123 in the thickness direction of the substrate 110, thereby reducing the difficulty of preparing the semiconductor device, reducing the preparation process, and improving the preparation efficiency of the method for preparing the semiconductor device.

[0101] For example, Fig.14 A schematic flow chart of the steps of sequentially removing a portion of the third sacrificial layer and a portion of the second sacrificial layer in a method for preparing a semiconductor device provided in an embodiment of the present application. Fig.14 As shown, in some feasible implementations, removing a portion of the third sacrificial layer and a portion of the second sacrificial layer in sequence includes:

[0102] like Fig.15 and Fig.16As shown, in step S310, the third sacrificial layer on one side of the substrate between adjacent initial structures and a portion of the third sacrificial layer on a side of the initial structure away from the substrate are removed.

[0103] Exemplarily, in step S300 , a second sacrificial layer 300 and a third sacrificial layer 400 are provided. A portion of the third sacrificial layer 400 may be removed by a dry etching process to obtain a third sacrificial structure 410 .

[0104] like Fig.17 As shown, in step S320, the second sacrificial layer on one side of the substrate between adjacent initial structures and a portion of the second sacrificial layer on a side of the initial structure away from the substrate are removed by a SiCoNi etching process.

[0105] Exemplarily, when etching is performed by a SiCoNi etching process, the etching gas can be excited into a plasma state by a remote plasma source to obtain a corresponding plasma, wherein the etching gas can include a mixed gas of nitrogen trifluoride and ammonia, etc. The plasma can react with the etched material to generate a product that is easily sublimated. The structure after the reaction is completed is raised to the vicinity of the hot reaction chamber shower head, and the structure after the reaction is completed is heated by the hot reaction chamber shower head to sublime the easily sublimated product formed on the surface of the structure, thereby achieving the etching effect.

[0106] It should be noted that the SiCoNi etching process is an etching process with a high selectivity ratio. When etching silicon oxide using the SiCoNi etching process, the selectivity of silicon oxide to silicon is greater than 20:1, and the selectivity of silicon oxide to silicon nitride is greater than 5:1. Therefore, in the process of etching the second sacrificial layer 300, damage to the substrate 110 and the third sacrificial structure 410 can be avoided, thereby ensuring the integrity of the surface morphology of the substrate 110, facilitating the improvement of the preparation quality of subsequent processes, and at the same time ensuring the integrity of the surface morphology of the third sacrificial structure 410, thereby improving the ability of the third sacrificial structure 410 to regulate epitaxial growth, improving the accuracy of the preparation process, and thereby improving the yield rate of semiconductor devices.

[0107] For example, Fig.18 A schematic flow chart of the steps of forming an epitaxial structure inside a substrate in a method for preparing a semiconductor device provided in an embodiment of the present application. Fig.18 As shown, in some feasible implementation manners, before the step of removing the third sacrificial structure by a wet etching process, the method further includes:

[0108] like Fig.19 and Fig. 20 As shown, in step S410, the substrate between adjacent initial structures is etched to obtain grooves.

[0109] Exemplarily, a cavity may be formed in the substrate 110 by a dry etching process to obtain a groove 111. The initial substrate structure 111 with the cavity may be further etched by a wet etching process to obtain a target substrate structure 112 with a groove. The groove formed in the target substrate structure 112 may be a groove of a reverse sigma structure.

[0110] like Fig.21 As shown, in step S420, an epitaxial structure is formed inside the trench.

[0111] For example, the epitaxial structure 500 may be formed inside the trench by an epitaxial growth process.

[0112] It should be understood that, although the steps in the above-mentioned flowcharts are shown in sequence according to the diagrams, these steps are not necessarily executed in sequence according to the order shown in the diagrams. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in each figure may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0113] The method for preparing a semiconductor device provided in an embodiment of the present application can improve the compressive stress of the PMOS device by epitaxially growing the epitaxial structure 500 on the substrate 110, thereby improving the response speed and response quality of the CMOS device, thereby improving the reliability and yield rate of the semiconductor device.

[0114] Fig. 22 A schematic structural diagram of a semiconductor device provided in an embodiment of the present application. Fig. 22 As shown, in a second aspect of the embodiment of the present application, a semiconductor device is provided, which is prepared by using any one of the methods for preparing a semiconductor device in the first aspect. The semiconductor device includes: a target substrate structure 112, an initial substructure 120, a first sacrificial structure 200, a second sacrificial structure 310 and an epitaxial structure 500. The initial substructure 120 includes a gate 121, a mask structure 122 and a protection structure 123.

[0115] The semiconductor device provided by the embodiment of the present application forms a protective structure 123 on the surface of the mask structure 122 away from the substrate 110, which can prevent the mask structure 122 from contacting the external water and oxygen environment, and forms a closed second sacrificial structure 310 on the surface of the first sacrificial structure 200 away from the initial substructure 120. The first sacrificial structure 200 and the initial substructure 120 can be protected by the second sacrificial structure 310 to avoid exposure of the first sacrificial structure 200, thereby ensuring the integrity of the surface morphology of the mask structure 122, thereby improving the mask quality of the mask structure 122, ensuring the preparation quality of subsequent processes, and improving the reliability and yield rate of semiconductor devices.

[0116] In some feasible implementations, when the semiconductor device includes the epitaxial structure 500 , the epitaxial structure 500 includes a germanium-silicon alloy.

[0117] The semiconductor device provided in the embodiment of the present application forms an epitaxial structure 500 by using a germanium-silicon alloy, which can increase the rate of electron migration in the semiconductor device, further reduce the power consumption of the semiconductor device, and increase the response speed of the semiconductor device.

[0118] In some feasible implementations, the materials of the mask structure 122 , the first sacrificial structure 200 , and the third sacrificial layer 400 include silicon nitride.

[0119] It should be noted that silicon nitride has high hardness, good thermal insulation and corrosion resistance, etc.

[0120] The semiconductor device provided in the embodiment of the present application forms the mask structure 122, the first sacrificial structure 200 and the third sacrificial layer 400 by silicon nitride, which can improve the stability of the structure and protect the devices inside the structure.

[0121] In some feasible implementations, the materials of the protection structure 123 and the second sacrificial layer 300 include silicon oxide.

[0122] The semiconductor device provided in the embodiment of the present application forms a protection structure 123 and a second sacrificial layer 300 by silicon oxide, which can avoid the influence of the etching of the protection structure 123 and the second sacrificial layer 300 on the surface morphology of the mask structure 122, the first sacrificial structure 200 and the third sacrificial layer 400, and can further improve the integrity of the mask structure 122, improve the mask quality of subsequent processes, and improve the yield rate of semiconductor devices.

[0123] The unexpected effect of the present application is that by forming a protective structure 123 on the surface of the mask structure 122 away from the substrate 110, the mask structure 122 can be prevented from contacting with the external water and oxygen environment. By adjusting the first size L1 of the second sacrificial layer 300 to be larger than the second size L2, the second sacrificial layer 300 on the surface of the substrate 110 between adjacent initial substructures 120 can be removed in one etching process, so as to facilitate etching of the substrate 110 to form the recess required for epitaxial growth. At the same time, it can be avoided that the second sacrificial structure 310 on the circumferential surface of the initial substructure 120 is completely etched away, resulting in the exposure of the first sacrificial structure 200. In the process of wet removal of the third sacrificial structure 410, the first sacrificial structure 200 and the initial substructure 120 can be protected by the second sacrificial structure 310, so as to avoid the etching solution from corroding the first sacrificial structure 200 and the mask structure 122. Therefore, the mask quality of the mask structure 122 can be improved, the preparation quality of the subsequent preparation process can be improved, and then the reliability and yield rate of the semiconductor device can be improved.

[0124] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0125] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0126] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: A semiconductor initial structure is provided, wherein the semiconductor initial structure comprises a substrate and a plurality of initial substructures spaced apart on one side of the substrate, the initial substructure comprises a gate, a mask structure and a protection structure, the mask structure is located on a side of the gate away from the substrate, and the protection structure is located on a side of the mask structure away from the substrate; forming a first sacrificial structure on a sidewall of the initial substructure; forming a second sacrificial layer and a third sacrificial layer in sequence on a side of the first sacrificial structure away from the substrate and on a sidewall of the first sacrificial structure, wherein a portion of the second sacrificial layer formed on a side of the first sacrificial structure away from the substrate has a first size in the thickness direction of the substrate, and a portion of the second sacrificial layer formed on a side of the substrate between adjacent initial substructures has a second size in the thickness direction of the substrate, and the first size is greater than the second size; removing a portion of the third sacrificial layer and a portion of the second sacrificial layer in sequence to obtain a second sacrificial structure and a third sacrificial structure, wherein the second sacrificial structure is located between the first sacrificial structure and the third sacrificial structure; The third sacrificial structure is removed by a wet etching process.

2. The method for preparing a semiconductor device according to claim 1, wherein: The forming of a first sacrificial structure on the sidewall of the initial substructure comprises: forming a first sacrificial layer on a side of the initial substructure away from the substrate; Simultaneously etching the first sacrificial layer on the substrate side between adjacent initial substructures and a portion of the first sacrificial layer on a side of the initial substructure away from the substrate to obtain an initial sacrificial structure; forming a fourth sacrificial layer between adjacent initial substructures; Etching the fourth sacrificial layer so that the distance between the surface of the fourth sacrificial layer away from the substrate after etching and the substrate is equal to the first distance; Etching the initial sacrificial structure to obtain the first sacrificial structure, wherein the distance between the surface of the first sacrificial structure away from the substrate and the substrate is a first distance; The fourth sacrificial layer is removed.

3. The method for preparing a semiconductor device according to claim 1, characterized in that: The distance between the surface of the first sacrificial structure away from the substrate and the substrate is a first distance, and the distance between the surface of the mask structure away from the substrate and the substrate is a second distance; An absolute value of a difference between the first distance and the second distance is smaller than a preset threshold.

4. The method for preparing a semiconductor device according to claim 3, characterized in that: The first distance is greater than or equal to the second distance.

5. The method for preparing a semiconductor device according to claim 3, characterized in that: The preset threshold is smaller than a dimension of the protection structure in a thickness direction of the substrate.

6. The method for preparing a semiconductor device according to claim 1, wherein: The sequentially removing a portion of the third sacrificial layer and a portion of the second sacrificial layer comprises: removing the third sacrificial layer on one side of the substrate between adjacent initial substructures and a portion of the third sacrificial layer on a side of the initial substructure away from the substrate; The second sacrificial layer on the substrate side between adjacent initial substructures and a portion of the second sacrificial layer on a side of the initial substructure away from the substrate are removed by a SiCoNi etching process.

7. The method for preparing a semiconductor device according to claim 1, characterized in that: Before the step of removing the third sacrificial structure by a wet etching process, the method further includes: etching the substrate between adjacent initial substructures to obtain grooves; An epitaxial structure is formed inside the trench.

8. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 7.

9. The semiconductor device according to claim 8, characterized in that In the case where the semiconductor device comprises an epitaxial structure, The epitaxial structure includes a germanium-silicon alloy.

10. The semiconductor device according to claim 8, characterized in that The materials of the mask structure, the first sacrificial structure and the third sacrificial layer include silicon nitride; and / or, The protection structure and the second sacrificial layer are made of silicon oxide.

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