Bearing structure and preparation method thereof, and preparation method of three-dimensional memory

Abstract

The invention provides a bearing structure and a preparation method thereof, and a preparation method of a three-dimensional memory, relates to the technical field of semiconductor chips, and aims to solve the problem that a carrier for manufacturing a semiconductor structure cannot be reused. The bearing structure comprises a substrate and an insulating supporting layer. The insulating supporting layer is located on one side of the substrate and comprises a base layer, a plurality of supporting structures and communicating grooves located among the supporting structures, and the supporting structures are located on the side, away from the substrate, of the base layer. The bearing structure can be used for supporting the semiconductor structure when the three-dimensional memory is manufactured.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a supporting structure and a preparation method thereof, and a preparation method of a three-dimensional memory. Background Art

[0002] Currently, when preparing a three-dimensional memory, for example, an array device is formed on a carrier, and then a peripheral circuit is disposed on the array device, so that the array device and the peripheral circuit are connected to form a three-dimensional memory. Summary of the invention

[0003] The embodiments of the present disclosure provide a carrier structure and a method for preparing the same, and a method for preparing a three-dimensional memory, which aim to solve the problem that a carrier used to manufacture a semiconductor structure cannot be reused.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] In one aspect, a bearing structure is provided, the bearing structure comprising: a substrate and an insulating support layer. The insulating support layer is located on one side of the substrate, the insulating support layer comprises a base layer, a plurality of support structures and a connecting groove located between the plurality of support structures, and the plurality of support structures are located on a side of the base layer away from the substrate.

[0006] In this solution, the first semiconductor structure can be bound to the supporting structure of the carrier structure, and the second semiconductor structure can be bonded to the first semiconductor structure, so that the first semiconductor structure and the second semiconductor structure form, for example, a three-dimensional memory. When separating the carrier structure from the first semiconductor structure, for example, a wet etching process can be used to allow the etching liquid to enter the connecting groove; since the connecting groove is located between multiple supporting structures, the etching liquid flows in the connecting groove, so that the etching liquid can etch all the supporting structures, thereby separating the carrier structure from the first semiconductor structure. In this process, the supporting structure of the carrier structure is eliminated, but the substrate is not eliminated, so the remaining substrate can be reused, thereby reducing costs.

[0007] In some embodiments, the ratio of the total area of ​​the surface of the plurality of support structures facing away from the base layer to the total area of ​​the surface of the base layer close to the substrate is 50% to 70%.

[0008] In some embodiments, the distance between adjacent support structures is 200 nm to 500 nm.

[0009] In some embodiments, the distance between the surface of the support structure facing away from the base layer and the base layer is 100 nm to 500 nm.

[0010] In some embodiments, the plurality of support structures are arranged in multiple rows and columns.

[0011] In some embodiments, two adjacent rows of support structures are staggered along the column direction.

[0012] In some embodiments, multiple support structures form multiple support units, and the multiple support units are arranged in multiple rows and columns. Each support unit includes multiple sub-support units diffusely arranged from the center to the periphery, and each sub-support unit includes multiple support structures arranged in sequence around the center.

[0013] In some embodiments, an orthographic projection of the plurality of support structures on the base layer includes at least one of a circle, an ellipse, a triangle, or a rectangle.

[0014] In some embodiments, the material of the insulating support layer includes at least one of oxide, silicon nitride, and a degradable nanocomposite material.

[0015] On the other hand, a method for preparing a bearing structure is provided, the method comprising: providing a substrate, forming an insulating support layer on one side of the substrate, the insulating support layer comprising a base layer, a plurality of support structures and connecting grooves between the plurality of support structures, the plurality of support structures being located on a side of the base layer away from the substrate.

[0016] In some embodiments, forming an insulating support layer on one side of a substrate includes: forming an insulating film layer on one side of the substrate, and removing a portion of the insulating film layer to form an insulating support layer including a base layer and a plurality of support structures.

[0017] In some embodiments, removing a portion of the insulating film layer includes: etching a portion of the insulating film layer through a mask.

[0018] In another aspect, a method for preparing a three-dimensional memory is provided, the method comprising: forming the above-mentioned supporting structure; forming a first semiconductor structure on a side of the insulating support layer away from the substrate; forming a second semiconductor structure on a side of the first semiconductor structure away from the insulating support layer; and removing the insulating support layer to separate the substrate from the first semiconductor structure.

[0019] In some embodiments, removing the insulating support layer includes: using a wet etching process to allow an etching solution to enter the connecting groove to remove the insulating support layer.

[0020] In some embodiments, after the step of forming the first semiconductor structure on the side of the insulating support layer away from the substrate and before the step of forming the second semiconductor structure on the side of the first semiconductor structure away from the insulating support layer, the method further includes: forming a protective layer, the protective layer being located on the side of the substrate. Before removing the insulating support layer, the method further includes: removing the protective layer.

[0021] In some embodiments, the material of the protection layer is the same as that of the insulating support layer.

[0022] In some embodiments, the protection layer is also located on a side surface of the first semiconductor structure and a side surface of the insulating support layer.

[0023] In some embodiments, the first semiconductor structure is one of an array device and a peripheral device, and the second semiconductor structure is the other of the array device and the peripheral device.

[0024] On the other hand, a storage system is provided. The storage system includes: the above-mentioned three-dimensional memory and a controller, wherein the controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

[0025] On the other hand, an electronic device is provided, and the electronic device includes the storage system as described above.

[0026] It can be understood that the beneficial effects that can be achieved by the method for preparing the supporting structure, the method for preparing the three-dimensional memory, the storage system and the electronic device provided by the above embodiments of the present disclosure can be referred to the beneficial effects of the supporting structure described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0028] Figure 1 is a front view of a bearing structure according to some embodiments;

[0029] Figure 2 to Figure 5 is a top view of a bearing structure according to some embodiments;

[0030] Figure 6 is a flow chart of a method for preparing a bearing structure according to some embodiments;

[0031] Figure 7 to Figure 9 is a process diagram of a method for preparing a bearing structure according to some embodiments;

[0032] Fig.10 is a flow chart of a method for preparing a three-dimensional memory according to some embodiments;

[0033] Figures 11 to 16 is a process diagram of a method for preparing a three-dimensional memory according to some embodiments;

[0034] Fig.17 is a structural diagram of a three-dimensional memory according to some embodiments;

[0035] Fig.18 is a structural diagram of a memory cell string according to some embodiments;

[0036] Fig.19 is an equivalent circuit diagram of a memory cell string according to some embodiments;

[0037] Fig. 20 is a block diagram of a storage system according to some embodiments;

[0038] Fig.21 is a block diagram of a storage system according to some other embodiments. DETAILED DESCRIPTION

[0039] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0040] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0041] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0042] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0043] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0044] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0045] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0046] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0047] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0048] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0049] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0050] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0051] The embodiment of the present disclosure provides a bearing structure. Figure 1 is a front view of a bearing structure according to some embodiments; Figure 2 to Figure 5 FIG. 4 is a top view of a bearing structure according to some embodiments. Figures 1 to 5 As shown, the supporting structure 20 may include a substrate 210 and an insulating support layer 220. The insulating support layer 220 is located on one side of the substrate 210; the insulating support layer 220 includes a base layer 221 and a plurality of supporting structures 222, the base layer 221 is located on one side of the substrate 210, and the plurality of supporting structures 222 are located on the side of the base layer 221 away from the substrate 210. In other words, the plurality of supporting structures 222, the base layer 221 and the substrate 210 are stacked in sequence; Figure 1 Taking the orientation shown in FIG. 2 as an example, the substrate 210 , the base layer 221 and the plurality of support structures 222 are stacked in sequence from bottom to top.

[0052] In the insulating support layer 220 , the base layer 221 and the plurality of support structures 222 are arranged to form a connecting groove 223 , that is, the insulating support layer 220 further includes a connecting groove 223 located between the plurality of support structures 222 .

[0053] The material of the insulating support layer 220 is an insulating material, for example, the insulating material may include at least one of oxide, silicon nitride and degradable nanocomposite material (DNC). For example, the material of the insulating support layer 220 is oxide (for example, silicon oxide); another example is the material of the insulating support layer 220 is silicon nitride; another example is the material of the insulating support layer 220 is degradable nanocomposite material; another example is the material of the insulating support layer 220 is oxide (for example, silicon oxide), silicon nitride and degradable nanocomposite material.

[0054] A supporting structure 20 provided in an embodiment of the present disclosure can be used to support a semiconductor structure during the process, and can achieve temporary bonding and de-bonding functions with the semiconductor structure to facilitate the processing of the semiconductor structure and the separation of the semiconductor structure from the supporting structure 20.

[0055] For example, when the bearing structure 20 is used, the following Fig.11 The first semiconductor structure 10 is bonded to the support structure 222 of the carrier structure 20, and the second semiconductor structure 60 is coupled to the first semiconductor structure 10, so that the first semiconductor structure 10 and the second semiconductor structure 60 form, for example, a three-dimensional memory. After the three-dimensional memory is formed, the carrier structure 20 is separated from the three-dimensional memory.

[0056] In order to separate the supporting structure 20 from the semiconductor structure (for example, the first semiconductor structure 10 and the second semiconductor structure 60 after coupling, that is, the three-dimensional memory), a wet etching process can be used to introduce the etching solution into the connecting groove 223; since the connecting groove 223 formed by the supporting structure 222 in the insulating supporting layer 220 is in a connected state, the connecting groove 223 can be used as a channel allowing the etching solution to flow. The etching solution flows in the connecting groove 223, so that the etching solution can etch away all the supporting structures 222, thereby separating the supporting structure 20 from the semiconductor structure.

[0057] It can be seen that the supporting structure 20 provided in the embodiment of the present disclosure can play the role of supporting the semiconductor structure in the process, and can realize the temporary bonding between the supporting structure 20 and the semiconductor structure by binding the supporting structure 222 and the semiconductor structure, and realize the debonding between the supporting structure 20 and the semiconductor structure by removing the supporting structure 222. In addition, in the process of debonding between the supporting structure 20 and the semiconductor structure, the supporting structure 222 of the supporting structure 20 is eliminated, but the substrate 210 is not eliminated, so the remaining substrate 210 can be reused, thereby reducing the cost.

[0058] Some semiconductor processes need to be carried out in a high temperature environment, so the supporting structure 20 also needs a certain ability to withstand high temperatures. After the semiconductor structure undergoes high temperature treatment, it is still necessary to ensure that the bonding strength between the supporting structure 20 and the semiconductor structure meets the process requirements.

[0059] The embodiments of the present disclosure also provide a comparative scheme. In the comparative scheme, the semiconductor structure and the substrate are bonded together by an organic adhesive. Although the organic adhesive can achieve temporary bonding between the semiconductor structure and the substrate, in some high-temperature processing processes, the high temperature will reduce the adhesion ability of the organic adhesive, thereby causing abnormal separation of the semiconductor structure and the substrate, affecting subsequent processes.

[0060] In the embodiment of the present disclosure, the semiconductor structure is bound to the surface of the side of the plurality of support structures 222 in the carrier structure 20 away from the base layer 221, and the material of the plurality of support structures 222 is an insulating material. Therefore, compared with the comparative solution, the carrier structure 20 in the embodiment of the present disclosure has a better ability to withstand high temperatures, and after undergoing a high temperature treatment process, the bonding strength between the carrier structure 20 and the semiconductor structure can still meet the process requirements.

[0061] From the above description, it can be seen that the supporting structure 20 provided in the embodiment of the present disclosure can achieve temporary bonding and debonding with the semiconductor structure, and the method is simple and easy to implement; in addition, the substrate 210 in the supporting structure 20 can be reused, which is beneficial to reducing costs; furthermore, the supporting structure 20 enables the bonding with the semiconductor structure to have better high temperature tolerance, and in the process of high temperature treatment of the semiconductor structure, it can be ensured that the bonding strength between the supporting structure 20 and the semiconductor structure can still meet the process requirements.

[0062] In some examples, the substrate 210 may include at least one of a variety of semiconductor materials such as amorphous silicon, polycrystalline silicon, single crystal silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, etc. For example, it may include at least one of a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. In other examples, the material of the substrate 210 may be glass, plastic, or sapphire wafer, etc.

[0063] In some embodiments, the ratio of the total area of ​​the surface of the plurality of support structures 222 facing away from the base layer 221 to the total area of ​​the surface of the base layer 221 close to the substrate 210 is 50% to 70% (e.g., 50%, 53%, 55%, 57%, 60%, 63%, 65%, 67%, 70%, etc.). Figure 1 As an example of the bearing structure 20 shown in FIG. 1 , the surface of the plurality of supporting structures 222 facing away from the base layer 221 is Figure 1 The surface indicated by A1 and the surface of the base layer 221 close to the substrate 210 are the surfaces indicated by A2.

[0064] In the support structure 20 adopting the above design, it can be ensured that the bonding strength between the support structure 20 and the semiconductor structure meets the requirements when they are bonded; and the support structure 20 and the semiconductor structure can be separated conveniently, quickly and effectively.

[0065] For some examples, see Figure 2, the distance D1 between adjacent support structures 222 is 200nm-500nm, for example, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm, etc., where the adjacent support structures 222 refer to two support structures 222 adjacent to each other in any direction. Figure 2 Taking the structure and orientation shown as an example, the adjacent support structures 222 may be two support structures 222 adjacent to each other in the horizontal direction, or two support structures 222 adjacent to each other in the vertical direction, or two support structures 222 adjacent to each other in the diagonal direction.

[0066] In the bearing structure 20 adopting the above design, the multiple supporting structures 222 are distributed relatively evenly, so that the distance between the connecting grooves 223 between two adjacent supporting structures 222 is roughly equal (equal). In addition, the spacing between adjacent supporting structures 222 is related to the width of the formed connecting grooves 223. The above design can make the width of the connecting grooves 223 relatively even and roughly equal (equal); when the supporting structures 222 are etched using a wet etching process, the etching liquid has good fluidity in the connecting grooves 223, and the flow distribution is uniform, so that all supporting structures 222 can be etched away quickly and evenly. This can avoid the problem of long etching time and uneven etching of the etching liquid, so that all supporting structures 222 can be completely etched away in a shorter time.

[0067] For some examples, see Figure 1 , the distance D2 from the surface of the support structure 222 away from the base layer 221 to the base layer 221 is 100nm-500nm, for example, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm, etc. With the above design, the accommodation space of the connecting groove 223 can be increased by increasing the depth of the connecting groove 223, so that the connecting groove 223 can accommodate more etching liquid, and the etching liquid can have better fluidity in the connecting groove 223, so that all the support structures 222 can be etched away faster.

[0068] For some examples, see Figure 3, the maximum size D3 of the support structure 222 in the bearing structure 20 is 400-1000nm, such as 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1000nm, etc. It should be noted that the maximum size here refers to the maximum value of the distance between any two points on the edge profile of the support structure 222 in the plane parallel to the base layer 221. With the above design, the contact area between the support structure 222 and the semiconductor structure can meet the requirements of the bonding strength between the two, and avoid affecting the flow rate of the etching solution due to the excessive size of the support structure 222.

[0069] In some embodiments, see Figure 2 to Figure 4 , the multiple support structures 222 in the bearing structure can be arranged in multiple rows and columns. In some examples, see Figure 4 , two adjacent rows of support structures 222 can be staggered along the column direction. Figure 2 and Figure 3 , two adjacent rows of support structures 222 can be aligned along the column direction.

[0070] In other embodiments, see Figure 5 , multiple support structures 222 form multiple support units ZC, and the multiple support units ZC are arranged in multiple rows and columns. Each support unit ZC includes multiple sub-support units ZZC that are diffusely arranged from the center ZX to the periphery, and each sub-support unit ZZC includes multiple support structures 222 that are arranged in sequence around the center ZX.

[0071] In some embodiments, the orthographic projections of the plurality of support structures 222 on the base layer 221 include at least one of a circle, an ellipse, a triangle, or a rectangle. For example, the orthographic projections of the plurality of support structures 222 on the base layer 221 are as follows: Figure 3 Another example is the positive projection of multiple support structures 222 on the base layer 221 is as follows Figure 2 , Figure 4 and Figure 5 Rectangle shown.

[0072] The embodiment of the present disclosure also provides a method for preparing a bearing structure. Figure 6 is a flow chart of a method for preparing a bearing structure according to some embodiments, Figure 7 to Figure 9 is a process diagram of a method for preparing a bearing structure according to some embodiments, such as Figures 6 to 9 As shown, the preparation method S100 of the bearing structure includes:

[0073] Step S110 : providing a substrate 210 .

[0074] Step S120 : forming an insulating support layer 220 on one side of the substrate 210 ; the insulating support layer 220 comprises a base layer 221 , a plurality of support structures 222 and connecting grooves 223 between the plurality of support structures 222 , and the plurality of support structures 222 are located on the side of the base layer 221 away from the substrate 210 .

[0075] The description of step S110 and step S120 may refer to the above description of the supporting structure 20 .

[0076] In some embodiments, see Figure 7 to Figure 9 Step S120 includes: forming an insulating film layer 230 on one side of the substrate 210 , removing a portion of the insulating film layer 230 , and forming an insulating support layer 220 including a base layer 221 and a plurality of support structures 222 .

[0077] In some examples, such as Figure 7 As shown, the insulating film layer 230 is deposited on the substrate 210. The insulating film layer 230 can be formed using one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0078] Among them, removing part of the insulating film layer 230 can be understood as the part of the insulating film layer 230 that is directly opposite to the connecting groove 223. In this way, by removing part of the insulating film layer 230, an insulating support layer 220 can be formed; the insulating support layer 220 includes a base layer 221, multiple support structures 222 and a connecting groove 223.

[0079] For some examples, see Figure 8 and Fig. 9 , removing part of the insulating film layer 230 includes: etching part of the insulating film layer 230 through a mask plate 240. For example, the mask plate 240 is arranged on a side of the insulating film layer 230 away from the substrate 210, and the mask plate has a hollow area 241. Part of the insulating film layer 230 is etched using the hollow area 241 to form the insulating support layer 220. The shape of the hollow area 241 is the same as the shape of the connecting groove 223.

[0080] The embodiment of the present disclosure also provides a method for preparing a three-dimensional memory. Fig.10 is a flow chart of a method for preparing a three-dimensional memory according to some embodiments. Figures 11 to 16 FIG. 1 is a process diagram of a method for manufacturing a three-dimensional memory according to some embodiments. Figures 10 to 16As shown, the method S200 for preparing the three-dimensional memory includes: step S100, step S210 to step S230.

[0081] In which, in step S100, the bearing structure 20 is formed; the description of step S100 may refer to the related description of the above-mentioned step S100.

[0082] Step S210 (please refer to Fig.11 ), forming the first semiconductor structure 10 on the side of the insulating support layer 220 away from the substrate 210. For example, the first semiconductor structure 10 is bonded on the side of the plurality of support structures 222 away from the substrate 210.

[0083] Step S220 (please refer to Fig.14 ), forming (eg bonding) a second semiconductor structure 60 on a side of the first semiconductor structure 10 away from the insulating support layer 220. The first semiconductor structure 10 and the second semiconductor structure 60 can form a whole, for example, forming a three-dimensional memory.

[0084] Step S230 (please refer to Fig.16 ), removing the insulating support layer 220 so that the substrate 210 is separated from the first semiconductor structure 10.

[0085] The first semiconductor structure 10 may be one of an array device and a peripheral device, and the second semiconductor structure 60 may be the other of the array device and the peripheral device. For example, the first semiconductor structure 10 is an array device, and the second semiconductor structure 60 is a peripheral device. For another example, the first semiconductor structure 10 is a peripheral device, and the second semiconductor structure 60 is an array device.

[0086] exist Figures 11 to 16 In the illustrated implementation manner, the preparation method provided by the embodiment of the present disclosure is exemplarily described by taking the first semiconductor structure 10 as an array device and the second semiconductor structure 60 as a peripheral device as an example.

[0087] In the preparation method of the three-dimensional memory provided in the embodiment of the present disclosure, the supporting structure 20 provided in the embodiment of the present disclosure is adopted, and the first semiconductor structure 10 is supported by the supporting structure 20. After the first semiconductor structure 10 and the second semiconductor structure 60 are coupled, the substrate 210 and the first semiconductor structure 10 are separated by removing the insulating support layer 220. Such a design is conducive to the reuse of the substrate 210, thereby reducing costs. In addition, it is convenient for temporary bonding and debonding, can withstand high temperatures, and can ensure the reliability of the connection between the supporting structure 20 and the first semiconductor structure 10 in the high-temperature treatment process (refer to the description of the supporting structure 20 above).

[0088] In some examples, step S230 includes: using a wet etching process to allow an etching solution to enter the connecting groove 223 to remove the insulating support layer 220 .

[0089] For example, the insulating support layer 220 is immersed in an etching solution, and the multiple support structures 222 in the insulating support layer 220 are removed, so that the multiple support structures 222 are separated from the first semiconductor structure 10, thereby separating the substrate 210 from the first semiconductor structure 10. The etching rate of the etching solution on the insulating support layer 220 is greater than the etching rate of the etching solution on the substrate 210, for example, the ratio of the etching rate of the etching solution on the insulating support layer 220 to the etching rate of the etching solution on the substrate 210 is greater than 10.

[0090] In some embodiments, please refer to Fig.10 The preparation S200 of the three-dimensional memory further includes: step S240 and step S250. Step S240 is between step S210 and step S220, and step S250 is between step S220 and step S230.

[0091] Step S240 (please refer to Fig.12 ), forming a protective layer 30, the protective layer 30 is located on the side of the substrate 210. For example, the protective layer 30 is disposed on the side of the substrate 210.

[0092] In some examples, such as Fig.13 and Fig.14 As shown, before step S240, the preparation S200 of the three-dimensional memory further includes: forming a first interconnection layer 40 on the first semiconductor structure 10. The first interconnection layer 40 of the first semiconductor structure 10 is connected to the second interconnection layer 50 of the second semiconductor structure 60, so that the first semiconductor structure 10 and the second semiconductor structure 60 are connected.

[0093] A first interconnection layer 40 may be formed on the first semiconductor structure 10 , and the protection layer 30 may be provided to reduce damage to the substrate 210 caused by processes or equipment when forming the first interconnection layer 40 .

[0094] In some examples, the protection layer 30 also includes portions located on the side surfaces of the first semiconductor structure 10 and the insulating support layer 220. The protection layer 30 may also reduce damage to the first semiconductor structure 10 and the insulating support layer 220.

[0095] In a possible implementation, the outer surface of the first semiconductor structure 10 is covered with a protective film, and the protective layer 30 can be arranged on the substrate 210, the insulating support layer 220 and the side of the protective film of the first semiconductor structure 10. The outer surface of the second semiconductor structure 60 is also covered with a protective film.

[0096] In some examples, the material of the protection layer 30 and the material of the insulating support layer 220 may be the same.

[0097] Step S250 (please refer to Fig.15 ), remove the protection layer 30. For example, the protection layer 30 is etched by an etching process.

[0098] The embodiment of the present disclosure further provides a three-dimensional memory, which can be prepared by the above-mentioned preparation method. Fig.17 is a structural diagram of a three-dimensional memory according to some embodiments, such as Fig.17 As shown, the three-dimensional memory includes an array device and peripheral devices. The array device 200 may include a stacked structure 280. The stacked structure 280 includes gate insulating layers 282 and gate layers 281 that are alternately stacked.

[0099] The stacked structure 280 includes a plurality of gate layers 281 stacked together, and a gate insulating layer 282 is disposed between each two adjacent gate layers 281. In addition, a gate insulating layer 282 may be disposed above a gate layer 281 located at the top. A gate insulating layer 282 may also be disposed below a gate layer 281 located at the bottom. Each gate layer 281 may include a plurality of gate lines.

[0100] The material of the gate insulating layer 282 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and a high dielectric constant insulating material, or other suitable materials. The gate layer 281 may include a conductive material, including but not limited to any combination of one or more of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, and silicide. In some embodiments, each gate layer 281 includes a metal layer, such as a tungsten layer. In some examples, each gate layer 281 may include a doped polysilicon layer.

[0101] The array device 200 may further include a source layer SL, and the stack structure 280 is stacked with the source layer SL.

[0102] The source layer SL may include a semiconductor material, such as single crystal silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Exemplarily, the source layer SL may include a doped region, and the doped region is doped with a p-type dopant. The source layer SL may also include a non-doped region.

[0103] The array device 200 may further include a channel structure 270, and the channel structure 270 penetrates the stack structure 280. In some embodiments, the channel structure 270 also extends into the source layer SL to achieve electrical connection between the channel structure 270 and the source layer SL.

[0104] In some embodiments, the channel structure 270 includes an insulating column penetrating the stacked structure 280, and a channel layer, a tunnel layer, a charge storage layer, and a barrier layer sequentially arranged outside the insulating column. The storage function layer may include: a tunnel layer, a charge storage layer, and a barrier layer.

[0105] The material of the channel layer may include a semiconductor material, such as a combination of one or more of amorphous, polycrystalline or single crystal silicon. The channel layer may be electrically connected to the source layer SL.

[0106] The material of the tunneling layer may include an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, or silicon oxynitride. Electrons and holes in the channel layer may tunnel to the charge storage layer through the tunneling layer.

[0107] The charge storage layer may be configured to store charge, and one or more memory cells in the memory cell string may be operated by storing charge in the charge storage layer or removing charge from the charge storage layer. The material of the charge storage layer may include silicon nitride, silicon oxynitride, silicon, or a combination of one or more thereof.

[0108] The blocking layer may be configured to prevent charges stored in the charge storage layer from leaking toward the gate line. The material of the blocking layer may include an insulating material, for example, the material of the blocking layer is a combination of one or more of silicon oxide, silicon nitride, or silicon oxynitride.

[0109] Fig.18 is a structural diagram of a memory cell string according to some embodiments. Fig.19 is an equivalent circuit diagram of a memory cell string according to some embodiments.

[0110] See also Fig.18 and Fig.19 The array device 200 may include a plurality of memory cell transistor strings (referred to herein as “memory cell strings”, such as NAND memory cell strings) 400. The source layer SL may be coupled to source terminals of the plurality of memory cell strings 400.

[0111] Specifically, see Fig.18 and Fig.19 , the memory cell string 400 may include a plurality of transistors T, a transistor T (eg Fig.19The transistors T1 to T6 in the embodiment of the present invention can be set as a memory cell, and these transistors T are connected together to form a memory cell string. A transistor T (for example, each transistor T) can be formed by a channel structure 270 and a gate line G surrounding the channel structure 270. The gate line G is configured to control the conduction state of the transistor.

[0112] It should be noted that Fig.19 The number of transistors is only illustrative, and the storage cell string of the three-dimensional memory provided by the embodiment of the present disclosure may also include other numbers of transistors, such as 4, 16, 32, or 64.

[0113] Further, the gate line located at the bottom among the multiple gate lines G (for example, the gate line closest to the source layer SL among the multiple gate lines G) is constructed as a source selection gate SGS, and the source selection gate SGS is configured to control the conduction state of the transistor T6, thereby controlling the conduction state of the source channel in the memory cell string 400. The gate line located at the top among the multiple gate lines G (for example, the gate line farthest from the source layer SL among the multiple gate lines G) is constructed as a drain selection gate SGD, and the drain selection gate SGD is configured to control the conduction state of the transistor T1, thereby controlling the conduction state of the drain channel in the memory cell string 400. The gate line located in the middle among the multiple gate lines G can be constructed as a plurality of word lines WL, for example, including word line WL0, word line WL1, word line WL2, and word line WL3. By writing different voltages on the word lines WL, data writing, reading, and erasing of each memory cell (for example, transistor T) in the memory cell string 400 can be completed.

[0114] Continue to see Fig.17 In some embodiments, the array device 200 may further include an array interconnect layer 290. The array interconnect layer 290 is located on a side of the stack structure 280 away from the source layer. The array interconnect layer 290 may be coupled to the memory cell string 400. The array interconnect layer 290 may include a drain terminal (i.e., a bit line BL) of the memory cell string 400, and the drain terminal may be coupled to each transistor T in at least one memory cell string 400.

[0115] The array interconnect layer 290 may include one or more first insulating layers 292. The array interconnect layer 290 may also include one or more first conductor layers 291. The first conductor layer 291 may include a plurality of connection lines, such as bit lines, and word line connection lines coupled to word lines. The material of the first conductor layer 291 may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the first insulating layer 292 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0116] The peripheral device 100 may include peripheral circuits. The peripheral circuits are configured to control and sense the array device 200. The peripheral circuits may be any suitable digital, analog, and / or mixed signal control and sensing circuits for supporting the operation (or work) of the array device 200, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits may also include any other circuits compatible with advanced logic processes, including logic circuits (e.g., processors and programmable logic devices (PLDs)) or storage circuits (e.g., static random access memories (SRAMs)).

[0117] Specifically, in some embodiments, the peripheral device 100 may include a substrate 110, a transistor 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuit may include the transistor 120. The material of the substrate 110 may be single crystal silicon, or other suitable materials, such as silicon germanium, germanium, or silicon-on-insulator thin film.

[0118] The peripheral interconnection layer 130 is coupled to the transistor 120 to transmit electrical signals between the transistor 120 and the peripheral interconnection layer 130. The peripheral interconnection layer 130 may include one or more second insulating layers 131, and may also include one or more second conductor layers 132. The material of the second conductor layer 132 may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the second insulating layer 131 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0119] The array device 200 is coupled to the peripheral device 100. The peripheral device 100 may be disposed at a side of the stack structure 280 away from the source layer SL.

[0120] For example, the peripheral interconnect layer 130 may be coupled to the array interconnect layer 290, so that the array device 200 and the peripheral device 100 may be coupled. Specifically, since the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, the peripheral circuit in the peripheral device 100 may be coupled to the memory cell string 400 in the array device 200, so as to realize the transmission of electrical signals between the peripheral circuit and the memory cell string 400. In some possible implementations, a bonding interface 500 may be provided between the peripheral interconnect layer 130 and the array interconnect layer 290, and the peripheral interconnect layer 130 and the array interconnect layer 290 may be bonded and coupled to each other through the bonding interface 500.

[0121] In some examples, when the first semiconductor structure 10 is an array device and the second semiconductor structure 60 is a peripheral device, the first interconnection layer 40 is an array interconnection layer and the second interconnection layer 50 is a peripheral interconnection layer. In other examples, when the first semiconductor structure 10 is a peripheral device and the second semiconductor structure 60 is an array device, the first interconnection layer 40 is a peripheral interconnection layer and the second interconnection layer 50 is an array interconnection layer.

[0122] The embodiment of the present disclosure also provides a storage system. Fig. 20 is a block diagram of a storage system according to some embodiments. Fig.21 is a block diagram of a storage system according to some other embodiments. Fig. 20 and Fig.21 , some embodiments of the present disclosure provide a storage system 1000. The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (for example, a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 1000 can be applied to and packaged into different types of electronic products, for example, mobile phones (such as mobile phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0123] The storage system 1000 includes a controller 1200 and a three-dimensional memory 1100, wherein the controller 1200 is coupled to the three-dimensional memory 1100. The controller 1200 is used to control the three-dimensional memory 1100 to store data.

[0124] For example, see Fig. 20The storage system 1000 includes a controller 1200 and a three-dimensional memory 1100. The storage system 1000 can be integrated into a memory card. The memory card includes any one of a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD) card, and a UFS.

[0125] Also illustratively, see Fig.21 The storage system 1000 includes a controller 1200 and a plurality of three-dimensional memories 1100. The storage system 1000 is integrated into a solid state drive (SSD).

[0126] In the storage system 1000, in some embodiments, the controller 1200 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In other embodiments, the controller 1200 is configured to operate in a high duty cycle environment SSD or eMMC, which is used for data storage in mobile devices such as smart phones, tablets, and laptops, as well as enterprise storage arrays.

[0127] Exemplarily, the controller 1200 may be configured to manage data stored in the three-dimensional memory 1100 and communicate with an external device (e.g., a host). Exemplarily, the controller 1200 may also be configured to control operations of the three-dimensional memory 1100, such as read, erase, and program operations. Exemplarily, the controller 1200 may also be configured to manage various functions regarding data stored or to be stored in the three-dimensional memory 1100, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. Exemplarily, the controller 1200 is also configured to process error correction codes regarding data read from or written to the three-dimensional memory 1100.

[0128] Of course, the controller 1200 may also perform any other suitable functions, such as formatting the three-dimensional memory 1100; for example, the controller 1200 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0129] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0130] Some embodiments of the present disclosure also provide an electronic device. The electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0131] The electronic device may include the storage system 1000 described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0132] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A bearing structure, characterized in that: include: substrate; The insulating support layer is located on one side of the substrate, and comprises a base layer, a plurality of support structures and connecting grooves between the plurality of support structures. The plurality of support structures are located on a side of the base layer away from the substrate.

2. The bearing structure according to claim 1, characterized in that: The ratio of the total area of ​​the surface of the plurality of support structures facing away from the base layer to the total area of ​​the surface of the base layer close to the substrate is 50% to 70%.

3. The bearing structure according to claim 2, characterized in that: The distance between adjacent support structures is 200nm-500nm.

4. The bearing structure according to claim 2, characterized in that: The distance between the surface of the support structure facing away from the base layer and the base layer is 100 nm to 500 nm.

5. The bearing structure according to any one of claims 1 to 4, characterized in that: The multiple supporting structures are arranged in multiple rows and columns.

6. The bearing structure according to claim 5, characterized in that: The support structures in two adjacent rows are staggered along the column direction.

7. The bearing structure according to any one of claims 1 to 4, characterized in that: The multiple support structures form a plurality of support units, and the multiple support units are arranged in multiple rows and columns. Each support unit includes a plurality of sub-support units diffusely arranged from the center to the periphery, and each sub-support unit includes a plurality of the support structures arranged in sequence around the center.

8. The bearing structure according to any one of claims 1 to 4, characterized in that: The orthographic projections of the plurality of support structures on the base layer include at least one of a circle, an ellipse, a triangle, or a rectangle.

9. The bearing structure according to any one of claims 1 to 4, characterized in that: The material of the insulating support layer includes at least one of oxide, silicon nitride and a degradable nanocomposite material.

10. A method for preparing a load-bearing structure, characterized in that: The preparation method comprises: providing a substrate; An insulating support layer is formed on one side of the substrate; the insulating support layer comprises a base layer, a plurality of support structures and connecting grooves between the plurality of support structures, wherein the plurality of support structures are located on a side of the base layer away from the substrate.

11. The preparation method according to claim 10, characterized in that: The step of forming an insulating support layer on one side of the substrate comprises: forming an insulating film layer on one side of the substrate; A portion of the insulating film layer is removed to form the insulating support layer including the base layer and the plurality of support structures.

12. The preparation method according to claim 11, characterized in that: The removing part of the insulating film layer comprises: A portion of the insulating film layer is etched through a mask.

13. A method for preparing a three-dimensional memory, characterized in that: include: Forming a load-bearing structure by the preparation method according to any one of claims 10 to 12; forming a first semiconductor structure on a side of the insulating support layer away from the substrate; forming a second semiconductor structure on a side of the first semiconductor structure away from the insulating support layer; The insulating support layer is removed to separate the substrate from the first semiconductor structure.

14. The method for preparing a three-dimensional memory according to claim 13, characterized in that: The removing of the insulating support layer comprises: The wet etching process is used to allow etching liquid to enter the connecting groove to remove the insulating support layer.

15. The method for preparing a three-dimensional memory according to claim 13, characterized in that: After the step of forming the first semiconductor structure on the side of the insulating support layer away from the substrate and before the step of forming the second semiconductor structure on the side of the first semiconductor structure away from the insulating support layer, the method further includes: forming a protective layer, wherein the protective layer is located on a side of the substrate; Before removing the insulating support layer, the method further comprises: The protective layer is removed.

16. The method for preparing a three-dimensional memory according to claim 15, characterized in that: The material of the protection layer is the same as that of the insulating support layer.

17. The method for preparing a three-dimensional memory according to claim 15 or 16, characterized in that: The protection layer is also located on the side surface of the first semiconductor structure and the side surface of the insulating support layer.

18. The method for preparing a three-dimensional memory according to claim 13, characterized in that: The first semiconductor structure is one of an array device and a peripheral device, and the second semiconductor structure is the other of the array device and the peripheral device.

19. A storage system, characterized in that: include: A three-dimensional memory prepared by the method for preparing a three-dimensional memory according to any one of claims 13 to 18; The controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

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