Active biasing and terminating methods for distributed amplifier circuits

Abstract

The invention relates to an active bias and termination method for a distributed amplifier circuit. An integrated distributed amplifier circuit may include an input transmission line structure comprising: a first cell comprising a first reactive circuit element and a first active circuit element; an output transmission line structure including a second unit including a second reactive circuit element and a second active circuit element; and a termination circuit coupled to one end of the input transmission line structure. The termination circuit may include a current mirror circuit to establish a specified bias current for biasing a respective first active circuit element of the input transmission line structure. This approach may provide one or more of a broadband termination impedance and a stable bias condition at different frequencies and power output levels.

Description

Technical Field

[0001] This document relates generally, but not limited to, amplifier circuits that may be implemented as integrated circuits and, more particularly, to biasing and transmission line termination circuits for integrated amplifier circuits that may have a distributed amplifier (DA) topology. Background Art

[0002] Integrated circuit technology can be used to implement a variety of different amplifier circuit topologies. One class of amplifiers can include monolithically integrated broadband amplifier circuits. For example, when implemented using high electron mobility transistor (HEMT) devices, such circuits can have higher operating frequency specifications in the tens of gigahertz (GHz) range. Depending on the application, such circuits can have a minimum operating frequency specification that is several orders of magnitude lower in frequency. For example, in some applications, such a minimum operating frequency specification can be in the megahertz (MHz) range, or even lower (e.g., one or tens of KHz). Applications for such broadband amplifiers can include communications, electronic warfare, radar, or metering, such as supporting terrestrial cellular or microwave communications, electrical signal chain components in fiber-optic communication systems, aviation or satellite-based communication systems, or remote sensing, as illustrative (but not limiting) examples. Broadband amplifier circuits can also provide flexibility, such as forming part of a signal chain in a software-defined radio architecture, particularly where such a radio architecture is frequency agile.

[0003] Different integrated amplifier circuit topologies can be used to achieve acceptable gain, linearity, and noise performance over a specified broadband operating frequency range. In one approach, a distributed amplifier (DA) topology can be used. Typically, a DA topology includes corresponding amplifier circuit sections (e.g., transconductor circuits) arranged in a cascaded manner to provide enhanced gain or bandwidth, or a combination of both (e.g., gain-bandwidth product) compared to a single amplifier circuit section. Summary of the invention

[0004] A distributed amplifier (DA) circuit topology typically includes amplifier circuit portions coupled to each other in a cascaded manner, as described above. As an example, a DA circuit may include an amplifier circuit portion that includes a cascade circuit topology in which the corresponding portions are coupled to each other using reactive circuit elements. In this manner, the corresponding transistors and reactive circuit elements may form cells of an artificial transmission line structure, in which the transistors provide shunt capacitance and the reactive circuit elements provide series inductance. As an example, a DA circuit may be implemented monolithically using field effect transistors (FETs), using monolithic co-integrated transmission line segments or monolithic co-integrated inductors to form amplifier circuit portions coupled to each other to provide series inductance between the corresponding amplifier circuit portions, with the gate-to-source capacitance of the corresponding FET providing shunt capacitance for the corresponding cell.

[0005] The signal input port of the DA circuit may include a node coupled to the gate structure of a corresponding FET defining an artificial input transmission line structure. In order to provide impedance matching within a specified operating frequency range, the input port and output port of the transmission line structure are typically coupled to a matching impedance corresponding to the characteristic impedance of the transmission line (nominal real-valued impedance of about 50 ohms). Such matching impedance may include the use of a discrete termination circuit at the end of the transmission line. In one approach, the termination circuit may include a passive circuit, such as a resistor, and one or more other components, such as one or more alternating current (AC) coupling capacitors connected in series with the termination resistor. The termination resistor may be implemented on the chip and monolithically integrated with other components. The AC coupling capacitor may also be located on the chip, or a combination of on-chip and off-chip components may be used.

[0006] The present inventors have recognized that the use of off-chip passive components may present various challenges. Such challenges may include undesirable resonances formed by a combination of lead or bond wire loop inductances or other packaging parasitics (e.g., in combination with AC coupling capacitors). For example, such resonances may result in non-uniformity in gain and return loss performance across frequency. Such an arrangement may also be inefficient in terms of circuit area. The present inventors have recognized that the use of on-chip termination circuits may help address such challenges, and such termination circuits may use passive circuits, or active termination circuits (e.g., transistor-based circuits in which the transistors themselves are used as termination load devices), or a combination thereof.

[0007] The inventors have also recognized that for the input transmission line structure of the DA circuit, the use of an active termination circuit can also provide a direct current (DC) gate bias for the input device in the corresponding amplifier circuit portion. For example, a diode-connected transistor topology (e.g., a FET circuit with the drain and source connected to each other) can provide a current mirror circuit, such as establishing a desired bias current through the input device in the corresponding amplifier circuit portion while providing a termination impedance for the input transmission line. In this way, the diode-connected transistor topology can provide a current reference.

[0008] As shown in the figure, and as shown by simulation results, using the termination and biasing method described in this article can provide enhanced performance in a DA circuit, such as a DA circuit implemented using a gallium arsenide (GaAs) enhancement mode pseudomorphic high electron mobility transistor device (e-mode pHEMT), allowing the DA circuit to operate to a lower operating frequency (e.g., 1 MHz to 10 MHz or lower operating frequency limit) compared to an approach using a passive off-chip termination circuit, while still maintaining high frequency performance. This approach is also applicable to other transistor types and semiconductor materials.

[0009] In one example, a distributed amplifier circuit includes: an input transmission line structure including a first unit, a corresponding one of the first units including a first reactive circuit element and a first active circuit element, the first reactive circuit element is coupled to an input node of the first active circuit unit, an input port of the input transmission line structure defines a signal input port of the distributed amplifier circuit, an output transmission line structure including a second unit, a corresponding one of the second units including a second reactive circuit element and a second active circuit element, the second reactive circuit element is coupled to an output node of the second active circuit element, an output port of the output transmission line structure defines an amplified signal output port of the distributed amplifier circuit, and a termination circuit coupled to one end of the input transmission line structure, the termination circuit is configured to establish a specified termination impedance, the termination circuit includes a current mirror circuit to establish a specified bias current for biasing a corresponding first active circuit element of the input transmission line structure. The corresponding first active circuit element can be coupled with the corresponding second active circuit element to form a corresponding amplifier circuit, the corresponding amplifier circuit using the corresponding first reactive circuit element and the corresponding second reactive circuit element to be coupled to each other in a cascade manner.

[0010] In one example, the current mirror circuit is configured to establish the specified bias current and act as a dissipative element terminating the input transmission line structure. For example, the current mirror circuit may include a diode-connected transistor co-integrated monolithically with the corresponding first active circuit element and the corresponding second active circuit element. In another example, the termination circuit includes a passive termination coupled to the current mirror circuit.

[0011] In one example, the termination circuit includes a driver circuit, the driver circuit being controlled by the current mirror circuit and configured to maintain the specified bias current for biasing the corresponding first active circuit element. A resistor located within a feedback loop defined by the driver circuit and the current mirror circuit can at least partially provide termination.

[0012] In one example, a distributed amplifier circuit includes an input transmission line structure, an output transmission line structure, and an output transmission line, a termination circuit coupled to one end of the input transmission line structure, the termination circuit being configured to establish a specified termination impedance, the termination circuit including a current mirror circuit to establish a specified bias current for biasing a corresponding first active circuit element of the input transmission line structure, and a feedback resistor coupled between a node corresponding to an end of the input transmission line structure and a node of an output port of the output transmission line structure, the value of the feedback resistor at least partially establishing the specified bias current. The current mirror circuit may be monolithically co-integrated with the corresponding first active circuit element, and the distributed amplifier circuit may include a bias control node coupled to the current mirror circuit, the bias control node being coupleable to a bias control component that is not monolithically co-integrated with the current mirror circuit.

[0013] In one example, a monolithically integrated distributed amplifier circuit includes: an input transmission line structure including a corresponding first active circuit element, an output transmission line structure including a corresponding second active circuit element, and a termination circuit coupled to one end of the input transmission line structure, the termination circuit being configured to establish a specified termination impedance, the termination circuit including a current mirror circuit to establish a specified bias current for biasing the corresponding first active circuit element of the input transmission line structure. The corresponding first active circuit element and the corresponding second active circuit element may include compound semiconductor high electron mobility transistors (HEMTs), and the current mirror circuit includes a diode-connected field effect transistor (FET).

[0014] This summary is intended to provide an overview of the subject matter of this patent application. It is not intended to provide an exclusive or exhaustive explanation of the present invention. The detailed description is included to provide further information about this patent application. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In the accompanying drawings, which are not necessarily drawn to scale, like numbers may describe similar parts in different views. Like numbers with different letter suffixes may represent different instances of similar components. The accompanying drawings generally illustrate various embodiments discussed in this document by way of example and not by way of limitation.

[0016] Figure 1 An example is shown representing a distributed amplifier (DA) circuit topology including an active termination circuit that may also provide gate bias.

[0017] Figure 2 An illustrative example of simulated return loss (corresponding to active termination circuit impedance) versus frequency is shown, showing matching performance to tens of GHz.

[0018] Figure 3Illustrative examples of simulated output power versus input power for various frequencies are shown, illustrating gain compression behavior due at least in part to the use of an active termination circuit.

[0019] Figure 4A Shown by Figure 1 Illustrative example of simulated forward transmission gain (e.g., S21 parameter) of a DA circuit.

[0020] Figure 4B Shown by Figure 1 illustrative example of simulated input return loss (e.g., S11 parameter) of a DA circuit.

[0021] Figure 4C Shown by Figure 1 illustrative example of simulated output return loss (eg, S22 parameter) of a DA circuit.

[0022] Figure 5A An illustrative example of a simulated noise factor (in dB, corresponding to the noise figure, plotted against frequency using a logarithmic scale for the frequency axis) is shown, which would be similar to Figure 1 However, the DA circuit using passive termination is different from the one including active termination. Figure 1 DA circuit for comparison.

[0023] Figure 5B An illustrative example of a simulated noise factor (in dB, corresponding to the noise figure, plotted against frequency using a linear scaling of the frequency axis) is shown, which would be similar to Figure 1 However, the DA circuit using passive termination is different from the one including active termination. Figure 1 DA circuit for comparison.

[0024] Figure 6 An example is shown representing a distributed amplifier (DA) circuit topology including an active termination circuit that may also provide gate bias, where the active termination circuit includes a driver circuit (eg, a source follower circuit) and a corresponding feedback loop.

[0025] Fig. 7A Shows the observation Figure 6 Illustrative examples of simulated return loss (e.g., S11 parameter) for a termination circuit of FIG. 1 , where no external capacitor (CEXT) is used and a fixed termination bypass capacitor (CBYP) value is used, showing the effect of different RC filter (C1) capacitor values.

[0026] Figure 7B Shows the observation Figure 6illustrative example of simulated return loss (e.g., S11 parameter) of a termination circuit using a fixed termination bypass capacitor (CBYP) value and a fixed RC filter (C1) capacitor value, showing the effect of different external capacitor (CEXT) values.

[0027] Fig. 8A Shows Figure 6 Illustrative examples of simulated noise factor (in dB, corresponding to noise figure, plotted against frequency using a logarithmic scale for the frequency axis) of a DA circuit with no external capacitor (CEXT) used and with a fixed termination bypass capacitor (CBYP) value, showing the effect of different RC filter (C1) capacitor values.

[0028] Figure 8B Shows Figure 6 Illustrative example of the simulated noise factor (in dB, corresponding to the noise figure, plotted against frequency using a logarithmic scale for the frequency axis) of a DA circuit using a fixed termination bypass capacitor (CBYP) value and a fixed RC filter (C1) capacitor value, showing the effect of different external capacitor (CEXT) values.

[0029] Fig.9A An illustrative example of simulated output power versus input power for different source follower bias current levels is shown for a fixed terminating bypass capacitor (CBYP) value and an operating frequency of 10 MHz, illustrating the gain compression behavior.

[0030] Fig. 9B Illustrative examples of simulated output power versus input power for different operating frequencies are shown, illustrating the gain compression behavior for a fixed termination bypass capacitor (CBYP) value and a fixed source follower bias level of 4 milliamps (mA).

[0031] Fig. 10A Illustrative examples of simulated output third order intercept (IP3) values ​​for different operating frequencies are shown without CBYP, a fixed source follower bias level of 4 mA, and a 1 MHz tone spacing.

[0032] Fig. 10B Illustrative examples of simulated output third order intercept (IP3) values ​​for different operating frequencies are shown, using a fixed termination bypass capacitor (CBYP) value, a fixed source follower bias level of 4 mA, and a 1 MHz tone spacing.

[0033] Fig. 10C Illustrative examples of simulated output third order intercept (IP3) values ​​for different source follower bias current values ​​are shown, using fixed termination bypass capacitor (CBYP) values ​​and 1 MHz tone spacing. DETAILED DESCRIPTION

[0034] A distributed amplifier (DA) circuit typically includes a termination circuit at the end of an input transmission line structure that matches the characteristic impedance of the transmission line structure (e.g., provides a similar real-valued impedance or a conjugate complex-valued impedance). For example, when the DA circuit is implemented using field effect transistors (FETs), the input transmission line can be referred to as a "gate transmission line." The termination circuit is typically configured to achieve high return loss (e.g., corresponding to matching performance) and flat gain over a specified operating bandwidth of the DA circuit. As described elsewhere herein, in one approach, a resistor (e.g., a passive termination) can be used to establish such a termination.

[0035] Because the amplifier transistors in the DA circuit are DC biased, the passive gate termination resistor can be connected to the reference node through an AC coupling capacitor, or a DC blocking capacitor can be placed in the circuit to isolate the transistor DC bias from being disturbed by the gate termination resistor. The use of AC coupling capacitors or DC blocking capacitors (or both) may affect the minimum operating frequency limit of the DA circuit. Larger values ​​of AC coupling capacitors or DC blocking capacitors can be used to enhance the minimum operating frequency performance (e.g., pushing the minimum operating frequency limit to a lower frequency). However, such capacitors are typically located "off chip" because their capacitance values ​​are relatively large and they form resonances due to interaction with parasitic inductances (e.g., integrated circuit package wire bonds) or other interconnect structures (e.g., circuit board traces), and such resonances can cause undesirable ripples in the gain and input return loss responses of the DA circuit.

[0036] The examples in this article can address one or more challenges, such as those mentioned above. For example, the following Figure 1 and Figure 6 The described examples can provide both DC bias and broadband termination impedance to meet specified input return loss and flat gain without requiring multiple large value off-chip AC coupling capacitors. By way of example, using the typically achievable on-chip capacitor values ​​and topologies shown herein, a minimum operating frequency limit of about 1 MHz (or less) can be achieved. If off-chip capacitors are added, such capacitors can optionally be isolated from the broadband amplification portion of the DA circuit to avoid interfering with return loss or affecting gain flatness, and a minimum operating frequency limit in the kHz or less range can be achieved.

[0037] Figure 1 An example is shown representing a distributed amplifier (DA) circuit 100 topology including an active termination circuit 108A that may also provide gate bias. Figure 1The DA circuit 100 may include multiple amplifier circuit sections, such as a first amplifier circuit section 106A including monolithically integrated enhancement mode FET devices M1A and M2A, arranged in cascade with a second amplifier circuit section 106B including FET devices M1A and M2B, and a last amplifier circuit section 106N including FET devices M1N and M2N. Respective transmission line structures couple the respective amplifier circuit sections to each other so that each amplifier circuit section 106A, 106B, ... 106N makes a gain contribution. In this way, the gain-bandwidth product of the DA circuit 100 is enhanced overall compared to using a single amplifier circuit section. For various applications, the number of amplifier circuit sections 106A, 106B, ... 106N may be in the range of three to ten sections, or more.

[0038] As mentioned above, the DA circuit can establish a corresponding transmission line structure. Figure 1 As shown, the DA circuit 100 may include an input transmission line structure 102, for example, to establish an "artificial" transmission line formed by individual unit cells, corresponding to discrete elements, but without the need for discrete passive lumped elements. The input transmission line structure 102 may include a first unit, the first unit including a FET device (e.g., M1A) and a first reactive circuit element X1A (e.g., an integrated circuit transmission line segment or an integrated inductor) connected to the gate of the FET device M1A. In this way, the gate-source junction of the FET device M1A, together with the series inductance provided by the first reactive circuit element X1A, contributes a shunt capacitance to the artificial transmission line unit cell. Each corresponding amplifier circuit portion 106A, 106B, ... 106N can establish a corresponding unit along the input transmission line structure 102.

[0039] The DA circuit may also include an output transmission line structure to create another artificial transmission line, namely, output transmission line structure 104. For example, Figure 1As shown, the output transmission line structure 104 may include a second unit, the second unit including a FET device (e.g., M2A) and a first reactive circuit element X2A (e.g., an integrated circuit transmission line segment or an integrated inductor) connected to the drain of the FET device M2A. The output end of the output transmission line structure 104 may include a node RFOUT, for example, providing a portion of the signal output port of the DA circuit (e.g., a single-ended output port defined as node RFOUT and a reference node such as VSS). Generally, the output transmission line structure 104 may also be used to provide power to the FET devices M2A, M2B, ... M2N, for example including a node 116 located at the output end of the output transmission line architecture 104, the node 116 being powered by a positive power supply VDD, for example through a bias network (e.g., including a series inductor 114, which is located off-chip from the rest of the DA circuit 100). The opposite end of the output transmission line structure 104 may include a passive circuit 112 for termination and gate biasing of the FET devices M2A, M2B, ... M2N. The gate bias circuit for M2A, M2B, ... M2N may include series circuit elements XGA, XGB, e.g. Figure 1 shown.

[0040] The input end of the input (e.g., gate coupled) transmission line structure 102 may include a node RFIN, for example, providing a portion of a signal input port to the DA circuit 100 (e.g., a single-ended input port defined as the node RFIN and a reference node such as VSS). One end of the input transmission line structure 102 may be terminated using an active termination circuit 108A. The inventors have recognized that the active termination circuit 108A may also provide gate bias for each FET device M1A, M1B, ... M1N while providing a specified termination impedance. Figure 1 As shown, the termination circuit may include a FET device F1 arranged in a diode-connected configuration with the gate input and drain nodes connected together. A feedback resistor RFB or an external bias resistor RB (or both) may be used to establish a DC bias reference current I through the FET device F1. REF , thereby providing a current mirror circuit topology to induce a corresponding (eg, proportional to a first order approximation) bias current I through the corresponding amplifier circuit portion 106A, 106B, ... 106N. RF Typically, the FET device F1 is similar to the corresponding FETs M1A, M1B, ... M1N, for example with a proportionally smaller periphery, a different gate width or gate index, such that I RF Under static conditions, I REF The physical characteristics of F1, such as geometry and location, can be established to reduce or suppress I in addition to meeting the specified termination impedance value. REF Variations with temperature and process variations.

[0041] Figure 1 The configuration of the active termination circuit 108A differs from the active biasing approach in that the FET device F1 is not used as a dissipative termination circuit element. In this non-termination approach, an inductor or a large value resistor (e.g., in the kilo-ohm (kW) range) would typically be used to couple the current mirror bias circuit to the amplifier circuit portion 106N. Figure 1 In the approach shown, no such inductor or large value resistor is required, and the active termination circuit 108A can be directly connected to the amplifier circuit portion 106N to provide a specified termination impedance (e.g., a real valued impedance of approximately 50 ohms or appropriate real impedance and reactive impedance to provide a conjugate match to the input transmission line structure 102).

[0042] Alternatively, if Figure 1 As shown, a monolithically integrated feedback resistor RFB may be included as part of the DA circuit 100. Figure 1 In the method shown, a DC blocking capacitor in series with RFM is not required, and therefore, the value of RFB can at least partially help set the reference current I REF Because RFB generally has a value established to achieve the amplification performance (eg, gain flatness or linearity) of the DA circuit 100, RFB may not have a value low enough to achieve the desired reference current I REF Optionally, another resistor RB (on-chip or off-chip) can be used to establish the desired reference current I for gate biasing. REF , without interfering with the feedback behavior provided by RFB. For example, a bias control node (BIAS), such as an integrated circuit pad or integrated package "pin", can expose BIAS that can be coupled to an off-chip resistor RB or other bias control component.

[0043] If RB is used, a DC blocking capacitor may be included in series with RFB, and accordingly, RB will be used to set I REF , or RFB may be omitted entirely. Such an approach may provide more flexible selection characteristics for F1 to provide a specified (e.g., 50 ohm) termination impedance. Including a DC blocking capacitor in series with RFB may result in a higher minimum operating frequency of the DA circuit 100 (e.g., generally increase the minimum operating frequency).

[0044] Figure 2 An illustrative example of simulated return loss (corresponding to the impedance of the active termination circuit 108A) versus frequency is shown, showing matching performance over tens of GHz. Figure 2 As shown, less than -10dB S 11The value corresponds to a return loss of 10 dB or higher (eg, better), or a voltage standing wave ratio (VSWR) of approximately 2:1 or better.

[0045] Figure 3 Illustrative examples of simulated output power versus input power for various frequencies are shown, illustrating gain compression behavior due at least in part to the use of active termination circuit 108A. Using diode-connected FET structures, rather than more, may result in changes in gain compression behavior with respect to frequency, such as exhibiting an increasingly non-monotonic compression curve as frequency increases. This effect may be due to the rectification provided by FET device F1 to an AC signal (e.g., an RF signal) amplified by DA circuit 100. As the input signal power of DA circuit 100 increases, the rectification may perturb the biasing of FET devices M1A, M1B, ... M1N by reducing the gate-to-source voltage, biasing such FET devices downward, and reducing the corresponding drain current. Figure 6 Methods can help reduce or suppress this gain "flip" (where the output power changes from a positive slope to a negative slope in response to increasing input power) in the DA circuit 100, such as using a combination of a termination resistor and a source follower as a drive circuit. In particular, the source follower can reduce or suppress the under-bias behavior described above.

[0046] Figure 4A Shown by Figure 1 1 is an illustrative example of simulated forward transmission gain (eg, S21 parameter) of the DA circuit 100. The gain performance shows a relatively flat gain at frequencies below 25 GHz (-3 dB). Figure 4B Shown by Figure 1 The analog input return loss of the DA circuit 100 circuit (for example, S 11 Parameter), showing an RF input match with better than 10 dB (corresponding to a return loss of S11 parameter of -10 dB or less) just below 25 GHz. Figure 4C Shown by Figure 1 The simulated output return loss of the DA circuit 100 (e.g., S 22 Parameters), and also shows an output match with better than 10dB return loss through about 25GHz. Figure 4A , Figure 4B and Figure 4C It is also shown that the low frequency performance of the DA circuit 100 extends down to at least 1 KHz or lower, where Figure 4A , 4B The simulations of 4C span the frequency range from 1KHz to 30GHz.

[0047] For comparison, Figure 5AAn illustrative example of a simulated noise factor (in dB, corresponding to the noise figure, plotted against frequency using a logarithmic scale for the frequency axis) is shown, which would be similar to Figure 1 However, the DA circuit using passive termination is different from the one including active termination. Figure 1 The DA circuit is compared and Figure 5B A schematic example of a simulated noise factor (in dB, corresponding to the noise figure, plotted against frequency using a linear scale for the frequency axis) is shown. Figure 1 The use of the active termination circuit 108A approach relative to passive resistive termination can provide a noise factor (corresponding to noise figure) that is approximately 1.5 dB lower (better) than the passive resistive termination approach at low frequencies (eg, to 1 kHz or lower).

[0048] Figure 6 An example of a distributed amplifier (DA) circuit 600 topology is shown, which includes a termination circuit 108B that can also provide a gate bias, wherein the termination circuit 108B includes a driver circuit (e.g., a "helper") that includes a FET device F2 (e.g., arranged as a source follower circuit) and a corresponding feedback loop, wherein the loop is composed of a current mirror circuit reference FET device F1, a series resistor R1, a termination resistor R TERM and FET device F2. DA circuit 600 can be similar to Figure 1 DA circuit 100, whose architecture includes a cascade amplifier circuit portion, such as a final amplifier circuit portion 106N including FET devices M1N and M2N, an input transmission line structure 102 (having a final unit including M1N and a reactive circuit element X1N), an output transmission line structure 104 (having a final unit including M2N and a reactive circuit element X2N), an internal power supply node 116 powered by a power supply VDD, such as through an inductor 114, and includes an output port defined by a node RFOUT 110. The drain terminal of the FET device F2 can be coupled to the internal power supply node 116, such as through a resistor R3, so as to isolate the FET device F2 from the RF output signal provided at RFOUT. As another example, the drain terminal of the FET device F2 can be exposed via a pad or a package pin, such as can be coupled to the power supply VDD off-chip, such as at a node 115, wherein the inductor 114 isolates the node 115 from the RF output signal at RFOUT.

[0049] Similar to Figure 1 In this way, the current mirror reference FET device F1 can have a resistor RB (e.g. Figure 6The reference current I can be set by using an on-chip current source, for example, in the case of using a complementary transistor manufacturing process. REF .and Figure 1 compared to, Figure 6 The termination circuit 108B includes a passive termination resistor R connected in series between the input transmission line structure 102 and the source node of the driver circuit FET device F2. TERM In this way, the terminating resistor R TERM Within the feedback loop of the current mirror reference circuit, and the loop gain behavior presents a low impedance observed across the termination circuit 108B within the loop bandwidth, thereby allowing the DC gate bias voltages and corresponding drain currents of the devices M1A, M1B, ... M1N to be maintained. For example, the loop bandwidth may be set using monolithic co-integrated capacitors without the need for external off-chip capacitors. As an example, the loop bandwidth may be set to approximately 1 MHz (e.g., where the loop gain drops to approximately 0 dB), such as dominated by the pole established using the combination of R1 and C1 values ​​in the termination circuit 108B. A low frequency pole may be created, such as using RB and C EXT The combination of C EXT The amplifier section (e.g., 106N) is effectively decoupled. In this way, C EXT The high frequency performance of the DA circuit 600 will not be affected by undesired resonance. EXT The use of a combination of can extend the loop bandwidth down to the KHz range (see the simulation results below, for example Figure 7B and Figure 8B As an illustrative example, in the absence of an off-chip C EXT capacitor case, where C1 is set to 5pF, and where C BYP is set to 2pF, simulation results show that, assuming a source follower bias current of 4mA, the phase margin of the feedback loop of termination circuit 108B is greater than 90 degrees (where the loop gain drops to 1 at approximately 2MHz) and the gain margin is greater than 40dB. EXT Set to 10nF, the 0dB bandwidth is just over 1KHz, with a phase margin greater than 90 degrees, and a corresponding gain margin of tens of dB.

[0050] exist Figure 6 In the example, capacitor C BYP is shown at the source node of the source follower FET device F2. BYPCan help maintain a specified termination impedance over the operating bandwidth of the DA circuit 600. Resistor R2 can provide a DC bias for the source follower FET device F2. Other techniques, such as a current source, can be used, although the use of an active current source relative to a passive resistor may negatively impact the noise factor linearity. Figure 6 The termination circuit 108B is capable of sinking DC current in addition to sourcing DC current. Therefore, if the feedback resistor RFB is included, a DC blocking capacitor in series with RFB is not required. As described above, the use of a series DC blocking capacitor can hinder the low frequency performance of the DA circuit 600 (e.g., resulting in a higher minimum operating frequency compared to a topology without a series DC blocker).

[0051] As in Figure 1 In the example, the quiescent bias current I RF Usually I REF The first-order scaling of represents, for example, scaling by the peripheral ratio of F1 to M1N. REF corresponds roughly to the value (VDD-2*VGS) / RB, where the feedback resistor RFB is not included, or where there is a DC blocking cap in series with RFB (e.g., where no DC current flows through R TERM RB may be a discrete value resistor located off-chip, for example, a 1% tolerance may be acceptable. Alternatively, additionally, or alternatively, one or more resistors may be monolithically integrated with other portions of the DA circuit 600 connected in a manner similar to RB.

[0052] The inventors have recognized that TERM Positioning within the termination circuit 108B feedback loop allows for maintaining I RF To-I RF The current scaling of the termination circuit 108B is achieved while also providing a specified termination impedance. As described above, the loop bandwidth of the feedback looped by the termination circuit 108B can be established at least in part by a resistor-capacitor (RC) loop filter formed by the values ​​of R1 and C1. In the event that the loop gain of the termination circuit 108B feedback loop drops below 1, the termination impedance Z TERM It can be expressed as Z TERM =R TERM +(R2||Z SF ), where Z SF represents the impedance looking into the source of FET device F2. R TERM , F2 and R2 to establish the desired DA circuit 600 amplifier input return loss and noise figure. The size and bias of F2 are also set to maintain the bias current I RF , which is sufficient to maintain the specified linearity and distortion performance of the DA circuit 600 (e.g., as shown by the third-order intercept or gain compression behavior).RTERM Compared with Z SF The magnitude of the effective impedance associated with the parallel resistor R2 will be relatively low, so as an example, R TERM The value of can be about 50 ohms. According to simulation, the DC bias current I RF As the temperature and process parameters change, they remain relatively constant, as shown in Tables 1 and 2 below, and as shown in Table 1 RF and overall I DD Static DC current values ​​are shown.

[0053] <![CDATA[I RF (mA, per section)]]> <![CDATA[I DD (mA, total)]]> Normal value 23.1 82.2 Maximum 24.8 86.2 Minimum 21.8 79.4 %change + / -7％ + / -5％

[0054] Table 1.I RF and I DD The quiescent current values ​​are simulated with different manufacturing process parameters and a constant temperature of 25 degrees Celsius.

[0055] <![CDATA[I RF (mA, each part)]]> <![CDATA[I DD (mA, total value)]]> -55℃ 23.2 82.6 25℃ 23.1 82.2 85℃ 23.3 82.8 125℃ 24 85

[0056] Table 2.I RF and I DD Quiescent current values ​​simulated at different temperatures and assuming nominal process parameters

[0057] For the simulation results shown in Tables 1 and 2 above, a corner analysis was performed. For example, such a corner includes FET parameters that affect DC performance, such as threshold voltage variation (e.g., I ds With V gs Compared to) and transconductance (G m ) Change V gs Also included are FET parameters that affect RF performance, as well as variations in resistors (thin film / mesa) and metal-insulator-metal (MIM) capacitors. Corner cases cover 3 sigma variations in each parameter.

[0058] Fig. 7A Shows the observation Figure 6 The simulated return loss of the termination circuit 108B (eg, S 11 Parameters) where no external capacitor (C EXT ) and use a 2 picofarad (pF) fixed-termination bypass capacitor (C BYP ) values, showing the effect of different RC filter (C1) capacitor values ​​(and resulting cutoff frequencies) from 2pF to 20pF. Fig. 7A As shown, according to the C1 value, in the absence of C EXT and R TERM With a value of 51 ohms, the gate termination is effective to approximately 1 to 10 MHz.

[0059] Figure 7B Shows the observation Figure 6 The simulated return loss of the termination circuit 108B (eg, S 11 Parameters) using a 2pF fixed termination bypass capacitor (C BYP ) values, using a fixed RC filter (C1) capacitor value of 5 pF, and showing different external capacitors (C EXT ) value. Figure 7B As shown, non-zero C EXT The value does not significantly affect high frequency performance and reduces the minimum operating frequency from tens of MHz to the KHz range.

[0060] Fig. 8A Shows Figure 6 Illustrative example of a simulated noise factor (in dB, corresponding to noise figure, plotted against frequency using a logarithmic scale for the frequency axis) of a DA circuit without using an external capacitor (C EXT ), and use a 2pF fixed termination bypass capacitor (C BYP ) values, showing the effect of different RC filter (C1) capacitor values ​​from 2pF to 20pF.

[0061] Figure 8B Shows Figure 6 Illustrative example of a simulated noise factor (in dB, corresponding to noise figure, plotted against frequency using a logarithmic scale for the frequency axis) of a DA circuit using a 2pF fixed termination bypass capacitor (C BYP ) value, and using a fixed RC filter (C1) capacitor value of 5pF, different external capacitors (C EXT ) value. Fig. 8A and Figure 8B shows that when no external capacitor is used, the noise factor performance is similar to a 3dB passive termination, depending on the C1 value down to about 1 to 10MHz, and using C EXT This performance can be extended to lower frequencies. Fig. 7A , Figure 7B , Fig. 8A and Figure 8B In each simulation shown, a 51 ohm R TERM value.

[0062] Fig.9A shows the fixed termination bypass capacitor (C BYP ) values ​​and an operating frequency of 10 MHz, the illustrative examples of simulated output power versus input power for different source follower bias current levels illustrate the gain compression behavior. In general, increasing the source follower (e.g., Figure 6The FET device F2) shown has a bias current that improves compression performance. Similarly, Fig. 9B An illustrative example of simulated output power versus input power for different operating frequencies is shown for a fixed termination bypass capacitor (C BYP ) value and a fixed source follower bias level of 4 milliamps (mA). Fig. 9B As the frequency increases, C BYP The presence of can improve the output compression behavior.

[0063] Fig. 10A shows that in the absence of C BYP , illustrative examples of analog output third order intercept (IP3) values ​​for different operating frequencies with a fixed source follower bias level of 4 mA and a 1 MHz tone spacing, and Fig. 10B Illustrative examples of simulated output third-order intercept (IP3) values ​​for different operating frequencies are shown, using a fixed-termination bypass capacitor (C BYP ) value, a fixed source follower bias level of 4mA and a 1MHz tone spacing. Fig. 10B As shown, when using C BYP , the third-order intercept performance improves with increasing frequency.

[0064] The biasing and termination methods shown in this article are applicable to DA circuits used in low noise amplifier (LNA) applications or power amplifier (PA) applications. For example, Fig. 10C Illustrative examples of simulated output third order intercept (IP3) values ​​for different source follower bias current values ​​using a fixed termination bypass capacitor (C BYP ) value and 1MHz tone spacing. Fig. 10C As shown, the use of a 2mA to 4mA source follower bias current appears to be suitable for LNA applications, and a higher current such as a 32mA bias current may be more suitable for power amplifier applications, as an example.

[0065] Various precautions

[0066] Typically, in the examples discussed herein, FET devices are modeled using process and device parameters corresponding to gallium arsenide (GaAs) enhancement mode pseudo high electron mobility transistors (HEMTs), such as powered by a forward voltage source. However, the inventors also recognize that the methods described herein can be used for other transistor architectures or materials. For example, the techniques described herein can be applied to circuit implementations using complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors such as heterojunction bipolar transistors (HBTs), or depletion mode devices using a corresponding negative supply voltage. The techniques herein can be applied to other compound semiconductors, such as gallium nitride, or silicon-based transistors.

[0067] Each of the above non-limiting aspects may exist independently or may be combined with one or more of the other aspects or other subject matter described in this document in various permutations or combinations.

[0068] The above detailed description includes reference to the accompanying drawings that form a part of the detailed description. The accompanying drawings illustrate specific embodiments in which the present invention can be put into practice in a diagrammatic manner. These embodiments are also generally referred to as "examples". Such examples may include elements other than those shown or described. However, the inventors also contemplate providing examples of only those elements shown or described. In addition, the inventors also contemplate using any combination or arrangement of those elements (or one or more aspects thereof) shown or described relative to a specific example (or one or more aspects thereof) or relative to other examples (or one or more aspects thereof) shown or described herein.

[0069] In the event of an inconsistency in usage between this document and any document incorporated by reference, the usage in this document controls.

[0070] In this document, the terms "a" or "an" as commonly used in patent documents include one or more, independent of any other instances or uses of "at least one" or "one or more". In this document, the term "or" is used to refer to a non-exclusive or, so that "A or B" includes "A but not B", "B but not A", and "A and B" unless otherwise noted. In this document, the terms "including" and "wherein" are used as synonyms for the respective terms "comprising" and "wherein". In addition, in the following claims, the terms "including" and "comprising" are open-ended, that is, systems, devices, articles, compositions, preparations, or processes that include these elements in addition to the elements listed after the term in the claim are still deemed to fall within the scope of the claim. In addition, in the following claims, the terms "first", "second", and "third", etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0071] The above description is intended to be illustrative, not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, such as by a person of ordinary skill in the art when reviewing the above description. The abstract is provided to allow the reader to quickly determine the nature of the technical disclosure. It is understood when submitting this document that this document is not used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features may be grouped together to simplify the disclosure. This should not be interpreted as intending to make unclaimed public features essential to any claim. On the contrary, the subject matter of the present invention may be less than all the features of a particular disclosed embodiment. Therefore, the following claims are incorporated into the detailed description as examples or embodiments, each claim being independently a separate embodiment, and it is conceivable that such embodiments may be combined with each other in various combinations or arrangements. The scope of the present invention should be determined with reference to the appended claims and the full scope of equivalents enjoyed by these claims.

Claims

1. A distributed amplifier circuit, comprising: an input transmission line structure comprising first cells, a respective one of the first cells comprising a first reactive circuit element and a first active circuit element, the first reactive circuit element being coupled to an input node of the first active circuit element, an input port of the input transmission line structure defining a signal input port of the distributed amplifier circuit; an output transmission line structure comprising second cells, a respective one of the second cells comprising a second reactive circuit element and a second active circuit element, the second reactive circuit element being coupled to an output node of the second active circuit element, an output port of the output transmission line structure defining an amplified signal output port of the distributed amplifier circuit; and a termination circuit coupled to one end of the input transmission line structure, the termination circuit being configured to establish a specified termination impedance, the termination circuit including a current mirror circuit to establish a specified bias current for biasing a corresponding first active circuit element of the input transmission line structure; and Wherein the respective first active circuit element is coupled with the respective second active circuit element to form a respective amplifier circuit, and the respective amplifier circuit is coupled to each other in a cascade manner using the respective first reactive circuit element and the respective second reactive circuit element.

2. The distributed amplifier circuit of claim 1, wherein the current mirror circuit is configured to establish the specified bias current and act as a dissipative element terminating the input transmission line structure.

3. The distributed amplifier circuit of claim 2, wherein the current mirror circuit comprises a diode-connected transistor monolithically co-integrated with the respective first active circuit element and the respective second active circuit element.

4. The distributed amplifier circuit of claim 1, wherein the termination circuit comprises a passive termination coupled to the current mirror circuit.

5. The distributed amplifier circuit of claim 4, wherein the termination circuit comprises a driver circuit controlled by the current mirror circuit and configured to maintain the specified bias current for biasing the corresponding first active circuit element; and Wherein the passive termination comprises a resistor located within a feedback loop defined by the driver circuit and the current mirror circuit.

6. The distributed amplifier circuit of claim 5, wherein the termination circuit is monolithically co-integrated with the respective first active circuit element and the respective second active circuit element.

7. The distributed amplifier circuit of claim 6, wherein the termination circuit comprises a resistor-capacitor (RC) filter in the feedback loop, the RC filter establishing a cutoff frequency corresponding to a minimum operating frequency specification of the distributed amplifier circuit.

8. The distributed amplifier circuit of claim 5, wherein the resistor is located in series between the driver circuit and a node corresponding to the end of the input transmission line structure.

9. The distributed amplifier circuit of claim 1, comprising a feedback resistor coupled between a node corresponding to an end of the input transmission line structure and a node of an output port of the output transmission line structure; Wherein a value of the feedback resistor at least partially establishes the specified bias current.

10. The distributed amplifier circuit of claim 9, wherein the feedback resistor is monolithically co-integrated with the respective first active circuit element and the respective second active circuit element.

11. The distributed amplifier circuit of claim 1 , wherein the current mirror circuit is monolithically co-integrated with the corresponding first active circuit element and the corresponding second active circuit element; and The distributed amplifier circuit further includes a bias control node coupled to the current mirror circuit, the bias control node being coupleable to a bias control component that is not monolithically integrated with the current mirror circuit.

12. The distributed amplifier circuit of claim 11, wherein the bias control node is coupleable to a reactive component that establishes a cutoff frequency corresponding to a minimum operating frequency specification of the distributed amplifier circuit.

13. The distributed amplifier circuit of claim 12, wherein the bias control component comprises a resistor and the reactive component comprises a capacitor.

14. The distributed amplifier circuit of claim 1 wherein the respective first active circuit element and the respective second active circuit element comprise transistors monolithically co-integrated with the current mirror circuit.

15. The distributed amplifier circuit of claim 14, wherein the transistor comprises a field effect transistor comprising a compound semiconductor high electron mobility transistor (HEMT).

16. The distributed amplifier circuit of claim 1, wherein within a corresponding first cell, the first reactive circuit element establishes a series inductance and the first active circuit element establishes a parallel capacitance.

17. A distributed amplifier circuit comprising: Input transmission line structure; Output transmission line structure; a termination circuit coupled to one end of the input transmission line structure, the termination circuit being configured to establish a specified termination impedance, the termination circuit including a current mirror circuit to establish a specified bias current for biasing a corresponding first active circuit element of the input transmission line structure; and a feedback resistor coupled between a node corresponding to an end of the input transmission line structure and a node of an output port of the output transmission line structure, the feedback resistor having a value that at least partially establishes the specified bias current; wherein the current mirror circuit is monolithically co-integrated with the corresponding first active circuit element; and The distributed amplifier circuit further includes a bias control node coupled to the current mirror circuit, the bias control node being coupleable to a bias control component that is not monolithically integrated with the current mirror circuit.

18. The distributed amplifier circuit of claim 17, further comprising the bias control component, the bias control component comprising a resistor.

19. The distributed amplifier circuit of claim 17, wherein the bias control node is coupleable to a reactive component that establishes a cutoff frequency corresponding to a minimum operating frequency specification of the distributed amplifier circuit.

20. A monolithic integrated distributed amplifier circuit comprising: an input transmission line structure including a corresponding first active circuit element; an output transmission line structure including a corresponding second active circuit element; and a termination circuit coupled to one end of the input transmission line structure, the termination circuit being configured to establish a specified termination impedance, the termination circuit including a current mirror circuit to establish a specified bias current for biasing a corresponding first active circuit element of the input transmission line structure; wherein the respective first active circuit element and the respective second active circuit element comprise a compound semiconductor high electron mobility transistor (HEMT); and The current mirror circuit includes a diode-connected field effect transistor (FET).

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