DMA-based configurable shaping filter generation device and control method thereof

Abstract

The present disclosure provides a configurable shaping filter generating device based on DMA, which includes host computer software, the host computer software includes a software control module and a monitoring program, the host computer software is bidirectionally connected to a DMA interface control module, the DMA interface control module and the read data control module are respectively connected to a dual-port RAM unit, the dual-port RAM unit includes N dual-port RAMs that can load a group of shaping filter coefficients respectively, all the dual-port RAMs are respectively connected to an input data shaping processing module, and the input data shaping processing module is connected to an output data processing module; at the same time, the host computer software is respectively connected to the DMA interface control module, each of the dual-port RAMs, and the input data shaping processing module one by one.

Description

Technical Field

[0001] The present disclosure relates to the fields of satellite communication and digital signal processing technology, and in particular to a configurable shaping filter generating device based on DMA and a control method thereof. Background Art

[0002] In the application fields of satellite communications and digital signals, shaping filtering is the most common technology for eliminating inter-symbol interference. Digital shaping filters can specially process the spectrum of communication baseband signals to compress the signal frequency band and improve the utilization rate of the spectrum while eliminating inter-symbol interference and achieving optimal detection. This is of great significance in solving the problem of frequency band congestion in modern digital communications.

[0003] Digital shaping filters usually use root raised cosine filters. Each roll-off coefficient corresponds to a set of shaping filter parameters, and the corresponding shaping filter parameters are obtained through matlab simulation software. The traditional shaping filter module stores the existing shaping filter parameters in a single-port RAM (random access memory) in the form of a lookup table. Each time the FPGA (field programmable gate array) loads a shaping filter parameter, if different shaping filter parameters are required, the lookup table IP core needs to be regenerated, and the FPGA loading file needs to be regenerated, which is extremely inefficient. In actual work, there will be application scenarios that require real-time switching of multiple shaping filter parameters, so it is necessary to generate multiple lookup table IP cores corresponding to the shaping filter parameters, which occupies a large amount of hardware resources in the FPGA and easily leads to layout and wiring timing problems, thereby causing unstable system operation.

[0004] Currently, existing technologies all focus on studying how to optimize the internal hardware resources of FPGA, but do not focus on the real-time switching technology of multiple different shaping filter parameters.

[0005] In this regard, there is currently no technical solution on the market to solve the above technical problems. Summary of the invention

[0006] In response to the above technical problems in the related art, the present disclosure proposes a DMA-based configurable shaping filter generation device that can screen out products within the required power range and capable of constant power control before installation, which can overcome the above shortcomings of the prior art.

[0007] To achieve the above technical objectives, the technical solution of the present disclosure is implemented as follows:

[0008] The first object of the present disclosure is to provide a configurable shaping filter generating device based on DMA, comprising a host computer software, the host computer software comprising a software control module and a monitoring program, the host computer software being bidirectionally connected to a DMA interface control module, the DMA interface control module and the read data control module being respectively connected to a dual-port RAM unit, the dual-port RAM unit comprising N dual-port RAMs capable of loading a set of shaping filter coefficients respectively, all the dual-port RAMs being respectively connected to an input data shaping processing module, the input data shaping processing module being connected to an output data processing module; at the same time, the host computer software being respectively connected to the DMA interface control module, each of the dual-port RAMs, and the input data shaping processing module one by one;

[0009] The software control module is used to generate a software reset signal, the monitoring program is used to select and load the N groups of filter coefficients specifically needed, and the software reset signal is used to control the read and write enable clocks of each of the dual-port RAMs; when the host computer software writes a corresponding group of filter coefficients to each of the dual-port RAMs, the software reset signal value is set to 0, indicating that the write operation is in progress and the read end of the dual-port RAM is prohibited from reading; when the host computer software 1 has completed the write operation of each group of filter coefficients, the software reset signal value is set to 1, indicating that the write operation has been completed and the read end of the dual-port RAM allows the read operation;

[0010] The DMA interface control module numbers each constituent filter coefficient and generates a corresponding address and enable signal, which are then aggregated into an array and transmitted to the dual-port RAM unit;

[0011] The dual-port RAM unit receives the software reset signal from the host computer software, and the read enable or write enable of each dual-port RAM is controlled by the software reset signal: when the software reset signal is 0, the write enable clock is valid, and each dual-port RAM receives a corresponding set of molding filter coefficients written by the host computer software 1, and generates write data and write address accordingly; when the software reset signal is 1, the read enable clock is valid, and when the read address is ready, the read operation starts-the input data molding processing module reads the output data of each dual-port RAM;

[0012] The read data control module generates a corresponding read address addrb for the output data of each dual-port RAM, and transmits it to the dual-port RAM unit;

[0013] The input data shaping processing module includes an N-bit shift register, which receives the input serial data and outputs N-bit shift data. The input data shaping processing module ANDs the read output data of each dual-port RAM with the N-bit shift data, and outputs the result to the output data processing module;

[0014] The output data processing module adds the data obtained from the input data shaping processing module through an L-level adder to obtain the final shaping filtering result. The adder is used to add two signed data. If the sign bits are the same, the two data are directly added. If the sign bits are different, the number with a larger absolute value is subtracted from the number with a smaller absolute value, and the sign is the sign corresponding to the value with a larger absolute value.

[0015] Preferably, the upper computer software writes each group of filter coefficients into each of the dual-port RAMs in a DMA manner, and each of the dual-port RAMs has a one-to-one correspondence with each group of filter coefficients.

[0016] Preferably, the DMA interface control module numbers each group of filter coefficients and generates corresponding addresses and enable signals, which are respectively summarized into a 26-bit array DMA_tdata[25:0] and transmitted to the corresponding dual-port RAM, and each array DMA_tdata[25:0] corresponds to one dual-port RAM;

[0017] Among them, DMA_tdata[11:0] is used to store data, that is, the data width is 12 bits;

[0018] DMA_tdata [21:12] is used to store data corresponding to address 0-1023;

[0019] DMA_tdata [25:22] has 4 bits in total and is used to store the numbers of all component filter coefficients. The number range is 0 to (N-1), corresponding to the number of each component filter coefficient; N=2 M , 0≤M≤4, N represents the maximum number of groups of shaping filter coefficients that can be written to DMA_tdata [25:22] in binary format.

[0020] Preferably, the number of the dual-port RAMs is N, where N=1 or 2 or 4 or 8 or 16, that is, 2 to the power of 0-4.

[0021] Preferably, the data reading control module extracts 10-bit phase information corresponding to the data rate synchronization clock as the generated read address addrb of the output data of each of the dual-port RAMs, and transmits it to the dual-port RAM unit.

[0022] Preferably, the input data shaping processing module first reads the output data of each of the dual-port RAMs, the output data of the dual-port RAMs corresponding to a set of shaping filter coefficients; then inputs the serial 1-bit data through an N-bit shift register, and finally, ANDs the output data of each of the dual-port RAMs with the codeword symbol of the corresponding shift register, and outputs them to the output data processing module.

[0023] Preferably, the shift register is used for data storage and transmission, and adopts a serial input and parallel output left shift mode; the input serial 1-bit data is input into the shift register bit by bit in a serial manner, and the shift register finally outputs in N-bit parallel form. Here, N is equal to the total number N of dual-port RAM 301.

[0024] Preferably, the adder is used to add two signed data; if the sign bits are the same, the two data are directly added; if the sign bits are different, the number with a larger absolute value is subtracted from the number with a smaller absolute value, and the sign is the sign corresponding to the value with the larger absolute value.

[0025] The second object of the present disclosure is to provide a control method for the DMA-based configurable shaping filter generation device, comprising the following steps:

[0026] Preparation before S1: First, several roll-off coefficients are identified; then, a simulation tool is used to generate a corresponding lookup table unit in the coe format for each roll-off coefficient, each lookup table unit includes N constituent filter coefficients, and each constituent filter coefficient is stored in the lookup table unit in the form of a lookup table; the number of constituent filter coefficients in each lookup table unit is equal to the number of all the dual-port RAMs 301; finally, all roll-off coefficients and their corresponding lookup table units are stored in the system local disk;

[0027] S2 initialization: initializing the host computer software and hardware devices, the hardware devices including FPGA; wherein the host computer software generates the software reset signal through the software control module, and the software reset signal is used to control the read and write enable clocks of each of the dual-port RAMs;

[0028] S3 loads the lookup table: a certain roll-off coefficient is first selected by the host computer software as the working roll-off coefficient required for a specific work; the monitoring program automatically selects and loads the lookup table unit corresponding to the working roll-off coefficient from the local disk, and parses out the various component filter coefficients included in the lookup table unit;

[0029] S4 write preparation: the software control module sets the software reset signal to 0, which means entering the write operation. The DMA interface control module numbers each constituent filter coefficient of the lookup table unit selected in S3, generates the corresponding address and wea enable signal, and then summarizes and transmits them to the dual-port RAM unit;

[0030] S5 executes writing: the host computer software writes each component filter coefficient of the lookup table unit selected in S3 to the write end of each dual-port RAM one by one, and each dual-port RAM is written with a corresponding set of filter coefficients;

[0031] S6 Read Preparation: The software control module sets the software reset signal to 1, which represents entering a read operation, and the data read control module extracts the phase information corresponding to the data synchronization clock as the read address of each of the dual-port RAMs;

[0032] S7 input processing: the input data shaping processing module first reads the output data in each of the dual-port RAMs, which corresponds to a group of shaping filter coefficients. The output data of the dual-port RAM corresponds to a group of shaping filter coefficients. Then, the input serial 1-bit data is passed through the shift register to obtain the N-bit shift data. Finally, the output data of each of the dual-port RAMs is ANDed with the N-bit shift data, and output to the output data processing module.

[0033] S8 output processing: the output data processing module performs accumulation processing on the data transmitted from S7 through an L-level adder, thereby obtaining the final shaped filtering result, and then outputs it.

[0034] Preferably, L is determined according to actual needs, and is preferably 3. L can also be an integer such as 1, 2, 3, 4, etc.

[0035] Preferably, in S1, each group of filter coefficients corresponds to one of the dual-port RAMs.

[0036] Preferably, in S1, the value range of all kinds of roll-off coefficients is 0.05-1.00, and the step value corresponding to the roll-off coefficient is 0.05.

[0037] Beneficial effects of the present disclosure: The configurable shaping filter generation device based on DMA proposed in the present disclosure has a variable shaping filter coefficient, and the lookup table corresponding to each shaping filter coefficient is different. In order to save FPGA resources, a dual-port RAM301 is used as a lookup table. The lookup tables of different coefficients are first stored on the hard disk. In the system initialization stage, the monitoring program finds the corresponding lookup table data according to the specific shaping filter coefficient of the task, and writes it into the dual-port RAM301 through DMA. In the system working stage, the value in the lookup table is no longer modified, but the corresponding shaping amplitude value in the lookup table is read out according to the address, and finally the total amplitude value after shaping is obtained by adding 8-way data. The present invention realizes that the roll-off coefficient corresponds to different shaping filter coefficients in the range of 0.05-1.00, the step value is 0.05, the shaping filter parameters are switched in real time, the FPGA hardware resources are reduced, and the work efficiency is improved; the system data rate range is adapted to be variable from 1Ksps to 20Mbps, and the data clock output to the DAC module can reach up to 200MHz. Therefore, the present disclosure can easily match various different shaping filter parameter real-time switching technologies, and better adapt to the system under different shaping filter coefficients to achieve fast loading.

[0038] The present invention can realize the roll-off coefficient corresponding to different shaping filter coefficients in the range of 0.05-1.00, with a step value of 0.05, and switch the shaping filter parameters in real time, reduce FPGA hardware resources, and improve work efficiency; adapt to the system data rate range of 1Ksps~20Mbps, and the data clock output to the DAC module can reach up to 200MHz.

[0039] The present disclosure can also realize that the roll-off coefficient corresponds to different shaping filter coefficients in the range of 0.05-1.00, and the step value is adjustable. Different shaping filter parameters are stored in the form of coe files, and multiple parameter files are stored in the local disk, which does not occupy the internal hardware resources of FPGA and is flexible and convenient.

[0040] The present disclosure can load shaping filter parameters in real time through DMA, and switch shaping filter parameters in real time according to actual work requirements, thereby reducing FPGA hardware resources and improving work efficiency.

[0041] The present disclosure can adapt to a system data rate range of 1Ksps to 20Mbps, and the output data rate after forming can reach up to 200Mbps. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0043] Figure 1 It is a schematic diagram of the structure of a configurable shaping filter generating device based on DMA disclosed in an embodiment of the present invention.

[0044] Figure 2 The present invention is a flowchart of a control method of the DMA-based configurable shaping filter generation device disclosed in an embodiment of the present invention.

[0045] Figure 3 It is a schematic diagram of the structure of the dual-port RAM described in an embodiment of the present invention.

[0046] Figure 4 This is the implementation method of the AND operation and the accumulation operation in the embodiment of the present invention. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0048] like Figure 1-4 As shown, in order to facilitate the understanding of the above technical solutions of the present disclosure, the above technical solutions of the present disclosure are described in detail below through specific usage methods.

[0049] The first object of the present disclosure is to provide a configurable shaping filter generating device based on DMA, comprising a host computer software 1, wherein the host computer software 1 comprises a software control module 101 and a monitoring program 102, wherein the host computer software 1 is bidirectionally connected to a DMA interface control module 2, wherein the DMA interface control module 2 and the read data control module 4 are respectively connected to a dual-port RAM unit 3, wherein the dual-port RAM unit 3 comprises N dual-port RAMs 301 each capable of loading a set of shaping filter coefficients, wherein all the dual-port RAMs 301 are respectively connected to an input data shaping processing module 5, wherein the input data shaping processing module 5 is connected to an output data processing module 6; meanwhile, the host computer software 1 is respectively connected to the DMA interface control module 2, each of the dual-port RAMs 301, and the input data shaping processing module 5;

[0050] The software control module 101 is used to generate a software reset signal, and the monitoring program 102 is used to select and load the N groups of filter coefficients that are specifically needed. The software reset signal is used to control the read and write enable clocks of each of the dual-port RAMs 301; when the host computer software 1 writes a corresponding group of filter coefficients to each of the dual-port RAMs 301, the software reset signal value is set to 0, indicating that the write operation is in progress and the read end of the dual-port RAM 301 prohibits the read operation; when the host computer software 1 has completed the write operation of each group of filter coefficients, the software reset signal value is set to 1, indicating that the write operation has been completed and the read end of the dual-port RAM 301 allows the read operation;

[0051] The DMA interface control module 2 numbers each constituent filter coefficient and generates corresponding addresses and enable signals, which are then aggregated into an array and transmitted to the dual-port RAM unit 3;

[0052] The dual-port RAM unit 3 receives the software reset signal from the host computer software 1, and the read enable or write enable of each dual-port RAM 301 is controlled by the software reset signal: when the software reset signal is 0, the write enable clock is valid, and each dual-port RAM 301 receives a corresponding set of molding filter coefficients written by the host computer software 1, and generates write data and write address accordingly; when the software reset signal is 1, the read enable clock is valid, and when the read address is ready, the read operation starts-the input data molding processing module 5 reads the output data of each dual-port RAM 301;

[0053] The read data control module 4 generates a corresponding read address addrb for the output data of each dual-port RAM 301 and transmits it to the dual-port RAM unit 3;

[0054] The input data shaping processing module 5 includes an N-bit shift register, which receives the input serial data and outputs N-bit shift data. The input data shaping processing module 5 performs AND operation on the output data of each of the dual-port RAMs 301 and the N-bit shift data, and outputs the result to the output data processing module 6.

[0055] The output data processing module 6 adds the data obtained from the input data shaping processing module 5 through an L-level adder to obtain the final shaping filtering result. The adder is used to add two signed data. If the sign bits are the same, the two data are directly added. If the sign bits are different, the number with a larger absolute value is subtracted from the number with a smaller absolute value, and the sign is the sign corresponding to the value with a larger absolute value.

[0056] In one embodiment, the host computer software 1 writes each group of filter coefficients into each of the dual-port RAMs 301 in a DMA manner, and each of the dual-port RAMs 301 has a one-to-one correspondence with each group of filter coefficients.

[0057] In one embodiment, the DMA interface control module 2 numbers each group of filter coefficients and generates corresponding addresses and enable signals, which are summarized into a 26-bit array DMA_tdata[25:0] and transmitted to the corresponding dual-port RAM301. Each array DMA_tdata[25:0] corresponds to one dual-port RAM301.

[0058] Among them, DMA_tdata[11:0] is used to store data, that is, the data width is 12 bits;

[0059] DMA_tdata [21:12] is used to store data corresponding to address 0-1023;

[0060] DMA_tdata [25:22] has 4 bits in total and is used to store the numbers of all component filter coefficients. The number range is 0 to (N-1), corresponding to the number of each component filter coefficient; N=2 M , 0≤M≤4, N represents the maximum number of groups of shaping filter coefficients that can be written to DMA_tdata [25:22] in binary format.

[0061] In one embodiment, the number of the dual-port RAMs 301 is preferably N, where N=1 or 2 or 4 or 8 or 16, that is, 2 to the power of 0-4.

[0062] In one embodiment, the data reading control module 4 extracts 10-bit phase information corresponding to the data rate synchronization clock as the generated read address addrb of the output data of each of the dual-port RAMs 301 and transmits it to the dual-port RAM unit 3 .

[0063] In a certain embodiment, the input data shaping processing module 5 first reads the output data of each of the dual-port RAMs 301, where the output data of the dual-port RAMs 301 corresponds to a set of shaping filter coefficients; then the input serial 1-bit data is passed through an N-bit shift register, and finally the output data of each of the dual-port RAMs 301 is ANDed with the code element symbol of the corresponding shift register, and output to the output data processing module 6.

[0064] In one embodiment, the shift register is used for data storage and transmission, and adopts a serial input and parallel output left shift mode; the input serial 1-bit data is input into the shift register bit by bit in a serial manner, and the shift register finally outputs in N-bit parallel form. Here, N is equal to the total number N of the dual-port RAM 301.

[0065] In a certain embodiment, the adder is used to add two signed data; if the sign bits are the same, the two data are directly added; if the sign bits are different, the number with a larger absolute value is subtracted from the number with a smaller absolute value, and the sign is the sign corresponding to the value with a larger absolute value.

[0066] The second object of the present disclosure is to provide a control method for the DMA-based configurable shaping filter generation device, comprising the following steps:

[0067] Preparation before S1: First, several roll-off coefficients are identified; then, a simulation tool is used to generate a corresponding lookup table unit in the coe format for each roll-off coefficient, each lookup table unit includes N constituent filter coefficients, and each constituent filter coefficient is stored in the lookup table unit in the form of a lookup table; the number of constituent filter coefficients in each lookup table unit is equal to the number of all the dual-port RAMs 301; finally, all roll-off coefficients and their corresponding lookup table units are stored in the system local disk;

[0068] S2 initialization: initializing the host computer software 1 and hardware devices, the hardware devices including FPGA; wherein the host computer software 1 generates the software reset signal through the software control module 101, and the software reset signal is used to control the read and write enable clocks of each of the dual-port RAMs 301;

[0069] S3 loads the lookup table: a certain roll-off coefficient is first selected by the host computer software 1 as the working roll-off coefficient required for a specific work; the monitoring program 102 automatically selects and loads the lookup table unit corresponding to the working roll-off coefficient from the local disk, and parses out the constituent filter coefficients included in the lookup table unit;

[0070] S4 write preparation: the software control module 101 sets the software reset signal to 0, which means entering the write operation. The DMA interface control module 2 numbers each constituent filter coefficient of the lookup table unit selected in S3, generates the corresponding address and wea enable signal, and then summarizes and transmits them to the dual-port RAM unit 3;

[0071] S5 executes writing: the host computer software 1 writes each constituent filter coefficient of the lookup table unit selected in S3 to the write end of each dual-port RAM 301 one by one, and each dual-port RAM 301 is written with a corresponding group of constituent filter coefficients;

[0072] S6 Read preparation: the software control module 101 sets the software reset signal to 1, which represents entering the read operation, and the data read control module 4 extracts the phase information corresponding to the data synchronization clock as the read address of each of the dual-port RAMs 301;

[0073] S7 Input processing: The input data shaping processing module 5 first reads the output data in each of the dual-port RAMs 301, which corresponds to a group of shaping filter coefficients. The output data of the dual-port RAMs 301 corresponds to a group of shaping filter coefficients. Then, the input serial 1-bit data is passed through the shift register to obtain the N-bit shift data. Finally, the output data of each of the dual-port RAMs 301 is ANDed with the N-bit shift data, and output to the output data processing module 6.

[0074] S8 output processing: the output data processing module 6 performs accumulation processing on the data transmitted from S7 through an L-level adder, thereby obtaining the final shaped filtering result, and then outputs it.

[0075] In one embodiment, L is determined according to actual needs, and is preferably 3. L can also be an integer such as 1, 2, 3, 4, etc.

[0076] In one embodiment, in S1 , each group of filter coefficients corresponds to one of the dual-port RAMs 301 .

[0077] In one embodiment, in S1, all types of roll-off coefficients have a value range of 0.05-1.00, and the step value corresponding to the roll-off coefficient is 0.05.

[0078] Working principle: In order to achieve real-time switching of different shaping filter parameters and better adapt to different shaping filter coefficients, the system can be quickly loaded. This method proposes a configurable shaping filter generation device based on DMA. Because the shaping filter coefficient is variable, the lookup table corresponding to each shaping coefficient is different. In order to save FPGA resources, a dual-port RAM301 is used as a lookup table, and several lookup tables corresponding to different shaping filter coefficients are first stored on the local hard disk; in the system initialization stage, the system finds the corresponding lookup table from the local hard disk according to the shaping filter coefficient required for the specific task, and then writes it to the dual-port RAM301 through DMA.

[0079] In the system working stage, the value of the lookup table is no longer modified, but the corresponding shaping amplitude value in the lookup table is read out according to the address, and finally the total amplitude value after shaping is obtained by adding 8 data. The present invention realizes that the roll-off coefficient corresponds to different shaping filter coefficients in the range of 0.05-1.00, the step value is 0.05, and the shaping filter parameters are switched in real time, which reduces FPGA hardware resources and improves work efficiency; the system data rate range is adaptable to 1Ksps~20Mbps, and the data clock output to the DAC module can reach up to 200MHz.

[0080] The technical solution of the present invention is described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific technical features in the embodiments are merely illustrations of the technical solution of the present invention, rather than limitations. The embodiments of the present invention and the specific technical features in the embodiments may be combined with each other if there is no conflict.

[0081] The specific implementation principle, selecting N=8, L=3, can be understood by referring to the following example:

[0082] (i) First, several roll-off coefficients can be identified; then, a simulation tool is used to generate a corresponding lookup table unit in the coe format for each roll-off coefficient, each lookup table unit includes N component filter coefficients, and each component filter coefficient is stored in the lookup table unit in the form of a lookup table; the number of component filter coefficients in each lookup table unit is equal to the number of all the dual-port RAMs 301; finally, all roll-off coefficients and their corresponding lookup table units are stored in the system local disk.

[0083] Specifically, before the system works, a simulation tool is used to generate shaping filter coefficients corresponding to each roll-off coefficient. Each shaping filter coefficient has 8 files corresponding to 8 dual-port RAMs 301 .

[0084] The shaping filter uses a square root raised cosine roll-off filter, and its time domain expression is:

[0085] Formula (1)

[0086] Where Tb is the symbol period and a is the roll-off coefficient. In this system, the roll-off coefficient ranges from 0.05 to 1.0, with a step of 0.05. The shaping filter realizes a variable data rate of 1Ksps to 20Mbps. The data rate output to the digital-to-analog converter needs to be fixed at 200Mbps. Therefore, when using shaping filtering, it is not possible to simply perform integer multiple interpolation. Figure 4The method shown in the figure realizes shaping filtering to ensure that the data rate after shaping is fixed when the data rate changes. The group delay of this system is set to 8. The 8-bit coding symbols before and after the shaping filter are related. Several lookup table units are established using simulation tools. Each lookup table unit includes 8 groups of shaping filter coefficients. Each lookup table unit can correspond to a coding symbol. The clock phase after encoding corresponds to the absolute value address of the lookup table, and the sign bit of the lookup table address is determined by the corresponding coding symbol.

[0087] (ii) the host computer software 1 and the hardware device can be initialized, the hardware device including the FPGA; wherein the host computer software 1 generates the software reset signal through the software control module 101, and the software reset signal is used to control the read and write enable clocks of each of the dual-port RAMs 301.

[0088] Specifically, the reset signal is 0 in the initialization stage, serving as the write enable clock signal of each dual-port RAM 301, and simultaneously selecting the required lookup table unit to determine the required filter coefficients of each component, wherein the roll-off coefficient can be selected in the range of 0.05 to 1.00, and the step value can be set to 0.05.

[0089] (III) A certain roll-off coefficient may be selected as the working roll-off coefficient required for a specific work by the host computer software 1, and a lookup table unit corresponding to the working roll-off coefficient may be automatically selected and loaded from the local disk.

[0090] (iv) The software reset signal can be set to 0, the 8-component filter coefficients of the loaded lookup table unit are numbered respectively, and the corresponding address addra and wea enable signals are generated.

[0091] Specifically, if Figure 3 As shown, the DMA_tdata signal width is 32 bits, where DMA_tdata[11:0] is the data, DMA_tdata[21:12] is the address 0-1023 corresponding to the data; DMA_tdata[25:22] is the corresponding file number 0-7.

[0092] When writing data to FPGA via DMA, the configurable shaping filter generation device can automatically generate a DMA_tvalid signal, which is 1 when writing data and 0 when idle. For example, the system uses DMA_tvalid && DMA_data[25:22]==1 as the write enable signal wea of ​​the dual-port RAM1. The software reset signal en reads the enable clock enb, and the inverted signal of en controls the write enable clock ena. The system clock clk is 200MHz, and the read and write clocks are both 200MHz. The read address is the input data synchronization clock phase information, and [9:0] is taken as the read-out end address addrb, which ranges from 0 to 1023, and the input data rate ranges from 100bps to 20Mbps. Because the configurable shaping filter generation device based on DMA is a serial output data system, it can also be expanded to a parallel system to adapt to a higher data rate range. The existing technology used in this paragraph is only for understanding the principle, and is not a limited description part.

[0093] (V) Since the software reset signal is 0, the upper computer software 1 reads the shaping filter coefficients of each group in turn, and writes the shaping filter parameters to the writing end of each dual-port RAM 301 through DMA.

[0094] Specifically, when the software reset signal is 0, the write enable clock ena of each dual-port RAM 301 is valid, and the host computer software reads the corresponding lookup table unit from the local disk, and then reads the 8 component filter coefficients stored in the lookup table form in the lookup table unit. The host computer software 1 writes the read component filter coefficients into the 8 dual-port RAMs in turn, and each dual-port RAM 301 corresponds to a group of filter coefficients. The address range of each group of filter coefficients is 0~1023, and the data bit width is 12 bits.

[0095] (VI) After the writing of parameters is completed, the software reset signal is set to 1 (indicating that the writing operation is completed and the reading operation is started). The system uses the phase information generated by the data synchronization clock as the read address of the dual-port RAM to read the shaping filter parameters in the RAM;

[0096] Specifically, when the software reset signal is 1, the read enable clock of the dual-port RAM 301 is valid (enb), and the corresponding shaping filter coefficient is output according to the value of the read-out end address addrb.

[0097] (VII) Perform AND operations on the output data of the eight dual-port RAMs 301 and the processed input serial 1-bit data.

[0098] Specifically, if Figure 4As shown, the input data is serial 1-bit data, which passes through an 8-bit shift register to obtain the 8-bit symbol data related to the front and back, which is used to determine the output data symbols of 8 DPRAMs; the output data of the 8 lookup tables are added together to obtain the final formed data.

[0099] (VIII) After three levels of accumulation processing, the final shaping filter result is output.

[0100] Subsequently, the roll-off coefficient can be reset through the host computer software interface according to system needs, and the above operation can be repeated until the required shaping filter result is determined.

[0101] Through the present disclosure, a configurable shaping filter system with low resource occupancy and high working efficiency can be realized, the roll-off coefficient can switch the shaping filter parameters in real time from 0.05 to 1.00, and the output shaping filtered data rate is 200Mbps.

[0102] As Figure 1 As shown: the software control module 101 generates a software reset signal, the monitoring program 102 automatically selects to load the shaping filter coefficient, and controls the read and write enable clocks of the DMA interface control module 2.

[0103] The host computer software 1 includes a software control module 101 and a monitoring program 102. The software control module 101 is used to generate a software reset signal, and the monitoring program 102 is used to select and load the N groups of shaping filter coefficients that are specifically needed. The software reset signal is used to control the read and write enable clocks of each of the dual-port RAMs 301. When the host computer software 1 writes a corresponding group of shaping filter coefficients to each of the dual-port RAMs 301, the software reset signal value is set to 0, indicating that the write operation is in progress and the read end of the dual-port RAM 301 prohibits the read operation. When the host computer software 1 has completed the writing operation of each group of shaping filter coefficients, the software reset signal value is set to 1, indicating that the write operation has been completed and the read end of the dual-port RAM 301 allows the read operation. The monitoring program 102 can load the stored shaping filter coefficients from the local disk, and the shaping filter coefficients can be stored in the form of a lookup table.

[0104] DMA interface control module 2, numbers each component filter coefficient, generates corresponding address and enable signal, each filter coefficient needs to be written into 8 files, DMA_tdata[11:0] is data, DMA_tdata[21:12] is the address 0-1023 corresponding to the data; DMA_tdata[25:22] is the corresponding file number 0-7, corresponding to 8 files of each group of parameters;

[0105] Each dual-port RAM301 of the dual-port RAM unit is controlled by a software reset signal to control read enable and write enable. When the software reset signal is 0, the write enable clock is valid, and at the same time, the 8-group filter coefficient file written by DMA is received, and the write data and write address are generated accordingly. When the software reset signal is 1, the read enable clock is valid, and when the read address and conditions are met, the read operation starts;

[0106] The data read control module extracts the 10-bit phase information corresponding to the data rate synchronization clock as the read address addrb of the dual-port RAM;

[0107] Input data shaping processing module 5, input serial 1-bit data, pass through 8-bit shift register, and AND the output of DPRAM with the corresponding shift register symbol, and output to output data processing module;

[0108] The output data processing module 6 adds the data obtained from the input data shaping processing module 5, that is, the output data of the 8 dual-port RAMs 301 after the AND operation, through a 3-stage adder to obtain the final shaping filter result. The shaping filter coefficients are stored in the corresponding dual-port RAMs 301 in the form of a lookup table.

[0109] In summary, through the unique design of the present disclosure, compared with the prior art, the configurable shaping filter generation device based on DMA proposed by the present disclosure has a variable shaping filter coefficient, and the lookup table corresponding to each shaping coefficient is different. In order to save FPGA resources, a dual-port RAM is used as a lookup table, and the lookup tables of different coefficients are first stored on the hard disk. In the system initialization stage, the monitoring program finds the corresponding lookup table data according to the specific shaping coefficient of the task, and writes it into the dual-port RAM through DMA. In the system working stage, the value in the lookup table is no longer modified, but the corresponding shaping amplitude value in the lookup table is read out according to the address, and finally the total amplitude value after shaping is obtained by adding 8-way data. The present disclosure can easily match various different shaping filter parameter real-time switching technologies, and better adapt to the system under different shaping filter coefficients to achieve fast loading.

[0110] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A configurable shaping filter generation device based on DMA, characterized in that: The invention comprises a host computer software (1), wherein the host computer software (1) comprises a software control module (101) and a monitoring program (102), wherein the host computer software (1) is bidirectionally connected to a DMA interface control module (2), wherein the DMA interface control module (2) and a data reading control module (4) are respectively connected to a dual-port RAM unit (3), wherein the dual-port RAM unit (3) comprises N dual-port RAMs (301) each capable of loading a group of shaping filter coefficients, wherein all the dual-port RAMs (301) are respectively connected to an input data shaping processing module (5), and the input data shaping processing module (5) is connected to an output data processing module (6); and at the same time, the host computer software (1) is respectively connected to the DMA interface control module (2), each of the dual-port RAMs (301), and the input data shaping processing module (5); The software control module (101) is used to generate a software reset signal, the monitoring program (102) is used to select and load N groups of filter coefficients that are specifically needed, and the software reset signal is used to control the read and write enable clocks of each of the dual-port RAMs (301); when the host computer software (1) writes a corresponding group of filter coefficients to each of the dual-port RAMs (301), the software reset signal value is set to 0, indicating that the write operation is in progress and the read end of the dual-port RAM (301) is prohibited from the read operation; when the host computer software (1) has completed the write operation of each group of filter coefficients, the software reset signal value is set to 1, indicating that the write operation has been completed and the read end of the dual-port RAM (301) is allowed to read. The DMA interface control module (2) numbers each constituent filter coefficient and generates a corresponding address and enable signal, which are then aggregated into an array and transmitted to the dual-port RAM unit (3); The dual-port RAM unit (3) receives the software reset signal from the host computer software (1), and the read enable or write enable of each dual-port RAM (301) is controlled by the software reset signal: when the software reset signal is 0, the write enable clock is valid, and each dual-port RAM (301) receives a corresponding set of shaping filter coefficients written by the host computer software (1), and generates write data and write addresses accordingly; when the software reset signal is 1, the read enable clock is valid, and when the read address is ready, the read operation starts-the input data shaping processing module (5) reads the output data of each dual-port RAM (301); The read data control module (4) generates a corresponding read address addrb for the output data of each dual-port RAM (301), and transmits the read address addrb to the dual-port RAM unit (3); The input data shaping processing module (5) comprises an N-bit shift register, the shift register receives input serial data and outputs N-bit shift data, the input data shaping processing module (5) performs AND operation on the output data read from each of the dual-port RAMs (301) and the N-bit shift data, and outputs the result to the output data processing module (6); The output data processing module (6) adds the data obtained from the input data shaping processing module (5) through an L-level adder, thereby obtaining a final shaping filtering result after shaping.

2. The configurable shaping filter generation device based on DMA according to claim 1, characterized in that: The upper computer software (1) writes each group of filter coefficients into each dual-port RAM (301) in a DMA manner, and each dual-port RAM (301) has a one-to-one correspondence with each group of filter coefficients.

3. The configurable shaping filter generation device based on DMA according to claim 1, characterized in that: The DMA interface control module (2) numbers each group of filter coefficients and generates corresponding addresses and enable signals, which are respectively aggregated into a 26-bit array DMA_tdata[25:0] and transmitted to the corresponding dual-port RAM (301), wherein each array DMA_tdata[25:0] corresponds to one dual-port RAM (301); Among them, DMA_tdata[11:0] is used to store data, that is, the data width is 12 bits; DMA_tdata [21:12] is used to store data corresponding to address 0-1023; DMA_tdata [25:22] has 4 bits in total and is used to store the numbers of all component filter coefficients. The number range is 0 to N-1, corresponding to the number of each component filter coefficient; N=2 M , 0≤M≤4, N represents the maximum number of groups of shaping filter coefficients that can be written to DMA_tdata [25:22] in binary format.

4. The configurable shaping filter generation device based on DMA according to claim 1, characterized in that: The number of the dual-port RAMs (301) is N, where N=1 or 2 or 4 or 8 or 16 - that is, 2 to the power of 0-4.

5. The configurable shaping filter generation device based on DMA according to claim 1, characterized in that: The data reading control module (4) extracts 10-bit phase information corresponding to the data rate synchronization clock as the generated read address addrb of the output data of each of the dual-port RAMs (301), and transmits it to the dual-port RAM unit (3).

6. The configurable shaping filter generation device based on DMA according to claim 1, characterized in that: The input data shaping processing module (5) first reads the output data of each of the dual-port RAMs (301), the output data of the dual-port RAMs (301) corresponding to a set of shaping filter coefficients; then inputs serial 1-bit data through the shift register to obtain the N-bit shift data; finally, the output data of each of the dual-port RAMs (301) are ANDed with the N-bit shift data respectively, and output to the output data processing module (6).

7. The control method of the configurable shaping filter generation device based on DMA according to any one of claims 1 to 6, characterized in that: The following steps are involved: Preparation before S1: First, several roll-off coefficients are identified; then, a simulation tool is used to generate a corresponding lookup table unit in the coe format for each roll-off coefficient, each of which includes N component filter coefficients, and each component filter coefficient is stored in the lookup table unit in the form of a lookup table; The number of shaping filter coefficients in each lookup table unit is equal to the number of all the dual-port RAMs (301); finally, all roll-off coefficients and their corresponding lookup table units are stored in the system local disk; S2 initialization: initializing the host computer software (1) and hardware devices, wherein the hardware devices include FPGA; wherein the host computer software (1) generates the software reset signal through the software control module (101), and the software reset signal is used to control the read and write enable clocks of each of the dual-port RAMs (301); S3 loading the lookup table: a certain roll-off coefficient is first selected by the host computer software (1) as the working roll-off coefficient required for a specific work; the monitoring program (102) automatically selects and loads the lookup table unit corresponding to the working roll-off coefficient from the local disk, and parses out the constituent filter coefficients included in the lookup table unit; S4 write preparation: the software control module (101) sets the software reset signal to 0, which means entering the write operation. The DMA interface control module (2) numbers the constituent filter coefficients of the lookup table unit selected in S3, generates corresponding addresses and wea enable signals, and then summarizes and transmits them to the dual-port RAM unit (3); S5 executes writing: the upper computer software (1) writes each component filter coefficient of the lookup table unit selected by S3 to the write end of each dual-port RAM (301) one by one, and each dual-port RAM (301) is written with a corresponding group of filter coefficients; S6 Reading preparation: the software control module (101) sets the software reset signal to 1, which represents entering a reading operation, and the data reading control module (4) extracts phase information corresponding to the data synchronization clock as a reading address of each of the dual-port RAMs (301); S7 input processing: the input data shaping processing module (5) first reads the output data in each of the dual-port RAMs (301), i.e., the corresponding set of shaping filter coefficients. The output data of the dual-port RAMs (301) corresponds to the corresponding set of shaping filter coefficients. Then, the input serial 1-bit data is passed through the shift register to obtain the N-bit shift data. Finally, the output data of each of the dual-port RAMs (301) is ANDed with the N-bit shift data, and outputted to the output data processing module (6). S8 output processing: the output data processing module (6) performs accumulation processing on the data transmitted from S7 through an L-level adder, thereby obtaining the final shaped filtering result, and then outputs it.

8. The control method according to claim 7, characterized in that: L is level 3.

9. The control method according to claim 7, characterized in that: In the S1, each group of filter coefficients corresponds to one of the dual-port RAMs (301).

10. The control method according to claim 7, characterized in that: In S1, the value range of all kinds of roll-off coefficients is 0.05-1.00, and the step value corresponding to the roll-off coefficient is 0.05.

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