Single-stage and multi-stage voltage level shifter

Abstract

The disclosed structures include single-stage and multi-stage voltage level shifters. In one embodiment, each structure includes a plurality of transistors, optionally all of which are symmetric low voltage transistors, and the structures are configured to avoid operation outside a safe operating area (SOA) of such transistors. The first stages of the single-stage voltage level shifter and the multi-stage voltage level shifter may be substantially the same. In operation, an input voltage pulse (including an input voltage pulse transitioning between a first positive voltage (V1) equal to a transistor nominal voltage and ground) may be received at a source node of the N-type transistor, and in response, an output voltage pulse (including at V1 and above V1 (e.g., a first positive voltage (V3)) may be received at the source node of the N-type transistor. An intermediate output voltage pulse converted between a second positive voltage (V2), which is twice of V1), and an output voltage pulse converted between ground and V2 may be output.

Description

Technical Field

[0001] The present disclosure relates to on-chip voltage level shifters, and more particularly to embodiments of single-stage and multi-stage voltage level shifters. Background Art

[0002] Considerations in modern integrated circuit (IC) design include, but are not limited to, performance improvements, size scaling, and power consumption. Typically, design changes made to improve one aspect of a design may produce undesirable tradeoffs with respect to one or more other aspects of the design. For example, a voltage level shifter in an IC design may be configured to convert (i.e., shift) a voltage signal from one logic level or voltage domain to another. Voltage level shifter designs that include low-voltage transistors to reduce power consumption have been developed. However, at least some of the low-voltage transistors in these voltage level shifters tend to operate quickly outside the safe operating area (SOA). Design modifications intended to avoid operation outside the SOA include, for example, using an asymmetric high-voltage transistor (e.g., a lateral diffusion metal oxide semiconductor field effect transistor (LDMOSFET)) to replace a risky low-voltage transistor and / or using a discrete bias circuit. Although such design modifications can successfully avoid operation outside the SOA, they also increase circuit complexity, power consumption, and area. Summary of the invention

[0003] Disclosed herein is a structure, specifically an embodiment of a voltage level shifter circuit structure. The structure may include: a first voltage rail, which is at a first positive voltage; a second voltage rail, which is at a second positive voltage higher than the first positive voltage (e.g., substantially twice the first positive voltage). The structure may also include: a voltage level shifter, which is connected to the first voltage rail and the second voltage rail. The voltage level shifter may be configured to receive a plurality of input voltage pulses and output a plurality of output voltage pulses. The input voltage pulses may include input voltage pulses converted between the first positive voltage and ground. The output voltage pulses may include: intermediate output voltage pulses converted between the first positive voltage and the second positive voltage, and final output voltage pulses converted between ground and the second positive voltage.

[0004] In some embodiments disclosed herein, the structure may specifically include a single-stage voltage level shifter. In these embodiments, the structure may include: a first voltage rail at a first positive voltage; and a second voltage rail at a second positive voltage higher than the first positive voltage (e.g., substantially twice the magnitude of the first positive voltage). The structure may also include a voltage level shifter connected to the first voltage rail and the second voltage rail. The voltage level shifter may include two input nodes and four output nodes. The voltage level shifter may also include two N-type transistors having source regions connected to the input nodes, respectively, and also having a gate connected to receive the first positive voltage. The voltage level shifter may be configured to receive two input voltage pulses at the input nodes, respectively, and output four output voltage pulses at the output nodes, respectively. The input voltage pulses may include: an input voltage pulse converted between the first positive voltage and ground; and an inverted input voltage pulse, when the input voltage pulse is converted from the first positive voltage to ground, the inverted input voltage pulse is converted from ground to the first positive voltage, and vice versa. The output voltage pulse may include an intermediate output voltage pulse that switches between the first positive voltage and the second positive voltage; and an inverted intermediate output voltage pulse that switches from the second positive voltage to the first positive voltage when the intermediate output voltage switches from the first positive voltage to the second positive voltage, and vice versa. The output voltage pulse may also include a final output voltage pulse that switches between ground and the second positive voltage; and an inverted final output voltage pulse that switches from the second positive voltage to ground when the final output voltage pulse switches from ground to the second positive voltage, and vice versa.

[0005] In other embodiments, the structure may specifically include a multi-stage voltage level shifter. In these embodiments, the structure may include a plurality of voltage rails, the plurality of voltage rails including at least: a first voltage rail at a first positive voltage; a second voltage rail at a second positive voltage higher than the first positive voltage (e.g., substantially twice the magnitude of the first positive voltage); and a third voltage rail at a third positive voltage higher than the second positive voltage (e.g., substantially three times the magnitude of the first positive voltage). The structure may also include a voltage level shifter having a plurality of voltage shifting stages. The voltage shifting stages may include at least: a first voltage shifting stage connected to the first voltage rail and the second voltage rail, and a second voltage shifting stage connected to the second voltage rail and the third voltage rail. The first voltage shifting stage may be configured to receive a plurality of first input voltage pulses and output a plurality of first output voltage pulses. The first input voltage pulse may include a first input voltage pulse converted between the first positive voltage and ground. The first output voltage pulse may include an intermediate first output voltage pulse converted between the first positive voltage and the second positive voltage and a final first output voltage pulse converted between ground and the second positive voltage. The second voltage shifting stage may receive the first output voltage pulses and may output second output voltage pulses. The second output voltage pulses may include at least intermediate second output voltage pulses converted between the second positive voltage and the third positive voltage, additional intermediate second output voltage pulses converted between the first positive voltage and the third positive voltage, and a final second output voltage pulse converted between ground and the third positive voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram illustrating an embodiment of a single-stage voltage level shifter (or alternatively, a first stage of a multi-stage voltage level shifter);

[0007] Figure 2 is shown in more detail Figure 1 A schematic diagram of the structure of

[0008] Figure 3 It is shown that Figure 1 and Figure 2 The input voltage pulse of the structure and the Figure 1 and Figure 2 The timing diagram of the output voltage pulse of the structure;

[0009] Figure 4 is a schematic diagram illustrating an embodiment of a multi-stage voltage level shifter;

[0010] Figure 5 is shown in more detail Figure 4 A schematic diagram of a second voltage shifting stage of a structure of;

[0011] Figures 6A-6C It is shown that Figure 5 The input voltage pulse of the second voltage shift stage and the Figure 5 2 is a timing diagram of the output voltage pulses of the second voltage shifting stage. DETAILED DESCRIPTION

[0012] As described above, considerations in modern integrated circuit (IC) design include, but are not limited to, performance improvements, size scaling, and power consumption. Typically, design changes made to improve one aspect of a design may produce undesirable tradeoffs with respect to one or more other aspects of the design. For example, a voltage level shifter in an IC design may be configured to convert (i.e., shift) a voltage signal from one logic level or voltage domain to another. Voltage level shifter designs that include low-voltage transistors (such as 2.0V transistors or lower (e.g., 1.8V transistors, 1.5V transistors, 0.8V transistors, etc.) to reduce power consumption have been developed. However, at least some of the low-voltage transistors in these voltage level shifters tend to operate quickly outside the safe operating area (SOA). Those skilled in the art will recognize that SOA refers to the maximum time that a transistor (e.g., a metal oxide semiconductor field effect transistor (MOSFET)) can be exposed to a specific voltage and current (e.g., the drain current (ID) and drain-source voltage (VDS) in the case of a MOSFET, etc.). To avoid operation outside the SOA, and thereby avoid device stresses that could lead to early device failure, the data sheet for a given MOSFET will specify, for example, the maximum operating VDS, the maximum operating gate-source voltage (VGS), and the maximum operating gate-drain voltage (VGD). Voltage level shifter designs that include all low voltage transistors are typically unable to achieve the desired voltage level shift without violating at least one of these maximums in at least one of the low voltage transistors. Design modifications intended to avoid operation outside the SOA include, for example, using asymmetric high voltage transistors (e.g., laterally diffused metal oxide semiconductor field effect transistors (LDMOSFETs)) to replace risky low voltage transistors and / or using discrete bias circuits. While such design modifications can successfully avoid operation outside the SOA, they also increase circuit complexity, power consumption, and area.

[0013] In view of the above, embodiments of structures including a single-stage voltage level shifter or a multi-stage voltage level shifter are disclosed herein. A first voltage shifting stage of the single-stage voltage level shifter or the multi-stage voltage level shifter may be connected to a first positive voltage rail at a first positive voltage (V1) and a second positive voltage rail at a second positive voltage (V2) substantially twice the magnitude of the first positive voltage V1. The voltage level shifter may also be configured to receive a plurality of input voltage pulses (including input voltage pulses converted between V1 and ground (e.g., at 0 volts)) and output a plurality of output voltage pulses (including intermediate output voltage pulses converted between voltages V1 and V2 and final output voltage pulses converted between ground and V2). In a multi-stage voltage level shifter, each downstream stage may receive an output voltage pulse from a previous stage as input and may similarly output a plurality of output voltage pulses (as discussed in more detail below). For example, a voltage level shifter may include all low voltage (V) transistors (e.g., 3.3V transistors or lower (e.g., 1.8V, 1.5V, or 0.8V) transistors), and these transistors may all be designed to be symmetrical (without any process variations) in order to reduce power consumption and circuit complexity while still avoiding operation outside of the SOA.

[0014] More specifically, Figure 1 is a schematic diagram generally illustrating an embodiment of a circuit structure 100, Figure 2 1 is a schematic diagram showing a specific embodiment of the circuit structure 100. The circuit structure 100 can be a stand-alone single-stage voltage level shifter, such as Figure 1 and Figure 2 Alternatively, as discussed in more detail below and in Figure 4 As generally shown in FIG. 1 , the circuit structure 100 may be a first voltage shifting stage of a multi-stage voltage level shifter 400 .

[0015] Circuit structure 100 (as described above, which may be Figure 1 A single-stage voltage level shifter as shown, or Figure 4The first voltage shifting stage of the multi-stage voltage level shifter 400 shown in the figure) may include multiple transistors. As discussed in more detail below, these transistors may include P-type transistors and N-type transistors. For the purpose of illustration, the P-type transistors and N-type transistors are described below and shown in the figures as metal oxide semiconductor field effect transistors (MOSFETs), and specifically are P-type field effect transistors (PFETs) and N-type field effect transistors (NFETs), respectively. MOSFET refers to a transistor having a semiconductor channel region laterally positioned between a source region and a drain region, and a gate (e.g., including a gate dielectric-gate conductor stack) adjacent to the channel region. However, it should be understood that the drawings and discussions of the present disclosure are not intended to be limiting. For example, alternatively, bipolar junction transistors (BJTs), specifically PNP BJTs and NPN BJTs, may be used to form similar circuit structures.

[0016] The transistors may all have the same maximum rated voltage, and in order to reduce power consumption, the maximum rated voltage (VDDW) may be relatively low, as specified in the transistor data sheet. For example, the transistor may have a maximum rated voltage of 3.3 volts (V) or less. In some embodiments, the transistor may have a maximum rated voltage of 1.8V, 1.5V, or 0.8V. In order to minimize manufacturing complexity, the transistors may all be symmetrical. That is, they may be designed so that the source region and the drain region are identical (e.g., the same size, doping, etc.) except for minor process variations, and so that the same maximum rated voltage is applied to the gate-source voltage (VGS), the gate-drain voltage (VGD), and the drain-source voltage (VDS). As discussed in more detail below, the circuit structure 100 may also be configured to achieve voltage level shifting without violating any of these maximum rated voltages, thereby avoiding device stress and ensuring operation within the SOA.

[0017] Specifically, the circuit structure 100 can be electrically connected to a first voltage rail 191 at a first positive voltage (V1). V1 can be specifically set to be equal to the maximum rated voltage (VDDW) of the transistor. The circuit structure 100 can also be electrically connected to a second voltage rail 192 at a second positive voltage (V2). V2 can be higher than V1, and more specifically, can be substantially twice the size of V1. For the purposes of this disclosure, "substantially twice the size" means twice the size plus or minus 10% thereof (e.g., if V1 is 1.8V, then V2=3.6V+ / -.36V, etc.). Thus, for example, if the maximum rated voltage of the transistor is 1.8V, then V1 can be set to 1.8V and V2 can be set to 3.6V. If the maximum rated voltage is 1.5V, then V1 can be set to 1.5V and V2 can be set to 3.0V. If the maximum rated voltage is 0.8V, then V1 can be set to 0.8V and V2 can be set to 1.6V. The circuit structure 100 may include two input nodes 145a and 145b and four output nodes, including two intermediate output nodes 125a-125b and two final output nodes 135a-135b.

[0018] The circuit structure 100 can be connected to receive two input voltage pulses at two input nodes, specifically, an input voltage pulse (IN1) that switches between V1 and ground (e.g., 0 volts) at input node 145a, and an inverted input voltage pulse (IN1b) at input node 145b, IN1b being inverted relative to IN1 so that when IN1 switches from V1 to ground, IN1b switches from ground to V1, and vice versa. The circuit structure 100 can also be configured to generate and output four different output voltage pulses, including two intermediate output voltage pulses at intermediate output nodes 125a-125b and two final output voltage pulses at final output nodes 135a-135b. The two intermediate output voltage pulses may include an intermediate output voltage pulse (OUT1) at the intermediate output node 125b that switches between V1 and V2. i ), and the inverted intermediate output voltage pulse (OUT1B) at the intermediate output node 125a i ), OUT1B i Relative to OUT1 i Inverting, therefore, when OUT1 i When switching from V1 to V2, OUT1B iThe two final output voltage pulses may include a final output voltage pulse (OUT1) at the final output node 135b that switches between ground and V2, and an inverted final output voltage pulse (OUT1B) at the final output node 135a that is inverted relative to OUT1, so that when OUT1 switches from ground to V2, OUT1B switches from V2 to ground, and vice versa.

[0019] For purposes of this disclosure, a "voltage pulse" refers to a substantially rectangular DC voltage signal that switches between a low voltage level and a high voltage level at regular and repetitive intervals, such that the pulse remains at the low voltage level for a first time period (t1), then switches to a high voltage level and remains at the high voltage level for a second time period (t2) (which may be the same or different from t1), then switches back to the low voltage level and remains at the low voltage level again for t1, and so on.

[0020] refer to Figure 2 In some embodiments, the circuit structure 100 may include symmetrical branches 101a-101b connected in parallel between a first voltage rail 191 and a second voltage rail 192.

[0021] Each branch 101a, 101b may include a first PFET 110a, 110b and a second PFET 120a, 120b connected in series between a first voltage rail 191 and a second voltage rail 192. That is, the first PFET 110a, 110b may include a drain region 113a, 113b, a gate 112a, 112b, and a source region 111a, 111b electrically connected to the first voltage rail 191. The second PFET 120a, 120b may include a drain region 123a, 123b electrically connected to the source region 111a, 111b of the first PFET 110a, 110b, a gate 122a, 122b, and a source region 121a, 121b electrically connected to the second voltage rail 192. In some embodiments, the source regions 111a, 111b of the first PFET 110a, 110b and the drain regions 123a, 123b of the second PFET 120a, 120b may be shared source / drain regions. In other embodiments, the source regions 111a, 111b of the first PFET 110a, 110b and the drain regions 123a, 123b of the second PFET 120a, 120b may be separate regions electrically connected by interconnects.

[0022] Each branch 101a, 101b may also include a third PFET 130a, 130b electrically connected to a junction 116a, 116b between the first PFET 110a, 110b and the second PFET 120a, 120b and an intermediate output node 125a, 125b. The third PFET 130a, 130b may specifically include: a source region 131a, 131b electrically connected to the junction 116a, 116b between the first PFET 110a, 110b and the second PFET 120a, 120b; a drain region 133a, 133b electrically connected to the final output node 135a, 135b and also electrically connected to the gate 112a, 112b of the first PFET 110a, 110b; and a gate 132a, 132b electrically connected to, for example, the first voltage rail 191 to receive V1.

[0023] In addition, the second PFET 120a of the branch 101a and the second PFET 120b of the branch 101b can be cross-coupled. That is, the gate 122a of the second PFET 120a in the branch 101a can be electrically connected to the junction 116b between the first PFET 110b and the second PFET 120b in the branch 101b, and the gate 122b of the second PFET 120b in the branch 101b can be electrically connected to the junction 116a between the first PFET 110a and the second PFET 120a in the branch 101a.

[0024] Finally, each branch 101a, 101b may also include an NFET 140a, 140b (also referred to herein as a pass-gate NFET). The NFET 140a, 140b may include: a source region 141a, 141b, which is electrically connected to the input node 145a, 145b; a drain region 143a, 143b, which is electrically connected to the final output node 135a, 135b (and thus electrically connected to the drain region 133a, 133b of the third PFET 130a, 130b and the gate 112a, 112b of the first PFET 110a, 110b).

[0025] Figure 3 1 and 1B illustrate input voltage pulses IN1 and IN1B to the circuit structure 100 and output voltage pulses OUT1 from the circuit structure 100. i OUT1B i, OUT1, OUT2, where the maximum rated voltage of all transistors 110a-110b, 120a-120b, 130a-130b, and 140a-140b is 1.8V. That is, maxVGS=1.8V, maxVDS=1.8V, maxVGD=1.8V. Therefore, V1 is 1.8V and V2 is 2*1.8V or 3.6V. In addition, the rising edge (0 to 1.8V) and falling edge (1.8 to 0V) of IN1 at input node 145a will be synchronized with the falling edge (1.8 to 0V) and rising edge (0 to 1.8V) of IN1B at input node 145b.

[0026] In operation, V1 (which is equal to the maximum rated voltage (VDDW) of the transistors) is continuously applied to the gates 142a, 142b of the NFETs 140a, 140b and the gates 132a, 132b of the third PFETs 130a, 130b. When IN1 switches from ground to V1 and IN1B switches from V1 to ground, in branch 101b, the gate voltage and source voltage of NFET 140b are at V1 and ground, respectively, thus reaching the threshold voltage (VT) of NFET 140b. NFET 140b turns on and pulls the voltage on the final output node 135b down to ground, so OUT1 is at ground. When the voltage on the final output node 135b is at ground, the gate voltage on the first PFET 110b is at ground and reaches the VT of the first PFET 110b. The first PFET 110b turns on, pulling the voltage at the intermediate output node 125b down to V1, so OUT1 i The gate voltage and source voltage of the third PFET 130b are both at V1, so the third PFET 130b remains off. In branch 101a, the gate voltage of the second PFET 120a is at V1 and the source voltage is at V2, so the VT of the second PFET 120a is reached. The second PFET 120a is turned on, thereby pulling the voltage on the intermediate output node 125a up to V2, so OUT1B i 135a is turned on, and the voltage on the final output node 135a is pulled up to V2, so OUT1B becomes V2. The third PFET 130a also pulls up the gate voltage of the first PFET 110a to V2, so the first PFET 110 remains off. Since the gate voltage and source voltage of the NFET 140a are both at V1, the NFET 140a also remains off.

[0027] When the IN1 transistor switches from V1 to ground and the IN1B transistor switches from ground to V1, a phase reversal occurs. In branch 101a, the gate voltage and source voltage on NFET 140a are at V1 and ground, respectively, and thus reach the VT of NFET 140a. NFET 140a turns on and pulls the voltage on the final output node 135a down to ground, so OUT1B is at ground. When the voltage on the final output node 135a is at ground, the gate voltage on the first PFET 110a is at ground and reaches the VT of the first PFET 110a. The first PFET 110a turns on, pulling the voltage at the intermediate output node 125a down to V1, so OUT1B i The gate voltage and source voltage of the third PFET 130a are both at V1, so the third PFET 130a remains off. In addition, in branch 101b, the gate voltage on the second PFET 120b is at V1 and the source voltage is at V2, thus reaching the VT of the second PFET 120b. The second PFET 120b is turned on, thereby pulling the voltage on the intermediate output node 125b up to V2, so OUT1 i 135b is turned on, and the voltage on the final output node 135b is pulled up to V2, so OUT1 becomes V2. When the intermediate output node 125b is at V2, the second PFET 120a remains off. In addition, the gate voltage and the source voltage on the third PFET 130b are at V1 and V2, respectively, so the VT of the third PFET 130b is reached. The third PFET 130b is turned on, pulling up the voltage on the final output node 135b to V2, so OUT1 becomes V2. The third PFET 130b also pulls up the gate voltage on the first PFET 110b to V2, so the first PFET 110b remains off. Since the gate voltage and the source voltage on the NFET 140b are both at V1, the NFET 140b also remains off.

[0028] Therefore, as shown, OUT1 at the intermediate output node 125b i Switching between V1 and V2 and back (e.g., switching between 1.8V and 3.6V and back), OUT1B at the intermediate output node 125a i Relative to OUT1 i Inverting (that is, when OUT1 i When switching from 1.8V to 3.6V, OUT1B i1.8V and vice versa). In addition, OUT1 at the final output node 135b switches between ground and V2 and back (e.g., between 0V and 3.6V and back), and OUT1B at the final output node 135a is inverted relative to OUT1 (i.e., when OUT1 switches from 0V to 3.6V, OUT1B switches from 3.6V to 0V and vice versa). However, all transistors 110a-110b, 120a-120b, 130a-130b, 140a-140b are low voltage symmetrical transistors, and none of these transistors 110a-110b, 120a-102b, 130a-130b, 140a-140b operates above the maximum VGS. Therefore, the transistors operate within the SOA.

[0029] As described above, the circuit structure 100 can be a stand-alone single-stage voltage level shifter that operates to provide a voltage level shift up to V2 (ie, up to 2*V1). Alternatively, as discussed in more detail below and in Figure 4 As generally shown in FIG. 1 , the circuit structure 100 can be incorporated into another circuit structure, and more specifically, can be used as the first voltage shifting stage of a multi-stage voltage level shifter 400 configured to further shift the voltage (e.g., to 3*V1, to 4*V1, etc.).

[0030] refer to Figure 4 , this document also discloses an embodiment of a multi-stage voltage level shifter 400, which includes the circuit structure 100 as a first voltage shift stage (VS STAGE 1) as described in detail above, and includes one or more additional voltage shift stages, including a second voltage shift stage 200 (VS STAGE 2), and optionally, includes additional voltage shift stages up to the nth stage (VS STAGE n).

[0031] The multi-stage voltage level shifter 400 may include multiple positive voltage rails. For a two-stage voltage level shifter, the positive voltage rails may include: a first voltage rail 191 at V1, V1 being equal to the maximum rated voltage (VDDW) of the transistors; and a second voltage rail 192 at V2, V2 being substantially twice the size of V1 (as described above); and a third voltage rail 292 at a third positive voltage (V3), V3 being substantially three times the size of V1. For purposes of this disclosure, "substantially three times the size" means three times the size plus or minus 10% thereof (e.g., if V1 is 1.8V, then V3 = 5.4V + / - .54V, etc.). Thus, for example, if the transistors are all 1.8V transistors, then V1 of the first voltage rail 191 may be 1.8V, V2 of the second voltage rail 192 may be 3.6V, and V3 of the third voltage rail may be 5.4V. Alternatively, if the transistors are all 1.5V transistors, V1 of the first voltage rail 191 may be 1.5V, V2 of the second voltage rail 192 may be 3.0V, and V3 of the third voltage rail may be 4.5V. Alternatively, if the transistors are all 0.8V transistors, V1 of the first voltage rail 191 may be 0.8V, V2 of the second voltage rail 192 may be 1.6V, and V3 of the third voltage rail may be 2.4V.

[0032] As mentioned above, the configuration of VS STAGE 1 can be Figure 1-2 Therefore, VSSTAGE 1 can receive two first input voltage pulses including IN1 and IN1B, and can output OUT1 i OUT1B i , OUT1, and OUT1B. VS STAGE 2 can be connected to the second voltage rail 192 (at V2=2*V1) and the third voltage rail 292 (at V3=3*V1). VS STAGE 2 can also be connected to receive the four first output voltage pulses from VS STAGE 1 (i.e., OUT1 i OUT1B i , OUT1 and OUT1B) as inputs, and can also be configured to generate and output a plurality of second output voltage pulses, specifically six second output voltage pulses (including a final second output voltage pulse (OUT2) converted between ground and V3, as discussed in more detail below).

[0033] Optionally, the multi-stage voltage level shifter 400 may include additional voltage shifting stages. For example, the multi-stage voltage level shifter 400 may also include a third voltage shifting stage 300 (VS STAGE 3). VS STAGE 3 may be connected to the third voltage rail 292 (at V3=3*V1) and the fourth voltage rail (at V4=4*V1). VS STAGE 3 may also be connected to receive the six second output voltage pulses from VS STAGE 2 as input, and may be configured to generate and output a plurality of third output voltage pulses, specifically eight third output voltage pulses, which (as discussed in more detail below) include a final third output voltage pulse (OUT3) converted between ground and V4. Optionally, the multi-stage voltage level shifter 400 may also include additional voltage shifting stages up to the nth stage. In a multi-stage voltage level shifter embodiment, each additional voltage shifting stage has a similar structure to the previous voltage shifting stage, but with the addition of four additional transistors (one PFET and one NFET added to each of the two parallel branches), and also has two additional inputs and two additional outputs.

[0034] Figure 5 It is shown that it can be incorporated into Figure 4 Schematic diagram of an example of a second voltage shift stage 200 (VSSTAGE 2) in a multi-stage voltage level shifter 400. As shown, the second voltage shift stage 200 (VS STAGE 2) can be connected to the second voltage rail 192 (at V2=2*V1) and the third voltage rail 292 (at V3=3*V3). The configuration of the second voltage shift stage 200 can be similar to that of VS STAGE 1, but with a total of twelve transistors instead of ten, as described below. Specifically, VS STAGE 2 can include symmetrical branches 201a-201b connected in parallel between the second voltage rail 192 and the third voltage rail 292. Each branch 201a, 201b can include a first PFET 210a, 210b and a second PFET 220a, 220b connected in series between the second voltage rail 192 and the third voltage rail 292. That is, the first PFETs 210a, 210b may include drain regions 213a, 213b, gates 212a, 212b, and source regions 211a, 211b electrically connected to the second voltage rail 192. The second PFETs 220a, 220b may include drain regions 223a, 223b electrically connected to the source regions 211a, 211b of the first PFETs 210a, 210b, gates 222a, 222b, and source regions 221a, 221b electrically connected to the third voltage rail 292.

[0035] Each branch 201a, 201b may also include a third PFET 230a, 230b electrically connected to a junction 216a, 216b between the first PFET 210a, 210b and the second PFET 220a, 220b and an intermediate output node 225a, 225b. The third PFET 230a, 230b may specifically include: a source region 231a, 231b electrically connected to the junction 216a, 216b between the first PFET 210a, 210b and the second PFET 220a, 220b; a drain region 233a, 233b electrically connected to another intermediate output node 235a, 235b and also electrically connected to the gate 212a, 212b of the first PFET 210a, 210b; and a gate 232a, 232b electrically connected to, for example, the second voltage rail 192 to receive V2.

[0036] Each branch 201a, 201b may also include a first NFET 240a, 240b (also referred to herein as a first pass-gate NFET). The first NFET 240a, 240b may include: a source region 241a, 241b electrically connected to an intermediate input node 245a, 245b; a drain region 243a, 243b electrically connected to an intermediate output node 235a, 235b (and thereby electrically connected to the drain region 233a, 233b of the third PFET 230a, 230b and the gate 212a, 212b of the first PFET 210a, 210b); and a gate 242a, 242b electrically connected to, for example, the second voltage rail 192 to receive V2. The intermediate input node 245a may be connected to receive OUT1B from VS STAGE 1 i As an input, intermediate input node 245b can be connected to receive OUT1 from VS STAGE 1 i As mentioned above, OUT1 i Switching between V1 and V2, OUT1B i Relative to OUT1 i Invert.

[0037] Each branch 201a, 201b may also include a final output node 255a, 255b and a fourth PFET 250a, 250b electrically connected in series between the third PFET 230a, 230b and the final output node 255, 255b. The fourth PFET 250a, 250b may specifically include: a source region 251a, 251b electrically connected to the intermediate output node 235a, 235b; a drain region 253a, 253b electrically connected to the final output node 255a, 255b; and a gate 252a, 252b. The gate 252a of the fourth PFET 250a in the branch 201a may specifically be connected to the intermediate input node 245a to receive OUT1B from VS STAGE 1. i As an input, the gate 252b of the fourth PFET 250b in the branch 201b can be specifically connected to the intermediate input node 245b to receive OUT1 from VS STAGE 1. i As mentioned above, OUT1 i Switching between V1 and V2, OUT1B i Relative to OUT1 i Invert.

[0038] Each branch 201a, 201b may also include a second NFET 260a, 260b (also referred to herein as a second pass-gate NFET). The second NFET 260a, 260b may include: a source region 261a, 261b, which is electrically connected to the input node 265a, 265b; a drain region 263a, 263b, which is electrically connected to the final output node 255a, 255b (and thus electrically connected to the drain region 253a, 253b of the fourth PFET 250a, 250b); and a gate 262a, 262b. The gate 262a of the second NFET 260a may be specifically connected to receive OUT1B from the intermediate input node 245a. i , and the gate 262b of the second NFET 260b may be specifically connected to receive OUT1 from the intermediate input node 245b i Additionally, input node 265a may be connected to receive OUT1B from VS STAGE 1 as an input, and input node 265b may be connected to receive OUT1 from VS STAGE 1 as an input. As described above, OUT1 switches between ground and V2, and OUT1B is inverted relative to OUT1.

[0039] The second PFET 220a of the branch 201a and the second PFET 220b of the branch 201b may be cross-coupled. That is, the gate 222a of the second PFET 220a in the branch 201a may be electrically connected to the junction 216b between the first PFET 210b and the second PFET 220b in the branch 201b, and the gate 222b of the second PFET 220b in the branch 201b may be electrically connected to the junction 216a between the first PFET 210a and the second PFET 220a in the branch 201a.

[0040] Figures 6A-6C An example of a timing diagram is shown, which illustrates the entry (eg, as described in more detail below) of the multi-stage voltage level shifter 400, particularly in the case where the maximum rated voltage of all transistors in the multi-stage voltage level shifter 400 is 1.8V. Figure 4 The multi-stage voltage level shifter 400 (eg, as shown) Figure 5 ) VS STAGE 2 configured as shown and various voltage pulses output from VS STAGE 2. That is, maxVGS = 1.8V, maxVDS = 1.8V, maxVGD = 1.8V. Therefore, V1 is 1.8V, V2 is 2*1.8V or 3.6V, and V3 is 5.4V.

[0041] Fig. 6A Specifically, four first output voltage pulses OUT1 are shown. i OUT1B i , OUT1, and OUT1B, which are generated and output by VSSTAGE 1 and received as input by VS STAGE 2. As discussed in detail above and shown in the figure, OUT1 i Switching between V1 and V2, OUT1B i Relative to OUT1 i Inverting, OUT1 switches between ground and V2, and OUT1B is inverted relative to OUT1.

[0042] Figure 6B Specifically, four intermediate second output voltage pulses generated and outputted by VS STAGE 2 in response to the voltage pulse received from VS STAGE 1 are shown. These intermediate second output voltage pulses include: an intermediate second output voltage pulse (OUT2 ) generated and outputted at an intermediate output node 225 b in branch 201 b; i1 ), an inverted intermediate second output voltage pulse (OUT2B) generated and output at the intermediate output node 225a in the branch 201a. il ), an additional intermediate second output voltage pulse (OUT2 i2), and an inverted additional intermediate second output voltage pulse (OUT2B) generated and output at the intermediate output node 235b in branch 201b. i2 ). As indicated, OUT2 i1 Switching between V2 and V3, OUT2B il Relative to OUT2 i1 Inverting (i.e., when OUT2 il When switching from V3 to V2, OUT2B il from V3 to V2 and vice versa), OUT2 i2 Switching between V1 and V3, OUT2B i2 Relative to OUT2 i2 Inverting (i.e., when OUT2 i2 When switching from V1 to V3, OUT2B i2 from V3 to V1 and vice versa).

[0043] Figure 6C Specifically shown are two final second output voltage pulses generated and output by VS STAGE 2, including: a final second output voltage pulse (OUT2) generated and output at a final output node 255b in branch 201b, and an inverted final second output voltage pulse (OUT2B) generated and output at a final output node 255a in branch 201a. As indicated, OUT2 switches between ground and V3, and OUT2B is inverted relative to OUT2 (i.e., when OUT2 switches from ground to V3, OUT2B switches from V3 to ground, and vice versa).

[0044] Reference again Figure 4 Optionally, the multi-stage voltage level shifter 400 may include one or more additional voltage shifting stages. As described above, in a multi-stage voltage level shifter embodiment, each additional voltage shifting stage will be connected between the high voltage rail from the previous voltage shifting stage and the next higher voltage rail. Each additional voltage shifting stage is similar in structure to the previous voltage shifting stage, but has an additional voltage rail, four additional transistors (one PFET and one NFET added to each branch), and has two additional inputs and two additional outputs.

[0045] For example, in a three-stage voltage level shifter, VS STAGE 1 would be connected to a first voltage rail and a second voltage rail at V1 and V2, respectively, and VS STAGE 2 would be connected to a second voltage rail and a third voltage rail at V2 and V3, respectively. The third voltage shift stage 300 (VS STAGE 3) would be further connected to a third voltage rail at V3 and a fourth voltage rail at a fourth positive voltage level (V4) that is four times greater than V1. Thus, for example, if the transistors are all 1.8V transistors, then V1 of the first voltage rail 191 would be 1.8V, V2 of the second voltage rail 192 would be 3.6V, V3 of the third voltage rail would be 5.4V, and V4 of the fourth voltage rail would be 7.2V. Alternatively, if the transistors are all 1.5V transistors, then V1 of the first voltage rail 191 would be 1.5V, V2 of the second voltage rail 192 would be 3.0V, V3 of the third voltage rail would be 4.5V, and V4 of the fourth voltage rail would be 6.0V. Alternatively, if the transistors are all 0.8V transistors, then V1 of the first voltage rail 191 will be 0.8V, V2 of the second voltage rail 192 will be 1.6V, V3 of the third voltage rail will be 2.4V, and V4 of the fourth voltage rail will be 3.2V.

[0046] The configuration of VS STAGE 3 is similar to that of VS STAGE 2, except that in each branch of VS STAGE 3, the drain regions of the second NFET and the fourth PFET will be connected to another intermediate output node, the fifth PFET will be electrically connected in series between the fourth PFET and the final output node, and the third NFET will also be electrically connected to the final output node. The third voltage shift stage will receive as input the six second output voltage pulses from VS STAGE 2 (as described above), and will generate and output eight third output voltage pulses, as shown, including a final third output voltage (OUT3) that switches between ground and V4, and an inverted final third output voltage (OUT3B) that is inverted relative to OUT3 (i.e., when OUT3 switches from ground to V4, OUT3B switches from V4 to ground, and vice versa).

[0047] In the single-stage and multi-stage voltage level shifters disclosed herein and shown in the figures, all transistors (in all stages) can have the same maximum rated voltage, and to reduce power consumption, the maximum rated voltage (VDDW) can be relatively low, as specified in the transistor data sheet (e.g., 3.3 volts (V) or lower maximum rated voltage, such as 1.8V, 1.5V or 0.8V). To minimize manufacturing complexity, the transistors can also all be symmetrical. That is, they can be designed so that the source and drain regions are substantially the same (e.g., the same size, the same doping, the same distance separated from the gate, etc.) except for minor process variations, and so that the same maximum rated voltage is applied to the gate-source voltage (VGS), the gate-drain voltage (VGD), and the drain-source voltage (VDS). In addition, given the unique configuration of each stage (e.g., including input voltage pulses on the source region of the NFET pass-gate transistor and cross-coupled PFETs, etc.), voltage level shifting is achieved without violating any maximum rated voltage to avoid device stress and ensure operation within the SOA. Furthermore, stack power consumption is minimized since there is no direct path between power and ground and no additional biasing circuits are required.

[0048] The above-described embodiments including single-stage voltage level shifters and multi-stage voltage level shifters may be incorporated into, for example, any circuit that requires the use of various different voltage pulses (eg, for generating different clock signals, different control signals, etc.).

[0049] It should be understood that the terms used herein are used to describe the disclosed structures and methods and are not intended to be limiting. For example, as used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. In addition, as used herein, the terms "comprises", "comprising", "includes", and / or "including" specify the presence of the features, wholes, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts, and / or groups thereof. In addition, as used herein, when oriented and shown in the figures, terms such as "right", "left", "vertical", "horizontal", "top", "bottom", "upper", "lower", "below", "under", "underlying", "above", "overlying", "parallel", "vertical", etc. are intended to describe relative positions (unless otherwise specified), and terms such as "touching", "direct contact", "adjacent", "directly adjacent", "immediately adjacent", etc. are intended to indicate that at least one element is in physical contact with another element (no other elements separate the elements). The term "laterally" is used herein to describe the relative position of elements and, more specifically, to indicate that one element is to the side of another element, rather than above or below the other element, when the elements are oriented and shown in the figures. For example, an element positioned laterally adjacent to another element will be to the side of the other element, an element positioned laterally next to another element will be directly to the side of the other element, and an element laterally surrounding another element will be adjacent to and bordering the outer sidewall of the other element. The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the following claims are intended to include any structure, material, or act for performing a function in combination with other claimed elements as specifically claimed.

[0050] The description of the various disclosed embodiments is given for the purpose of illustration, but is not intended to be exhaustive or limiting. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosed embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications or technical improvements to technologies found on the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising: a first voltage rail at a first positive voltage; a second voltage rail at a second positive voltage higher than the first positive voltage; as well as a voltage level shifter connected to the first voltage rail and the second voltage rail, The voltage level shifter receives a plurality of input voltage pulses and outputs a plurality of output voltage pulses. wherein the plurality of input voltage pulses include input voltage pulses converted between the first positive voltage and ground, and The plurality of output voltage pulses include an intermediate output voltage pulse converted between the first positive voltage and the second positive voltage, and a final output voltage pulse converted between ground and the second positive voltage.

2. The structure according to claim 1, in, The voltage level shifter further comprises a plurality of transistors, wherein the plurality of transistors have a same rated voltage equal to the first positive voltage, and Wherein, the second positive voltage is substantially twice the first positive voltage.

3. The structure according to claim 2, wherein: The plurality of transistors are symmetrical transistors.

4. The structure according to claim 1, wherein: The first positive voltage is 3.3 volts or less.

5. The structure according to claim 1, wherein: The first positive voltage is one of 1.8 volts, 1.5 volts, and 0.8 volts.

6. The structure according to claim 1, wherein: The voltage level shifter comprises: two input nodes, which respectively receive the plurality of input voltage pulses, wherein the plurality of input voltage pulses include the input voltage pulse and an inverted input voltage pulse; and Four output nodes respectively output the plurality of output voltage pulses, wherein the plurality of output voltage pulses include the final output voltage pulse, an inverted final output voltage pulse, the intermediate output voltage pulse and an inverted intermediate output voltage pulse.

7. The structure according to claim 6, in, The voltage level shifter further comprises two branches connected between the first voltage rail and the second voltage rail, and Each branch includes: an input node and an N-type transistor, wherein the N-type transistor has a source region connected to the input node and a gate connected to receive the first positive voltage.

8. The structure according to claim 7, wherein: Each branch includes: a first P-type transistor; a second P-type transistor, wherein the first P-type transistor and the second P-type transistor are connected in series between the first voltage rail and the second voltage rail; an intermediate output node located at a junction between the first P-type transistor and the second P-type transistor; and a third P-type transistor having a source region connected to the junction, a gate connected to receive the first positive voltage, and a drain region connected to an output node, the drain region of the N-type transistor, and the gate of the first P-type transistor, and Wherein, between the two branches, the second P-type transistor is cross-coupled.

9. A structure comprising: a first voltage rail at a first positive voltage; a second voltage rail at a second positive voltage higher than the first positive voltage; as well as a voltage level shifter connected to the first voltage rail and the second voltage rail, The voltage level shifter comprises: two input nodes; two N-type transistors having source regions respectively connected to the input nodes and also having gates connected to receive the first positive voltage; and four output nodes, The voltage level shifter receives two input voltage pulses at the input nodes respectively, and outputs four output voltage pulses at the output nodes respectively, The two input voltage pulses include: an input voltage pulse converted between the first positive voltage and ground; and an inverted input voltage pulse, and Among them, the four output voltage pulses include: an intermediate output voltage pulse converted between the first positive voltage and the second positive voltage; an inverted intermediate output voltage pulse; a final output voltage pulse converted between ground and the second positive voltage; and an inverted final output voltage pulse.

10. The structure according to claim 9, in, The voltage level shifter further comprises a plurality of transistors, wherein the plurality of transistors have a same rated voltage equal to the first positive voltage, and Wherein, the second positive voltage is substantially twice the first positive voltage.

11. The structure according to claim 10, wherein: The plurality of transistors are symmetrical transistors.

12. The structure according to claim 9, wherein: The first positive voltage is 3.3 volts or less.

13. The structure according to claim 9, wherein: The first positive voltage is one of 1.8 volts, 1.5 volts, and 0.8 volts.

14. The structure according to claim 9, in, The voltage level shifter comprises two branches, Each branch includes: a first P-type transistor; a second P-type transistor, wherein the first P-type transistor and the second P-type transistor are connected in series between the first voltage rail and the second voltage rail; an intermediate output node located at a junction between the first P-type transistor and the second P-type transistor; and a third P-type transistor having a source region connected to the junction, a gate connected to receive the first positive voltage, and a drain region connected to an output node, the drain region of the N-type transistor, and the gate of the first P-type transistor, and Wherein, between the two branches, the second P-type transistor is cross-coupled.

15. A structure comprising: a plurality of voltage rails including at least: a first voltage rail at a first positive voltage; a second voltage rail at a second positive voltage higher than the first positive voltage; and a third voltage rail at a third positive voltage higher than the second positive voltage; and A voltage level shifter comprising a plurality of voltage shifting stages, the voltage shifting stages comprising at least: a first voltage shifting stage connected to the first voltage rail and the second voltage rail, wherein the first voltage shifting stage receives a plurality of first input voltage pulses and outputs a plurality of first output voltage pulses, wherein the plurality of first input voltage pulses includes first input voltage pulses converted between the first positive voltage and ground, and wherein the plurality of first output voltage pulses includes intermediate first output voltage pulses converted between the first positive voltage and the second positive voltage and final first output voltage pulses converted between ground and the second positive voltage; and a second voltage shifting stage connected to the second voltage rail and the third voltage rail, wherein the second voltage shifting stage receives the plurality of first output voltage pulses and outputs a plurality of second output voltage pulses, and wherein the plurality of second output voltage pulses include at least intermediate second output voltage pulses converted between the second positive voltage and the third positive voltage, additional intermediate second output voltage pulses converted between the first positive voltage and the third positive voltage, and a final second output voltage pulse converted between ground and the third positive voltage.

16. The structure according to claim 15, in, The voltage level shifter further comprises a plurality of transistors, wherein the plurality of transistors are symmetrical transistors having the same rated voltage equal to the first positive voltage, wherein the second positive voltage is substantially twice the first positive voltage, and Wherein, the third positive voltage is substantially three times the first positive voltage.

17. The structure of claim 15, wherein: The first positive voltage is 3.3 volts or less.

18. The structure of claim 15, wherein: The first positive voltage is one of 1.8 volts, 1.5 volts, and 0.8 volts.

19. The structure according to claim 15, in, The first voltage shifting stage further comprises: two first input nodes, which respectively receive the plurality of first input voltage pulses, wherein the plurality of first input voltage pulses include the first input voltage pulse and an inverted first input voltage pulse; and four first output nodes, which respectively output the plurality of first output voltage pulses, wherein the plurality of first output voltage pulses include the final first output voltage pulse, the inverted final first output voltage pulse, the intermediate first output voltage pulse and the inverted intermediate first output voltage pulse, and Wherein, the second voltage shift stage further includes: four second input nodes, which respectively receive the plurality of first output voltage pulses; and six second output nodes, which respectively output the plurality of second output voltage pulses, wherein the plurality of second output voltage pulses include the final second output voltage pulse, the inverted final second output voltage pulse, the intermediate second output voltage pulse, the inverted intermediate second output voltage pulse, the additional intermediate second output voltage pulse, and the inverted additional intermediate second output voltage pulse.

20. The structure of claim 15, wherein: The second voltage shifting stage includes four more transistors than the first voltage shifting stage.

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