Space-time interference cancellation algorithm parallelization FPGA implementation device and method

Abstract

The application belongs to the technical field of digital signal processing, and specifically discloses a space-time interference cancellation algorithm parallelization FPGA implementation device and method. The device comprises: an input vector generation module, which delays and arranges a reference signal of multiple channels to obtain a space-time input vector of the reference signal; a correlation matrix calculation module, which obtains an autocorrelation matrix and a cross-correlation vector; a matrix decomposition module, which performs matrix decomposition on the autocorrelation matrix to obtain an upper triangular matrix; a weight determination module, which solves the weight by using the upper triangular matrix and the cross-correlation vector to obtain an optimal weight; a delay matching module, which delays the reference signal, aligns the reference signal and the optimal weight in time sequence, and obtains a delay matching result; and a weighted combination module, which weights the reference signal after time sequence alignment according to the optimal weight, combines the weighted signal and a received signal, and realizes interference cancellation of the received signal. The application can improve real-time tracking capability and reduce processing delay.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of digital signal processing, and more particularly to a space-time interference cancellation algorithm parallelization FPGA implementation device and method. BACKGROUND

[0002] In space-limited systems such as warships, tanks and aircraft, the intensive deployment of a large number of high-power transceivers and high-sensitivity receivers makes the co-site electromagnetic interference between radio frequency systems increasingly serious. In addition, malicious human interference from outside the platform will also have a huge impact on the normal reception of high-sensitivity receivers, affecting the efficiency of wireless communication.

[0003] Traditional anti-interference means has limited suppression ability, and has the problems of low spectrum utilization and poor communication timeliness, which cannot meet the interference cancellation requirements. With the development of signal processing technology, adaptive interference cancellation technology has been proven to effectively suppress interference signals in wireless communication systems, significantly improving the reliability of communication, and has become an effective means to solve the two types of interference, i.e. self-interference and external interference.

[0004] Currently, adaptive interference cancellation technology usually adopts LMS algorithm, normalized LMS algorithm, direct matrix inversion (DMI) algorithm and covariance matrix eigenvalue decomposition algorithm. However, the current algorithms still have many problems such as poor convergence stability, slow convergence speed, poor environmental adaptability, difficulty in meeting dynamic tracking requirements, high hardware implementation cost, large system delay and poor dynamic tracking performance.

[0005] Therefore, how to improve the real-time tracking capability of interference cancellation technology and reduce the processing delay is a technical problem that needs to be solved at present. SUMMARY

[0006] In view of the defects of the prior art, the purpose of the present application is to provide a space-time interference cancellation algorithm parallelization FPGA implementation device and method, which aims to solve the problems of large system delay and poor dynamic tracking performance of the current interference cancellation technology.

[0007] The present application provides a space-time interference cancellation algorithm parallelization FPGA implementation device, comprising: an input vector generation module, a correlation matrix calculation module, a matrix decomposition module, a weight determination module, a delay matching module and a weighted combination module.

[0008] The input vector generation module is used to collect the reference signals of multiple channels of a wireless transceiver radio frequency system, delay and arrange the reference signals of the multiple channels, and obtain the space-time input vector of the reference signals.

[0009] The correlation matrix calculation module is configured to obtain a self-correlation matrix based on the space-time input vector and obtain a cross-correlation vector based on the space-time input vector and a receiving signal of the wireless transceiver radio frequency system;

[0010] The matrix decomposition module is configured to perform matrix decomposition on the self-correlation matrix to obtain an upper triangular matrix.

[0011] The weight determination module is configured to solve weights by using the upper triangular matrix and the cross-correlation vector to obtain optimal weights.

[0012] The delay matching module is configured to delay the reference signal, time-align the reference signal and the optimal weights, and obtain a delay matching result.

[0013] The weighted combination module is configured to weight the time-aligned reference signal according to the optimal weights to obtain a weighted signal, combine the weighted signal with the receiving signal, and obtain a combined signal to realize interference cancellation of the receiving signal.

[0014] The application ensures synchronization of the reference signal and the actual signal in space and time through delay and arrangement, provides accurate input for subsequent processing, adaptively responds to signal environment changes through the correlation matrix adaptive module, obtains optimal weights through the weight determination module, enables the system to quickly converge and thus improves real-time tracking capability of the signal, reduces weight calculation delay, achieves the purpose of reducing cancellation processing delay and improving tracking performance, and through delay matching processing, time-aligns the reference signal and the optimal weights, reduces time delay in the signal processing process, reduces time delay in the processing process through weighting and signal combination, effectively suppresses interference, and improves interference cancellation effect.

[0015] In some optional examples, the input vector generation module includes N*(M-1) first delay units, N is a number of space domain reference signals, M is a time domain filter order, and N and M are positive integers.

[0016] The first delay unit is configured to generate M time domain signal sequences from N*M space domain reference signals, and sequentially arrange the N time domain signal sequences of the space domain to generate an N*M-dimensional space-time input vector.

[0017] In some optional examples, the correlation matrix calculation module includes a self-correlation matrix sub-module and a cross-correlation vector sub-module.

[0018] The self-correlation matrix includes ((N*M) 2 +N*M) / 2 first correlators.

[0019] The first correlator is configured to realize parallel calculation of N*M×N*M-dimensional space-time input vector self-correlation matrix elements.

[0020] wherein each first correlator calculates one element in the upper triangle of the auto-correlation matrix;

[0021] when i≤j, the element in the ith row and jth column of the auto-correlation matrix is set as the output result of the conjugate of the ith element and jth element of the space-time input vector through the first correlator;

[0022] when i>j, the element in the ith row and jth column of the auto-correlation matrix is set as the conjugate of the element in the jth row and ith column;

[0023] i and j represent the row and column of the auto-correlation matrix respectively.

[0024] In some optional examples, the cross-correlation vector module includes N*M second correlators;

[0025] The second correlators are configured to implement the calculation of the cross-correlation vector element of the (N*M)*1-dimensional space-time input vector in parallel;

[0026] wherein the ith element of the cross-correlation vector is set as the output result of the conjugate of the ith element of the space-time input vector and the received signal through the second correlator.

[0027] In some optional examples, the first correlator is further configured to calculate one element in the cross-correlation vector;

[0028] The first correlator includes a multiplier, a divider, an adder, a counter, an equal decision device and two double-channel selectors;

[0029] The multiplier is configured to perform multiplication calculation on the space-time input vector and the received signal to obtain a multiplication result input to the divider;

[0030] The divider is configured to perform division operation on the multiplication result by a preset length to obtain an operation result input to the adder;

[0031] The adder is configured to accumulate the operation result and a previous calculation result to obtain an accumulation result;

[0032] The counter is configured to determine whether the preset length is reached, and generate a count result in the case of reaching the preset length;

[0033] The equal decision device is configured to generate a calculation completion signal according to the count result;

[0034] The double-channel selector is configured to output the accumulation result.

[0035] In some optional examples, the matrix decomposition module includes N*M diagonal element calculation units and ((N*M) 2N*M) / 2 non-diagonal element calculation units;

[0036] The diagonal element calculation unit is configured to calculate the diagonal element of the ith row.

[0037] The non-diagonal element calculation unit is configured to calculate the element of the jth column of the ith row when i

[0038] In some optional examples, the diagonal element calculation unit of the ith row includes i-1 squarers, i-1 adders, i-1 second delay units, a subtractor and an opener.

[0039] The non-diagonal element calculation unit of the jth column of the ith row includes j-1 multipliers, j-1 adders, j-1 third delay units, a subtractor and an opener.

[0040] The application reduces the calculation complexity of the matrix inversion operation through matrix decomposition, and reduces the calculation delay through reasonable parallelization design between and inside the modules, thereby ensuring good realizability of the algorithm.

[0041] In some optional examples, the weight determination module includes a forward equation set solving submodule and a backward equation set solving submodule.

[0042] The forward equation set solving submodule includes N*M forward equation calculation units, and the forward equation calculation unit is configured to calculate data from 1 to N*M to realize N*M-element forward equation set solving.

[0043] The ith forward solving equation calculation unit includes j-1 multipliers, j-2 adders, j-1 fourth delay units, a subtractor and a divider.

[0044] The backward equation set solving submodule includes N*M backward equation calculation units, and the backward equation calculation unit is configured to calculate data from N*M to 1 to realize N*M-element backward equation set solving, thereby obtaining the optimal weight.

[0045] The ith backward solving equation calculation unit includes N*M-i multipliers, N*M-i-1 adders, 2N*M-2i+1 fifth delay units, a subtractor and a divider.

[0046] The application can obtain the optimal weight within a relevant time and eliminate interference, and has a faster convergence speed than the adaptive closed-loop tracking algorithm, and is more suitable for communication waveforms with fast agile characteristics, such as frequency hopping and time hopping communication waveforms.

[0047] In some optional examples, the delay matching module comprises N*M sixth delay units,

[0048] The sixth delay unit is configured to perform delay matching on the reference signal, the received signal and the optimal weight to obtain a delay matching result.

[0049] In some optional examples, the weighted combination module comprises N*M multipliers, N*M-1 adders and a seventh delay unit.

[0050] The multiplier is configured to implement weight combination, the adder is configured to implement interference cancellation, and the seventh delay unit is configured to perform signal alignment on the signal of the weight combination and the reference signal.

[0051] In a second aspect, the present application further provides a method for parallelizing FPGA implementation of a space-time interference cancellation algorithm, comprising:

[0052] Collecting reference signals of multiple channels of a wireless transceiving radio frequency system, performing delay and arrangement on the reference signals of the multiple channels to obtain a space-time input vector of the reference signals;

[0053] Obtaining a self-correlation matrix based on the space-time input vector, and obtaining a cross-correlation vector based on the space-time input vector and a received signal of the wireless transceiving radio frequency system;

[0054] Performing matrix decomposition on the self-correlation matrix to obtain an upper triangular matrix;

[0055] Solving weights by using the upper triangular matrix and the cross-correlation vector to obtain optimal weights;

[0056] Performing delay on the reference signals, performing time sequence alignment on the reference signals and the optimal weights to obtain a delay matching result;

[0057] Weighting the time sequence aligned reference signals according to the optimal weights to obtain a weighted signal, combining the weighted signal and the received signal to obtain a combined signal to implement interference cancellation of the received signal.

[0058] In a third aspect, the present application provides an electronic device, comprising: at least one memory configured to store a program; and at least one processor configured to execute the program stored in the memory, and when the program stored in the memory is executed, the processor is configured to execute the method described in the first aspect or any possible implementation manner of the first aspect.

[0059] In a fourth aspect, the present application provides a computer readable storage medium, and the computer readable storage medium stores a computer program, and when the computer program runs on a processor, the processor is caused to execute the method described in the first aspect or any possible implementation manner of the first aspect.

[0060] In a fifth aspect, the present application provides a computer program product, which, when executed on a processor, enables the processor to execute the method described in the first aspect or any possible implementation of the first aspect.

[0061] It can be understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0062] In general, the above technical solutions conceived by this application have the following beneficial effects compared with the existing technologies:

[0063] (1) The present application ensures the spatial and temporal synchronization of the reference signal and the actual signal through delay and arrangement, providing accurate input for subsequent processing, adaptively responding to changes in the signal environment through the correlation matrix adaptive module, and obtaining the optimal weight through the weight determination module, so that the system can converge quickly and thus improve the real-time tracking capability of the signal. By reducing the weight calculation delay, the purpose of reducing the cancellation processing delay and improving the tracking performance is achieved, and the reference signal and the optimal weight are aligned in time through the delay matching processing, reducing the delay in the signal processing process, and reducing the delay in the processing process through weighted signal merging, effectively suppressing interference and improving the effect of interference elimination.

[0064] (2) This application can obtain the optimal weight within a relevant time and eliminate interference. Compared with adaptive closed-loop tracking algorithms, it has a faster convergence speed and is more suitable for communication waveforms with fast agile characteristics, such as frequency hopping and time hopping communication waveforms.

[0065] (3) This application is based on an open-loop calculation mechanism, which has better tracking convergence performance and greater stability for weight changes caused by dynamic changes in waveforms or environments. It is more suitable for environments where interference channels change dramatically.

[0066] (4) This application reduces the computational complexity of the matrix inversion operation through matrix decomposition, and reduces the computational delay through reasonable parallelization design between and within modules, thereby ensuring good feasibility of the algorithm.

[0067] (5) This application significantly improves the interference cancellation effect in a multipath environment by improving the algorithm convergence speed, stability and computational complexity, and achieves better cancellation ratio and cancellation bandwidth performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] Figure 1 This is a schematic diagram of the structure of a parallel FPGA implementation device for a space-time interference cancellation algorithm provided in an embodiment of the present application;

[0069] Figure 2is a functional implementation block diagram of a space-time interference cancellation algorithm parallel FPGA implementation device provided by an embodiment of the present application;

[0070] Figure 3 is a principle schematic diagram of a correlator provided by an embodiment of the present application;

[0071] Figure 4 is a principle block diagram of an i th diagonal element solving unit of an embodiment of the present application;

[0072] Figure 5 is a principle block diagram of an i th non-diagonal element solving unit of an embodiment of the present application;

[0073] Figure 6 is a principle block diagram of an i th forward equation group solving unit of an embodiment of the present application;

[0074] Figure 7 is a principle block diagram of an i th backward equation group solving unit of an embodiment of the present application;

[0075] Figure 8 is a functional principle block diagram of a delay matching module of an embodiment of the present application;

[0076] Figure 9 is a functional principle block diagram of a weighted combination module of an embodiment of the present application;

[0077] Figure 10 is a comparison schematic diagram of convergence performance of an embodiment of the present application and prior art;

[0078] Figure 11 is a flow schematic diagram of a space-time interference cancellation algorithm parallel FPGA implementation method provided by an embodiment of the present application;

[0079] Figure 12 is a structure schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0080] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0081] The term "and / or" herein is a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can mean that there are three cases of A alone, A and B together, and B alone. The symbol " / " in this paper represents the relationship of or, for example, A / B represents A or B.

[0082] The terms "first" and "second" and the like in the description and claims of this patent document are used for distinguishing between similar elements and not necessarily for describing a specific sequential or chronological order. For example, a first delay unit and a second delay unit are used for distinguishing between different functional delay units and not for describing a particular sequential or chronological order.

[0083] The words "example" and "exemplary" are used herein to mean serving as an example, instance, or illustration. Any implementation described herein as "example" or "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations. The

[0084] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more, for example, a plurality of delay units means two or more delay units, and the like; a plurality of elements means two or more elements, and the like.

[0085] Next, the technical solutions provided in the embodiments of the present application are introduced.

[0086] With reference to Figure 1 The present application provides a space-time interference cancellation algorithm parallelization FPGA implementation device, comprising: an input vector generation module 11, a correlation matrix calculation module 12, a matrix decomposition module 13, a weight determination module 14, a delay matching module 15, and a weighted combination module 16.

[0087] The input vector generation module 11 is configured to collect reference signals of multiple channels of a wireless transceiver radio frequency system, delay and arrange the reference signals of the multiple channels, and obtain a space-time input vector of the reference signals.

[0088] The correlation matrix calculation module 12 is configured to obtain an autocorrelation matrix based on the space-time input vector, and obtain a cross-correlation vector based on the space-time input vector and a received signal of the wireless transceiver radio frequency system.

[0089] The matrix decomposition module 13 is configured to perform matrix decomposition on the autocorrelation matrix to obtain an upper triangular matrix.

[0090] The weight determination module 14 is configured to solve weights by using the upper triangular matrix and the cross-correlation vector to obtain optimal weights.

[0091] The delay matching module 15 is configured to delay the reference signals, time-align the reference signals and the optimal weights, and obtain a delay matching result.

[0092] The weighting combining module 16 is configured to weight the time-aligned reference signals according to the optimal weights to obtain weighted signals, and combine the weighted signals with the received signals to obtain a combined signal to realize interference cancellation of the received signals.

[0093] Specifically, with reference to Figure 2 The correlation matrix module in the application includes a self-correlation matrix calculation submodule and a cross-correlation vector calculation submodule, the matrix decomposition module is a Cholesky matrix decomposition module, and the weight determination module includes a forward equation solving submodule and a backward equation solving submodule.

[0094] The input vector generation module is connected to the N-way spatial reference signals x 11 (n), x 21 (n), …, x N1 (n). The M*N-way output signals x1(n), x2(n), …, x MN (n) after space-time reconstruction are connected to the input ends of the self-correlation matrix calculation module, the cross-correlation vector calculation module and the delay matching module. The input vector generation module is configured to convert the spatial reference signals into space-time reference signals required by the algorithm.

[0095] The self-correlation matrix calculation module is connected to the M*N-way space-time reference signals x1(n), x2(n), …, x MN (n) output by the input vector generation module. The output end is an L-way self-correlation matrix element r1(n), r2(n), …, r L (n), where L=MN*MN, and is connected to the input end of the Cholesky matrix decomposition module. The self-correlation matrix calculation module is configured to calculate the self-correlation matrix of the space-time reference signals.

[0096] The cross-correlation vector calculation module is connected to the M*N-way space-time reference signals x1(n), x2(n), …, x MN (n) and the received signal d(n) output by the input vector generation module. The output end is an M*N-way cross-correlation matrix element p1(n), p2(n), …, p MN (n). The cross-correlation vector calculation module is configured to calculate the cross-correlation vector of the space-time reference signals and the input signals.

[0097] The Cholesky matrix decomposition module is connected to the output signals r1(n), r2(n), …, r L (n) of the self-correlation matrix calculation module. The output signal of the Cholesky matrix decomposition module is an upper triangular matrix element l1(n), l(n), …, l L(n), connected to the input end of the forward equation set solving module. The function of the Cholesky matrix decomposition module is to obtain an upper triangular matrix.

[0098] The input end of the forward equation set solving module is connected to the output signals l1(n), l(n),..., l L (n), and the output signal is the forward equation solution q1(n), q2(n),..., q MN (n), connected to the input end of the backward equation set solving module. The forward equation solving module realizes the solution of the forward equation set.

[0099] The input end of the backward equation set solving module is connected to the output signals q1(n), q2(n),..., q MN (n), and the output signal is the optimal weight w1(n), w2(n),..., w MN (n), connected to the input end of the weighted combination module. The backward equation solving module realizes the solution of the optimal weight.

[0100] The input end of the delay matching module is connected to the MN-way space-time reference signals x1(n), x2(n),..., x MN (n) and the received signal d(n). The output is the delayed signal x1(n-D), x2(n-D),..., x MN (n-D) and d(n-D). The delay matching module realizes the matching of the reference signal and the weight delay.

[0101] The input end of the weighted combination module is connected to the output signals x1(n-D), x2(n-D),..., x MN (n-D) and d(n-D) and the optimal weight w1(n), w2(n),..., w MN (n), and the output is the cancellation signal y(n).

[0102] In some optional examples, the input vector generating module includes N*(M-1) first delay units, N is the number of spatial reference signals, M is the order of the time domain filter, and N and M are positive integers.

[0103] The first delay unit is configured to generate M time domain signal sequences from N*M spatial reference signals, and sequentially arrange the N time domain signal sequences to generate an N*M-dimensional space-time input vector.

[0104] Further, the input vector generating module is composed of a time domain delay module and a space-time recombination module, and the time domain delay input is connected to N-way spatial reference signals x 11 (n), x 21(n), …, x N1 (n), the time domain delay output MN road space-time signal, output connected to space-time reorganization, after the output space-time reference signal x1(n), x2(n), …, x MN (n).

[0105] Specifically, composed of N*(M-1) delay units, wherein N is the number of spatial reference signals, and M is the order of time domain filter. The N spatial reference signals are sequentially generated M time domain signal sequences by the (M-1) delay units, and then the N spatial time domain sequences are sequentially arranged to generate an N*M-dimensional space-time input vector.

[0106] In some optional examples, the correlation matrix calculation module includes an autocorrelation matrix submodule and a cross-correlation vector submodule;

[0107] The autocorrelation matrix includes ((N*M) 2 +N*M) / 2 first correlators;

[0108] The first correlator is configured to implement autocorrelation matrix element calculation of an N*M×N*M-dimensional space-time input vector in parallel;

[0109] Each first correlator calculates an element in the upper triangular matrix of the autocorrelation matrix.

[0110] When i≤j, the element of the i-th row and the j-th column of the autocorrelation matrix is set to the output result of the first correlator of the conjugate of the i-th element and the j-th element of the space-time input vector;

[0111] When i>j, the element of the i-th row and the j-th column of the autocorrelation matrix is set to the conjugate of the element of the j-th row and the i-th column.

[0112] i and j represent the row and column of the autocorrelation matrix, respectively.

[0113] The autocorrelation matrix submodule uses ((N*M) 2 +N*M) / 2 correlators to implement autocorrelation matrix element calculation of an N*M*N*M-dimensional input vector in parallel, and each correlator calculates an element in the upper triangular matrix of the autocorrelation matrix. When i≤j, the element of the i-th row and the j-th column of the autocorrelation matrix is set to the output result of the correlator of the conjugate of the i-th element and the j-th element of the input vector; when i>j, the element of the i-th row and the j-th column of the autocorrelation matrix is set to the conjugate of the element of the j-th row and the i-th column.

[0114] In some optional examples, the cross-correlation vector submodule includes N*M second correlators;

[0115] The second correlator is configured to implement cross-correlation vector element calculation of an (N*M)*1-dimensional space-time input vector in parallel.

[0116] The ith element of the cross-correlation vector is set as the output result of the conjugate of the ith element of the space-time input vector and the received signal through the second correlator.

[0117] The cross-correlation vector submodule uses N*M correlators to realize (N*M)*1-dimensional input vector self-correlation correlation matrix element calculation in parallel, and the ith element of the cross-correlation vector is set as the result of the ith element of the input vector and the received signal conjugate through the correlator.

[0118] In some optional examples, the first correlator is further configured to calculate one element in the cross-correlation vector;

[0119] The first correlator includes a multiplier, a divider, an adder, a counter, an equal decision device, and two double-channel selectors.

[0120] The multiplier is configured to perform multiplication calculation on the space-time input vector and the received signal to obtain a multiplication result input to the divider.

[0121] The divider is configured to perform division operation on the multiplication result by a preset length to obtain an operation result input to the adder.

[0122] The adder is configured to accumulate the operation result and a previous calculation result to obtain an accumulation result.

[0123] The counter is configured to determine whether the preset length budget is reached, and generate a count result in the case of reaching.

[0124] The equal decision device is configured to generate a calculation completion signal according to the count result.

[0125] The double-channel selector is configured to output the accumulation result.

[0126] Further, the correlator of the self-correlation matrix element and the cross-correlation vector element includes a multiplier, a divider, an adder, a counter, an equal decision device, and two channel selectors.

[0127] Referring to Figure 3 , Figure 3 is a schematic diagram of the principle of the correlator.

[0128] Two data related to the input of the multiplier are x1(n) and x2(n), and the output of the multiplier is x1(n)*x2(n). The multiplier output end is connected with the divisor end of the divider, and the divider divisor end is connected with the preset length. It should be noted that the preset length in the embodiment refers to the data bit width or a specific factor, which depends on the design requirements and application scenarios. Then, the data accumulation with the length of Len is realized through the adder, and the correlation result is output through the channel selector.

[0129] In some optional examples, the matrix decomposition module includes N*M diagonal element calculation units and ((N*M) 2 -N*M) / 2 non-diagonal element calculation units.

[0130] The diagonal element calculation unit is configured to calculate the diagonal element of the ith row.

[0131] The non-diagonal element calculation unit is configured to calculate the element of the ith row and the jth column when i

[0132] In some optional examples, the diagonal element calculation unit of the ith row includes i-1 squarers, i-1 adders, i-1 second delay units, a subtractor, and an opener.

[0133] The non-diagonal element calculation unit of the ith row and the jth column includes j-1 multipliers, j-1 adders, j-1 third delay units, a subtractor, and an opener.

[0134] Reference Figure 4 , Figure 4 is a principle block diagram of the diagonal element calculation unit of the Cholesky matrix decomposition module.

[0135] Specifically, the diagonal element calculation unit of the Cholesky matrix decomposition module is used to calculate the diagonal element. The diagonal element calculation unit of the ith row is composed of a squaring module, an adder, a subtractor, and an opener module. The squaring module of the diagonal element calculation unit of the ith row is composed of i-1 squarers, which are used to calculate the square of r i1 (), r i2 (), …, r i(i-1) (), and the output is connected with the adder. The r i1 () is matched and added through the level-by-level delay, and the output result is connected with the minuend input port of the subtractor. i2 (), …, r i(i-1) () is matched and added through the level-by-level delay, and the output result is connected with the minuend input port of the subtractor. ii (), and the output is connected with the adder. The r ii () is matched and added through the level-by-level delay, and the output result is connected with the minuend input port of the subtractor. i i2 ReferenceFigure 5 , Figure 5 is the i-th non-diagonal element solving unit principle diagram.

[0137] Further, the non-diagonal element solving unit for solving the non-diagonal element of the Cholesky matrix decomposition module is composed of multipliers, adders and subtractors and dividers. The multiplier of the non-diagonal element calculation module of the i-th row and j-th column is realized by i-1 multipliers, which multiply r i 1(), r i2 (), …, r i(i-1) () respectively with its co-torsion multiplication, and the output is connected to the adder. The matching and addition are realized by the stage-by-stage delay matching and addition, and the output result is connected to the minuend input port of the subtractor. i 1(), r i2 (), …, r i(i-1) () and its co-torsion multiplication, and the output result is connected to the minuend input port of the subtractor. The minuend input end of the subtractor is connected to r ii () after the delay matching, and the minuend port is connected to the output port of the adder. The output port is connected to the input interface of the divider. The input port of the divider is connected to the output port of the subtractor and the data l ii , and the output signal l ij() .

[0138] In some optional examples, the weight determination module includes a forward equation set solving submodule and a backward equation set solving submodule;

[0139] The forward equation set solving submodule includes N*M forward equation calculation units, and the forward equation calculation units are used to calculate data from 1 to N*M to realize N*M-element forward equation set solving.

[0140] The i-th forward solving equation calculation unit includes j-1 multipliers, j-2 adders, j-1 fourth delay units, a subtractor and a divider.

[0141] The backward equation set solving submodule includes N*M backward equation calculation units, and the backward equation calculation units are used to calculate data from N*M to 1 to realize N*M-element backward equation set solving to obtain the optimal weight.

[0142] Reference Figure 6 , Figure 6 is the i-th forward equation set solving principle diagram.

[0143] The i-th backward solving equation calculation unit includes N*M-i multipliers, N*M-i-1 adders, 2N*M-2i+1 fifth delay units, a subtractor and a divider.

[0144] Furthermore, the i-th forward equation solving unit is composed of a multiplier, an adder, a subtractor, and a divider. The i-th forward equation solving unit is composed of i-1 multipliers to realize the l i1 (), l i2 (),……,l i(i-1) () are respectively related to y1(), y2(), ..., y i The output of () is connected to the adder, and the sum of the multiplier output elements is achieved through step-by-step delay matching and addition. The output result is connected to the minuend input port of the subtractor. The subtrahend input of the subtractor is connected to p i () After the delay matching signal, the minuend port is connected to the adder output port, and the output port is connected to the divider input interface. The divider input port is connected to the subtractor output port and the data l ii , output signal y i ().

[0145] Reference Figure 7 , Figure 7 This is the principle block diagram for solving the i-th backward equation system.

[0146] Furthermore, the backward equation solving submodule is composed of multipliers, adders, subtractors and dividers. The forward equation solving unit of the i-th row is realized by N*Mi multipliers. MN (), l MN-1 (), ... l i(i+1) () respectively with y MN (),y MN-1 (),……,y i+1 The multiplication operation of () is connected to the adder, and the sum of the multiplier output elements is achieved through step-by-step delay matching and addition. The output result is connected to the minuend input port of the subtractor. The subtrahend input of the subtractor is connected to y i () After the delay is matched, the minuend port is connected to the adder output port, and the output port is connected to the divider input port. The divider input port is connected to the subtractor output port and the data lii is output after the delay is matched, and the output signal w i ().

[0147] In some optional examples, the delay matching module includes N*M sixth delay units,

[0148] The sixth delay unit is used to perform delay matching on the reference signal, the received signal and the optimal weight to obtain a delay matching result.

[0149] Reference Figure 8 , Figure 8 This is the functional principle block diagram of the delay matching module. The time domain delay input is connected to N spatial reference signals x 11 (n), x21 (n), …, x N1 (n), through time domain delay output MN road space-time signal, output connection to space-time reorganization, after the output space-time reference signal x1(n), x2(n), …, x MN (n).

[0150] Referring to Figure 9 , Figure 9 is the functional principle diagram of the weighted combination module. The weighted combination module includes N*M multipliers, N*M-1 adders, and a seventh delay unit;

[0151] The multiplier is used to realize weight combination, the adder is used to realize interference cancellation, and the seventh delay unit is used to align the signals of weight combination with the reference signal.

[0152] Referring to Figure 10 , Figure 10 is a comparison diagram of the convergence performance of the embodiment and the prior art. Red in the figure indicates before cancellation, blue indicates the LMS algorithm, green indicates the NLMS algorithm, and black indicates the algorithm implemented by the present application. It can be seen that the error signal power of the method of the embodiment is the smallest, the stability is the strongest, and the iteration number is the least.

[0153] Referring to Figure 11 The present application also provides a space-time interference cancellation algorithm parallelization FPGA implementation method, comprising:

[0154] S111. Collecting the reference signals of multiple channels of a wireless transceiver radio frequency system, delaying and arranging the reference signals of the multiple channels to obtain a space-time input vector of the reference signals;

[0155] S112. Obtaining a autocorrelation matrix based on the space-time input vector, and obtaining a cross-correlation vector based on the space-time input vector and a received signal of the wireless transceiver radio frequency system;

[0156] S113. Matrix decomposing the autocorrelation matrix to obtain an upper triangular matrix;

[0157] S114. Solving the weight value by using the upper triangular matrix and the cross-correlation vector to obtain an optimal weight value;

[0158] S115. Delaying the reference signal, time-aligning the reference signal and the optimal weight value to obtain a delay matching result;

[0159] S116. Weighting the time-aligned reference signal according to the optimal weight value to obtain a weighted signal, combining the weighted signal with the received signal to obtain a combined signal to realize interference cancellation of the received signal.

[0160] Specifically, the space-time interference cancellation algorithm parallelization FPGA implementation method of the embodiment of the application comprises the following steps in detail:

[0161] Step S1: starting input vector generation at time T0, comprising the following sub-steps:

[0162] Sub-step S11: inputting N space reference signals x 11 (n), x 21 (n), ……, x N1 (n) into M-1 delay units in parallel to generate x 11 (n), x 21 (n), ……, x N1 (n), x1(n-T), x 21 (n-T), ……, x N1 (n-T), ……, x 11 (n(M-1)T), x 21 (n(M-1)T) x N1 (n(M-1)T);

[0163] Sub-step S12: for the i-th (1≤i≤MN) element, generating MN*1-dimensional space-time reference signal matrix x1(n), x2(n), ……, x MN (n) in parallel according to the mapping relationship xi(n) = x Mod(i, M)1(n-(M-rem(i, M))T).

[0164] Step S2: starting autocorrelation matrix calculation at time T1, wherein T1=T0+(M-1). ((N*M) 2 +N*M) / 2 correlators are used to realize N*M*N*M-dimensional input vector autocorrelation matrix element calculation in parallel, and each correlator calculates one element in the upper triangular matrix of the autocorrelation matrix. When i≤j, the element rij(n) of the i-th row and the j-th column of the autocorrelation matrix is set to the output result of the conjugate of the i-th element and the j-th element of the input vector through the correlator; when i>j, the element rij(n) of the i-th row and the j-th column of the autocorrelation matrix is set to the conjugate of the element of the j-th row and the i-th column.

[0165] Step S3: starting cross-correlation vector calculation at time T1, wherein T1=T0+(M-1). N*M correlators are used to realize (N*M)*1-dimensional cross-correlation vector calculation in parallel, and the i-th element pi(n) of the cross-correlation vector is set to the result of the conjugate of the i-th element of the input vector and the received signal through the correlator.

[0166] Step S4: Cholesky matrix decomposition operation is started at time T2, where T2=T1+D1, D1 is the time delay of correlator operation. The lower triangular matrix calculation is implemented by N*M diagonal element calculation units and ((N*M) 2 -N*M) / 2 non-diagonal element calculation units. For diagonal elements, the diagonal element I ii () is calculated by diagonal element calculation unit; for non-diagonal elements, when i

[0167] Step S5: Forward equation set solving operation is started at time T3, where T3=T2+D2, D2 is the time delay of Cholesky matrix decomposition operation. N*M forward equation calculation units are used to implement N*M forward equation set solving, and the calculation is performed in the order from q1 to qN*M, and the i-th (1≤i≤N*M) solution qi is set as the output result of the i-th forward equation set solving unit.

[0168] Step S6: Backward equation set solving operation is started at time T4, where T4=T4+D3, D3 is the time delay of forward equation set solving operation. N*M forward equation calculation units are used to implement N*M forward equation set solving, and the calculation is performed in the order from qM*N to q1, and the i-th (1≤i≤N*M) solution wi is set as the output result of the i-th backward equation set solving unit.

[0169] Step S7: Backward equation set solving operation and delay matching are started at time T1, and the data streams x1(n), x2(n), …, x MN (n) and d(n) are sequentially passed through D delay units in parallel, where D=D1+D2+D3+D4, and D4 is the time delay of the i-th (1≤i≤N*M) delay unit, and the data streams x1(n-D), x2(n-D), …, x MN (n-D) and d(n-D) are obtained, which are matched with the weight values.

[0170] Step S8: Post-weighted combination is started at time T5, where T4=T4+D3, D3 is the time delay of backward equation set solving operation. It includes the following sub-steps:

[0171] S81: Space-time weighting is performed by MN multipliers to complete the multiplication of space-time reference signals and weight values, where the i-th (1≤i≤N*M) multiplier inputs x1(n-D) and w1(n), and outputs M*N combination results y1(n), y2(n), …, y MN (n).

[0172] S82: Spatial domain combining, using MN-1 adders to combine y1(n), y2(n),..., y MM (n) to obtain y(n) according to the binary tree structure.

[0173] S83: Delay matching, using a delay unit to delay match y(n) and d(n-D).

[0174] S84: Interference cancellation, using a subtractor to subtract the combined interference signal y(n) from the matched received signal d(n-D) to obtain the cancellation output error e(n).

[0175] Referring to Figure 12 Based on the method in the above embodiment, an electronic device is provided, which can include a processor 121, a communications interface 122, a memory 123, and a communications bus 124, wherein the processor 121, the communications interface 122, and the memory 123 complete communication with each other through the communications bus 124. The processor 121 can invoke a logical instruction in the memory 123 to execute the method in the above embodiment.

[0176] In addition, the logical instruction in the memory 123 described above can be implemented in the form of a software functional unit and sold or used as an independent product, which can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium, includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application.

[0177] Based on the method in the above embodiment, a computer-readable storage medium is provided, which stores a computer program, and when the computer program runs on a processor, the processor executes the method in the above embodiment.

[0178] Based on the method in the above embodiment, a computer program product is provided, and when the computer program product runs on a processor, the processor executes the method in the above embodiment.

[0179] It can be understood that the processor in the embodiments of the present application can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor can be a microprocessor or any conventional processor.

[0180] The method steps in the embodiments of the present application can be implemented in the form of hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable read-only memory (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), a register, a hard disk, a mobile hard disk, a CD-ROM or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor, so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and the storage medium can be located in an ASIC.

[0181] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions can be stored in or transmitted by a computer readable storage medium. The computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through a wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) manner. The computer readable storage medium can be any available medium accessible by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media sets. The available media can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)), etc.

[0182] It can be understood that various numerical numbers involved in the embodiments of the present application are only distinguished for convenience of description, and are not used to limit the scope of the embodiments of the present application.

[0183] Those skilled in the art easily understand that the above only describes the preferred embodiments of the present application, and is not used to limit the present application, and any modification, equivalent replacement and improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A device for parallelizing space-time interference cancellation algorithm FPGA implementation, characterized in that, The application relates to a wireless transceiving system interference cancellation method and device. The method comprises the following steps: An input vector generation module, a correlation matrix calculation module, a matrix decomposition module, a weight determination module, a delay matching module and a weighted combination module; The input vector generation module is used for collecting reference signals of multiple channels of a wireless transceiving system, delaying and arranging the reference signals of the multiple channels to obtain space-time input vectors of the reference signals; The correlation matrix calculation module is used for obtaining a self-correlation matrix based on the space-time input vectors and obtaining a cross-correlation vector based on the space-time input vectors and a received signal of the wireless transceiving system; The matrix decomposition module is used for performing matrix decomposition on the self-correlation matrix to obtain an upper triangular matrix; The weight determination module is used for solving optimal weights by using the upper triangular matrix and the cross-correlation vector; The delay matching module is used for delaying the reference signals, time-aligning the reference signals and the optimal weights to obtain a delay matching result; 2. The parallelized FPGA implementation of the space-time interference cancellation algorithm of claim 1, wherein, The weighted combination module is used for weighting the time-aligned reference signals according to the optimal weights to obtain a weighted signal, combining the weighted signal and the received signal to obtain a combined signal to realize interference cancellation of the received signal. The input vector generation module comprises N*(M-1) first delay units, N is the number of space domain reference signals, M is the order of a time domain filter, and N and M are positive integers; 3. The parallelized FPGA implementation of the space-time interference cancellation algorithm of claim 1, wherein, The first delay unit is used for delaying each signal in N space domain reference signals to obtain time domain signal sequences of the signals; the time domain signal sequences corresponding to the space domain reference signals are arranged in sequence according to space domain sequences to be spliced to generate space-time input vectors of N*M dimensions; the time domain signal sequences comprise M continuous time point sampling points; and each time domain signal sequence is a vector of M dimensions. The autocorrelation matrix includes ((N*M) 2 + N*M) / 2 first correlators; The correlation matrix calculation module comprises a self-correlation matrix sub-module and a cross-correlation vector sub-module; The first correlator is used for parallelly realizing N*M*N*M-dimensional space-time input vector self-correlation matrix element calculation; Each first correlator calculates one element in the upper triangular matrix of the self-correlation matrix; When i<=j, the element of the i-th row and the j-th column of the self-correlation matrix is set as the output result of the first correlator after the i-th element and the j-th element of the space-time input vector are conjugated; When i>j, the element of the i-th row and the j-th column of the self-correlation matrix is set as the conjugate of the element of the j-th row and the i-th column; 4. The parallelized FPGA implementation of the space-time interference cancellation algorithm of claim 3, wherein, i and j respectively represent the row and the column of the self-correlation matrix. The cross-correlation vector sub-module comprises N*M second correlators; The second correlator is used for parallelly realizing (N*M)*1-dimensional space-time input vector cross-correlation vector element calculation; 5. The parallelized FPGA implementation of the space-time interference cancellation algorithm of claim 3, wherein, The i-th element of the cross-correlation vector is set as the output result of the second correlator after the i-th element of the space-time input vector and a received signal are conjugated. The first correlator is also used for calculating one element in the cross-correlation vector; The first correlator comprises a multiplier, a divider, an adder, a counter, an equal sign decision device and two double-channel selectors; the double-channel selector comprises a first selector and a second selector; The multiplier is configured to multiply the space-time input vector and the received signal to obtain a multiplication result input to the divider; The divider is configured to divide the multiplication result by a preset length to obtain an operation result input to the adder; The adder is configured to accumulate the operation result and a previous calculation result to obtain an accumulation result; The counter is configured to determine whether a budget of the preset length is reached, and generate a count result in the case of reaching the budget; The equal sign determinator is configured to generate a calculation completion signal according to the count result; The first selector is configured to obtain the previous calculation result according to the calculation completion signal, and input the previous calculation result to the adder; The second selector is configured to output the accumulation result.

6. The parallelized FPGA implementation of the space-time interference cancellation algorithm of claim 1, wherein, The matrix decomposition module includes N*M diagonal element calculation units and ((N*M) 2 (N*M) / 2 non-diagonal element calculation units. The diagonal element calculation unit is configured to calculate a diagonal element of the ith row; The non-diagonal element calculation unit is configured to calculate an element of the ith row and the jth column when i 7. The parallelized FPGA implementation of the space-time interference cancellation algorithm of claim 6, wherein, The diagonal element calculation unit of the ith row includes i-1 square units, i-1 adders, i-1 second delay units, a subtractor and an opener; The non-diagonal element calculation unit of the ith row and the jth column includes j-1 multipliers, j-1 adders, j-1 third delay units, a subtractor and an opener.

8. The parallelized FPGA implementation of the space-time interference cancellation algorithm of claim 1, wherein, The weight determination module includes a forward equation group solving submodule and a backward equation group solving submodule; The forward equation group solving submodule includes N*M forward equation calculation units, and the forward equation calculation unit is configured to calculate data from 1 to N*M to realize N*M-element forward equation group solving; The i-th forward solving equation calculation unit includes j-1 multipliers, j-2 adders, j-1 fourth delay units, a subtractor and a divider; The backward equation group solving submodule includes N*M backward equation calculation units, and the backward equation calculation unit is configured to calculate data from N*M to 1 to realize N*M-element backward equation group solving to obtain the optimal weight value; The i-th backward solving equation calculation unit includes N*M-i multipliers, N*M-i-1 adders, 2N*M-2i+1 fifth delay units, a subtractor and a divider.

9. The parallelized FPGA implementation of the space-time interference cancellation algorithm of claim 1, wherein, The delay matching module includes N*M sixth delay units, The sixth delay unit is configured to delay match the reference signal, the received signal and the optimal weight value to obtain a delay matching result.

10. The parallelized FPGA implementation of the space-time interference cancellation algorithm of claim 1, wherein, The weighted combination module includes N*M multipliers, N*M-1 adders and a seventh delay unit; The multiplier is configured to realize weight combination, the adder is configured to realize interference cancellation, and the seventh delay unit is configured to align signals of the weight combination and the reference signal.

11. A method for parallelizing space-time interference cancellation algorithm FPGA implementation, characterized in that, The method comprises: Collecting a multi-channel reference signal of a wireless transceiver radio frequency system, delaying and arranging the multi-channel reference signal to obtain a space-time input vector of the reference signal; Obtaining an autocorrelation matrix based on the space-time input vector, and obtaining a cross-correlation vector based on the space-time input vector and a received signal of the wireless transceiver radio frequency system; Performing matrix decomposition on the autocorrelation matrix to obtain an upper triangular matrix; The upper triangular matrix and the cross-correlation vector are used to solve the weights and obtain the optimal weights; Delaying the reference signal, performing time alignment on the reference signal and the optimal weight value, and obtaining a delay matching result; The time-aligned reference signal is weighted according to the optimal weight value to obtain a weighted signal, and the weighted signal is combined with the received signal to obtain a combined signal to achieve interference elimination of the received signal.

12. An electronic device, comprising: include: at least one memory for storing a computer program; At least one processor is configured to execute the program stored in the memory, and when the program stored in the memory is executed, the processor is configured to execute the method according to claim 11.

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