SPI full duplex data transmission method, system and device and storage medium

Abstract

The invention discloses an SPI (Serial Peripheral Interface) full-duplex data transmission method, which comprises the steps of transmitting data between a host and a slave and verifying the data after the transmission is completed, and is characterized in that a full-duplex transmission method is realized by setting a signaling with a fixed length and only needing one signaling in the whole transmission process, and efficient full-duplex transmission is realized by using the full-duplex transmission method. The problems that the bus utilization rate is low, data transmission is not real-time, and data retransmission is complex are solved.

Description

Technical Field

[0001] The invention relates to the field of embedded systems, and in particular to an SPI full-duplex data transmission method. Background Art

[0002] SPI is a full-duplex transmission peripheral communication bus interface. According to the protocol specification, it is generally composed of 4 signal lines, namely: chip select signal, clock signal, master input slave output data signal, master output slave input data signal. In the SPI bus topology, it is a one-master-multiple-slave structure. There is usually only one host in the entire bus, and there can be multiple slaves. Each bus transmission session is initiated by the host and provides a communication clock, and the slave responds passively according to the chip select signal triggered by the host. In the present invention, the main method of realizing full-duplex communication based on software on the SPI bus protocol is to realize.

[0003] At present, in most scenarios, the use of SPI communication cannot fully reflect the characteristics of full-duplex. The following problems are generally faced: 1. The host does not know whether the slave is ready to communicate with the host; 2. The host does not know how much data the slave needs to transmit to the host; 3. The slave also faces similar problems, not knowing when the host will get the data, nor how much data the host needs to transmit to the slave; The more common processing methods for the above problems are: 1. For problem 1, a separate IO signal line is added in the hardware design, which is used for the slave to inform the host whether it is ready to communicate. For example, the slave indicates whether the slave is ready by pulling up or down this IO line, or as disclosed in the patent number 201210215933.3; For problems 2 and 3, the host and the slave generally agree on a set of transmission signaling, which is used to clarify whether the host sends data to the slave or reads data from the slave, and the signaling can be added to indicate the length and content of the data that the host needs to send, or the signaling can be added to indicate that the host wants to read data from the slave.

[0004] It can be seen that the entire communication process is divided into many signaling stages. In each signaling stage, the bus is in a unidirectional signaling transmission state, which cannot give full play to the advantages of full-duplex communication. Based on these means, not only does it need to increase hardware IO resources, but it also cannot fully utilize the bus bandwidth. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a transmission method similar to signaling, but the entire transmission process only needs one signaling, which is a full-duplex transmission method.

[0006] The present invention is achieved through the following technical solutions.

[0007] The present invention provides an SPI full-duplex data transmission method, including data transmission between a host and a slave, and verifying the data after the transmission is completed. The data transmission method between the host and the slave, wherein the data transmission process includes several signaling stages, the signaling length is fixed, and the signaling sending cycle is fixed.

[0008] Further, setting the fixed length signaling includes the following methods: Set the signaling length to 16 bytes, and define fields for the first byte to the sixteenth byte respectively; A field is defined in the signaling to indicate the length of data that has been prepared for transmission, to inform the receiving end to prepare the buffer in advance, and to help the host determine the session window size for the next transmission session.

[0009] Further, determining the session window size of the next transmission session for the host includes the following methods: Determine a maximum transmission packet size to control chip select and clock cycle.

[0010] Furthermore, the data transmission method between the host and the slave includes the following steps: S101. The host pulls down the chip select signal and initiates transmission; S102. The host provides a hardware clock signal for the bus and determines the number of clock signals required for this transmission based on the signaling; S103. When the transmission is completed, the chip select signal is pulled high and the transmission stops; S104. The host and the slave respectively parse the received data packets.

[0011] Further, the host and the slave respectively parse the received data packets including a sequence number verification method and a non-sequence number verification method, wherein the sequence number verification method includes: S201. Check whether the signaling packet CRC16 received by the receiving end is correct, perform CRC16 check on the contents of the first 14 bytes of the signaling, and compare the values ​​of the fifteenth and sixteenth bytes of the signaling. If the CRC values ​​match, the check passes; If the CRC values ​​do not match after the nth data transmission, the signaling's own session sequence number and the expected sequence number of the other party will not increase. When the n+1th data transmission is performed, the sender will try to identify that the sequence number has not increased, and retransmit the nth transmission packet during the n+2th transmission; S202. Determine whether the fifth byte matches the sixth byte. If they do not match, the sequence number is not incremented, and the next communication is attempted by the other party and retransmission occurs; If its own fifth byte does not match the received sixth byte, reset its own fifth byte to the received sixth byte and retransmit; If the sixth byte of the packet does not match the fifth byte of the other party, the packet does not increment its sixth byte and waits for the sender to retransmit. If the sequence numbers match then the sequence number is incremented after the communication; S203. If the received header CRC8 is wrong, only the fifth byte of itself is added and retransmission is expected.

[0012] The non-serial number byte verification steps include: S204. Check whether the send-ready flag and receive-ready flag in the signaling are in place. If they are in place, data can be transmitted, and the ready data length in the transmission packet is rdy_len, and the valid data length is data_len; if they are not in place, data cannot be transmitted; The send-ready flag and the receive-ready flag are the values ​​of the second byte of the signaling.

[0013] The present invention also provides an SPI full-duplex data transmission system, including a host and a slave, wherein the host and the slave communicate via an SPI bus, wherein the communication between the host and the slave is controlled by signaling, wherein the signaling includes signaling and other fields, wherein the fixed length of the signaling is 16 bytes, and the first byte to the sixteenth byte respectively have the following functions: The first byte is a reserved byte, and the default value is 0; The second byte is the send or receive ready flag, a reserved field, and the default value is 0; The third byte and the fourth byte are combined into an unsigned integer to indicate the length of the data that is ready to be transmitted; The fifth byte is used to transmit its own session sequence number; The sixth byte indicates the sequence number that the transmission expects from the other party; The seventh and eighth bytes are combined into an unsigned integer to indicate the length of data to be transmitted after signaling; Bytes 9 to 12 are used to represent signaling packets, and are used as reference fields when searching for signaling packet synchronization in the buffer when a data field error occurs; The thirteenth and fourteenth bytes are combined into an unsigned integer, which is used to represent the CRC16 checksum of the data transmitted after the signaling; The fifteenth byte and the sixteenth byte are combined into an unsigned integer, which is used to represent the CRC16 checksum of the first 14 bytes of the signaling.

[0014] Correspondingly, the present invention also includes an SPI full-duplex data transmission device, including a module for executing any of the above methods, characterized in that it includes a processor and an interface circuit, the interface circuit is used to receive signals from other devices other than the device for executing kernel mode commands and transmit them to the processor or send signals from the processor to other devices other than the device for executing kernel mode commands, and the processor is used to implement any of the above methods through logic circuits or execution code instructions.

[0015] Correspondingly, the present invention also includes a computer-readable storage medium on which a computer program is stored, characterized in that when the computer program is executed by a processor, it implements any of the methods described above.

[0016] The beneficial effects of the present invention are: a fixed-length signaling plus an optional data field is used to ensure a full-duplex transmission mechanism, which improves bus bandwidth utilization compared to multi-signaling half-duplex transmission; a fixed-cycle transmission of fixed signaling can reduce hardware flow control pins; the field design in the signaling can provide data verification at the software layer to ensure reliable communication; and retransmission and fault self-recovery (indicating synchronous transmission) can be achieved through a formulated signaling sequence number matching detection mechanism. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the communication method between the host and the slave of the present invention; Figure 2 It is a schematic diagram of the communication transmission mechanism of the present invention; Figure 3 This is a schematic diagram of 16-byte signaling in the present invention; Figure 4 is a schematic diagram of the transmission mechanism of Example 1; Figure 5 is a flow chart of the data transmission method in Example 1; Figure 6 This is a flow chart of the data analysis process of Example 1. DETAILED DESCRIPTION

[0018] The technical solution of the present invention is further described below, but the scope of protection claimed is not limited to the description.

[0019] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] Example 1 The application scenario of this embodiment is in vehicle-mounted domain control. The chip model is tc397. SPI multi-machine communication is implemented on the MCU of the tc397 chip. Before communication, a fixed length of 16 bytes of signaling is set, such as Figure 3 As shown, The first byte (field reserved) is a reserved byte used for extended functions. The default value is 0. The use of reserved bits can not only be used as a function expansion, but also allow some multi-byte fields to be accessed in a memory-aligned manner. The lower 4 bits of the second byte (field flag): 0 means that data cannot be sent or received; 1 means that data can be received, which is usually 1 when the receiving buffer is available; 2 means that data needs to be sent; 3 means that both receiving and sending can be performed; the ready state of receiving and sending can be distinguished according to the bit state. The main function of this field is to realize the flow control of the master and slave machines; The second byte high 4 bits (field phase): reserved field, the default value is 0; The third and fourth bytes (field rdy_len): are combined into a 16-bit unsigned integer to indicate the length of data that has been prepared for transmission. This field can transmit up to 65535 bytes of data, which is used to inform the receiver to prepare the buffer in advance, and secondly, it is used by the host to determine the session window size of the next transmission session (determine the longest transmission packet size, thereby controlling the chip select and clock cycle for a complete transmission); The fifth byte (field seq): the serial number of this transmission. The serial number increases in sequence each time it is transmitted. One chip select signal is defined as one transmission. The increment range is 0~255. When it reaches 255, it will return to 0 the next time. The sixth byte (field expected_seq): the sequence number expected by the other party for this transmission. Generally, it is the sequence number received from the other party last time plus one. If it is the first transmission, it is 0. It is usually used to identify packet loss. When the expected sequence number is inconsistent with the sequence number transmitted by the other party, it means that packet loss or abnormality has occurred during the communication transmission process. The seventh and eighth bytes (field data_len): 2 bytes in length, combined into a 16-bit unsigned integer, used to indicate the length of data to be transmitted after signaling, or 0 if there is no data to be transmitted; Bytes 9 to 12 (magicl_num field): 4 bytes in length, fixed to 0x98BADCFE on the host side and 0x67452301 on the slave side. This field is mainly used to indicate signaling packets. It can be used as a reference field when a data domain error occurs and it is necessary to find signaling packet synchronization in the buffer. Generally, when a large buffer is established in the SPI transmit and receive direction, it can effectively identify the location of a signaling packet, thereby helping to quickly search for the next valid signaling packet in the event of packet loss or misalignment in the communication data. The 13th and 14th bytes (field datacrc): 2 bytes in length, combined into a 16-bit unsigned integer, used to represent the CRC16 checksum of the data transmitted after signaling. Used to check the data part. When there is no data, this field is 0; The fifteenth and sixteenth bytes (field hdrcrc): two bytes in length, combined into a 16-bit unsigned integer, used to represent the CRC16 checksum of the first 14 bytes of this signaling; After setting the above fixed-length signaling, the communication in this embodiment also adopts a fixed transmission cycle. The master and slave machines need to negotiate a fixed transmission cycle to periodically perform transmission sessions without adding additional pins for flow control, ensuring that the master and slave machines can transmit stably and in real time.

[0021] Before communication, both the host and the slave need to prepare the signaling or data for the next communication. Since the method adopted by the present invention is full-duplex transmission, the data required for this transmission must be prepared in advance when each SPI transmission is started, and the data to be transmitted is placed in the buffer in advance, and the data to be transmitted is directly obtained from the buffer when the next transmission is started; if the signaling or data is not prepared in advance, it will be too late to prepare the data for this transmission during the transmission process. Usually, when the host chip select signal is not released and the clock signal is always generated, the slave will automatically send the data from the shift register of the SPI controller to the data line with the clock signal of the host. Generally, in a controller with DMA or FIFO, the data must be prepared in advance and filled into the DMA and FIFO to prepare for the next transmission.

[0022] In this communication, when there is data that needs to be transmitted, the data that needs to be transmitted will follow the signaling. If there is no data transmission, there is no data domain. If it is sent by the host, it means the data transmitted by the host to the slave. If the host has no data to send, but the slave has data to transmit to the host, this domain can be ignored on the host side, and the data status on the bus is invalid and should be discarded on the slave side. If it is sent by the slave, when the slave has data to transmit to the host, this domain is the data that the slave needs to transmit to the host. If the slave has no data to send to the host, but the host has data to send to the slave, the host should discard this invalid data at this time. If both the host and the slave need to transmit data to each other at the same time, the longest side is selected as the session transmission length, and the host needs to control the effective chip select and clock length to ensure that the longest side data is transmitted completely. If neither side has data to transmit, this stage does not exist on the bus, which is manifested as only transmitting one signaling header.

[0023] From this we can see that the bus exhibits four transmission states: no data transmission between the two parties, unidirectional data transmission by the host, unidirectional data transmission by the slave, and bidirectional data transmission between the master and the slave.

[0024] Based on the field setting and communication mechanism of the above signaling, this embodiment takes the host needing to read the slave as an example, and the specific method is as follows Figure 2 As shown: The transmission is initiated by the host, which is defined as when the host pulls down the chip select signal, the host provides the hardware clock signal of the bus, and determines how many clock signals need to be transmitted for this transmission based on the signaling to ensure that the data packets of both the master and the slave can be fully transmitted; After completing a transmission, the chip select signal is pulled high to stop the transmission; The host sends a signaling packet to read the slave, waits for the slave to prepare a response signaling packet, reads the data status signaling packet prepared by the slave, parses the data status signaling packet of the slave, and decides whether to continue reading data based on whether the slave has data. During the whole process, the chip select is not released and is always in the hold state.

[0025] Each time a transmission is completed, according to the definition of this method, both the master and the slave can obtain the transmission data packet of this time from their own SPI receiving buffer. The specific receiving method can be received by fifo, dma or a single data register. In this embodiment, dma is used for receiving, and then both parties parse the received data packets. The data parsing method is as follows Figure 4 As shown: First check whether the CRC16 of the signaling packet is correct, that is, do a CRC16 check on the content of the first 14 bytes of the signaling, and then compare it with the values ​​of the 15th and 16th bytes in the signaling field. If the CRC values ​​match, the check is passed. If an error occurs, it means that an error occurred in this transmission. When preparing the signaling packet data for the next transmission, do not increment the "expected sequence number of the other party", so that the other party will find that the sequence number does not match during the next transmission, and thus retransmit the previous packet of data. The retransmission rule here is that when an error occurs in the nth packet sequence, it will be detected at the n+1th time, and the nth packet will be retransmitted at the n+2th time.

[0026] When the CRC check of the signaling packet passes, it is directly determined whether the sequence number matches. The sequence number matching rule here is whether the received sequence number seq (the value of the fifth byte of the signaling) matches its own expected_seq (the value of the sixth byte of the signaling). If they do not match, expected_seq will no longer be incremented and will remain unchanged, so that the other party can retransmit the packet during the next transmission.

[0027] If the received expected_seq does not match your own seq, it means that the other party wants you to retransmit the data packet associated with its sequence number. Then you should prepare the next data packet in advance, which should be the retransmitted data packet. And reset your own seq to the sequence number of the retransmitted data packet.

[0028] Both the master and slave machines can cache the three most recent data packets. Let's assume that the data packets are bound to the serial numbers and the data packets are identified by the serial numbers. Assuming that the next transmitted data packet is n+1, then the next three data packets n, n-1, and n+1 need to be cached respectively, because n+1 is the packet to be transmitted next, n is the currently transmitted packet, and n-1 is the last transmitted packet.

[0029] If the party has data to transmit, it needs to set the lower 4 bits of the second byte in the signaling (bit 1 equals 1, indicating that there is data to be sent). Otherwise, the corresponding position is 0; If the user has data to transmit, the third and fourth fields in the signaling need to be filled with the length of the data to be transmitted. Otherwise, set them to 0; If the data packet of the other party's data can be received (usually indicating that there is an idle buffer that can be used as a receiving buffer), the corresponding bit needs to be set on the lower 4 bits of the second byte in the signaling (bit 0 equals 1 to indicate that it can be received), otherwise the corresponding bit is 0; If the data is transmitted immediately after the signaling packet, the length of the data needs to be filled in the seventh and eighth fields of the signaling packet. If there is no data transmission, it is set to 0; If there is data to be transmitted, the CRC16 checksum of the data portion needs to be filled into the thirteenth and fourteenth byte fields of the signaling packet.

[0030] The other reserved fields are filled with 0, and the fixed fields are filled with fixed values. Finally, the CRC16 check algorithm is performed on the first 14 bytes of the entire signaling, and the check code is filled in the fifteenth and sixteenth bytes of the signaling.

[0031] The above embodiments are preferred solutions for implementing the present invention. It should be noted that any obvious substitutions and minor changes are within the protection scope of the present invention without departing from the concept of the present invention.

Claims

1. A SPI full-duplex data transmission method, comprising the transmission of data between a host and a slave, and verifying the data after the transmission is completed, characterized in that: A data transmission method between a host and a slave, wherein the data transmission process includes several signaling stages, the signaling length is fixed and the signaling sending cycle is fixed.

2. SPI full-duplex data transmission method as claimed in claim 1, characterized in that, The following methods are used to set fixed-length signaling: Set the signaling length to 16 bytes, and define fields for the first byte to the sixteenth byte respectively; A field is defined in the signaling to indicate the length of data that has been prepared for transmission, to inform the receiving end to prepare the buffer in advance, and to help the host determine the session window size for the next transmission session.

3. SPI full-duplex data transmission method as claimed in claim 2, characterized in that, The following methods are used to determine the session window size for the next transmission session for the host: Determine a maximum transmission packet size to control chip select and clock cycle.

4. SPI full-duplex data transmission method as claimed in claim 1, characterized in that, The data transmission method between the host and the slave includes the following steps: S101. The host pulls down the chip select signal and initiates transmission; S102. The host provides a hardware clock signal for the bus and determines the number of clock signals required for this transmission based on the signaling; S103. When the transmission is completed, the chip select signal is pulled high and the transmission stops; S104. The host and the slave respectively parse the received data packets.

5. The SPI full-duplex data transmission method as claimed in claim 4, wherein: The host and the slave respectively parse the received data packets including the sequence number verification method and the non-sequence number verification method, wherein the sequence number verification method includes: S201. Check whether the signaling packet CRC16 received by the receiving end is correct, perform CRC16 check on the contents of the first 14 bytes of the signaling, and compare the values ​​of the fifteenth and sixteenth bytes of the signaling. If the CRC values ​​match, the check passes; If the CRC values ​​do not match after the nth data transmission, the signaling's own session sequence number and the expected sequence number of the other party will not increase. When the n+1th data transmission is performed, the sender will try to identify that the sequence number has not increased, and retransmit the nth transmission packet during the n+2th transmission; S202. Determine whether the fifth byte matches the sixth byte. If they do not match, the sequence number is not incremented, and the next communication is attempted by the other party and retransmission occurs; If its own fifth byte does not match the received sixth byte, reset its own fifth byte to the received sixth byte and retransmit; If the sixth byte of the packet does not match the fifth byte of the other party, the packet does not increment its sixth byte and waits for the sender to retransmit. If the sequence numbers match then the sequence number is incremented after the communication; S203. If the received header CRC8 is wrong, only the fifth byte of itself is increased and retransmission is expected; The non-serial number byte verification steps include: S204. Check whether the send-ready flag and receive-ready flag in the signaling are in place. If they are in place, data can be transmitted, and the ready data length in the transmission packet is rdy_len, and the valid data length is data_len; if they are not in place, data cannot be transmitted; The send-ready flag and the receive-ready flag are the values ​​of the second byte of the signaling.

6. An SPI full-duplex data transmission system, comprising a host and a slave, wherein the host and the slave communicate via an SPI bus, wherein: The communication between the master and the slave is controlled by signaling, which includes signaling and other fields. The fixed length of the signaling is 16 bytes, and the first to sixteenth bytes have the following functions respectively: The first byte is a reserved byte, and the default value is 0; The second byte is the send or receive ready flag, a reserved field, and the default value is 0; The third byte and the fourth byte are combined into an unsigned integer to indicate the length of the data that is ready to be transmitted; The fifth byte is used to transmit its own session sequence number; The sixth byte indicates the sequence number that the transmission expects from the other party; The seventh and eighth bytes are combined into an unsigned integer to indicate the length of data to be transmitted after signaling; Bytes 9 to 12 are used to represent signaling packets, and are used as reference fields when searching for signaling packet synchronization in the buffer when a data field error occurs; The thirteenth and fourteenth bytes are combined into an unsigned integer, which is used to represent the CRC16 checksum of the data transmitted after the signaling; The fifteenth byte and the sixteenth byte are combined into an unsigned integer, which is used to represent the CRC16 checksum of the first 14 bytes of the signaling.

7. An SPI full-duplex data transmission device, comprising a module for executing the method according to any one of claims 1 to 5, characterized in that: It includes a processor and an interface circuit, wherein the interface circuit is used to receive signals from other devices other than the device for executing kernel mode commands and transmit them to the processor or send signals from the processor to other devices other than the device for executing kernel mode commands, and the processor is used to implement the method as described in any one of claims 1 to 5 through logic circuits or execution code instructions.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 5 is implemented.

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