Near-memory dma data transposition controller, data transposition method, medium and product

Abstract

The application provides a near-memory DMA data transposition controller, a data transposition method, a medium and a product. The near-memory DMA data transposition controller is arranged on a data transmission path between a far-end memory and a near-end memory of an AI computing chip, and comprises a first DMA control module and a second DMA control module. The transposition operation only occurs after data is read from the near-end memory, thereby reducing independent transposition processing links, reducing transposition power consumption overhead and operation delay, avoiding a decrease in bus bandwidth utilization caused by transposition, and reducing hardware resource overhead. A dynamic splitting strategy concentrates non-aligned access in a first data block, thereby improving overall bandwidth utilization. The transposition operation is separated from a computing unit, the transposition is completed synchronously in a data carrying process, computing resources are released, and an operation period and power consumption overhead are reduced.

Description

Technical Field

[0001] This application relates to the field of data transposition technology in AI networks, and in particular to a near-memory DMA data transposition controller, data transposition method, medium, and product. Background Technology

[0002] In the computation of artificial intelligence (AI) networks, data transpose is a key task in data preprocessing and computation. Its main function is to adjust the memory arrangement of multidimensional tensors to adapt to the access patterns of different computational cores, and it is widely used in various deep learning tasks. For example, in computer vision, input image data often needs to have its dimensional order adjusted (e.g., from [height, width, channels] to [channels, height, width]) to meet the computational requirements of convolutional neural networks (CNNs). In natural language processing (NLP) tasks, tensors after word embeddings also frequently need dimensional adjustment to adapt to the computational rules of attention mechanisms.

[0003] Currently, the industry mainly adopts the following two transposition implementation schemes:

[0004] (1) Perform transpose operation within the computing unit

[0005] This approach first transmits data to the computation unit, which then performs the transpose operation. However, since computation units are typically optimized for computational tasks such as matrix multiplication and convolution, their microarchitecture is inefficient when performing data transpose, consuming significant computational resources and increasing computation cycles, leading to a decrease in overall computational efficiency. Furthermore, transposing a single tensor requires multiple computation cycles, significantly increasing overall computational latency. In addition, the transpose operation itself does not involve numerical computation; it only adjusts the data arrangement. Therefore, having the computation unit perform this operation wastes valuable computational resources and reduces the overall processing speed of the AI ​​network.

[0006] (2) Perform transpose operation in DMA (Direct Memory Access) module

[0007] This scheme attempts to perform the transposition operation during data transfer, which theoretically reduces the burden on the computing unit. However, existing DMA schemes typically design linear transfer and transposition transfer as independent modules, with the data path only sharing the bus interface. This results in low data path reuse and requires additional buffers, increasing the hardware area of ​​the DMA. When the starting address and dimension step of the source tensor are not aligned with the bus width, the static block strategy during transposition can trigger frequent non-contiguous memory accesses, significantly reducing bus bandwidth utilization and impacting data transfer efficiency. Summary of the Invention

[0008] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a near-memory DMA data transposition controller, data transposition method, medium and product to solve the technical problems of long operation cycle and low bus bandwidth utilization in the existing data transposition scheme.

[0009] To achieve the above and other related objectives, a first aspect of this application provides a near-memory DMA data transposition controller, disposed on the data transmission path between the far-end memory and the near-end memory of an AI computing chip. The near-memory DMA data transposition controller includes a first DMA control module and a second DMA control module; wherein:

[0010] The first DMA control module is configured to, based on the first command configuration information and a preset dynamic partitioning strategy, read multiple first data blocks from the remote memory, which are divided row by row index according to the first target partitioning dimension, and write each first data block into the spare memory area of ​​the near-end memory; read each first data block from the spare memory area of ​​the near-end memory, and, based on a preset first transpose condition, perform a shift and recombination operation on each first data block before writing it into the first target storage area of ​​the near-end memory;

[0011] The second DMA control module is used to read multiple second data blocks, which are divided row by row index on the second target segmentation dimension, from the near-end memory based on the second command configuration information and the preset dynamic segmentation strategy; and to perform shift and recombination operations on each of the second data blocks based on the preset second transpose condition, and then write them into the second target storage area of ​​the far-end memory.

[0012] In some embodiments of the first aspect of this application, the first DMA control module includes a first command control module, a first transmission segmentation module, a block space identification module, and a block write operation construction module; the near-end memory is provided with multiple spare memory regions, each of which is used to store multiple first data blocks with the same row index; wherein, the method of reading multiple first data blocks of the first data to be converted from the far-end memory, which are divided row by row index according to the first target segmentation dimension, based on the first command configuration information and a preset dynamic segmentation strategy, and writing each of the first data blocks into the spare memory regions of the near-end memory respectively includes:

[0013] The first command control module is used to receive first command configuration information, which includes dimension and address parameters of the first data to be converted.

[0014] The first transmission segmentation module is used to generate multiple bus read operation requests that conform to the bus protocol based on the dimension size parameter information and address parameter information of the first data to be converted and a preset dynamic segmentation strategy; determine the priority of each bus read operation request; and send each bus read operation request according to the priority to read multiple first data blocks of the first data to be converted, which are divided row by row index on the first target segmentation dimension, from the remote memory.

[0015] The block space identification module is used to record the usage information of each of the spare memory regions;

[0016] The block write operation construction module is used to receive each of the first data blocks read from the remote memory, and generate multiple write operation control signals according to the usage information of each of the spare memory regions; and write each of the first data blocks into the spare memory region corresponding to the near memory according to each of the write operation control signals.

[0017] In some embodiments of the first aspect of this application, the first DMA control module further includes a block read control module and a first remodeling module; wherein, the method of reading each of the first data blocks from the spare memory area of ​​the near-end memory, performing a shift and reorganization operation on each of the first data blocks based on a preset first transpose condition, and writing them into the first target memory area of ​​the near-end memory includes:

[0018] The block read control module is used to generate multiple first read operation control signals based on the usage information of each of the backup memory regions; and to read the first data blocks with different row indices from each of the backup memory regions according to each of the first read operation control signals.

[0019] The first reshaping module is used to perform a shift operation on the first data block with different row indices to obtain multiple third data blocks; according to a preset first transpose condition, it performs a reorganization operation on each of the third data blocks to obtain each row of data in the first target data set, and writes each row of data in the first target data set into the first target storage area corresponding to the near-end memory.

[0020] In some embodiments of the first aspect of this application, the second DMA control module includes a second command master control module, a source information generation module, and a block read operation construction module; wherein, based on the second command configuration information and a preset dynamic segmentation strategy, the method of reading multiple second data blocks of the second data to be converted from the near-end memory, segmented row by row according to the second target segmentation dimension, includes:

[0021] The second command control module is used to receive second command configuration information, which includes dimension parameters and address parameters of the second data to be converted.

[0022] The source information generation module is used to generate row index information of the second data to be converted in the second target segmentation dimension and the starting address information corresponding to each row index of the second data to be converted in the second target segmentation dimension, based on the dimension size parameter information and address parameter information of the second data to be converted.

[0023] The block read operation construction module is used to generate multiple second read operation control signals based on the row index information of the second data to be converted in the second target segmentation dimension and the starting address information corresponding to each row index of the second data to be converted in the second target segmentation dimension, and based on a preset dynamic segmentation strategy; and to read multiple second data blocks of the second data to be converted, which are divided row by row index in the second target segmentation dimension, from the near-end memory according to each second read operation control signal.

[0024] In some embodiments of the first aspect of this application, the second DMA control module includes a second reshaping module and a bus write data construction module; wherein, based on a preset second transpose condition, the method of writing each of the second data blocks into the second target storage area of ​​the remote memory after performing shift and reorganization operations includes:

[0025] The second reshaping module is used to perform shift operations on the second data blocks with different row indices to obtain multiple fourth data blocks; according to the preset second transpose condition, the fourth data blocks are recombined to obtain each row of data in the second target data set, and each row of data in the second target data set is sent to the bus write data construction module.

[0026] The bus write data construction module is used to perform byte shifting operations on each row of data in the second target data set based on the target address offset, and then write it into the second target storage area corresponding to the remote memory.

[0027] In some embodiments of the first aspect of this application, the second DMA control module further includes a second transmission segmentation module, which is used to generate multiple bus write operation requests conforming to the bus protocol based on the dimension parameter information and address parameter information of the second data to be converted.

[0028] In some embodiments of the first aspect of this application, the preset dynamic segmentation strategy includes: (1) when the segmentation progress information of each row index of the data to be converted in the target segmentation dimension is not recorded, the data to be converted is segmented row by row in the target segmentation dimension in ascending order of row index; (2) when the segmentation progress information of each row index of the data to be converted in the target segmentation dimension has been recorded, the row index with the smallest amount of segmented data is selected for priority segmentation.

[0029] To achieve the above and other related objectives, a second aspect of this application provides a data transposition method applied to a near-memory DMA data transposition controller as described above. The near-memory DMA data transposition controller is disposed on the data transmission path between the far-end memory and the near-end memory of an AI computing chip. The near-memory DMA data transposition controller includes a first DMA control module and a second DMA control module. The data transposition method includes:

[0030] The first DMA control module, based on the first command configuration information and the preset dynamic partitioning strategy, reads multiple first data blocks from the remote memory, which are divided row by row index according to the first target partitioning dimension, and writes each first data block into the spare memory area of ​​the near-end memory; it then reads each first data block from the spare memory area of ​​the near-end memory, performs a shift and recombination operation on each first data block based on the preset first transpose condition, and writes it into the first target storage area of ​​the near-end memory.

[0031] The second DMA control module reads multiple second data blocks from the near-end memory based on the second command configuration information and the preset dynamic segmentation strategy, which are divided row by row index on the second target segmentation dimension. Based on the preset second transpose condition, the module performs a shift and recombination operation on each second data block and writes it into the second target storage area of ​​the far-end memory.

[0032] To achieve the above and other related objectives, a third aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the data transposition method described above.

[0033] To achieve the above and other related objectives, a fourth aspect of this application provides a computer program product comprising computer program code that, when executed on a computer, causes the computer to implement the data transposition method as described above.

[0034] As described above, the near-memory DMA data transposition controller, data transposition method, medium, and product of this application have the following beneficial effects:

[0035] (1) Reduced transpose power consumption: Whether it is the data transmission path from the remote memory to the near memory or the data transmission path from the near memory to the remote memory, the transpose operation only occurs after the data is read from the near memory, which reduces the independent transpose processing steps, reduces transpose power consumption and operation delay, and avoids the decrease in bus bandwidth utilization caused by transpose.

[0036] (2) Dynamic segmentation improves bandwidth utilization: When the data to be converted is processed for the first time, it is segmented according to the row index order. In subsequent operations, the row index with the slower progress is dynamically selected for priority processing. Only the first data block will have bandwidth loss due to address misalignment. All subsequent data blocks are accessed in alignment. Compared with the static segmentation strategy, each block may waste bandwidth due to address misalignment. The dynamic segmentation strategy of this application concentrates the misalignment access on the first data block, thereby improving the overall bandwidth utilization.

[0037] (3) Reduce hardware resource overhead: The transpose operation only occurs after reading data from the near-end memory. Taking advantage of the near-end memory's multi-storage narrow bit width characteristics, the first reshaping module and the second reshaping module only need to align the depth and width to the storage data bit width of the near-end memory, and no cache needs to be configured, which reduces the hardware design logic overhead, maintains high bus utilization, and improves the execution efficiency of the transpose operation.

[0038] (4) Reduce the occupation of computing resources: The transpose operation is separated from the computing unit and embedded in the data transmission path. The transpose is completed synchronously during the data transfer process, releasing computing resources. This avoids the inefficiency of the computing unit performing transpose in the existing technology, reduces the operation cycle and power consumption, and improves the bus bandwidth utilization, thereby improving the overall processing speed of the AI ​​network. Attached Figure Description

[0039] Figure 1 The diagram shown is a structural schematic of the first DMA control module in one embodiment of this application.

[0040] Figure 2 The diagram shown is a structural schematic of the second DMA control module in one embodiment of this application.

[0041] Figure 3 The diagram shown is a segmentation schematic of a dynamic segmentation strategy in one embodiment of this application.

[0042] Figure 4 The diagram shown is a flowchart illustrating a data transposition method according to an embodiment of this application.

[0043] Figure 5 This is shown as another flowchart of a data transposition method in one embodiment of this application. Detailed Implementation

[0044] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0045] Before providing a further detailed description of the present invention, the nouns and terms used in the embodiments of the present invention are explained, and the nouns and terms used in the embodiments of the present invention are subject to the following interpretations:

[0046] <1> DMA (Direct Memory Access) is a data transfer technology in computer systems that allows external devices (such as hard drives, graphics cards, etc.) to directly access system memory without the intervention of the central processing unit.

[0047] <2> Buffer: A buffer or data buffer refers to a storage area used to temporarily store data during data transmission or processing.

[0048] Existing technologies mainly employ two transposition implementation schemes: the first is to perform the transposition operation within the computing unit; the second is to perform the transposition operation within the DMA (Direct Memory Access) module. Performing the transposition operation within the computing unit suffers from problems such as consuming computing resources, increasing computation cycles, and reducing the overall processing speed of the AI ​​network. Performing the transposition operation within the DMA module results in low hardware resource reuse due to its independent module design, requires additional buffers, increases the DMA hardware area, and the static block partitioning strategy causes a decrease in bus bandwidth utilization during unaligned access, affecting data transmission efficiency.

[0049] To address the technical problems existing in the background art, this application provides a near-memory DMA data transposition controller, data transposition method, medium, and product, aiming to solve the technical problems of long operation cycle and low bus bandwidth utilization in existing data transposition schemes.

[0050] To facilitate understanding of the embodiments of this application, firstly, in conjunction with Figure 1-2 Detailed explanation. Figure 1 A schematic diagram of the structure of the first DMA control module in an embodiment of the present invention is shown. Figure 2A schematic diagram of the structure of the second DMA control module in an embodiment of the present invention is shown. The near-memory DMA data transposition controller is disposed on the data transmission path between the far-end memory and the near-end memory of the AI ​​computing chip. The near-memory DMA data transposition controller includes a first DMA control module and a second DMA control module; wherein:

[0051] The first DMA control module is used to read multiple first data blocks, which are divided row by row index on the first target segmentation dimension, from the remote memory based on the first command configuration information and the preset dynamic segmentation strategy, and write each of the first data blocks into the spare memory area of ​​the near-end memory; read each of the first data blocks from the spare memory area of ​​the near-end memory, and perform a shift and recombination operation on each of the first data blocks based on the preset first transpose condition, and write them into the first target storage area of ​​the near-end memory.

[0052] The second DMA control module is used to read multiple second data blocks, which are divided row by row index on the second target segmentation dimension, from the near-end memory based on the second command configuration information and the preset dynamic segmentation strategy; and to perform shift and recombination operations on each of the second data blocks based on the preset second transpose condition, and then write them into the second target storage area of ​​the far-end memory.

[0053] In this embodiment, the near-memory DMA data transposition controller reads data from or writes data to the remote memory via a network-on-chip (NoC). A network-on-chip (NoC) is a communication subsystem architecture used for communication between multiple processing elements in an integrated circuit. It enables high-bandwidth, low-latency, and scalable data interaction between core components (such as GPUs and AI accelerators), storage units, and I / O modules within the chip via routers and network links. The NoC can employ a bus protocol to achieve data interaction between the remote memory and the near-memory DMA data transposition controller.

[0054] In this embodiment, the near-memory DMA data transposition controller is integrated into the near-end memory side of the computing unit close to the AI ​​computing chip. On the data transfer path from the far-end memory to the near-end memory, the near-memory DMA data transposition controller transposes the first data to be converted read from the far-end memory and writes it into the near-end memory. On the data transfer path from the near-end memory to the far-end memory, the near-memory DMA data transposition controller transposes the second data to be converted read from the near-end memory and writes it into the far-end memory. The two types of data transfer paths are decoupled in hardware and can perform transposition independently to meet the needs of different conversion scenarios.

[0055] In this embodiment, the types of remote memory include, but are not limited to, DDR and 3D DRAM, and the types of near-end memory include, but are not limited to, Private Memory, Local Memory, and Global Memory. DDR Double Data Rate Synchronous Dynamic Random Access Memory is a synchronous dynamic random access memory technology that achieves double the data transfer rate by transmitting data twice per clock cycle (rising edge and falling edge). 3D DRAM is a high-density memory that integrates multiple layers of DRAM memory cells into a single package using vertical stacking technology. Private Memory refers to dedicated memory, a storage area exclusively used by each processing unit, which cannot be directly accessed by other processing units. Local Memory refers to shared memory, a storage space shared by multiple processing units within the same cluster (such as multiple cores within a computing unit group). Global Memory refers to global memory, a unified storage space accessible to all processing units, typically located outside the chip or as the last layer of cache on-chip.

[0056] In this embodiment, as Figure 1 As shown, the first DMA control module includes a first command control module (DMA_CMD_QUEUE1), a first transfer segmentation module (AXI_TRANS_SPLIT1), a block space identifier module (TILE_SPACE_TAG), and a block write operation construction module (TILE_WR_BUILD); the near-end memory is provided with multiple spare memory areas, each of which is used to store multiple first data blocks with the same row index; wherein, the method of reading multiple first data blocks of the first data to be converted from the far-end memory according to the row index on the first target segmentation dimension based on the first command configuration information and the preset dynamic segmentation strategy, and writing each of the first data blocks into the spare memory areas of the near-end memory respectively includes:

[0057] (1) The first command control module (DMA_CMD_QUEUE1) is used to receive the first command configuration information, which includes the dimension size parameter information and address parameter information of the first data to be converted.

[0058] In this embodiment, the dimensional size parameter information of the first data to be converted includes the data volume information of the first data to be converted in each dimension (height H, width W, channel C); the address parameter information of the first data to be converted includes the source address information of the first data to be converted, the target address information of the transposed first data to be converted, the address step value of each dimension of the first data to be converted in the source address information, and the address step value of each dimension of the first data to be converted in the target address information, etc.

[0059] (2) The first transmission segmentation module (AXI_TRANS_SPLIT1) is used to generate multiple bus read operation requests that conform to the bus protocol based on the dimension size parameter information and address parameter information of the first data to be converted and a preset dynamic segmentation strategy; determine the priority of each bus read operation request, and send each bus read operation request according to the priority to read multiple first data blocks of the first data to be converted from the remote memory, which are divided row by row index on the first target segmentation dimension.

[0060] In this embodiment, based on the dimension and address parameters of the first data to be converted and a preset dynamic splitting strategy, multiple bus read operation requests (AR req) conforming to the bus protocol are generated. Each bus read operation request includes the source address of the first data block to be read, the address of the spare memory region to be written to after the first data block is read, and the address of the first target storage region to be written after transposition.

[0061] In this embodiment, the first transmission segmentation module (AXI_TRANS_SPLIT1) selects a suitable first target segmentation dimension by parsing the dimensional size parameter information (such as height, width, and number of channels) and address parameter information (such as the address stride value of each dimension of the first data to be converted in the source address information). For example, when it is detected that the address stride value of the row dimension (H) is aligned with the bus width and the data within the row is continuous, the row is selected as the first target segmentation dimension.

[0062] In this embodiment, as Figure 3 The diagram shown illustrates a segmentation schematic of a dynamic segmentation strategy in an embodiment of the present invention. The preset dynamic segmentation strategy includes the following methods:

[0063] (1) When the segmentation progress information of each row index of the data to be transformed in the target segmentation dimension is not recorded, the data to be transformed is segmented row by row in the target segmentation dimension according to the order of the row index from smallest to largest.

[0064] (2) When the splitting progress information of each row index of the data to be transformed in the target splitting dimension has been recorded, select the row index with the smallest amount of split data for priority splitting.

[0065] In this embodiment, on the data transmission path from the remote storage to the near storage, the data to be converted is the first data to be converted. When the segmentation progress information of each row index of the first data to be converted in the first target segmentation dimension has not been recorded, the first data to be converted is segmented row by row in the first target segmentation dimension in ascending order of row index. When the segmentation progress information of each row index of the first data to be converted in the first target segmentation dimension has been recorded, the row index with the smallest amount of segmented data is selected for priority segmentation.

[0066] (3) The block space identification module (TILE_SPACE_TAG) is used to record the usage information of each of the spare memory regions.

[0067] In this embodiment, as Figure 1 , 3 As shown, the first transmission segmentation module (AXI_TRANS_SPLIT1), combined with the information recorded by the block space identification module (TILE_SPACE_TAG), divides the first data to be converted into the first target segmentation dimension, and sends the generated bus read operation request to the remote memory through the on-chip network (NoC) to read the multiple segmented first data blocks. Here, row 0-row n represent row indices, dim 0 represents the row dimension, and dim 1 represents the column dimension. For example, the first target segmentation dimension is the row dimension. Based on the address stride value of the row dimension of the first data to be converted in the source address information, the byte offset between the starting addresses of two adjacent rows is determined. Combining the starting address of the first row and the address stride value, the source memory region of any row (row i) can be determined to ensure that the bus read operation request can locate the first data block of each row in the original memory. The shape difference of the first data block stems from the non-alignment characteristics of the source address, while the uniformity of subsequent blocks is guaranteed by the address stride value meeting the bus alignment requirements.

[0068] In this embodiment, the block space identification module (TILE_SPACE_TAG) is also used to record the segmentation progress information of each row index of the first data to be converted in the first target segmentation dimension. When the block space identification module (TILE_SPACE_TAG) does not record the segmentation progress information of each row index of the first data to be converted in the first target segmentation dimension, the first data to be converted is segmented row by row in the first target segmentation dimension according to the row index in ascending order, starting from the minimum row index value (row 0) and processing downwards row by row (row 1→ row 2→...→ row n), and gray represents the shape of the first data block after segmentation.

[0069] In this embodiment, when the TILE_SPACE_TAG module records the segmentation progress information of each row index of the first data to be transformed in the first target segmentation dimension, the row index with the smallest amount of already segmented data is selected for priority segmentation to ensure that all rows are segmented as synchronously as possible. For example, if the amount of already segmented data in row 2 is less than that in row 1, the next segmentation block will be taken from row 2 instead of processing row 1 in sequence.

[0070] In this embodiment, the block space identification module (TILE_SPACE_TAG) is also used to record the identifier (AXI ID) of each bus read operation request and the row index corresponding to the identifier of each bus read operation request, thereby determining which row the first data block read from the remote memory belongs to and the spare memory area to be written. For the first data to be converted, the bus read operation request corresponding to the first data block generated by prioritizing the first data block on the first target segmentation dimension is transmitted as the highest priority. When the high priority queue is empty, the bus read operation requests are sent in the order they were generated. After the bus read operation request is sent out through the on-chip network (NoC), it triggers the response process of the remote memory. R info represents read response information, which corresponds to the bus read operation request, so that the block space identification module (TILE_SPACE_TAG) records the identifier (AXI ID) of each bus read operation request and the row index corresponding to the identifier of each bus read operation request.

[0071] (4) The block write operation building module (TILE_WR_BUILD) is used to receive each of the first data blocks read from the remote memory and generate multiple write operation control signals according to the usage information of each of the spare memory regions; according to each of the write operation control signals, each of the first data blocks is written to the spare memory region corresponding to the near memory.

[0072] In this embodiment, the block write operation building module (TILE_WR_BUILD) receives a first data block (R data) read from the remote memory. If the space of the spare memory region to be written to is not occupied, a write operation control signal (MEM WR0) is generated to write the read first data block to the corresponding spare memory region. If the space of the spare memory region to be written to is occupied, the data is read out through the block read control module (MEM_RD_SPLIT), and after the space of the corresponding spare memory region is released, a write operation control signal (MEM WR0) is generated, and then the data is written.

[0073] In this embodiment, the near-end memory is further provided with multiple first target storage areas, which can be used to store the transposed first data to be converted or the transposed second data to be converted, such as Bank 0-Bank n. The first DMA control module further includes a block read control module (MEM_RD_SPLIT) and a first reshaping module (RESHAPE_REG_ARRARY1); wherein, the method of reading each first data block from the spare memory area of ​​the near-end memory, and performing a shift and reorganization operation on each first data block based on a preset first transpose condition, and then writing it into the first target storage area of ​​the near-end memory includes:

[0074] (1) The block read control module (MEM_RD_SPLIT) is used to generate multiple first read operation control signals according to the usage information of each of the backup memory regions; and to read the first data blocks with different row indices from each of the backup memory regions according to each of the first read operation control signals.

[0075] (2) The first reshaping module (RESHAPE_REG_ARRARY1) is used to perform shift operations on the first data blocks with different row indices read to obtain multiple third data blocks; according to the preset first transpose condition, the third data blocks are recombined to obtain each row of data in the first target data set, and each row of data in the first target data set is written into the first target storage area corresponding to the near-end memory.

[0076] In this embodiment, since the first data block returned via the on-chip network (NoC) is out of order—for example, the first data block of the last 10 rows might be returned first—the block read control module (MEM_RD_SPLIT) can determine which rows of the first data block have been written based on the usage information of each of the spare memory regions recorded in the block space identification module (TILE_SPACE_TAG), thus preparing for sequential reading of the first data blocks of each row. After determining that each spare memory region stores the first data block corresponding to the row index, multiple first read operation control signals are generated to read the first data blocks of different row indices and perform address alignment, i.e. Figure 1 MEM RD1 in the middle.

[0077] In this embodiment, the block read control module (MEM_RD_SPLIT) reads the first data block of each row index sequentially in row priority order; then, it reads the second data block of each row index in the same manner, and so on until all the first data blocks have been read. For example, the first data block of row indices row 0-row 9 is read first; then, the second data block of row indices row 0-row 9 is read, and so on, until all the first data blocks of all row indices have been read.

[0078] In this embodiment, the preset first transpose condition includes the bit width of the first target storage area. The first reshaping module (RESHAPE_REG_ARRARY1) performs a shift operation on the first data blocks with different row indices read by the block read control module (MEM_RD_SPLIT) to remove invalid data in the first data blocks, obtaining multiple third data blocks, and storing them in the first register of the first reshaping module. When the sum of the number of valid bytes in the multiple third data blocks is equal to the bit width of the first target storage area, the multiple third data blocks whose sum of valid bytes is equal to the bit width of the first target storage area are read from the first register and reassembled to obtain a new row of data in the first target data set, and the new row of data in the first target data set is written into the corresponding first target storage area, i.e. Figure 1 In the MEM WR1 register, the space of the first register is freed to receive the next round of third data blocks. For redundant third data blocks, wait for the next round of third data blocks, and reassemble them into the next row of data when the sum of the number of valid bytes equals the bit width of the first target storage area. This process is repeated until all first data blocks have been shifted and reassembled, thereby changing the dimensional layout of the first data to be converted, achieving data transposition.

[0079] In this embodiment, for example, the first reshaping module (RESHAPE_REG_ARRARY1) shifts the first data block of row indices row 0-row 9 to remove invalid data, obtaining multiple corresponding third data blocks, and stores them in the first register of the first reshaping module. When the sum of the number of valid bytes of the multiple third data blocks stored in the first register is equal to the bit width of the first target storage area, it is read out, reassembled into a new row of data, and written into the corresponding first target storage area. When the sum of the number of valid bytes of the multiple third data blocks stored in the first register is less than the bit width of the first target storage area, it waits for the block read control module (MEM_RD_SPLIT) to read a new first data block. The first reshaping module (RESHAPE_REG_ARRARY1) shifts the second data block of row indices row 0-row 9, removes invalid data, obtaining multiple corresponding third data blocks. The multiple third data blocks whose sum of valid bytes is equal to the bit width of the first target storage area are read out of the first register, reassembled into a new row of data, and written into the corresponding first target storage area. When the sum of the number of valid bytes in the multiple third data blocks stored in the first register exceeds the width of the first target storage area, the multiple third data blocks whose sum of valid bytes equals the width of the first target storage area are read from the first register, reassembled into a new row of data, and written into the corresponding first target storage area. The excess third data blocks are then reassembled with the third data blocks of the next round. This process is repeated until all data has been written.

[0080] In this embodiment, as Figure 2 As shown, the second DMA control module includes a second command master control module (DMA_CMD_QUEUE2), a source information generation module (SRC_INFO_GEN), and a block read operation construction module (TILE_RD_BUILD); wherein, based on the second command configuration information and the preset dynamic segmentation strategy, the method of reading multiple second data blocks of the second data to be converted from the near-end memory, which are divided row by row index on the second target segmentation dimension, includes:

[0081] (1) The second command control module (DMA_CMD_QUEUE2) is used to receive the second command configuration information, which includes the dimension size parameter information and address parameter information of the second data to be converted.

[0082] In this embodiment, the dimension size parameter information and address parameter information of the second data to be converted include the data volume information of the second data to be converted in each dimension (height H, width W, channel C); the address parameter information of the second data to be converted includes the source address information of the second data to be converted, the target address information of the transposed second data to be converted, the address step value of each dimension of the second data to be converted in the source address information, and the address step value of each dimension of the second data to be converted in the target address information, etc.

[0083] (2) The source information generation module (SRC_INFO_GEN) is used to generate the row index information of the second data to be converted on the second target segmentation dimension and the starting address information corresponding to each row index of the second data to be converted on the second target segmentation dimension according to the dimension size parameter information and address parameter information of the second data to be converted.

[0084] In this embodiment, the source information generation module (SRC_INFO_GEN) analyzes the alignment relationship between the address stride values ​​of each dimension of the second data to be converted in the source address information and the target storage bit width, and combines this with the dimension size parameters (height H, width W, number of channels C) of the second data to be converted to determine a suitable second target segmentation dimension. Subsequently, based on the second target segmentation dimension, the second data to be converted is divided into several row indices, and the starting address information of each row index is generated based on the source address information of the second data to be converted.

[0085] (3) The block read operation construction module (TILE_RD_BUILD) is used to generate multiple second read operation control signals based on the row index information of the second data to be converted in the second target segmentation dimension and the starting address information corresponding to each row index of the second data to be converted in the second target segmentation dimension, and based on a preset dynamic segmentation strategy; according to each second read operation control signal, it reads multiple second data blocks of the second data to be converted from the near-end memory, which are divided row by row according to the row index in the second target segmentation dimension.

[0086] In this embodiment, the preset dynamic segmentation strategy for the data transmission path from near-end memory to far-end memory is similar to the dynamic segmentation strategy for the data transmission path from far-end memory to near-end memory, and will not be described again here. The data to be converted is the second data to be converted. When the segmentation progress information of each row index of the second data to be converted in the second target segmentation dimension has not been recorded, the second data to be converted is segmented row by row in the second target segmentation dimension in ascending order of row index. When the segmentation progress information of each row index of the second data to be converted in the second target segmentation dimension has been recorded, the row index with the smallest amount of segmented data is selected for priority segmentation.

[0087] In this embodiment, the block read operation construction module (TILE_RD_BUILD) uses the segmentation progress information of each row index of the second data to be converted in the second target segmentation dimension, which it records, combined with the row index information of the second data to be converted in the second target segmentation dimension and the starting address information corresponding to each row index of the second data to be converted in the second target segmentation dimension, to segment the second data to be converted in the second target segmentation dimension, and generates multiple second read operation control signals, so that the corresponding second data block is read according to the second read operation control signals, i.e. Figure 2 In MEM RD2, the second read operation control signal corresponding to the second data block generated by the second target segmentation dimension is prioritized and transmitted as the highest priority. When the high-priority queue is empty, the signals are transmitted in the order they were generated.

[0088] In this embodiment, the block read operation building module (TILE_RD_BUILD) reads the second data blocks of different row indices in a row-priority order according to the second read operation control signal. The reading method is the same as the reading method of the block read control module (MEM_RD_SPLIT) for reading the first data block, and will not be described again here.

[0089] In this embodiment, the second DMA control module further includes a second transfer segmentation module (AXI_TRANS_SPLIT2), which is used to generate multiple bus write operation requests (AW req) conforming to the bus protocol based on the dimension size parameter information and address parameter information of the second data to be converted.

[0090] In this embodiment, as Figure 2 As shown, the second DMA control module includes a second reshaping module (RESHAPE_REG_ARRARY2) and a bus write data construction module (AXI_WDATA_BUILD); wherein, based on a preset second transpose condition, the method of writing each of the second data blocks into the second target storage area of ​​the remote memory after performing shift and reorganization operations includes:

[0091] (1) The second reshaping module (RESHAPE_REG_ARRARY2) is used to perform shift operations on the second data blocks with different row indices to obtain multiple fourth data blocks; according to the preset second transpose condition, the fourth data blocks are reassembled to obtain each row of data in the second target data set, and each row of data in the second target data set is sent to the bus write data construction module (AXI_WDATA_BUILD).

[0092] (2) The bus write data construction module (AXI_WDATA_BUILD) is used to perform byte shifting operations on each row of the second target data set based on the target address offset, and then write it into the second target storage area corresponding to the remote memory.

[0093] In this embodiment, the preset second transpose condition includes the bus width. The second reshaping module (RESHAPE_REG_ARRARY2) performs a shift operation on the second data blocks with different row indices read by the block read operation building module (TILE_RD_BUILD) to remove invalid data in the second data blocks, obtaining multiple fourth data blocks, which are then stored in the second register of the second reshaping module. When the sum of the number of valid bytes in the multiple fourth data blocks equals the bus width, the multiple fourth data blocks whose sum of valid bytes equals the bus width are read from the second register and reassembled to obtain a new row of data in the second target data set. This row of data is then sent to the bus write data building module (AXI_WDATA_BUILD), and the space in the second register is released to receive the next round of fourth data blocks. For redundant fourth data blocks, the system waits for the next round of fourth data blocks, and when the sum of the number of valid bytes equals the bus width, it reassembles them into the next row of data. This process is repeated until all the shifting and reassembly of the second data blocks are completed, thereby changing the dimensional layout of the second data blocks and realizing data transpose. The second reshaping module operates on the same principle as the first reshaping module, and will not be elaborated upon here.

[0094] In this embodiment, the bus write data construction module (AXI_WDATA_BUILD) performs byte shifting operations on the current row data of the received second target data set based on the target address offset to achieve bus address alignment, and writes the current row data after the byte shifting operation into the second target storage area corresponding to the remote memory. Figure 2 Wdata in the middle.

[0095] In this embodiment, after writing all rows of data from the second target data set to the remote memory, the remote memory feeds back a response signal (B rsp) through the on-chip network (NoC), which corresponds to the bus write operation request, and determines whether the total amount of data written is correct based on the amount of data received by the second reshaping module (RESHAPE_REG_ARRARY2).

[0096] It is worth noting that the near-memory DMA data transposition controller of this application has the following advantages:

[0097] (1) Reduced transpose power consumption: Whether it is the data transmission path from the remote memory to the near memory or the data transmission path from the near memory to the remote memory, the transpose operation only occurs after the data is read from the near memory, which reduces the independent transpose processing steps, reduces transpose power consumption and operation delay, and avoids the decrease in bus bandwidth utilization caused by transpose.

[0098] (2) Dynamic segmentation improves bandwidth utilization: When the data to be converted is processed for the first time, it is segmented according to the row index order. In subsequent operations, the row index with the slower progress is dynamically selected for priority processing. Only the first data block will have bandwidth loss due to address misalignment. All subsequent data blocks are accessed in alignment. Compared with the static segmentation strategy, each block may waste bandwidth due to address misalignment. The dynamic segmentation strategy of this application concentrates the misalignment access on the first data block, thereby improving the overall bandwidth utilization.

[0099] (3) Reduce hardware resource overhead: The transpose operation only occurs after reading data from the near-end memory. Taking advantage of the near-end memory's multi-storage narrow bit width characteristics, the first reshaping module and the second reshaping module only need to align the depth and width to the storage data bit width of the near-end memory, and no cache needs to be configured, which reduces the hardware design logic overhead, maintains high bus utilization, and improves the execution efficiency of the transpose operation.

[0100] (4) Reduce the occupation of computing resources: The transpose operation is separated from the computing unit and embedded in the data transmission path. The transpose is completed synchronously during the data transfer process, releasing computing resources. This avoids the inefficiency of the computing unit performing transpose in the existing technology, reduces the operation cycle and power consumption, and improves the bus bandwidth utilization, thereby improving the overall processing speed of the AI ​​network.

[0101] In the embodiments of this application, terms such as "first" and "second" are used to distinguish identical or similar items with essentially the same function and purpose. For example, "first data block" and "second data block" are used only to distinguish different data blocks and do not limit their order. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or execution order, and that "first" and "second" do not necessarily imply that they are different.

[0102] It should be noted that, in the embodiments of this application, the words "exemplary" or "for example" indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0103] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0104] Figure 4 This is a flowchart illustrating the data transposition method provided in this application embodiment. The data transposition method is applied to the near-memory DMA data transposition controller described above. The near-memory DMA data transposition controller is located on the data transmission path between the far-end memory and the near-end memory of the AI ​​computing chip. The near-memory DMA data transposition controller includes a first DMA control module and a second DMA control module; wherein, the data transposition method includes:

[0105] S401: The first DMA control module reads multiple first data blocks from the remote memory based on the first command configuration information and the preset dynamic segmentation strategy, dividing the first data to be converted into multiple first data blocks by row index on the first target segmentation dimension, and writes each of the first data blocks into the spare memory area of ​​the near memory.

[0106] S402: The first DMA control module reads each of the first data blocks from the spare memory area of ​​the near-end memory, and after performing a shift and reorganization operation on each of the first data blocks based on a preset first transpose condition, writes them into the first target storage area of ​​the near-end memory.

[0107] In this embodiment, Figure 5 This is another schematic flowchart of the data transposition method provided in this application embodiment. The data transposition method includes:

[0108] S501: The second DMA control module reads multiple second data blocks from the near-end memory based on the second command configuration information and the preset dynamic segmentation strategy, which are divided row by row according to the row index of the second data to be converted in the second target segmentation dimension.

[0109] S502: When the second DMA control module performs a shift and recombination operation on each of the second data blocks based on the preset second transpose condition, it writes them into the second target storage area of ​​the remote memory.

[0110] It should be understood that the specific process of each module performing the above-mentioned corresponding steps has been described in detail in the above device embodiments, and will not be repeated here for the sake of brevity.

[0111] It should also be understood that the module division in the embodiments of this application is illustrative and only represents a logical functional division; in actual implementation, there may be other division methods. Furthermore, the functional modules in the various embodiments of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0112] According to the method provided in the embodiments of this application, this application also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method described above. Figures 4 to 5 The data transposition method described in any of the embodiments shown.

[0113] According to the method provided in the embodiments of this application, this application also provides a computer program product, which includes computer program code. When the computer program code is run on a computer, it causes the computer to perform the following... Figures 4 to 5 The data transposition method described in any of the embodiments shown.

[0114] As used in this specification, the terms "component," "module," "system," etc., are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0115] Those skilled in the art will recognize that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0116] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0117] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0118] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0119] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0120] In the above embodiments, the functions of each functional unit can be implemented entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., high-density digital video discs, DVDs), or semiconductor media (e.g., solid-state disks, SSDs, etc.).

[0121] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0122] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0123] In summary, this application provides a near-memory DMA data transposition controller, data transposition method, medium, and product. The transposition operation only occurs after data is read from the near-end memory, reducing independent transposition processing steps, reducing transposition power consumption and operation latency, avoiding the decrease in bus bandwidth utilization caused by transposition, and reducing hardware resource overhead. The dynamic partitioning strategy confines unaligned access to the first data block, improving overall bandwidth utilization. By separating the transposition operation from the computing unit and completing the transposition synchronously during data transfer, computing resources are released, reducing computation cycles and power consumption. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0124] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A near- store DMA data transpose controller, comprising: The near-memory DMA data transposition controller is arranged on a data transmission path between a far-end memory and a near-end memory of an AI computing chip, and includes a first DMA control module and a second DMA control module. The first DMA control module is configured to read, based on first command configuration information and a preset dynamic splitting strategy, a plurality of first data blocks of first data to be converted, which are split by row index on a first target splitting dimension, from the far-end memory, and write each of the first data blocks into a spare memory area of the near-end memory; read each of the first data blocks from the spare memory area of the near-end memory, and write, after performing a shift and reorganization operation on each of the first data blocks based on a preset first transposition condition, each of the first data blocks into a first target storage area of the near-end memory; the first DMA control module includes a block reading control module and a first reshaping module; the manner of reading each of the first data blocks from the spare memory area of the near-end memory, and writing, after performing a shift and reorganization operation on each of the first data blocks based on a preset first transposition condition, each of the first data blocks into a first target storage area of the near-end memory includes that the block reading control module is configured to generate a plurality of first reading operation control signals according to usage information of each of the spare memory areas; read the first data blocks of different row indexes from each of the spare memory areas according to each of the first reading operation control signals; and the first reshaping module is configured to perform a shift operation on the first data blocks of different row indexes that are read to obtain a plurality of third data blocks; perform a reorganization operation on each of the third data blocks according to a preset first transposition condition to obtain each row of data of a first target data set, and write each row of data of the first target data set into a corresponding first target storage area of the near-end memory; The second DMA control module is configured to read, based on second command configuration information and a preset dynamic splitting strategy, a plurality of second data blocks of second data to be converted, which are split by row index on a second target splitting dimension, from the near-end memory; and write, after performing a shift and reorganization operation on each of the second data blocks based on a preset second transposition condition, each of the second data blocks into a second target storage area of the far-end memory.

2. The near copy DMA data transpose controller of claim 1, wherein, The first DMA control module further includes a first command general control module, a first transmission splitting module, a block space identification module, and a block writing operation construction module; the near-end memory is provided with a plurality of spare memory areas, and each of the spare memory areas is configured to store a plurality of first data blocks of the same row index; and the manner of reading, based on first command configuration information and a preset dynamic splitting strategy, a plurality of first data blocks of first data to be converted, which are split by row index on a first target splitting dimension, from the far-end memory, and writing each of the first data blocks into a spare memory area of the near-end memory includes that the first command general control module is configured to generate a plurality of first reading operation control signals according to usage information of each of the spare memory areas; read the first data blocks of different row indexes from each of the spare memory areas according to each of the first reading operation control signals; and the first transmission splitting module is configured to perform a splitting operation on each of the first data blocks to obtain a plurality of first data blocks of different row indexes, and write each of the first data blocks of different row indexes into a corresponding spare memory area of the near-end memory. The first command total control module is configured to receive first command configuration information, which includes dimension size parameter information and address parameter information of first data to be converted. The first transmission segmentation module is configured to generate a plurality of bus read operation requests conforming to a bus protocol according to the dimension size parameter information and the address parameter information of the first data to be converted and based on a preset dynamic segmentation strategy; determine priorities of the bus read operation requests; and send the bus read operation requests according to the priorities to read a plurality of first data blocks of the first data to be converted segmented row by row on a first target segmentation dimension from the remote memory. The block space identification module is configured to record usage information of each of the spare memory areas. The block write operation construction module is configured to receive each of the first data blocks read from the remote memory, generate a plurality of write operation control signals according to the usage information of each of the spare memory areas, and write each of the first data blocks into a corresponding spare memory area of the near-end memory according to each of the write operation control signals.

3. The near copy DMA data transpose controller of claim 1, wherein, The second DMA control module includes a second command total control module, a source information generation module, and a block read operation construction module; and the manner of reading a plurality of second data blocks of second data to be converted segmented row by row on a second target segmentation dimension from the near-end memory based on second command configuration information and a preset dynamic segmentation strategy includes: The second command total control module is configured to receive second command configuration information, which includes dimension size parameter information and address parameter information of second data to be converted. The source information generation module is configured to generate row index information of the second data to be converted on the second target segmentation dimension and starting address information corresponding to each row index of the second data to be converted on the second target segmentation dimension according to the dimension size parameter information and the address parameter information of the second data to be converted. The block read operation construction module is configured to generate a plurality of second read operation control signals according to the row index information of the second data to be converted on the second target segmentation dimension and the starting address information corresponding to each row index of the second data to be converted on the second target segmentation dimension and based on a preset dynamic segmentation strategy, and read a plurality of second data blocks of the second data to be converted segmented row by row on the second target segmentation dimension from the near-end memory according to each of the second read operation control signals.

4. The near copy DMA data transpose controller of claim 1, wherein, The second DMA control module includes a second remodeling module and a bus write data construction module; and the manner of writing each of the second data blocks into a second target storage area of the remote memory after a shift and reorganization operation based on a preset second transposition condition includes: The second reshaping module is configured to perform a shift operation on the read second data blocks of different row indexes to obtain a plurality of fourth data blocks, perform a reorganization operation on each of the fourth data blocks according to a preset second transposition condition to obtain row data of a second target data set, and send the row data of the second target data set to the bus write data construction module; The bus write data construction module is configured to perform a byte bit shift operation on the row data of the second target data set based on a target address offset, and write the row data of the second target data set into a corresponding second target storage area of the remote memory.

5. The near-memory DMA data transpose controller of claim 3, wherein, The second DMA control module further includes a second transmission segmentation module configured to generate a plurality of bus write operation requests conforming to a bus protocol according to dimension size parameter information and address parameter information of the second to-be-converted data.

6. The near-memory DMA data transpose controller of claim 1, wherein, The preset dynamic segmentation strategy includes: (1) When segmentation progress information of each row index in the target segmentation dimension of the to-be-converted data is not recorded, performing row-by-row segmentation on the to-be-converted data in the target segmentation dimension in ascending order of the row index; (2) When the segmentation progress information of each row index in the target segmentation dimension of the to-be-converted data is recorded, selecting a row index with the smallest segmented data amount for priority segmentation.

7. A data transposing method characterized by, The near-memory DMA data transposition controller is arranged on a data transmission path between a remote memory and a near-memory of an AI computing chip, and includes a first DMA control module and a second DMA control module. The data transposition method includes: The first DMA control module reads, based on first command configuration information and a preset dynamic segmentation strategy, a plurality of first data blocks obtained by performing row-by-row segmentation on first to-be-converted data in a first target segmentation dimension from the remote memory, and writes each of the first data blocks into a spare memory area of the near-memory; reads each of the first data blocks from the spare memory area of the near-memory, and writes each of the first data blocks into a first target storage area of the near-memory after performing a shift and reorganization operation on each of the first data blocks based on a preset first transposition condition; The second DMA control module reads, based on second command configuration information and a preset dynamic segmentation strategy, a plurality of second data blocks obtained by performing row-by-row segmentation on second to-be-converted data in a second target segmentation dimension from the near-memory; writes each of the second data blocks into a second target storage area of the remote memory after performing a shift and reorganization operation on each of the second data blocks based on a preset second transposition condition.

8. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by a processor to implement the data transposition method of claim 7.

9. A computer program product, characterised in that, The computer program product includes computer program code, which, when executed on a computer, causes the computer to implement the data transposition method of claim 7.

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