Synchronization circuit and chip

Abstract

The invention relates to a synchronous circuit and a chip. The synchronous circuit comprises a cache module; a storage module; the write control module is used for determining write address information according to the write command and generating a trigger signal under the condition that the write address information is an address in the cache module; the synchronous control module is used for determining a current count value according to the trigger signal and the write address information, and adding one to the current count value and generating a first synchronous enable signal under the condition that the current count value is smaller than a time threshold value, resetting the current count value and generating a second synchronization enable signal under the condition that the current count value is equal to the time threshold value; and the write control module is also used for writing the write data into an address corresponding to the cache module according to the first synchronous enable signal and the write address information and / or writing the write data into the storage module according to the second synchronous enable signal and the write address information. The dynamic power consumption can be reduced, and the bandwidth utilization rate and the data access efficiency can be improved.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a synchronization circuit and a chip. Background Art

[0002] With the continuous advancement of storage technology, the requirements for data access speed are increasing. The synchronization circuit in the related technology stores all data in the memory unit. The access end may only need to frequently access a small part of it in a short period of time. At this time, this small part of data is stored in a cache unit that is closer to the access source to speed up the access end to access the data. However, in order to ensure data consistency, it is necessary to set a synchronization controller to refresh the latest value back to the memory unit once every period of time.

[0003] The write controller in the synchronous circuit can choose to write to the cache unit or the memory unit. The read controller in the synchronous circuit queries the bitmap to obtain whether the corresponding cache unit is valid. If it is valid, the cache unit is read. If it is invalid, the memory unit is read. When the result of reading the memory unit is returned, the result is written to the cache unit and the corresponding position of the bitmap is set to valid. The synchronous controller in the synchronous circuit controls the count of the counter according to whether the corresponding position of the bitmap is valid. After the count value reaches the preset time threshold, the cache unit is read, the count value is cleared, and the corresponding position of the bitmap is set to invalid, and the result is written to the memory unit. When the write controller writes the memory unit, the corresponding position of the bitmap is set to invalid.

[0004] Based on the above, it can be known that the synchronization circuit in the related art controls whether data is written into the cache unit or the memory unit through counter timing. When the bitmap is valid, the counter is always flipping, and the dynamic power consumption is very high. In addition, if the preset threshold of the counter is set to a small value, the data will be updated to the memory unit before the next use, and the content in the memory unit is the latest. If you want to obtain the latest value, you need to read the memory unit again, which wastes the access bandwidth and has low access efficiency. Summary of the invention

[0005] Based on this, it is necessary to provide a synchronization circuit and chip that reduces dynamic power consumption and improves bandwidth utilization and data access efficiency.

[0006] In a first aspect, an embodiment of the present application provides a synchronization circuit, including:

[0007] Cache module, used to store data;

[0008] A storage module, used for storing data;

[0009] A write control module, configured to determine write address information according to a received write command, and to generate a trigger signal when the write address information is an address in the cache module;

[0010] a synchronization control module, configured to determine a current count value according to the trigger signal and the write address information, and to increase the current count value by one to obtain a processed count value and generate a first synchronization enable signal when the current count value is less than a number threshold value, and to reset the current count value to obtain a processed count value and generate a second synchronization enable signal when the current count value is equal to the number threshold value;

[0011] The write control module is also used to write the write data corresponding to the write command into the address corresponding to the cache module according to the first synchronization enable signal and the write address information and / or write the write data corresponding to the write command into the storage module according to the second synchronization enable signal and the write address information.

[0012] In one embodiment, the synchronization control module includes:

[0013] a storage unit, used to store a current count value of cache data at a corresponding address of the cache module, and output the current count value according to the trigger signal;

[0014] A comparator, used to determine whether the current count value is less than a number threshold value, and if so, generate a first synchronization enable signal, otherwise generate a second synchronization enable signal, and reset the current count value in the storage unit;

[0015] An adder, used for adding one to the current count value to obtain a processed count value;

[0016] The multiplexer is used to write the count value after the addition process into the corresponding address of the storage unit, or write the count value after the reset process into the corresponding address of the storage unit.

[0017] In one embodiment, the synchronization circuit further includes a bitmap,

[0018] The bitmap is used to store identification information of whether the storage data at the corresponding address of the cache module is valid;

[0019] The write control module is further configured to write the write data corresponding to the write command into the storage module when the write address information is an address in the storage module;

[0020] The write control module is further used to set the identification information corresponding to the write address information in the bitmap to be invalid.

[0021] In one embodiment, the synchronization circuit further includes a read control module.

[0022] The read control module is used to determine the read address information according to the received read command, and when the read address information is the storage address in the cache module, read the identification information at the corresponding address in the bitmap, and when it is determined that the identification information indicates that the storage data is valid, read the data from the read address of the cache module, and when it is determined that the identification information indicates that the storage data is invalid, read the data from the read address of the storage module.

[0023] In one of the embodiments, the write control module is further used to write the data read from the read address of the storage module into the corresponding address of the cache module, and set the identification information corresponding to the write address information in the bitmap to be valid.

[0024] In one of the embodiments, the read control module is further configured to generate a read response after reading the data, wherein the read response includes the data read by the read control module.

[0025] In one embodiment, the synchronization circuit further includes a decoding module.

[0026] The decoding module is used to receive and parse data access commands. When the data access command is a write command, the write address information and write data corresponding to the write command are sent to the write control module. When the data access command is a read command, the read address information corresponding to the read command is sent to the read control module.

[0027] In one embodiment, the synchronization circuit also includes an access interface, which is connected to the write control module, the read control module, and the storage module respectively, and the access interface is used to convert the write command and / or the read command into an interface signal to access the storage module.

[0028] In one of the embodiments, the synchronization control module is further configured to receive and store the number threshold value.

[0029] In a second aspect, an embodiment of the present application provides a chip, characterized in that it includes a synchronization circuit as described above.

[0030] The above-mentioned synchronization circuit and chip receive a write command through a write control module, and generate a trigger signal when the write address information of the write command is an address in the cache module. The synchronization control module determines the current count value according to the trigger signal and the write address information, and compares the current count value with the number threshold value. If the current count value is less than the number threshold value, in this case, the current count value is added by one to obtain the processed count value and generate a first synchronization enable signal. If the current count value is equal to the number threshold value, in this case, the current count value is reset to obtain the processed count value and generate a second synchronization enable signal. The write control module writes the write data corresponding to the write command to the address corresponding to the cache module according to the first synchronization enable signal and the write address information and / or writes the write data corresponding to the write command to the storage module according to the second synchronization enable signal and the write address information. The present application counts only when the write control module performs a write operation on the cache module, and there is no need to always keep the count flipping, which reduces dynamic power consumption, and only when the current count value reaches the count threshold value will a write back to the memory module be generated, which can significantly reduce the number of bus accesses, thereby improving bandwidth utilization and data access efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] FIG1 is a schematic diagram of the structure of a synchronous controller;

[0033] FIG2 is a schematic diagram of the structure of a synchronization circuit provided by an embodiment;

[0034] FIG3 is a schematic diagram of the structure of a synchronization control module provided by an embodiment;

[0035] FIG4 is a schematic diagram of the structure of a cache module, a bitmap and a storage unit provided by an embodiment;

[0036] FIG5 is a schematic diagram of the structure of a chip provided by an embodiment.

[0037] Description of reference numerals:

[0038] 10 - cache module, 20 - storage module, 30 - write control module, 40 - synchronization control module, 410 - storage unit, 420 - comparator, 430 - adder, 440 - multiplexer, 50 - bitmap, 60 - read control module, 70 - access interface, 80 - decoding module, 100 - synchronization circuit. DETAILED DESCRIPTION

[0039] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0041] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element. For example, without departing from the scope of this application, a cache module may be referred to as a storage module, and similarly, a storage module may be referred to as a cache module. Both a cache module and a storage module are storage modules, but they are not the same storage module.

[0042] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0043] It is understood that "at least one" means one or more, and "plurality" means two or more. "At least part of an element" means part or all of an element. When used herein, the singular forms "one", "an" and "said / the" may also include plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0044] As mentioned in the background technology, in order to ensure data consistency between the cache and the memory, data synchronization operations must be performed regularly. In the related art, the synchronization controller uses a counter to time the data storage time in the cache, and when the time threshold is reached, the data in the cache is refreshed back to the memory. As can be seen from the structure shown in Figure 1, the synchronization controller implements timing through a counter. When the data in the cache is valid, the counter is always flipping, and the dynamic power consumption is very high. In addition, if the preset time threshold is set to a small value, the data will be updated to the memory before the next use, and the content in the memory is the latest. If you want to obtain the latest value, you need to read the memory again, which wastes the access bandwidth and has low access efficiency.

[0045] The present application provides a synchronization circuit and chip, which performs data synchronization operations when the number of write operations on the cache module reaches a number threshold, that is, adopts the number threshold control logic, reduces dynamic power consumption, and reduces the number of write-backs to a certain extent, thereby improving bandwidth utilization and data access efficiency.

[0046] In one embodiment, as shown in FIG2 , a synchronization circuit is provided. The synchronization circuit includes a cache module 10, a storage module 20, a write control module 30 and a synchronization control module 40. Among them, the cache module 10 is used to store data. The storage module 20 is used to store data. In an embodiment of the present application, the cache module 10 has no refresh requirement, and the storage module 20 has a refresh requirement. Exemplarily, the cache module 10 can be an SRAM (Static Random-Access Memory) or a register, and the storage module 20 can be a DDR (Double Data Rate Synchronous Dynamic Random Access Memory).

[0047] The write control module 30 is connected to the cache module 10 and the storage module 20 respectively. The write control module 30 is used to determine the write address information according to the received write command, and generate a trigger signal when the write address information is the address in the cache module 10. The write address information is used to indicate the write position of the write data corresponding to the write command, and the write address information includes the address of the cache module 10 or the address of the storage module 20. The trigger signal is used to trigger the synchronization control module 40 to determine whether to perform a data synchronization operation.

[0048] The synchronization control module 40 is connected to the write control module 30. The synchronization control module 40 is used to determine the current count value according to the trigger signal and the write address information, and when the current count value is less than the number threshold value, the current count value is increased by one to obtain the processed count value and generate the first synchronization enable signal, and when the current count value is equal to the number threshold value, the current count value is reset to obtain the processed count value and generate the second synchronization enable signal. Among them, the current count value is used to indicate the number of times the write control module 30 currently performs write operations on the addresses in the cache module 10, and each count value corresponds to an address in the storage module 20. Exemplarily, taking address 0 of the cache module 10 as an example, the current count value corresponding to address 0 is 3, which means that the write control module 30 currently performs write operations on address 0 of the cache module 10 for 3 times. The number threshold value is a preset value, which can be set accordingly according to the synchronization requirements of the internal synchronization circuit. For example, the number threshold can be 5, 10, 20 or other suitable values, which are not limited too much here. Among them, when the current count value is equal to the number threshold, the synchronization control module 40 resets the current count value, which can be understood as resetting the current count value to a reset value, or an initial value, wherein the reset value is pre-set and the reset value is less than the number threshold value, for example, the reset value is set to 0, and the reset value can also be other values ​​such as 1, 2, etc., which are not limited here.

[0049] The write control module 30 is also used to write the write data corresponding to the write command into the address corresponding to the cache module 10 according to the first synchronization enable signal and the write address information, and / or write the write data corresponding to the write command into the storage module 20 according to the second synchronization enable signal and the write address information.

[0050] As an example, the number threshold is 5. In the application, the write control module 30 receives a write command, and the write address information determined according to the write command is address 0 in the cache module 10, and a trigger signal is generated; if the synchronization control module 40 determines that the current count value corresponding to address 0 is 3 and is less than the number threshold value 5 according to the trigger signal and the write address information, the current count value 3 is added by one to obtain the processed count value 4 and a first synchronization enable signal is generated, and the write control module 30 writes the write data corresponding to the write command to the address 0 corresponding to the cache module 10 according to the first synchronization enable signal and the write address information; if the synchronization control module 40 determines that the current count value corresponding to address 0 is 5 and is equal to the number threshold value 5 according to the trigger signal and the write address information, the current count value 5 is reset to obtain the processed count value 0, and a second synchronization enable signal is generated, and the write control module 30 writes the write data corresponding to the write command to the address 0 of the storage module 20 according to the second synchronization enable signal and the write address information.

[0051] The above-mentioned synchronization circuit receives a write command through the write control module 30. When the write address information of the write command is the address in the cache module 10, it indicates that the purpose of the write command is to update a new value to the address in the cache module 10. In this regard, the synchronization circuit generates a trigger signal through the write control module 30 to instruct the synchronization control module 40 to determine whether to perform a data synchronization operation. Specifically, the synchronization circuit determines the current count value according to the trigger signal and the write address information through the synchronization control module 40, and compares the current count value with the number threshold value. If the current count value is less than the number threshold value, it indicates that the number of write operations of the write control module 30 on the address of the cache module 10 does not meet the data synchronization condition. In this case, the current count value is increased by one to obtain the processing The count value after the processing is obtained and a first synchronization enable signal is generated, so that the write control module 30 writes the write data corresponding to the write command to the address corresponding to the cache module according to the first synchronization enable signal and the write address information, that is, no data synchronization operation is performed; if the current count value is equal to the number threshold value, it indicates that the number of write operations of the write control module 30 on the address of the cache module 10 reaches the data synchronization condition. In this case, the current count value is reset to obtain the processed count value and a second synchronization enable signal is generated, so that the write control module 30 writes the write data corresponding to the write command to the storage module according to the second synchronization enable signal and the write address information, that is, a data synchronization operation is performed, thereby realizing automatic refresh of the storage module 20 according to the number of write operations of the cache module 10.

[0052] The synchronization circuit of this embodiment counts only when the write control module 30 performs a write operation on the cache module 10. There is no need to always keep the count flipping, which reduces dynamic power consumption. A write back to the memory module is only generated when the current count value reaches the count threshold value, which can significantly reduce the number of bus access times, thereby improving bandwidth utilization and data access efficiency.

[0053] In one embodiment, the synchronization control module 40 is also used to receive and store a number threshold value, so that the current count value can be compared with the number threshold value, so as to write data to the write cache module 10 when the current count value is less than the number threshold value, or write data to the storage module 20 when the current count value is greater than or equal to the number threshold value, thereby using the number of write operations on the cache module 10 as the threshold comparison object, thereby achieving the purpose of reducing dynamic power consumption and improving bandwidth utilization and data access efficiency.

[0054] In one embodiment, as shown in FIG. 3 , the synchronization control module 40 includes a storage unit 410 , a comparator 420 , an adder 430 , and a multiplexer 440 .

[0055] Among them, the storage unit 410 is used to store the current count value of the cache data at the corresponding address of the cache module 10, and output the current count value according to the trigger signal. Exemplarily, the storage unit 410 includes a storage entity. For example, as shown in Figure 4, there are N addresses in the cache module 10, namely addr0, add1, ..., addrN, and each address in the cache module 10 stores corresponding data, for example, addr0 stores data0, addr1 stores data1, and addrN stores dataN. Correspondingly, the storage unit 410 stores the current count values ​​of N addresses in the cache module 10, for example, the current count value corresponding to addr0 is cnt_val0, the current count value corresponding to addr1 is cnt_val1, and the current count value corresponding to addrN is cnt_valN.

[0056] The comparator 420 is connected to the storage unit 410. The comparator 420 is used to determine whether the current count value is less than the number threshold value, and if so, a first synchronization enable signal is generated, otherwise a second synchronization enable signal is generated, and the current count value in the storage unit 410 is reset. In the application, the comparator 420 obtains the current count value corresponding to the write address information from the storage unit 410 according to the trigger signal and the write address information, and generates a comparison result according to the current count value and the number threshold value, and generates a first synchronization enable signal when the comparison result is that the current count value is less than the number threshold value, and generates a second synchronization enable signal when the comparison result is that the current count value is equal to the number threshold value. The number threshold value is stored in the comparator 420.

[0057] The adder 430 is used to add one to the current count value to obtain a processed count value when the comparison result shows that the current count value is less than the number threshold value. In the application, the adder 430 can obtain the current count value corresponding to the write address information from the storage unit 410 according to the trigger signal and the write address information, and add one to the current count value to obtain the processed count value.

[0058] The multiplexer 440 is connected to the adder 430 and the comparator 420 respectively. The multiplexer 440 is used to write the count value after the adder 430 adds one to the corresponding address of the storage unit 410, or write the count value after the reset process to the corresponding address of the storage unit 410.

[0059] For example, the number threshold is 5. In the application, the write control module 30 receives a write command, and the write address information determined according to the write command is address 0 in the cache module 10, and a trigger signal is generated. If the current count value of address 0 stored in the storage unit 410 is 3, the comparator 420 compares the current count value 3 to be less than the number threshold value 5, and generates a first synchronization enable signal. The adder 430 adds one to the current count value 3 to obtain a processed count value 4, and the multiplexer 440 writes the count value 4 after adding one to the corresponding address 0 of the storage unit 410. If the current count value of address 0 stored in the storage unit 410 is 5, the comparator 420 compares the current count value 5 to be equal to the number threshold value 5, and generates a second synchronization enable signal and resets the current count value to obtain a processed count value 0. The multiplexer 440 writes the reset count value 0 to the corresponding address 0 of the storage unit 410.

[0060] The above-mentioned synchronization circuit stores the current count value of the cache data at the corresponding address of the cache module 10 through the storage unit 410, determines whether the current count value is less than the number threshold value through the comparator 420, and generates a first synchronization enable signal if it is less than the number threshold value, otherwise generates a second synchronization enable signal and resets the current count value in the storage unit 410, adds one to the current count value through the adder 430 to obtain the processed count value, and writes the added count value to the corresponding address of the storage unit 410 through the multiplexer 440, and writes the reset count value to the corresponding address of the storage unit 410, thereby realizing the counting of the number of write operations of the write control module 30 on the cache module 10, and when the current count value is equal to the number threshold value, writes the write data to the storage module 20, thereby realizing data synchronization between the cache module 10 and the storage module 20.

[0061] In one embodiment, as shown in FIG4 and FIG5, the synchronization circuit 100 further includes a bitmap 50, and the bitmap 50 is used to store identification information of whether the storage data at the corresponding address of the cache module 10 is valid. Wherein, the identification information is valid, for example, when the identification information is 1, the storage data at the corresponding address of the cache unit is valid, and the current count corresponding to the address stored in the storage unit 410 is valid; the identification information is invalid, for example, when the identification information is 0, the storage data at the corresponding address of the cache unit is invalid, and the current count corresponding to the address stored in the storage unit 410 is invalid.

[0062] For example, there are N addresses in the cache module 10, namely addr0, add1, ..., addrN, and each address of the cache module 10 stores corresponding data, for example, addr0 stores data0, addr1 stores data1, and addrN stores dataN. Correspondingly, the bitmap 50 stores identification information of whether the storage data of N addresses in the cache module 10 are valid. For example, 1 bit is used to store the identification information of whether the storage data of 1 address in the storage module 20 is valid, and the bitmap 50 includes N bits of identification information. For example, if the 0th bit of the bitmap 50, i.e., bit0, is 0, the storage data of the address addr0 in the cache module 10 is invalid, and the current count value cnt_val0 of the address addr0 stored in the storage unit 410 is invalid; if the 1st bit of the bitmap 50, i.e., bit1, is 1, the storage data of the address addr1 in the cache module 10 is valid, and the current count value cnt_val1 of the address addr1 stored in the storage unit 410 is valid.

[0063] The write control module 30 is also used to write the write data corresponding to the write command into the storage module 20 when the write address information is the address in the storage module 20, and the write control module 30 is also used to invalidate the identification information corresponding to the write address information in the bitmap 50. There is a mapping relationship between the cache module 10 and the address (referred to as address) used to store data in the storage module 20. For example, the N addresses in the cache module 10 are addr0, add1, ..., addrN, and correspondingly, the N addresses in the storage module 20 are addr0, add1, ..., addrN; wherein, addr0 of the cache module 10 corresponds to addr0 of the storage module 20, addr1 of the cache module 10 corresponds to addr1 of the storage module 20, and so on, addrN of the cache module 10 corresponds to addrN of the storage module 20. For example, when the write address information is the address addr0 in the storage module 20 , the write control module 30 writes the write data corresponding to the write command into the address addr0 in the storage module 20 , and sets the bit corresponding to the address addr0 in the bitmap 50 to 0.

[0064] The above-mentioned synchronization circuit 100 stores identification information of whether the storage data at the corresponding address of the cache module 10 is valid through the bit map 50, and writes the write data corresponding to the write command into the storage module 20 through the write control module 30 when the write address information is the address in the storage module 20, and sets the identification information corresponding to the write address information in the bit map 50 to be invalid through the write control module 30. That is, it is possible to identify whether the storage data at the corresponding address of the cache module 10 is valid through the bit map 50, and further, it is possible to identify whether the current count value stored in the storage unit 410 at the address is valid, and write the write data to the storage module 20 at the write address to set the corresponding identification information of the bit map 50 to be invalid, which is helpful for cyclic synchronization control.

[0065] In one embodiment, please continue to refer to Figure 5. The synchronization circuit 100 also includes a read control module 60, which is used to determine the read address information according to the received read command. When the read address information is a storage address in the cache module 10, the identification information at the corresponding address in the bit map 50 is read. When it is determined that the identification information indicates that the storage data is valid, the data is read from the read address of the cache module 10. When it is determined that the identification information indicates that the storage data is invalid, the data is read from the read address of the storage module 20.

[0066] If the identification information at the corresponding address in the bitmap 50 is valid, for example, when the identification information is 1, it indicates that the storage data at the corresponding address of the cache module 10 is valid. In this case, the cache module 10 can be accessed to read data from the read address of the cache module 10, which helps to improve the data reading efficiency. If the identification information at the corresponding address in the bitmap 50 is invalid, it indicates that the storage data at the corresponding address of the cache module 10 is invalid. In this case, the data can be read from the read address of the storage module 20 by accessing the storage module, thereby realizing the read operation of the synchronization circuit 100.

[0067] Please continue to refer to Figure 5. In one embodiment, the write control module 30 is also used to write the data read from the read address of the storage module 20 to the corresponding address of the cache module 10, and set the identification information corresponding to the write address information in the bitmap 50 to be valid, thereby realizing the effective storage of the read data by the cache module 10, so that when the data of the corresponding address is read again subsequently, it can be read directly from the cache module 10 without accessing the storage module 20, which helps to improve data access efficiency.

[0068] In one embodiment, please continue to refer to Figure 5. The read control module 60 is also used to generate a read response after reading the data. The read response includes the data read by the read control module 60. In this way, the data read from the synchronization circuit 100 can be fed back through the read response, thereby realizing an effective data read operation.

[0069] In one embodiment, please continue to refer to Figure 5, the synchronization circuit 100 also includes an access interface 70. Among them, the access interface 70 is connected to the write control module 30, the storage module 20, and the read control module 60 respectively. The access interface 70 is used to convert write commands and / or read commands into interface signals to access the storage module 20. The access interface 70 is pre-configured, for example, a MIPI interface, a GPIO interface, or other suitable interface types. Specifically, a suitable access interface 70 can be selected according to the specific structure of the storage module 20, and no excessive restrictions are made here. In this way, the write control module 30 and the read control module 60 can transmit data between the storage module 20 through the access interface 70, respectively, which helps to improve data access efficiency.

[0070] In one embodiment, please continue to refer to FIG. 5 , the synchronization circuit 100 further includes a decoding module 80. The decoding module 80 is used to receive and parse the data access command. When the data access command is a write command, the write address information and write data corresponding to the write command are sent to the write control module 30. When the data access command is a read command, the read address information corresponding to the read command is sent to the read control module 60. The decoding module 80 is connected to the write control module 30. Exemplarily, the decoding module 80 is also connected to the read control module 60. In this way, the synchronization circuit 100 can distinguish between read and write commands through the decoding module 80, so that the subsequent read control module 60 implements a read operation according to the read command, and the write control module 30 implements a write operation according to the write command.

[0071] Based on the same inventive concept, the embodiment of the present application also provides a chip for implementing the synchronization circuit involved above. The implementation solution provided by the chip to solve the problem is similar to the implementation solution recorded in the above synchronization circuit, so the specific limitations in one or more chip embodiments provided below can refer to the limitations on the synchronization circuit above, and will not be repeated here.

[0072] In one embodiment, please continue to refer to FIG. 5 , which provides a chip including a synchronization circuit 100. The synchronization circuit 100 can refer to the above-mentioned related description, which will not be repeated here. Exemplarily, the chip can be a DPU (Data Process Unit), etc., which is not limited here.

[0073] In one embodiment, please continue to refer to FIG. 5 for an introduction to the chip provided in the embodiment of the present application. The chip includes a synchronization circuit 100. The synchronization circuit 100 includes a cache module 10, a storage module 20, a write control module 30, a read control module 60, a bitmap 50, an access interface 70, a decoding module 80, and a synchronization control module 40. The cache module 10 is SRAM, the storage module 20 is DDR, the write control module 30 is a write controller, the read control module 60 is a read controller, the bitmap 50 is a register, and the synchronization control module 40 is a synchronization controller. The synchronization controller adopts the structure shown in FIG. 3 as an example for explanation.

[0074] The decoding module 80 is used to decode the data access command to distinguish between the read and write commands.

[0075] Each bit of the bitmap 50 records whether the storage data at each address in the cache module 10 is valid, 0 for invalid, 1 for valid, and all 0s after reset. When reading data from the storage module 20 and writing it to the cache module 10, the corresponding bit position of the bitmap 50 is set to 1, and when writing data to the storage module 20, the corresponding bit position of the bitmap 50 is set to 0.

[0076] The write control module 30 is respectively connected to the decoding module 80, the bitmap 50, the cache module 10, and the access interface 70. The write control module 30 is used to parse the write command to select whether to write to the cache module 10 or the storage module 20. If the write control module 30 parses that the storage module 20 needs to be written, the control logic of the synchronization control module 40 is not considered. In addition, when writing to the storage module 20, the corresponding bitmap is set to 0.

[0077] The read control module 60 is respectively connected to the decoding module 80, the bitmap 50, the cache module 10, and the access interface 70. The read control module 60 is used to obtain the bit corresponding to the bitmap 50 according to the read command, and select whether to read the cache module 10 or the storage module 20. If the bit corresponding to the bitmap 50 is 1, the cache module 10 is read, and if it is 0, the storage module 20 is read. When the result of reading the storage module 20 is returned, the result is written to the cache module 10, and the bit position corresponding to the bitmap 50 is updated to 1 when writing.

[0078] The access interface 70 is used to convert read and write commands into interface signals to access the storage module 20 .

[0079] The synchronization control module 40 is used to record how many times each valid data in the cache module 10 is updated. When the count value is less than the number threshold, the cache module 10 is written, and when the count value is equal to the number threshold, the storage module 20 is written. As shown in FIG3 , the synchronization control module 40 includes a storage unit 410, a comparator 420, an adder 430, and a multiplexer 440.

[0080] The above chip only counts when the write control module 30 performs a write operation on the cache module 10. There is no need to always keep the count flipping, which reduces dynamic power consumption. Only when the current count value reaches the count threshold value will a write back to the storage module 20 be generated, which can significantly reduce the number of bus access times, thereby improving bandwidth utilization and data access efficiency.

[0081] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0082] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0083] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A synchronous circuit, characterized in that: include: Cache module, used to store data; A storage module, used for storing data; A write control module, configured to determine write address information according to a received write command, and to generate a trigger signal when the write address information is an address in the cache module; a synchronization control module, configured to determine a current count value according to the trigger signal and the write address information, and to increase the current count value by one to obtain a processed count value and generate a first synchronization enable signal when the current count value is less than a number threshold value, and to reset the current count value to obtain a processed count value and generate a second synchronization enable signal when the current count value is equal to the number threshold value; The write control module is also used to write the write data corresponding to the write command into the address corresponding to the cache module according to the first synchronization enable signal and the write address information and / or write the write data corresponding to the write command into the storage module according to the second synchronization enable signal and the write address information.

2. The synchronization circuit according to claim 1, characterized in that: The synchronization control module comprises: a storage unit, used to store a current count value of cache data at a corresponding address of the cache module, and output the current count value according to the trigger signal; A comparator, used to determine whether the current count value is less than a number threshold value, and if so, generate a first synchronization enable signal, otherwise generate a second synchronization enable signal, and reset the current count value in the storage unit; An adder, used for adding one to the current count value to obtain a processed count value; The multiplexer is used to write the count value after the addition process into the corresponding address of the storage unit, or write the count value after the reset process into the corresponding address of the storage unit.

3. The synchronization circuit according to claim 2, characterized in that: The synchronization circuit also includes a bitmap, The bitmap is used to store identification information of whether the storage data at the corresponding address of the cache module is valid; The write control module is further configured to write the write data corresponding to the write command into the storage module when the write address information is an address in the storage module; The write control module is further used to set the identification information corresponding to the write address information in the bitmap to be invalid.

4. The synchronization circuit according to claim 3, characterized in that: The synchronization circuit also includes a read control module, The read control module is used to determine the read address information according to the received read command, and when the read address information is the storage address in the cache module, read the identification information at the corresponding address in the bitmap, and when it is determined that the identification information indicates that the storage data is valid, read the data from the read address of the cache module, and when it is determined that the identification information indicates that the storage data is invalid, read the data from the read address of the storage module.

5. The synchronization circuit according to claim 4, characterized in that: The write control module is further used to write the data read from the read address of the storage module into the corresponding address of the cache module, and to set the identification information corresponding to the write address information in the bitmap to be valid.

6. The synchronization circuit according to claim 4, characterized in that: The read control module is further configured to generate a read response after reading the data, wherein the read response includes the data read by the read control module.

7. The synchronization circuit according to claim 4, characterized in that: The synchronization circuit also includes a decoding module, The decoding module is used to receive and parse data access commands. When the data access command is a write command, the write address information and write data corresponding to the write command are sent to the write control module. When the data access command is a read command, the read address information corresponding to the read command is sent to the read control module.

8. The synchronization circuit according to claim 4, characterized in that: The synchronization circuit also includes an access interface, which is connected to the write control module, the read control module, and the storage module respectively, and is used to convert the write command and / or the read command into an interface signal to access the storage module.

9. The synchronization circuit according to claim 1, characterized in that: The synchronization control module is also used to receive and store the number threshold value.

10. A chip, characterized in that: Comprising a synchronization circuit as described in any one of claims 1-9.

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