Selective deposition of masks for reduced nanosheet loss

Abstract

The present application provides selective deposition of a mask for reducing nanosheet loss. A method includes forming a protruding fin, forming a composite dielectric layer including a first dielectric layer and a second dielectric layer over the first dielectric layer. The first dielectric layer includes a first top portion on a top surface of the protruding fin and sidewall portions on sidewalls of the protruding fin. A second dielectric layer is over the first top portion and a top surface of the protruding fin, and is formed using an anisotropic deposition process. The method further includes forming a dummy gate electrode on the second dielectric layer, forming a gate spacer on a sidewall of the dummy gate electrode; removing the dummy gate electrode; and forming a replacement gate electrode in a space left by the dummy gate electrode.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly to selective deposition of a mask for reducing nanosheet loss. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers on a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be solved. Summary of the invention

[0004] According to one aspect of the present application, a method is provided, comprising: forming a protruding fin; forming a first dielectric layer, the first dielectric layer comprising: a first top portion located on a top surface of the protruding fin; and a first sidewall portion located on a sidewall of the protruding fin; forming a second dielectric layer on the first top portion of the first dielectric layer and above the top surface of the protruding fin, wherein the second dielectric layer is formed using an anisotropic deposition process; forming a dummy gate electrode on the second dielectric layer; forming a gate spacer on the sidewall of the dummy gate electrode; removing the dummy gate electrode; and forming a replacement gate electrode in the space left by the dummy gate electrode.

[0005] According to another aspect of the present application, a structure is provided, comprising: a dielectric isolation region; a plurality of semiconductor nanostructures located next to and above the dielectric isolation region, wherein a higher semiconductor nanostructure among the plurality of semiconductor nanostructures overlies a corresponding lower semiconductor nanostructure among the plurality of semiconductor nanostructures; a gate stack, comprising: a first portion located above a top nanostructure of the plurality of semiconductor nanostructures; and a second portion located between adjacent semiconductor nanostructures among the plurality of semiconductor nanostructures, wherein the second portion of the gate stack and the plurality of semiconductor nanostructures are interconnected to form a protruding fin; a first dielectric layer located on a top surface and sidewalls of the protruding fin; a second dielectric layer comprising a first portion above the first dielectric layer, wherein the first dielectric layer is more conformal than the second dielectric layer, and wherein at least a top portion of the first portion is higher than a top nanostructure among the plurality of semiconductor nanostructures; and a gate spacer above the second dielectric layer.

[0006] According to another aspect of the present application, a structure is provided, including: a semiconductor substrate; a first dielectric isolation region and a second dielectric isolation region located in the semiconductor substrate; a protruding fin located between the first dielectric isolation region and the second dielectric region and higher than the first dielectric isolation region and the second dielectric region; a first dielectric layer located on the top surface and sidewalls of the protruding fin; a second dielectric layer above the first dielectric layer, the second dielectric layer including: a first portion overlying the protruding fin; and a second portion overlying the first dielectric isolation region, wherein the first portion and the second portion are discrete portions of the second dielectric layer; and a gate spacer above the second dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figures 1 to 3 , Figure 4A , Figure 4B , Figure 5 , Fig. 6A , Figure 6B , Figure 6C , Figure 7 , Fig. 8A , Figure 8B , Figure 8C , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 11C , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig. 15C and Fig.15D A view of an intermediate stage in forming a gate all around (GAA) transistor is shown in accordance with some embodiments.

[0009] Fig.16 A process flow for forming a GAA transistor is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0011] Additionally, spatially relative terms (e.g., "below," "beneath," "lower," "above," "higher," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in a figure relative to another element(s) or feature(s). These spatially relative terms are also intended to encompass different orientations of the device in use or operation in addition to the orientation illustrated in the figures. The device may be oriented in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0012] A gate-all-around (GAA) transistor with reduced top semiconductor nanostructure loss and reduced shallow trench isolation (STI) regional loss and a corresponding method are provided. According to some embodiments, a first dielectric layer is formed on a protruding fin using a conformal deposition process. A second dielectric layer is formed on the first dielectric layer using an anisotropic deposition process. The second dielectric layer is used as a hard mask and is located on the top surface of the protruding fin, but may not be located on the sidewalls of the protruding fin. Therefore, a second dielectric layer with a thicker top can be formed to provide better protection without occupying the space between adjacent protruding fins. It should be understood that although GAA transistors are used as examples, other types of transistors (e.g., fin field effect transistors (FinFETs)) may also employ embodiments of the present disclosure.

[0013] The purpose of the embodiments discussed herein is to provide examples to enable the subject matter of the present disclosure to be made or used, and those of ordinary skill in the art will readily appreciate the modifications that can be made while remaining within the intended scope of the different embodiments. In the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although the method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0014] Figures 1 to 3 , Figure 4A , Figure 4B , Figure 5 , Fig. 6A , Figure 6B , Figure 6C , Figure 7 , Fig. 8A , Figure 8B , Figure 8C , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 11C , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig. 15C and Fig.15D 1 shows a view of an intermediate stage when forming a GAA transistor according to some embodiments. The corresponding process is also schematically reflected in Fig.16 The process flow is shown.

[0015] refer to Figure 1 , a perspective view of a wafer 10 including a substrate 20 is shown. A multilayer structure including a multilayer stack 22 is formed on the substrate 20. According to some embodiments, the substrate 20 is (or includes) a semiconductor substrate, which may be a silicon substrate, a silicon germanium (SiGe) substrate, etc., but other substrates and / or structures may be used, for example, semiconductor on insulator (SOI), strained SOI, silicon germanium on insulator, etc. The substrate 20 may be doped as a p-type semiconductor, but in other embodiments, it may be doped as an n-type semiconductor.

[0016] According to some embodiments, the multilayer stack 22 is formed by a series of epitaxial processes for depositing alternating materials. The corresponding processes are Fig.16 The process flow 200 is shown as process 202. According to some embodiments, the multilayer stack 22 includes a first layer 22A and a second layer 22B, wherein the first layer 22A is formed of a first semiconductor material and the second layer 22B is formed of a second semiconductor material different from the first semiconductor material. Because of epitaxy, the first layer 22A and the second layer 22B have the same lattice direction as the substrate 20.

[0017] According to some embodiments, the first semiconductor material of the first layer 22A is formed of or includes the following: SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, etc. According to some embodiments, the deposition of the first layer 22A (e.g., SiGe) is by epitaxial growth, and the corresponding deposition method may be vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), etc.

[0018] Once the first layer 22A has been deposited on the substrate 20, the second layer 22B is deposited on the first layer 22A. According to some embodiments, the second layer 22B is formed of or includes a second semiconductor material, such as Si, SiGe, Ge, GaAs, InSb, GasB, InAlAs, InGaAs, GasB, GaAsSB, and combinations thereof, and the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments in which the first layer 22A is silicon germanium, the second layer 22B can be formed of silicon, and vice versa. It should be understood that any suitable material combination can be used for the first layer 22A and the second layer 22B.

[0019] According to some embodiments, the second layer 22B is epitaxially grown on the first layer 22A using a deposition technique similar to that used to form the first layer 22A. According to some embodiments, the second layer 22B is formed to a similar thickness as the first layer 22A. The second layer 22B may also be formed to a different thickness than the first layer 22A.

[0020] According to some embodiments, the first layer 22A is removed in a subsequent process and is alternatively referred to as sacrificial layer 22A throughout the specification. According to an alternative embodiment, the second layer 22B is sacrificial and removed in a subsequent process.

[0021] According to some embodiments, a pad oxide layer 12 and a hard mask layer 14 are formed over the multilayer stack 22. The pad oxide layer 12 may include silicon oxide, silicon carbide, etc., while the hard mask layer 14 may include silicon nitride, and other materials may be used. The pad oxide layer 12 and the hard mask layer 14 are patterned to form a plurality of elongated strips, which are also referred to as pad oxide and hard mask.

[0022] refer to Figure 2, the multilayer stack 22 and a portion of the underlying substrate 20 are patterned in an etching process(es) such that a trench (filled by the isolation region 26) is formed. The trench extends into the substrate 20. The remaining portion of the multilayer stack is hereinafter referred to as the multilayer stack 22'. The corresponding process is Fig.16 The process flow 200 is shown as process 204. The underlying multilayer stack 22', some portions of the substrate 20 are left, and are referred to as substrate strip 20' hereinafter. The multilayer stack 22' includes a semiconductor layer 22A and a semiconductor layer 22B. The semiconductor layer 22A is alternatively referred to as a sacrificial layer, and the semiconductor layer 22B is alternatively referred to as a nanostructure hereinafter. The multilayer stack 22' and the portions of the underlying substrate strip 20' are collectively referred to as semiconductor strip 24.

[0023] In the above-described embodiments, the GAA transistor structure can be patterned by any suitable method. For example, one or more photolithography processes (including double patterning processes or multi-patterning processes) can be used to pattern these structures. Typically, a double patterning process or a multi-patterning process combines a photolithography process with a self-alignment process, thereby allowing the generation of patterns with, for example, a spacing smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0024] Next, the isolation region 26 is formed, which may also be referred to as a shallow trench isolation (STI) region throughout the specification. Fig.16 The process flow 200 is shown as process 206. The STI region 26 may include a liner oxide (not shown), which may be a thermal oxide formed by thermally oxidizing a surface layer of the substrate 20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, ALD, high density plasma chemical vapor deposition (HDPCVD), CVD, etc. The STI region 26 may also include a dielectric material on top of the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, HDPVCD, etc. A planarization process (e.g., a chemical mechanical polishing (CMP) process or a mechanical grinding process) may then be performed to make the top surface of the dielectric material, for example, flush with the top surface of the hard mask layer 14, and the remaining portion of the dielectric material is the STI region 26.

[0025] Further references Figure 3, the STI region 26 is recessed so that the top portion of the semiconductor strip 24 protrudes higher than the top surface 26T of the remaining portion of the STI region 26 to form a protruding fin (structure) 28 (also called a nanosheet). The corresponding process is Fig.16 The process flow 200 is shown as process 208. The protruding fin 28 includes some top portions of the substrate strip 20' and the multilayer stack 22'. The recessing of the STI region 26 can be performed by a dry etching process, wherein, for example, NF3 and NH3 are used as etching gases. During the etching process, a plasma can be generated. Argon gas can also be included. According to an alternative embodiment of the present disclosure, the recessing of the STI region 26 is performed by a wet etching process. For example, the etching chemical can include HF. The pad oxide layer 12 and the hard mask 14 are removed.

[0026] refer to Figure 4A and Figure 4B , a composite dielectric layer 32 including a dielectric layer 32A and a dielectric layer 32B is formed. The corresponding process is Fig.16 This is shown in the illustrated process flow 200 as process 210 . A dielectric layer 32A is deposited on the sidewalls and top surfaces of the protruding fins 28 and on the top surfaces of the STI regions 26 . Figure 4A shows a perspective view, Figure 4B Shows Figure 4A Vertical cross section 4B-4B is shown in FIG.

[0027] According to some embodiments, dielectric layer 32A is a single (homogeneous) layer, and the entire dielectric layer 32A is formed of the same material and has the same composition. Throughout the specification, when two layers are referred to as having the same composition, it means that the two layers have the same elements, and the percentages of the corresponding elements in the two layers are the same as each other. Conversely, when two layers are referred to as having different compositions, it means that at least one of the two layers has at least one element that is not in the other layer, or the two layers have the same elements but the percentages of the elements in the two layers are different from each other. According to an alternative embodiment, dielectric layer 32A is a composite layer including two or more sublayers.

[0028] According to some embodiments, dielectric layer 32A is formed using a conformal deposition process such that a vertical portion (also referred to as a sidewall portion) and a horizontal portion (also referred to as a top portion) of dielectric layer 32A have the same thickness, for example, with a variation of about 20%, less than about 10%, or less. The formation is performed by a conformal formation process (e.g., ALD, CVD, etc.). The material of dielectric layer 32A may include an oxide, for example, silicon oxide, silicon oxynitride, silicon oxycarbide, etc.

[0029] A dielectric layer 32B is then deposited on dielectric layer 32A using a non-conformal deposition process (also referred to as an anisotropic deposition process). Dielectric layer 32A and dielectric layer 32B are collectively referred to as composite dielectric layer 32 hereinafter. Dielectric layer 32B is also referred to as a hard mask layer because it prevents unwanted etching in subsequent dummy gate patterning and cleaning processes. Figure 4A and Figure 4B As shown, dielectric layer 32B may include horizontal portions over the top surfaces of protruding fins 28 and STI regions 26. Dielectric layer 32B may have no or substantially no vertical portions on the sidewalls of protruding fins 28.

[0030] According to alternative embodiments, dielectric layer 32B may include vertical portions on the sidewalls of protruding fins 28. However, thickness T2 of the vertical portions is significantly less than thickness T1 of the horizontal portions. For example, ratio T2 / T1 may be less than about 0.2 or less than about 0.1.

[0031] Figure 4B Some example vertical portions of dielectric layer 32B are shown. According to some embodiments, dielectric layer 32B is present on the sidewalls of the top portion of protruding fin 28. Dielectric layer 32B is absent from the sidewalls of the bottom portion of protruding fin 28, and the corresponding bottom portion of dielectric layer 32A is exposed. According to alternative embodiments, the vertical portions of dielectric layer 32B cover all sidewall portions of dielectric layer 32A, and thickness T2 is less than thickness T1.

[0032] Since the deposition of dielectric layer 32B is anisotropic, thinner vertical portions of dielectric layer 32B or no vertical portions of dielectric layer 32B will be formed between closely located protruding fins 28 , thereby reducing the process window.

[0033] According to some embodiments, dielectric layer 32B may be formed of a material different from that of dielectric layer 32A. For example, dielectric layer 32A may be formed of or include SiC, SiCN, SiN, SiO, SiOCN, SiON, etc., or a combination thereof. It should be noted that these value ranges are examples and may be different from those provided herein.

[0034] According to alternative embodiments, dielectric layer 32A and dielectric layer 32B have the same elements, e.g., Si, O, and N, or Si, O, C, and N, but the percentages of the corresponding elements are different when deposited and / or after a subsequent thermal treatment. For example, the atomic percentage of C and / or N in dielectric layer 32B may be higher than the atomic percentage of C and / or N in dielectric layer 32A, and the atomic percentage of O in dielectric layer 32A may be higher than the atomic percentage of O in dielectric layer 32B.

[0035] According to other alternative embodiments, dielectric layer 32B is a composite layer including a lower sublayer and an upper sublayer (referred to as sublayer 32B1 and sublayer 32B2, not shown). Sublayer 32B1 and sublayer 32B2 are shown for one dielectric layer 32B, but they may be in each of the shown portions of dielectric layer 32B. Each of sublayer 32B1 and sublayer 32B2 may be formed of or include a dielectric material different from the dielectric material of dielectric layer 32A. Although the materials of sublayer 32B1 and sublayer 32B2 are different from each other, each of sublayer 32B1 and sublayer 32B2 may be formed of a material having a lower etching rate than dielectric layer 32A in subsequent patterning and cleaning of dummy gate electrode 34 (as described above). For example, each of sub-layers 32B1 and 32B2 may be selected from the same group of candidate materials, which may include SiC, SiOC, SiON, SiCN, SiN, SiOCN, or the like.

[0036] According to other alternative embodiments where dielectric layer 32B is a composite layer, each of sublayers 32B1 and 32B2 may have a uniform composition. When dielectric layer 32B is a single layer, the entire dielectric layer 32B may be deposited to have a uniform composition. According to alternative embodiments, dielectric layer 32B has a gradually changing composition, with different portions including the same elements (e.g., silicon, oxygen, and nitrogen), while the percentage of the elements gradually changes from bottom to top. For example, the bottom portion of dielectric layer 32B may include SiO x , while the top portion may include SiAE y (or SiAE y ), where "AE" represents (one or more) substitution elements such as C and / or N. From the bottom of dielectric layer 32B to the top of dielectric layer 32B, the atomic percentage y of element AE gradually increases. For example, this can be achieved by gradually changing the flow rate of the precursor when using CVD.

[0037] According to some embodiments, dielectric layer 32 is formed using a first precursor and a second precursor. According to some embodiments, the first precursor includes a silicon-containing precursor, which may include silane, disilane, aminosilane, di-sec-butylaminosilane (DSBAS), di-(tert-butylamino)silane (BTBAS), etc. or a combination thereof. The second precursor may include other elements, such as C, N, and / or O, and may be referred to as an O / C / N-containing precursor hereinafter. For example, when N is to be included in the dielectric layer, the second precursor may include ammonia.

[0038] According to some embodiments, dielectric layer 32B is formed using an anisotropic deposition process (e.g., a plasma enhanced atomic layer deposition (PEALD) process) in which plasma is generated. During the PEALD deposition process, bias power is added. When bias power is added, the bias power may be greater than about 150 watts and may be in a range between about 10 watts and about 500 watts.

[0039] The plasma may be applied during and / or after pulsing the precursors (e.g., the silicon-containing precursor and the O / C / N-containing precursor), and may be applied, for example, after purging one precursor and before pulsing the next precursor. For example, the plasma may be turned off during pulsing the silicon-containing precursor, and turned on after pulsing the silicon-containing precursor and before pulsing the O / C / N-containing precursor. Similarly, the plasma may be turned off during pulsing the O / C / N-containing precursor, and turned on after pulsing the O / C / N-containing precursor and before pulsing the silicon-containing precursor. The plasma may be generated by a purge gas (e.g., argon, N2, etc.).

[0040] By using PEALD and applying bias power, the dielectric layer 32B is non-conformal, with the thickness T1 of the horizontal portion being greater than the thickness T2 of the vertical portion. To further enhance the anisotropic deposition effect, the process conditions of PEALD are adjusted to ensure that the deposition is in a diffusion mode. The diffusion mode can be achieved and enhanced by reducing the pulse modulation time (feed time), reducing the cleaning time, and reducing the plasma treatment time. In addition, the diffusion mode can be enhanced by increasing the chamber pressure during the pulse modulation of the precursor and / or when the plasma is turned on.

[0041] According to some embodiments, the pulse modulation time (feed time) of each of the precursors can be in a range between about 0.01 seconds and about 0.2 seconds. This is shorter than the pulse modulation time (feed time) of a typical non-diffusion mode deposition (where the pulse modulation time can be in a range between about 0.2 seconds and about 3 seconds). The plasma treatment time of each of the precursors can be in a range between about 0.1 seconds and about 0.3 seconds. This is shorter than the plasma treatment time of a typical non-diffusion mode deposition (where the pulse treatment time can be in a range between about 0.3 seconds and about 2 seconds). The cleaning time of each of the precursors can be reduced to a range between about 0.5 seconds and about 1.5 seconds.

[0042] According to an alternative embodiment, physical vapor deposition (PVD) is used to deposit dielectric layer 32B, and a bias power is applied to achieve anisotropic deposition. For example, the bias power may be in a range between about 1000 Watts and about 3000 Watts.

[0043] refer to Figure 5 , the dummy gate electrode layer 34 is deposited. The corresponding process is Fig.16 The process flow 200 is shown as process 212. A planarization process is then performed to level the top surface of the dummy gate electrode layer 34. For example, the dummy gate electrode layer 34 may be formed using polysilicon or amorphous silicon, and other materials such as amorphous carbon may also be used. One (or more) hard mask layers 36 are also formed on the dummy gate electrode layer 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbon nitride, or a multilayer thereof.

[0044] refer to Fig. 6A , Figure 6B and Figure 6C , the hard mask layer 36 and the dummy gate electrode layer 34 are patterned to form a dummy gate stack 37 including the hard mask 36 and the dummy gate electrode 34. The corresponding process is Fig.16 This is shown in the illustrated process flow 200 as process 214 . Figure 6B and Figure 6C They are shown respectively Fig. 6A 6B-6B and vertical section 6C-6C in FIG. According to some embodiments, the patterning process is performed by an anisotropic etching process. The etching gas may include an oxygen-containing gas, for example, a mixture of HBr, Cl2, and O2, or may include other processing gases, for example, fluorine (F2), chlorine (Cl2), hydrogen chloride (HCl), hydrogen bromide (HBr), bromine (Br2), C2F6, CF4, SO2, O2, or a combination thereof. The etching is performed using dielectric layer 32B as an etch stop layer.

[0045] Subsequently, a cleaning process may be performed. Cleaning may be performed using a cleaning chemical (e.g., diluted HF). According to some embodiments, by selecting a material for dielectric layer 32B, a chemical used to pattern dummy gate electrode layer 34, and an appropriate combination of cleaning chemicals, the etching (loss) rate of dielectric layer 32B (during patterning and cleaning) is lower than the etching rate of dielectric layer 32A, which may include silicon oxide. For example, the etching rate ER 32B / ER 32A can be greater than about 5 or greater than about 10, wherein ER 32B is the etch rate of dielectric layer 32B, ER 32A is the etch rate of dielectric layer 32 A. As a result, dielectric layer 32B in embodiments of the present disclosure is a better etch stop than silicon oxide, which may also be the gate oxide of an IO transistor (which may be formed in the same wafer / die as a GAA transistor).

[0046] Because the top portion of dielectric layer 32A is thicker and more resistant to etching and cleaning, the possibility of completely removing the top portion of dielectric layer 32B during the patterning process is reduced. Accordingly, the top nanostructure 22B below is less likely to be etched, or even if it is etched, the loss is less. Reoxidation of the top nanostructure 22B (also referred to as the top sheet) is reduced, and the loss of the top sheet is reduced.

[0047] During the etching and cleaning process, the vertical portion of the dielectric layer 32 may also be thinned ( Figure 6B and Figure 6C According to some embodiments, the vertical portion of dielectric layer 32B (if any) is completely removed because its thickness is very small. According to alternative embodiments, the vertical portion of dielectric layer 32B (if formed) is thinned but not completely removed.

[0048] Next, if Figure 7 As shown in FIG. 1 , the gate spacer 38 is formed on the sidewall of the dummy gate stack 37. The corresponding process is Fig.16 The process flow 200 is shown as process 216. According to some embodiments, the gate spacer 38 is formed of a dielectric material (e.g., silicon nitride (SiN), silicon dioxide (SiO2), silicon carbon nitride (SiCN), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), etc.), and may have a single-layer structure or a multi-layer structure including multiple dielectric layers. The formation process of the gate spacer 38 may include: depositing one or more dielectric layers, and then performing (one or more) anisotropic etching processes on (one or more) dielectric layers. The remaining portion of the (one or more) dielectric layer is the gate spacer 38.

[0049] Fig. 8A , Figure 8B and Figure 8C The formation of a recess 42 is shown from which the epitaxial region is formed. Fig. 8A Shows Figure 8C The vertical section 8A-8A in FIG. 8A passes through the portion of the protruding fin 28 that is not covered by the dummy gate stack 37 and the gate spacer. Fig. 8A Also shown in FIG. 2 are fin spacers 38 ′ located on the sidewalls of the protruding fins 28 . Figure 8B Shows Figure 8C Referring to the reference section 8B-8B in FIG. 8 , the reference section is parallel to the longitudinal direction of the protruding fin 28 .

[0050] like Fig. 8A , Figure 8B and Figure 8C As shown, the exposed portion of the dielectric layer 32 is etched. The corresponding process is Fig.16The process flow 200 is shown as process 218. The portion of the dielectric layer 32 and the protruding fin 28 directly below the dummy gate stack 37 and the gate spacer 38 remains after the etching process. Fig.16 The process flow 200 is shown as process 220. The remaining portion of the dielectric layer 32 is considered to be part of the dummy gate stack 37. According to some embodiments, the etching process includes a dry etching process performed using C2F6, CF4, SO2, a mixture of HBr, Cl2, and O2, a mixture of HBr, Cl2, O2, and CH2F2, etc. to etch the multilayer semiconductor stack 22' and the substrate strip 20' below. The bottom of the recess 42 is at least flush with the bottom of the multilayer semiconductor stack 22', or can be lower than the bottom of the multilayer semiconductor stack 22'. The etching can be anisotropic so that the sidewalls of the multilayer semiconductor stack 22' facing the recess 42 are vertical and straight.

[0051] refer to Figure 8B , the sacrificial semiconductor layer 22A is laterally recessed to form a lateral recess 41, which is recessed from the edges of the corresponding overlying nanostructure 22B and the corresponding underlying nanostructure 22B. Fig.16 The process flow 200 is shown as process 222. The lateral recessing of the sacrificial semiconductor layer 22A can be achieved by a wet etching process using an etchant that is more selective to the material of the sacrificial semiconductor layer 22A (e.g., silicon germanium (SiGe)) than to the material of the nanostructure 22B and the substrate 20 (e.g., silicon (Si)). For example, in an embodiment where the sacrificial semiconductor layer 22A is formed of silicon germanium and the nanostructure 22B is formed of silicon, the wet etching process can be performed using an etchant such as hydrochloric acid (HCl). The wet etching process can be performed using an immersion process, a spraying process, etc. According to an alternative embodiment, the lateral recessing of the sacrificial semiconductor layer 22A is performed by an isotropic dry etching process, or a combination of a dry etching process and a wet etching process.

[0052] Fig.9A and Fig. 9B The formation of the internal spacer 44 is shown. The corresponding process is Fig.16The process flow 200 is shown as process 224. The formation process includes depositing a spacer layer extending into the recess 41, and performing an etching process to remove a portion of the inner spacer layer outside the recess 41, thereby leaving the inner spacer 44 in the recess 41. The inner spacer 44 can be formed of or include SiOCN, SiON, SiOC, SiCN, etc. According to some embodiments, the etching of the spacer layer can be performed by a wet etching process, in which the etching chemical can include H2SO4, diluted HF, ammonia solution (NH4OH, ammonia solution), etc. or a combination thereof

[0053] Fig. 10A and Fig. 10B 4 shows a cross-sectional view and a perspective view of forming a source / drain region 48 in the recess 42 by epitaxy. Fig.16 The process flow 200 is shown as process 226. The source / drain region(s) may be referred to individually or collectively as source or drain, depending on the context. According to some embodiments, the source / drain region 48 may stress the nanostructure 22B that serves as the channel of the corresponding GAA transistor, thereby improving performance.

[0054] According to some embodiments, the corresponding transistor is n-type, so the epitaxial source / drain region 48 is formed to be n-type by doping with n-type dopants. For example, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. can be grown to form the epitaxial source / drain region 48. According to alternative embodiments, the corresponding transistor is p-type, so the epitaxial source / drain region 48 is formed to be p-type by doping with p-type dopants. For example, silicon boron (SiB), silicon germanium boron (SiGeB), etc. can be grown to form the epitaxial source / drain region 48. After filling the recess 42 with the epitaxial region 48, further epitaxial growth of the epitaxial region 48 causes the epitaxial region 48 to expand horizontally, and a small facet can be formed. Further growth of the epitaxial region 48 can also cause adjacent epitaxial regions 48 to merge with each other.

[0055] After the epitaxial process, the epitaxial region 48 may be further implanted with p-type impurities or n-type impurities to form source and drain regions, which are also indicated using reference numeral 48. According to an alternative embodiment of the present disclosure, when the epitaxial region 48 is in-situ doped with n-type impurities or p-type impurities during epitaxy and the epitaxial region 48 is also a source / drain region, the implantation process is skipped.

[0056] Fig.11A , Fig. 11B and Fig. 11C1 shows a cross-sectional view and a perspective view of the structure after forming a contact etch stop layer (CESL) 50 and an interlayer dielectric (ILD) 52. The corresponding process is shown in FIG. Fig.16 The process flow 200 is shown as process 228. CESL 50 may be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., and may be formed using CVD, ALD, etc. ILD 52 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or any other suitable deposition method. ILD 52 may be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based material, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0057] Fig. 12A and FIG. 12B to FIG. 15A and Fig. 15B A process for forming a replacement gate stack and contact plugs is shown. Fig. 12A and Fig. 12B In the process, a planarization process (eg, a CMP process or a mechanical grinding process) may be performed to level the top surface of the ILD 52. According to some embodiments, the planarization process may remove the hard mask 36 to expose the dummy gate electrode 34, such as Fig. 12A The corresponding process is Fig.16 This is shown as process 230 in the illustrated process flow 200. According to alternative embodiments, the planarization process may expose the hard mask 36 and be stopped on the hard mask 36. According to some embodiments, after the planarization process, the top surfaces of the dummy gate electrode 34 (or hard mask 36), the gate spacers 38, and the ILD 52 are level within process variations.

[0058] Next, in Fig.13A and Fig. 13B In the process shown, the dummy gate electrode 34 (and hard mask 36, if remaining) is removed in one or more etching processes, thereby forming the recess 58. The corresponding process is shown in FIG. Fig.16 This is shown as process 232 in the illustrated process flow 200. The portion of dielectric layer 32B in recess 58 is exposed.

[0059] According to some embodiments, the removal of the dummy gate electrode 34 may be performed by a dry and / or wet etching process. For example, when dry etching is performed, the etching gas may include F2, Cl2, HCl, HBr, Br2, C2F6, CF4, SO2, etc. or a combination thereof.

[0060] refer to Fig.14A and Fig. 14B , the exposed portion of the composite dielectric layer 32 is etched. The corresponding process is Fig.16 This is shown as process 234 in the illustrated process flow 200. On the other hand, the portion of the composite dielectric layer 32 directly below the gate spacer 38 is protected from being removed.

[0061] The sacrificial layer 22A is then removed to allow the recess 58 to extend between the nanostructures 22B. Fig.16 The process flow 200 is shown as process 236. The sacrificial layer 22A can be removed by performing an isotropic etching process (e.g., a wet etching process) using an etchant that is selective to the material of the sacrificial layer 22A, while the nanostructures 22B, the substrate 20, the STI regions 26, and the remaining dielectric layer 32A are relatively unetched compared to the sacrificial layer 22A. According to some embodiments in which the sacrificial layer 22A includes, for example, SiGe and the nanostructures 22B include, for example, silicon or carbon-doped silicon, chemicals such as tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. can be used to remove the sacrificial layer 22A.

[0062] refer to Fig.15A , Fig. 15B and Fig. 15C , the gate stack 70 is formed. The corresponding process is Fig.16 The process flow 200 is shown as process 238. First, a gate dielectric 62 is formed. According to some embodiments, each of the gate dielectrics 62 includes an interface layer 64 and a high-k dielectric layer 66 on the interface layer 64. The interface layer 64 can be formed of or include silicon oxide, which can be deposited by a conformal deposition process such as ALD or CVD. According to some embodiments, the high-k dielectric layer 66 includes one or more dielectric layers. For example, the high-k dielectric layer 66 can include a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof.

[0063] Gate electrode 68 is formed on gate dielectric 62. In the formation process, a conductive layer is first formed on high-k dielectric layer 66 to fill the remaining portion of recess 58. Gate electrode 68 may include a metal-containing material, such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multilayers thereof. Gate electrode 68 may also include a filler metal such as cobalt, tungsten, and the like. Gate dielectric 62 and gate electrode 68 also fill the space between adjacent nanostructures 22B in nanostructures 22B, and fill the space between the bottom nanostructure 22B in nanostructures 22B and the substrate strip 20' below. After filling recess 58, a planarization process (e.g., a CMP process or a mechanical grinding process) may be performed to remove excess portions of gate dielectric 62 and gate electrode 68 located above the top surface of ILD 52. Gate electrode 68 and gate dielectric 62 are collectively referred to as a gate stack 70 of the resulting nanoFET.

[0064] Next, the gate stack 70 is recessed so that recesses are formed directly above the gate stack 70 and between opposite portions of the gate spacers 38. A gate mask 74 including one or more layers of dielectric material (e.g., silicon nitride or silicon oxynitride, etc.) is filled in each of the recesses, and then a planarization process is performed to remove excess portions of the dielectric material extending beyond the first ILD 52.

[0065] like Fig.15A and Fig. 15B As further shown, ILD 76 is deposited over ILD 52 and gate mask 74. An etch stop layer (not shown) may or may not be deposited before forming ILD 76. According to some embodiments, ILD 76 is formed by FCVD, CVD, PECVD, etc. ILD 76 is formed of a dielectric material, which may be selected from silicon oxide, PSG, BSG, BPSG, USG, etc.

[0066] ILD 76, ILD 52, CESL 50, and gate mask 74 are etched to form recesses (occupied by contact plugs 80A and 80B) through which epitaxial source / drain regions 48 and gate stack 70 are exposed. The recesses may be formed by an anisotropic etching process (e.g., RIE, NBE, etc.). Fig. 15B Contact plug 80A and contact plug 80B are shown to be located in the same cross section, but in various embodiments, contact plug 80A and contact plug 80B can be formed in different cross sections to reduce the risk of shorting each other. After the recess is formed, silicide region 78 is formed on epitaxial source / drain region 48. According to some embodiments, silicide region 78 is formed by a metal deposition and annealing process.

[0067] The gate contact plug 80A and the source / drain contact plug 80B are formed. Fig.16 The process flow 200 shown is shown as process 240. The gate contact plug 80A is located above the gate electrode 68 and contacts the gate electrode 68. The source / drain contact plug 80B is formed above the silicide region 78. The contact plug 80A and the contact plug 80B can each include one or more layers, for example, a barrier layer and a filling material. The barrier layer can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The filling material can include copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process (e.g., a CMP process) can be performed to remove excess material from the surface of the ILD 76. Thus, the GAA transistor 82 is formed.

[0068] Dielectric layer 32A and dielectric layer 32B may be present in a final GAA transistor 82 . Fig.15D A cross section 15D-15D ( Fig. 15C ). Dielectric layer 32A may be a conformal layer on the protruding fin, which includes semiconductor nanostructure 22B and gate stack 70 between adjacent semiconductor nanostructures 22B. Semiconductor nanostructure 22B and portions of gate stack 70 between adjacent semiconductor nanostructures 22B together form a protruding fin that is higher than the top surface of STI region 26. Dielectric layer 32B may include a first horizontal portion above the protruding fin and a second horizontal portion on the top surface of STI region 26.

[0069] Dielectric layer 32B may not include or may include a sidewall portion on the sidewall of the protruding fin. When dielectric layer 32B has a sidewall portion, the bottommost end of the sidewall portion may be higher than, equal to, or lower than half the height of the protruding fin. The sidewall portion of dielectric layer 32B may be coupled to or spaced apart from a second horizontal portion of second dielectric layer 32B that is on the top surface of STI region 26.

[0070] Gate spacer 38 may be physically in contact with the sidewall portion of dielectric layer 32A and physically spaced apart from the top of dielectric layer 32A by dielectric layer 32B. Alternatively, according to some embodiments in which dielectric layer 32B further includes a sidewall portion (having a smaller thickness than the top) on all sidewall portions of dielectric layer 32A, gate spacer 38 is completely spaced apart from dielectric layer 32A by dielectric layer 32B.

[0071] Embodiments of the present disclosure have some advantageous features. By using an anisotropic deposition process to form a dielectric layer, the dielectric layer has a greater thickness on top of the protruding fins and STI regions. In the patterning and subsequent cleaning process for forming a dummy gate, the dielectric layer acts as a hard mask conforming to the underlying dielectric layer, so that it can reduce the top sheet loss of the semiconductor nanostructure and reduce the loss of the STI region.

[0072] According to some embodiments of the present disclosure, a method includes: forming a protruding fin; forming a first dielectric layer, the first dielectric layer including: a first top portion located on a top surface of the protruding fin and a first sidewall portion located on a sidewall of the protruding fin; forming a second dielectric layer on the first top portion of the first dielectric layer and over the top surface of the protruding fin, wherein the second dielectric layer is formed using an anisotropic deposition process; forming a dummy gate electrode (34) on the second dielectric layer; forming a gate spacer on the sidewall of the dummy gate electrode; removing the dummy gate electrode; and forming a replacement gate electrode in the space left by the dummy gate electrode. In an embodiment, the second dielectric layer has no portion located on the first sidewall portion of the first dielectric layer.

[0073] In an embodiment, the first dielectric layer and the second dielectric layer are formed using different deposition methods. In an embodiment, the first dielectric layer is deposited using a conformal deposition method. In an embodiment, the second dielectric layer is deposited using plasma enhanced atomic layer deposition with applied bias power. In an embodiment, the method further comprises: etching exposed portions of the first dielectric layer and the second dielectric layer after the dummy gate electrode is removed and before the replacement gate electrode is formed.

[0074] In an embodiment, after the exposed portions of the first dielectric layer and the second dielectric layer are etched, a first portion of the first dielectric layer directly under the gate spacer and a second portion of the second dielectric layer directly under the gate spacer remain. In an embodiment, the second portion of the second dielectric layer directly under the gate spacer is non-conformal. In an embodiment, the protruding fin includes a plurality of semiconductor nanostructures stacked and spaced apart from each other, and wherein the replacement gate electrode extends into a space between the plurality of semiconductor nanostructures.

[0075] In an embodiment, forming the dummy gate electrode comprises: depositing a polysilicon layer on the second dielectric layer, and patterning the polysilicon layer, wherein the patterning stops on the second dielectric layer. In an embodiment, the second dielectric layer comprises a second sidewall portion on the first sidewall portion, and wherein the second sidewall portion is removed in a cleaning process performed before forming the gate spacer.

[0076] According to some embodiments of the present disclosure, a structure includes: a dielectric isolation region; a plurality of semiconductor nanostructures located next to and above the dielectric isolation region, wherein a higher semiconductor nanostructure among the plurality of semiconductor nanostructures overlies a corresponding lower semiconductor nanostructure among the plurality of semiconductor nanostructures; a gate stack including: a first portion located above a top nanostructure of the plurality of semiconductor nanostructures and a second portion located between adjacent semiconductor nanostructures among the plurality of semiconductor nanostructures, wherein the second portion of the gate stack and the plurality of semiconductor nanostructures are interconnected to form a protruding fin; a first dielectric layer located on a top surface and sidewalls of the protruding fin; a second dielectric layer including a first portion above the first dielectric layer, wherein the first dielectric layer is more conformal than the second dielectric layer, and wherein at least a top portion of the first portion is higher than a top nanostructure among the plurality of semiconductor nanostructures; and a gate spacer above the second dielectric layer.

[0077] In an embodiment, the first dielectric layer is conformal and the first portion of the second dielectric layer has a bottommost end that is flush with the topmost surface of the top nanostructure. In an embodiment, the second dielectric layer further includes a second portion overlying the dielectric isolation region, wherein the first portion and the second portion are discrete portions of the second dielectric layer. In an embodiment, the first portion of the second dielectric layer further includes a second portion located on a sidewall of the protruding fin, wherein the second portion is thinner than the first portion. In an embodiment, the bottommost end of the second portion is higher than half the height of the protruding fin.

[0078] According to some embodiments of the present disclosure, a structure includes: a semiconductor substrate; a first dielectric isolation region and a second dielectric isolation region in the semiconductor substrate; a protruding fin located between the first dielectric isolation region and the second dielectric region and higher than the first dielectric isolation region and the second dielectric region; a first dielectric layer located on the top surface and sidewalls of the protruding fin; a second dielectric layer above the first dielectric layer, the second dielectric layer including a first portion overlying the protruding fin and a second portion overlying the first dielectric isolation region, wherein the first portion and the second portion are discrete portions of the second dielectric layer; and a gate spacer above the second dielectric layer.

[0079] In an embodiment, the gate spacer is physically in contact with a sidewall portion of the first dielectric layer and is spaced apart from a top portion of the first dielectric layer by a first portion of the second dielectric layer. In an embodiment, the first dielectric layer comprises silicon oxide and the second dielectric layer comprises silicon and an element selected from the group consisting of N, C, and combinations thereof. In an embodiment, the second dielectric layer further comprises a first vertical portion located on the second vertical portion of the first dielectric layer, and wherein the second vertical portion is located on a sidewall of the protruding fin.

[0080] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments introduced herein. It should also be appreciated by those skilled in the art that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A method comprising: Formation of protruding fins; A first dielectric layer is formed, wherein the first dielectric layer comprises: a first top portion located on a top surface of the protruding fin; and a first side wall portion, located on a side wall of the protruding fin; forming a second dielectric layer over a first top portion of the first dielectric layer and over a top surface of the protruding fin, wherein the second dielectric layer is formed using an anisotropic deposition process; forming a dummy gate electrode on the second dielectric layer; forming a gate spacer on a sidewall of the dummy gate electrode; removing the dummy gate electrode; and A replacement gate electrode is formed in the space left by the dummy gate electrode.

2. The method according to claim 1, wherein: The second dielectric layer has no portion located on the first sidewall portion of the first dielectric layer.

3. The method according to claim 1, wherein: The first dielectric layer and the second dielectric layer are formed using different deposition methods.

4. The method according to claim 3, wherein: The first dielectric layer is deposited using a conformal deposition method.

5. The method according to claim 1, wherein: The second dielectric layer is deposited using plasma enhanced atomic layer deposition with applied bias power.

6. The method according to claim 1, further comprising: After the dummy gate electrode is removed and before the replacement gate electrode is formed, exposed portions of the first dielectric layer and the second dielectric layer are etched.

7. The method according to claim 6, wherein: After the exposed portions of the first dielectric layer and the second dielectric layer are etched, a first portion of the first dielectric layer directly beneath the gate spacer and a second portion of the second dielectric layer directly beneath the gate spacer remain.

8. The method according to claim 7, wherein: The second portion of the second dielectric layer directly beneath the gate spacer is non-conformal.

9. A structure comprising: Dielectric isolation area; a plurality of semiconductor nanostructures located beside and above the dielectric isolation region, wherein a higher semiconductor nanostructure among the plurality of semiconductor nanostructures overlies a corresponding lower semiconductor nanostructure among the plurality of semiconductor nanostructures; Gate stack, including: A first portion located above a top nanostructure of the plurality of semiconductor nanostructures; and a second portion located between adjacent semiconductor nanostructures among the plurality of semiconductor nanostructures, wherein the second portion of the gate stack and the plurality of semiconductor nanostructures are connected to each other to form a protruding fin; a first dielectric layer disposed on the top surface and sidewalls of the protruding fin; a second dielectric layer comprising a first portion over the first dielectric layer, wherein the first dielectric layer is more conformal than the second dielectric layer, and wherein at least a top portion of the first portion is taller than a top nanostructure of the plurality of semiconductor nanostructures; and A gate spacer is on the second dielectric layer.

10. A structure comprising: Semiconductor substrate; a first dielectric isolation region and a second dielectric isolation region located in the semiconductor substrate; a protruding fin located between the first dielectric isolation region and the second dielectric region and higher than the first dielectric isolation region and the second dielectric region; a first dielectric layer disposed on the top surface and sidewalls of the protruding fin; A second dielectric layer, on the first dielectric layer, the second dielectric layer comprising: A first portion overlying the protruding fin; and A second portion overlies the first dielectric isolation region, wherein: The first portion and the second portion are discrete portions of the second dielectric layer; and A gate spacer is on the second dielectric layer.

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