MOS device and preparation method thereof

Abstract

The invention provides an MOS device and a preparation method thereof, the MOS device comprises a semiconductor structure, a well region, a source region, a contact region, a gate structure, a source electrode, a gate electrode and a drain electrode, and the semiconductor structure comprises a substrate and a drift region which are stacked in sequence; a plurality of well regions arranged at intervals are located on the upper surface layer of the drift region; the source region is located in the well region and is spaced from the side wall of the well region by a preset distance, and the bottom surface of the source region is higher than that of the well region; the gate structure covers the well region between two adjacent source regions in the adjacent well regions and the upper surface of the drift region, and extends to the upper part of the source region along the edge of the well region arrangement direction; the source electrode is electrically connected with the source region and the contact region, the grid electrode is electrically connected with the grid structure, and the drain electrode is electrically connected with the substrate. The depth of the well region is reduced, and the bottom surface of the contact region is lower than the bottom surface of the well region, so that the specific on-resistance of the device is reduced while the voltage endurance capability of the device is ensured, and the performance of the device is improved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a MOS device and a preparation method thereof. Background Art

[0002] Silicon carbide metal oxide semiconductor field effect transistor (SiC MOS) is widely used in high voltage fields due to its excellent performance. With the iteration and upgrading of SiC MOS generations and the needs of application scenarios, the size of the device needs to be continuously compressed, and the on-resistance of the device needs to be further reduced. It is usually calculated by the specific on-resistance (the product of the on-resistance of the device and the area of ​​the chip active area, that is, R SP =Ron*device active area) to judge the performance of the device. For SiC MOS, the channel resistance accounts for a large proportion in 1200V and 650V devices. The general practice is to reduce R by increasing the channel density per unit area. SP Or reduce the resistance of the JFET region (Junction Field-Effect Transistor) to reduce R SP However, as the device size becomes smaller and smaller, the size of the JFET region cannot be further compressed due to the influence of the device structure. At this time, it is impossible to further reduce the size to increase the channel density, such as Figure 1 As shown in FIG. 1 , it is a schematic diagram of the cross-sectional structure of a MOS device, including a semiconductor structure 01, a substrate 011, a drift region 012, a well region 013, a source region 014, a contact region 015, a gate structure 02, a gate oxide layer 021, a polysilicon gate 022, an interlayer dielectric layer 03, a source 04, and a drain 05. In addition, the reduction of the size of the JFET region must introduce a multi-step JFET region injection for adjustment, and even with the JFET region injection adjustment, the size of the JFET region has an inflection point. After the size of the JFET region is reduced to a certain extent, the JFET resistance will rise rapidly, resulting in R SP The voltage resistance and switching loss of the device are affected.

[0003] Therefore, there is an urgent need to find a method for preparing a MOS device that can reduce the device size while reducing the specific on-resistance of the device. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a MOS device and a method for manufacturing the same, so as to solve the problem in the prior art that the size of the device is reduced while the specific on-resistance of the device is increased.

[0005] To achieve the above object and other related objects, the present invention provides a method for preparing a MOS device, comprising the following steps:

[0006] A semiconductor structure is provided, wherein the semiconductor structure comprises a first conductive type substrate and a first conductive type drift region stacked in sequence;

[0007] A plurality of second conductive type well regions are formed at intervals on the upper surface of the drift region, and a first conductive type source region is formed in the well region at a preset distance from the sidewall of the well region, wherein the bottom surface of the source region is higher than the bottom surface of the well region;

[0008] forming a second conductive type contact region penetrating the well region and adjacent to the sidewall of the source region, wherein the bottom surface of the contact region is lower than the bottom surface of the well region;

[0009] forming a gate structure covering the upper surface of the well region and the drift region between two adjacent source regions in the adjacent well regions and extending along the edge of the well region arrangement direction to above the source region;

[0010] A source electrode electrically connected to the source region and the contact region is formed, a gate electrode electrically connected to the gate structure is formed, and a drain electrode electrically connected to the substrate is formed.

[0011] Optionally, the material of the substrate includes silicon carbide.

[0012] Optionally, a distance between a bottom surface of the well region and an upper surface of the drift region ranges from 0.3 μm to 0.7 μm, and a distance between a bottom surface of the well region and a bottom surface of the source region ranges from 0.1 μm to 0.3 μm.

[0013] Optionally, the distance between the bottom surface of the contact region and the upper surface of the drift region ranges from 0.8 μm to 1.5 μm, and the distance between the bottom surface of the contact region and the bottom surface of the well region ranges from 0.4 μm to 1 μm.

[0014] Optionally, the contact region includes a stacked voltage-withstand region and an ohmic contact region.

[0015] Optionally, the doping concentration of the ohmic contact region is greater than the doping concentration of the voltage-resistant region, and the upper surface of the voltage-resistant region is higher than the bottom surface of the well region, and the bottom surface of the voltage-resistant region is lower than the bottom surface of the well region.

[0016] Optionally, the gate structure includes a gate dielectric layer and a gate conductive layer stacked in sequence, the gate dielectric layer covers the upper surfaces of the well region and the drift region between two adjacent source regions in different well regions, and the edge of the gate dielectric layer along the arrangement direction of the well regions extends to the upper surface of the source region, and the gate is electrically connected to the gate conductive layer.

[0017] Optionally, the device is further provided with an interlayer dielectric layer covering the exposed surface of the gate structure and the exposed upper surface of the drift region, the gate penetrates the interlayer dielectric layer and is electrically connected to the gate structure, and the source penetrates the interlayer dielectric layer and is electrically connected to the source region and the contact region.

[0018] Optionally, the doping concentration of the substrate is greater than the doping concentration of the drift region, and the contact type between the drain and the substrate is ohmic contact.

[0019] The present invention also provides a MOS device, comprising:

[0020] The semiconductor structure comprises a first conductive type substrate and a first conductive type drift region stacked in sequence;

[0021] A plurality of well regions of the second conductivity type arranged at intervals and located on the upper surface layer of the drift region;

[0022] A first conductive type source region, located in the well region and spaced apart from a sidewall of the well region by a preset distance, wherein a bottom surface of the source region is higher than a bottom surface of the well region;

[0023] A second conductive type contact region, which penetrates the well region and is adjacent to a side wall of the source region, wherein a bottom surface of the contact region is lower than a bottom surface of the well region;

[0024] A gate structure, covering the well region between two adjacent source regions in the adjacent well regions and the upper surface of the drift region and extending along the edge of the well region arrangement direction to above the source region;

[0025] A source, a gate and a drain, the source is electrically connected to the source region and the contact region, the gate is electrically connected to the gate structure, and the drain is electrically connected to the substrate.

[0026] As described above, the MOS device and preparation method of the present invention improve the manufacturing process of the device, and when forming the well region, the depth of the formed well region is shallowed, so that the well region is only used to protect the source region and form a conductive channel of the device. When forming the contact region, doping with different energies is performed to obtain an ohmic contact region that forms an ohmic contact with the source and a bottom surface lower than the well region. Since the depletion region formed between the voltage-resistant region and the drift region is laterally widened and closed in the JEFT region of the device, the breakdown resistance of the device is guaranteed; due to the shallowing of the depth of the well region, the JEFT region of the device is relatively increased, and then the size of the device can be further reduced. While reducing the size of the device, there is no need to perform ion implantation to regulate the resistance of the JEFT region of the device, which simplifies the manufacturing process of the device, reduces the on-resistance of the device, reduces the switching loss of the device, reduces the specific on-resistance of the device, and improves the performance of the device, which has a high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Shown is a schematic diagram of the cross-sectional structure of a MOS device.

[0028] Figure 2 Shown is a process flow chart of the method for preparing the MOS device of the present invention.

[0029] Figure 3 The cross-sectional structure schematic diagram of the semiconductor structure of the method for preparing the MOS device of the present invention is shown.

[0030] Figure 4 It is a schematic diagram showing the cross-sectional structure after forming the well region in the method for preparing the MOS device of the present invention.

[0031] Figure 5 It is a schematic diagram showing the cross-sectional structure after forming the contact region in the method for preparing the MOS device of the present invention.

[0032] Figure 6 It is a schematic diagram showing the cross-sectional structure of the MOS device manufacturing method of the present invention after the gate structure is formed.

[0033] Figure 7 It is a schematic diagram showing the cross-sectional structure after forming an interlayer dielectric layer in the method for preparing a MOS device of the present invention.

[0034] Figure 8 It is a schematic diagram showing the cross-sectional structure after forming the drain in the method for preparing the MOS device of the present invention.

[0035] Fig. 9 Display as Figure 1 MOS devices and Figure 8 Breakdown curve of MOS device.

[0036] Fig.10 Display as Figure 1 MOS devices and Figure 8 The conduction curve of the MOS device in FIG.

[0037] Description of Figure Numbers

[0038] 01Semiconductor structure

[0039] 011 substrate

[0040] 012 Drift Zone

[0041] 013 Well

[0042] 014 Source Area

[0043] 015 Contact Area

[0044] 02Gate structure

[0045] 021 Gate oxide layer

[0046] 022 Polysilicon Gate

[0047] 03Interlayer dielectric layer

[0048] 04 Source

[0049] 05Drain

[0050] 1Semiconductor structure

[0051] 11 Substrate

[0052] 12 Drift Zone

[0053] 13-well region

[0054] 14 Source Area

[0055] 15 contact area

[0056] 151 Pressure Withstand Area

[0057] 152 ohm contact area

[0058] 2-gate structure

[0059] 21Gate dielectric layer

[0060] 22 gate conductive layer

[0061] 3 interlayer dielectric layer

[0062] 4 Source

[0063] 5 Drain DETAILED DESCRIPTION

[0064] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0065] See also Figures 2 to 10 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0066] Embodiment 1

[0067] This embodiment provides a method for preparing a MOS device, such as Figure 2 FIG. 1 is a process flow chart of the method for preparing the MOS device, comprising the following steps:

[0068] S1: providing a semiconductor structure, wherein the semiconductor structure comprises a first conductive type substrate and a first conductive type drift region stacked in sequence;

[0069] S2: forming a plurality of second conductive type well regions spaced apart on the upper surface layer of the drift region, and forming a first conductive type source region spaced apart from a sidewall of the well region by a preset distance in the well region, wherein the bottom surface of the source region is higher than the bottom surface of the well region;

[0070] S3: forming a second conductive type contact region penetrating the well region and adjacent to the sidewall of the source region, wherein a bottom surface of the contact region is lower than a bottom surface of the well region;

[0071] S4: forming a gate structure covering the well region between two adjacent source regions in the adjacent well regions and the upper surface of the drift region and extending along the edge of the well region arrangement direction to above the source region;

[0072] S5: forming a source electrode electrically connected to the source region and the contact region, forming a gate electrode electrically connected to the gate structure, and forming a drain electrode electrically connected to the substrate.

[0073] See also Figures 3 to 5 , perform step S1, step S2 and step S3: provide a semiconductor structure 1, the semiconductor structure 1 includes a first conductive type substrate 11 and a first conductive type drift region 12 stacked in sequence; form a plurality of second conductive type well regions 13 spaced apart on the upper surface layer of the drift region 12, and form a first conductive type source region 14 spaced apart from the sidewall of the well region 13 by a preset distance in the well region 13, the bottom surface of the source region 14 is higher than the bottom surface of the well region 13; form a second conductive type contact region 15 penetrating the well region 13 and adjacent to the sidewall of the source region 14, the bottom surface of the contact region 15 is lower than the bottom surface of the well region 13.

[0074] Specifically, the first conductivity type includes one of N type or P type, the second conductivity type includes one of N type or P type, and the first conductivity type is opposite to the second conductivity type. In this embodiment, the first conductivity type is N type, and the second conductivity type is P type.

[0075] As an example, Figure 3FIG. 1 is a schematic diagram of a cross-sectional structure of the semiconductor structure 1. The material of the substrate 11 includes silicon carbide or other suitable semiconductor materials, such as silicon or silicon germanium. In this embodiment, the material of the substrate 11 is silicon carbide.

[0076] Specifically, the doping concentration of the substrate 11 is greater than the doping concentration of the drift region 12 .

[0077] Specifically, the substrate 11 is a process platform for epitaxially growing the drift region 12 , and a method for epitaxially forming the drift region 12 on the substrate 11 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0078] As an example, the distance between the bottom surface of the well region 13 and the upper surface of the drift region 12 ranges from 0.3μm to 0.7μm, and the distance between the bottom surface of the well region 13 and the bottom surface of the source region 14 ranges from 0.1μm to 0.3μm, that is, the thickness of the well region 13 ranges from 0.3μm to 0.7μm.

[0079] Specifically, Figure 4 , which is a schematic diagram of the cross-sectional structure after forming the well region 13, wherein the method of forming the well region 13 includes ion implantation or other suitable methods. In this embodiment, the well region 13 is formed by multiple ion implantation processes so that the doping concentration of each region of the well region 13 is relatively uniform.

[0080] Specifically, the method for forming the source region 14 includes ion implantation or other suitable methods. In this embodiment, the source region 14 is formed by ion implantation, and the energy of the doping particles forming the source region 14 is slightly less than the energy of the doping particles forming the well region 13 .

[0081] As an example, Figure 5 As shown, it is a schematic diagram of the cross-sectional structure after the contact area 15 is formed, the distance range between the bottom surface of the contact area 15 and the upper surface of the drift area 12 is 0.8μm to 1.5μm, and the range between the bottom surface of the contact area 15 and the bottom surface of the well area 13 is 0.4μm to 1μm, that is, the thickness range of the contact area 15 is 0.8μm to 1.5μm.

[0082] Specifically, the contact area 15 is interconnected with the well area 13, and the method for forming the contact area 15 includes ion implantation or other suitable methods. In this embodiment, based on the patterned photoresist forming the contact area 15, doping is performed by multiple ion implantations to obtain the contact area 15 of a preset thickness, and the number of ion implantations to form the contact area 15 is not less than the number of ion implantations to form the well area 13, and the maximum energy of the doped ions forming the contact area 15 is greater than the maximum energy of the doped particles forming the well area 13.

[0083] As an example, the contact region 15 includes a stacked voltage-sustaining region 151 and an ohmic contact region 152 .

[0084] As an example, the doping concentration of the ohmic contact region 152 is greater than the doping concentration of the voltage-resistant region 151, and the upper surface of the voltage-resistant region 151 is higher than the bottom surface of the well region 13, and the bottom surface of the voltage-resistant region 151 is lower than the bottom surface of the well region 13. In this embodiment, the bottom surface of the voltage-resistant region 151 is not higher than the bottom surface of the source region 14 and is higher than the bottom surface of the well region 13, that is, in the process of forming the contact region 15, high-energy particles are used for ion implantation to form the voltage-resistant region 151, and lower-energy particles are used for ion implantation to form the ohmic contact region 152.

[0085] Specifically, the ohmic contact region 152 is used to form an ohmic contact with the source 4, and the voltage-resistant region 151 is used to bear the voltage resistance of the device. By adjusting the doping concentration of the voltage-resistant region 151, the PN junction width between the voltage-resistant region 151 and the drift region 12 can be adjusted to ensure the voltage resistance value of the device.

[0086] See also Figures 6 to 8 , perform step S4 and step S5: form a gate structure 2 covering the well region 13 between two adjacent source regions 14 in the adjacent well regions 13 and the upper surface of the drift region 12 and extending to the top of the source region 14 along the edge of the arrangement direction of the well region 13; form a source electrode 4 electrically connected to the source region 14 and the contact region 15, form a gate electrode electrically connected to the gate structure 2, and form a drain electrode 5 electrically connected to the substrate 11.

[0087] As an example, Figure 6 As shown, it is a schematic diagram of the cross-sectional structure after the gate structure 2 is formed, and the gate structure 2 includes a gate dielectric layer 21 and a gate conductive layer 22 stacked in sequence, and the gate dielectric layer 21 covers the upper surfaces of the well region 13 and the drift region 12 between two adjacent source regions 14 in different well regions 13, and the edge of the gate dielectric layer 21 along the arrangement direction of the well region 13 extends to the upper surface of the source region 14, and the gate is electrically connected to the gate conductive layer 22.

[0088] Specifically, forming the gate structure 2 includes the following steps: forming a gate dielectric material layer covering the exposed upper surfaces of the drift region 12, the well region 13, the source region 14 and the contact region 15 on the upper surface of the semiconductor structure 1, and forming a gate conductive material layer covering the upper surface of the gate dielectric material layer; forming a patterned shielding layer on the upper surface of the gate conductive material layer, and forming the gate conductive layer 22 and the gate dielectric layer 21 based on the patterned shielding layer, and the gate dielectric layer 21 and the gate conductive layer 22 constitute the gate structure 2.

[0089] Specifically, the method of forming the gate dielectric material layer includes thermal oxidation, chemical vapor deposition, physical vapor deposition or other suitable methods; the method of forming the gate conductive material layer includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0090] Specifically, the method for forming the patterned shielding layer is a common photoresist coating, exposure, and development process, which will not be described in detail here.

[0091] Specifically, the method of forming the gate conductive layer 22 based on the patterned shielding layer includes dry etching, wet etching or other suitable methods; the method of forming the gate dielectric layer 21 based on the patterned shielding layer includes dry etching, wet etching or other suitable methods. In this embodiment, the gate conductive material layer and the gate dielectric material layer are sequentially etched based on the patterned shielding layer to obtain the gate conductive layer 22 and the gate dielectric layer 21.

[0092] Specifically, under the condition of ensuring the device performance, the thickness of the gate dielectric layer 21 can be selected according to actual conditions and is not limited here.

[0093] As an example, Figure 7 As shown, it is a schematic diagram of the cross-sectional structure after the interlayer dielectric layer 3 is formed. The device is also provided with an interlayer dielectric layer 3 covering the exposed surface of the gate structure 2 and the exposed upper surface of the drift region 12. The gate passes through the interlayer dielectric layer 3 and is electrically connected to the gate structure 2. The source 4 passes through the interlayer dielectric layer 3 and is electrically connected to the source region 14 and the contact region 15.

[0094] Specifically, the method of forming the interlayer dielectric layer 3 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0095] Specifically, under the condition of ensuring the device performance, the thickness of the interlayer dielectric layer 3 can be selected according to actual conditions and is not limited here.

[0096] Specifically, the interlayer dielectric layer 3 is further provided with a gate contact hole and a source contact hole, the gate contact hole penetrates the interlayer dielectric layer 3 and the gate conductive layer 22 is exposed on the bottom surface, and the source contact hole penetrates the interlayer dielectric layer 3 and the contact area 15 and the source area 14 are exposed on the bottom surface.

[0097] Specifically, the method of forming the gate contact hole includes dry etching, wet etching or other suitable methods; the method of forming the source contact hole includes dry etching, wet etching or other suitable methods.

[0098] Specifically, while ensuring device performance, the opening shape and opening size of the gate contact hole can be selected according to actual conditions and are not limited here; the opening shape and opening size of the source contact hole can be selected according to actual conditions and are not limited here.

[0099] Specifically, the method of forming the source 4 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods; the method of forming the gate includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.

[0100] As an example, the doping concentration of the substrate 11 is greater than the doping concentration of the drift region 12 , and the contact type between the drain 5 and the substrate 11 is an ohmic contact.

[0101] Specifically, Figure 8 As shown, it is a schematic diagram of the cross-sectional structure after the drain 5 is formed. The method of forming the drain 5 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.

[0102] Specifically, by reducing the injection depth of the formed well region 13, and then reducing the spacing distance between the bottom surface of the well region 13 and the source region 14 located in the well region 13, the well region 13 is used to form a conductive channel and protect the source region 14, and the PN structure between the well region 13 and the drift region 12 does not serve as the main part that bears the device's withstand voltage.

[0103] Specifically, as the depth of the well region 13 becomes shallower, the JEF region of the device is relatively enlarged, thereby avoiding the subsequent ion implantation step for adjusting the JEF region resistance of the device and ensuring the current path, simplifying the process steps, and reducing the distance between two adjacent well regions 13, thereby reducing the size of the device.

[0104] Specifically, due to the influence of the characteristics of silicon carbide material itself, the width of its depletion region is several times that of the depletion region of silicon-based devices. By making the depth of the well region 13 shallower and reducing the size of the device, while deepening the depth of the voltage-resistant region 151 located at the bottom of the contact region 15, the upper surface of the voltage-resistant region 151 is higher than the bottom surface of the well region 13 and the bottom surface is lower than the bottom surface of the well region 13, and the doping concentration of the voltage-resistant region 151 is adjusted, so that the depletion region formed between the voltage-resistant region 151 and the drift region 12 is widened downward and also widened in the lateral region, and compensates to the JEFT region of the device, and then the depletion region of the JEFT region of the device is closed, thereby further reducing the size of the device, while reducing the specific on-resistance of the device and improving the voltage resistance of the device.

[0105] The preparation method of the MOS device of this embodiment improves the manufacturing process of the device so that the depth of the formed well region 13 becomes shallower and is only used to protect the source region 14 and form a conductive channel of the device, and the formed contact region 15 includes the ohmic contact region 152 in ohmic contact with the source 4 and the voltage-resistant region 151 whose bottom surface is lower than the bottom surface of the well region 13. The depletion region formed between the voltage-resistant region 151 and the drift region 12 is laterally widened to achieve the closing of the depletion region in the JEFT region of the device, thereby ensuring the voltage-resistant capability of the device. At the same time, due to the shallowing of the depth of the well region 13, the JEFT region of the device becomes larger, thereby further reducing the size of the device, and while reducing the size of the device, the step of ion implantation to adjust the resistance of the JEFT region of the device can be avoided.

[0106] Embodiment 2

[0107] This embodiment provides a MOS device, such as Figure 8 As shown, it is a schematic diagram of the cross-sectional structure of the MOS device, including a semiconductor structure 1, a second conductive type well region 13, a first conductive type source region 14, a second conductive type contact region 15, a gate structure 2, a source 4, a gate and a drain 5, wherein the semiconductor structure 1 includes a first conductive type substrate 11 and a first conductive type drift region 12 stacked in sequence; a plurality of well regions 13 arranged at intervals are located on the upper surface of the drift region 12; the source region 14 is located in the well region 13 and is spaced from the sidewall of the well region 13 by a preset distance, and the bottom surface of the source region 14 is higher than the bottom surface of the well region 13; the gate structure 2 covers the well region 13 between two adjacent source regions 14 in the adjacent well regions and the upper surface of the drift region 12 and extends along the edge of the arrangement direction of the well region 13 to above the source region 14; the source 4 is electrically connected to the source region 14 and the contact region 15, the gate is electrically connected to the gate structure 2, and the drain 5 is electrically connected to the substrate 11.

[0108] Specifically, the contact type between the substrate 11 and the drain 5 is an ohmic contact. Under the condition of ensuring the device performance, the thickness and doping concentration of the substrate 11 can be selected according to the actual situation, and are not limited here. The thickness here refers to the distance from the bottom surface of the substrate 11 to the top surface of the substrate 11.

[0109] Specifically, the drift region 12 is used to ensure the withstand voltage of the device. Under the condition of ensuring the performance of the device, the thickness and doping concentration of the drift region 12 can be selected according to the actual situation, and no restrictions are imposed here. The thickness here refers to the distance between the upper surface of the drift region 12 and the lower surface of the drift region 12.

[0110] Specifically, the thickness of the well region 13 is in the range of 0.3μm to 0.7μm, and the upper surface of the well region 13 is flush with the upper surface of the drift region 12. While ensuring the device performance, the shape, size and doping concentration of the well region 13 can be selected according to actual conditions and are no longer restricted here; the distance between two adjacent well regions 13 along the arrangement direction of the well regions 13 can be selected according to actual conditions and is no longer restricted here.

[0111] Specifically, the contact type between the source region 14 and the source electrode 4 is an ohmic contact, the thickness of the source region 14 is less than the thickness of the well region 13, and the distance between the bottom surface of the source region 14 and the bottom surface of the well region 13 is in the range of 0.1 μm to 0.3 μm. Under the condition of ensuring the performance of the device, the doping concentration and size of the source region 14 can be selected according to actual conditions, and are not limited here. The thickness here refers to the distance between the upper surface of the source region 14 and the lower surface of the source region 14.

[0112] Specifically, the thickness of the contact area 15 is in the range of 0.8 μm to 1.5 μm, and the distance between the bottom surface of the contact area 15 and the bottom surface of the well area 13 is in the range of 0.4 μm to 1 μm. The thickness here refers to the distance between the bottom surface of the contact area 15 and the upper surface of the contact area 15 (i.e., the upper surface of the well area 13).

[0113] Specifically, the contact region 15 includes a voltage-resistant region 151 and an ohmic contact region 152 stacked in sequence. The bottom surface of the voltage-resistant region 151 is lower than the bottom surface of the well region 13 and the top surface is higher than the bottom surface of the well region 13 .

[0114] Specifically, the ohmic contact region 152 is used to form an ohmic contact with the source electrode 4 . Under the condition of ensuring device performance, the doping concentration and thickness of the ohmic contact region 152 can be selected according to actual conditions and are not limited here.

[0115] Specifically, the voltage-resistant region 151 is used to ensure the voltage-resistant performance of the device. By adjusting the doping concentration of the voltage-resistant region 151, the depletion region formed between the voltage-resistant region 151 and the drift region 12 is laterally widened and closed to ensure the voltage-resistant capability of the device. While ensuring the performance of the device, the distance between the side wall of the voltage-resistant region 151 and the side wall of the well region 13 and the doping concentration of the voltage-resistant region 151 can be selected according to actual conditions and are no longer restricted here.

[0116] Specifically, the gate structure 2 includes a gate dielectric layer 21 and a gate conductive layer 22 stacked in sequence, the gate dielectric layer 21 covers the upper surfaces of the well region 13 and the drift region 12 between two adjacent source regions 14 in different well regions 13, and the edge of the gate dielectric layer 21 along the arrangement direction of the well region 13 extends to the upper surface of the source region 14, and the gate is electrically connected to the gate conductive layer 22.

[0117] Specifically, the gate dielectric layer 21 is made of silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials.

[0118] Specifically, the gate conductive layer 22 is made of polysilicon or other suitable conductive materials.

[0119] Specifically, the device is also provided with an interlayer dielectric layer 3 covering the exposed surface of the gate structure 2 and the exposed upper surface of the drift region 12, the gate passes through the interlayer dielectric layer 3 and is electrically connected to the gate structure 2, and the source 4 passes through the interlayer dielectric layer 3 and is electrically connected to the source region 14 and the contact region 15.

[0120] Specifically, the material of the interlayer dielectric layer 3 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials.

[0121] Specifically, the interlayer dielectric layer 3 is also provided with a gate contact hole and a source contact hole penetrating the interlayer dielectric layer 3, the bottom surface of the gate contact hole exposes the gate conductive layer 22, the bottom surface of the source contact hole exposes the source region 14 and the ohmic contact region 152, the gate is electrically connected to the gate conductive layer 22 through the gate contact hole, and the source 4 is electrically connected to the source region 14 and the ohmic contact region 152 through the source contact hole.

[0122] Specifically, the material of the source electrode 4 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials; the material of the gate electrode includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials; the material of the drain electrode 5 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials.

[0123] Specifically, by thinning the thickness of the well region 13 and changing the contact region 15 connected to the well region 13 to be composed of the ohmic contact region 152 and the voltage-resistant region 151 whose bottom surface is lower than the bottom surface of the well region 13, the well region 13 is only used to provide a conductive channel and protect the source region 14. By adjusting the doping concentration of the voltage-resistant region 151, the depletion region formed between the voltage-resistant region 151 and the drift region 12 can be closed under the gate structure 2, thereby ensuring the breakdown voltage of the device while reducing the on-resistance of the device.

[0124] Specifically, Fig. 9 and Fig.10 As shown, they are Figure 1 and Figure 8 MOS device breakdown curve and Figure 1 and Figure 8 The conduction curve of the MOS device when Vg = 18V (the horizontal axis is the source-drain voltage V d , the ordinate is the current I d , Vg is the gate voltage), where curve A and curve C are Figure 1 The current of MOS changes with voltage, curve B and curve D are Figure 8 The current of MOS changes with voltage. Figure 1 and Figure 8 The parameters of the substrate, drift region, source region and gate structure of the device are the same. Figure 1 and Figure 8 The distance and doping concentration between two adjacent well regions are the same. Figure 1 The depth of the middle well region is Figure 8 The depth of the contact area is the same. Figure 1 Middle contact area Figure 8 The doping concentration and depth of the ohmic contact region are the same. Figure 8 The distance between the bottom surface of the middle well region and the bottom surface of the contact region is 0.7 μm. Figure 8 The doping concentration in the medium withstand voltage region is Figure 1 The doping concentration in the middle well region is the same. Fig. 9 It can be seen that Figure 8 The MOS device in (MOS device of the present application) is relative to Figure 1 The breakdown voltage of the MOS devices in the Fig.10 It can be seen that Figure 8 The on-resistance ratio of MOS devices Figure 1 The on-resistance of the MOS device in the present application is lower, that is, compared with ordinary MOS devices, the MOS device of the present application ensures the breakdown voltage of the device while reducing the on-resistance of the device, thereby reducing the turn-off loss of the device and the specific on-resistance of the device, and improving the performance of the device.

[0125] Specifically, by improving the structure of the well region 13 and the contact region 15, the breakdown voltage of the device remains unchanged and the on-resistance is reduced when the distance between the well regions is the same, thereby reducing the switching loss of the device and the specific on-resistance of the device.

[0126] The MOS device of this embodiment improves the structure of the well region 13 and the contact region 15 in the device, thereby reducing the on-resistance of the device while ensuring the breakdown voltage of the device, thereby reducing the switching loss and specific on-resistance of the device and improving the performance of the device.

[0127] In summary, the MOS device and its preparation method of the present invention improve the manufacturing process of the device, so that the depth of the formed well region becomes shallower, so that it is only used to protect the source region and form the conductive channel of the device, so that the formed contact region is composed of an ohmic contact region that is in ohmic contact with the source electrode and a voltage-resistant region whose bottom surface is lower than the bottom surface of the well region, and the lateral widening of the depletion region formed between the voltage-resistant region and the drift region and closing in the JEFT region of the device is used to ensure the breakdown resistance of the device; due to the shallowing of the depth of the well region, the JEFT region of the device is relatively increased, thereby further reducing the size of the device, and while reducing the size of the device, it is not necessary to perform ion implantation to regulate the resistance of the JEFT region of the device, simplifying the manufacturing process of the device, reducing the on-resistance of the device, and then reducing the switching loss of the device, reducing the specific on-resistance of the device, and improving the performance of the device. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0128] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a MOS device, characterized in that: The following steps are involved: A semiconductor structure is provided, wherein the semiconductor structure comprises a first conductive type substrate and a first conductive type drift region stacked in sequence; A plurality of second conductive type well regions are formed at intervals on the upper surface of the drift region, and a first conductive type source region is formed in the well region at a preset distance from the sidewall of the well region, wherein the bottom surface of the source region is higher than the bottom surface of the well region; forming a second conductive type contact region penetrating the well region and adjacent to the sidewall of the source region, wherein the bottom surface of the contact region is lower than the bottom surface of the well region; forming a gate structure covering the upper surface of the well region and the drift region between two adjacent source regions in the adjacent well regions and extending along the edge of the well region arrangement direction to above the source region; A source electrode electrically connected to the source region and the contact region is formed, a gate electrode electrically connected to the gate structure is formed, and a drain electrode electrically connected to the substrate is formed.

2. The method for preparing a MOS device according to claim 1, characterized in that: The material of the substrate includes silicon carbide.

3. The method for preparing a MOS device according to claim 1, characterized in that: The distance between the bottom surface of the well region and the upper surface of the drift region ranges from 0.3 μm to 0.7 μm, and the distance between the bottom surface of the well region and the bottom surface of the source region ranges from 0.1 μm to 0.3 μm.

4. The method for preparing a MOS device according to claim 1, characterized in that: The distance between the bottom surface of the contact region and the upper surface of the drift region is in the range of 0.8 μm to 1.5 μm, and the distance between the bottom surface of the contact region and the bottom surface of the well region is in the range of 0.4 μm to 1 μm.

5. The method for preparing a MOS device according to claim 1, characterized in that: The contact region includes a stacked voltage-withstand region and an ohmic contact region.

6. The method for preparing a MOS device according to claim 5, characterized in that: The doping concentration of the ohmic contact region is greater than the doping concentration of the voltage-resistant region, and the upper surface of the voltage-resistant region is higher than the bottom surface of the well region, and the bottom surface of the voltage-resistant region is lower than the bottom surface of the well region.

7. The method for preparing a MOS device according to claim 1, characterized in that: The gate structure includes a gate dielectric layer and a gate conductive layer stacked in sequence, the gate dielectric layer covers the upper surfaces of the well region and the drift region between two adjacent source regions in the adjacent well regions, and the edge of the gate dielectric layer along the arrangement direction of the well regions extends to the upper surface of the source region, and the gate is electrically connected to the gate conductive layer.

8. The method for preparing a MOS device according to claim 1, characterized in that: The device is also provided with an interlayer dielectric layer covering the exposed surface of the gate structure and the exposed upper surface of the drift region, the gate penetrates the interlayer dielectric layer and is electrically connected to the gate structure, and the source penetrates the interlayer dielectric layer and is electrically connected to the source region and the contact region.

9. The method for preparing a MOS device according to claim 1, characterized in that: The doping concentration of the substrate is greater than the doping concentration of the drift region, and the contact type between the drain and the substrate is ohmic contact.

10. A MOS device, characterized in that: include: The semiconductor structure comprises a first conductive type substrate and a first conductive type drift region stacked in sequence; A plurality of well regions of the second conductivity type arranged at intervals and located on the upper surface layer of the drift region; A first conductive type source region, located in the well region and spaced apart from a sidewall of the well region by a preset distance, wherein a bottom surface of the source region is higher than a bottom surface of the well region; A second conductive type contact region, which penetrates the well region and is adjacent to a side wall of the source region, wherein a bottom surface of the contact region is lower than a bottom surface of the well region; A gate structure, covering the well region between two adjacent source regions in the adjacent well regions and the upper surface of the drift region and extending along the edge of the well region arrangement direction to above the source region; A source, a gate and a drain, the source is electrically connected to the source region and the contact region, the gate is electrically connected to the gate structure, and the drain is electrically connected to the substrate.

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