Semiconductor device and electronic device including the same

Abstract

The invention provides a semiconductor device and an electronic apparatus including the same. A semiconductor device includes: a channel layer including a first III-V semiconductor material; a barrier layer provided on an upper surface of the channel layer, the barrier layer including a second III-V semiconductor material different from the first III-V semiconductor material; a plurality of sources / drains spaced apart from each other on an upper surface of the barrier layer; a gate insulating layer covering an upper surface of the barrier layer and upper surfaces of the plurality of sources / drains; a gate electrode provided on an upper surface of the gate insulating layer, the gate electrode not overlapping the plurality of source electrodes / drain electrodes; a plurality of source / drain electrodes electrically connected to corresponding source / drain electrodes among the plurality of source / drain electrodes; and a gate electrode electrically connected to the gate electrode, in which the plurality of source / drain electrodes have a diagonally symmetrical arrangement.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a semiconductor device and an electronic apparatus including the semiconductor device. Background Art

[0002] Various types of power conversion systems require devices that control the flow of current by on / off switching, i.e., power devices. In power conversion systems, the efficiency of power devices can determine the efficiency of the entire system. As switching devices, power metal oxide semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs) using silicon (Si) are generally used, but due to the material limitations of Si itself, there are limitations to improving the efficiency of switching devices. In an attempt to overcome the material limitations of Si, research on high electron mobility transistors (HEMTs) using heterojunction structures of compound semiconductors has been actively conducted.

[0003] However, since HEMTs are mainly III-V semiconductor devices, it is difficult to manufacture HEMTs on a IV semiconductor substrate including Si. Therefore, electronic devices are manufactured by separately manufacturing HEMTs including III-V semiconductors and semiconductor devices including Si, and then wire-bonding the HEMTs and semiconductor devices on a printed circuit board (PCB). This increases the cost and complexity of the manufacturing process. Summary of the invention

[0004] Provided are a III-V semiconductor device having an electrode structure suitable for transfer by a fluid self-assembly (FSA) transfer method and an electronic device including the semiconductor device.

[0005] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments.

[0006] According to one aspect of an embodiment, a semiconductor device includes: a channel layer, including a first III-V semiconductor material; a barrier layer, provided on the upper surface of the channel layer, the barrier layer including a second III-V semiconductor material different from the first III-V semiconductor material; a plurality of source / drains, spaced apart from each other on the upper surface of the barrier layer; a gate insulating layer, covering the upper surface of the barrier layer and the upper surface of the plurality of source / drains; a gate, provided on the upper surface of the gate insulating layer, the gate not overlapping with the plurality of source / drains; a plurality of source / drain electrodes, electrically connected to corresponding source / drains among the plurality of source / drain electrodes; and a gate electrode, electrically connected to the gate, wherein the plurality of source / drain electrodes have a diagonally symmetrical arrangement.

[0007] The multiple source / drain electrodes may include: a first source / drain electrode provided on a first quadrant of the upper surface of the barrier layer; a second source / drain electrode provided on a second quadrant of the upper surface of the barrier layer; a third source / drain electrode provided on a third quadrant of the upper surface of the barrier layer; and a fourth source / drain electrode provided on a fourth quadrant of the upper surface of the barrier layer.

[0008] The first source / drain, the second source / drain, the third source / drain, and the fourth source / drain may not cover a central region of an upper surface of the barrier layer.

[0009] The first source / drain and the fourth source / drain may have shapes that are rotationally symmetric relative to the boundary between the first quadrant and the fourth quadrant, the first source / drain and the second source / drain may have shapes that are rotationally symmetric relative to the boundary between the first quadrant and the second quadrant, the second source / drain and the third source / drain may have shapes that are rotationally symmetric relative to the boundary between the second quadrant and the third quadrant, and the third source / drain and the fourth source / drain may have shapes that are rotationally symmetric relative to the boundary between the third quadrant and the fourth quadrant.

[0010] The semiconductor device may also include: a first conductive layer provided on the upper surface of the gate insulating layer and electrically connected to the first source / drain; a second conductive layer provided on the upper surface of the gate insulating layer and electrically connected to the second source / drain; a third conductive layer provided on the upper surface of the gate insulating layer and electrically connected to the third source / drain; and a fourth conductive layer provided on the upper surface of the gate insulating layer and electrically connected to the fourth source / drain.

[0011] The first conductive layer may be in the vertex region of the first quadrant on the upper surface of the gate insulating layer, the second conductive layer may be in the vertex region of the second quadrant on the upper surface of the gate insulating layer, the third conductive layer may be in the vertex region of the third quadrant on the upper surface of the gate insulating layer, and the fourth conductive layer may be in the vertex region of the fourth quadrant on the upper surface of the gate insulating layer.

[0012] The gate insulating layer may include a plurality of openings exposing a portion of the upper surface of each of the first source / drain, the second source / drain, the third source / drain, and the fourth source / drain, and the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may respectively contact the first source / drain, the second source / drain, the third source / drain, and the fourth source / drain through the plurality of openings.

[0013] The multiple source / drain electrodes may include: a first source / drain electrode electrically connected to the first source / drain; a second source / drain electrode electrically connected to the second source / drain; a third source / drain electrode electrically connected to the third source / drain; and a fourth source / drain electrode electrically connected to the fourth source / drain.

[0014] The gate electrode may be in a central portion of the semiconductor device, the first source / drain electrode and the third source / drain electrode may face each other in a first diagonal direction and be a first distance away from the center of the gate electrode, the second source / drain electrode and the fourth source / drain electrode may face each other in a second diagonal direction and be a second distance away from the center of the gate electrode, the second diagonal direction intersects the first diagonal direction, and the second distance is different from the first distance.

[0015] The gate may include: a central gate disposed in a central portion of an upper surface of the gate insulating layer; and a plurality of branch gates extending between two adjacent source / drain electrodes among the plurality of source / drain electrodes.

[0016] Each of the plurality of branch gates may have a meandering curved shape.

[0017] Each of the plurality of branch gates may have a straight line shape.

[0018] The gate insulating layer may cover sidewalls of the barrier layer and sidewalls of the channel layer.

[0019] Each of the plurality of branch gates may extend along a surface of the gate insulating layer to face a sidewall of the barrier layer and a sidewall of the channel layer.

[0020] The semiconductor device may further include a passivation layer configured to cover the gate insulating layer and the gate, and the gate electrode and the plurality of source / drain electrodes may pass through the passivation layer.

[0021] The multiple sources / drains may include a first source / drain, a second source / drain, and a third source / drain extending in a first direction, and the first source / drain, the second source / drain, and the third source / drain may be arranged sequentially in a second direction perpendicular to the first direction, and the gate may include: a first branch gate extending in the first direction between the first source / drain and the second source / drain; and a second branch gate extending in the first direction between the second source / drain and the third source / drain.

[0022] According to one aspect of the present disclosure, an electronic device includes: a substrate including a first semiconductor material; a first semiconductor device provided on the substrate; and a second semiconductor device provided on the substrate and including a second semiconductor material different from the first semiconductor material, wherein the second semiconductor device includes: a channel layer including a first III-V semiconductor material; a barrier layer provided on an upper surface of the channel layer, the barrier layer including a second III-V semiconductor material different from the first III-V semiconductor material; a plurality of source / drain electrodes spaced apart from each other on the upper surface of the barrier layer; a gate insulating layer covering an upper surface of the barrier layer and an upper surface of the plurality of source / drain electrodes; a gate provided on an upper surface of the gate insulating layer, the gate not overlapping with the plurality of source / drain electrodes; a plurality of source / drain electrodes electrically connected to corresponding source / drain electrodes among the plurality of source / drain electrodes; and a gate electrode electrically connected to the gate, and wherein the plurality of source / drain electrodes have a diagonally symmetrical arrangement.

[0023] The first semiconductor device may be one of a transistor, a light emitting device, and a sensor device.

[0024] The substrate may include a recessed groove in an upper surface of the substrate, and the second semiconductor device may be provided in the groove such that the gate electrode and the plurality of source / drain electrodes face the outside of the groove.

[0025] The gate electrode and the plurality of source / drain electrodes may face an upper surface of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other aspects, features and advantages of certain embodiments will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0027] Figure 1 is a plan view showing an example of an electrode arrangement of a semiconductor device according to an embodiment;

[0028] Figure 2A It is along Figure 1 A schematic cross-sectional view of the structure of the semiconductor device taken along line AA';

[0029] Figure 2B It is along Figure 1 A schematic cross-sectional view of the structure of the semiconductor device taken along line BB';

[0030] Figure 2C It is along Figure 1 A schematic cross-sectional view of the structure of the semiconductor device taken along line CC';

[0031] Figure 3 yes Figure 1 A schematic plan view of an electrode arrangement structure of a semiconductor device shown;

[0032] Figure 4 is a plan view showing an example of the shape of a gate in a semiconductor device according to another embodiment;

[0033] FIG. 5A to FIG. 5L It shows the manufacturing Figure 1 A view showing an example of a process for a semiconductor device is shown;

[0034] 6A to 6F It is shown that by Figure 1 A view showing an example of a process for manufacturing an electronic device by integrating a semiconductor device on a heterogeneous semiconductor substrate;

[0035] Figure 7 is a plan view showing an example of the arrangement of a plurality of electrode pads included in the resulting electronic device;

[0036] FIG. 8A to FIG. 8C It shows that Figure 1 A view showing an example of a process for transferring a semiconductor device by fluid self-assembly (FSA) onto a foreign semiconductor substrate;

[0037] 9A to 9C FIG. 2 is a diagram showing a method for communicating with an electronic device according to an embodiment of the present invention. Figure 1 A view showing examples of various conductive pattern diagrams for electrical connections to the semiconductor device shown;

[0038] Fig.10 is a circuit diagram showing an example of an equivalent circuit of an electronic device according to an embodiment;

[0039] Fig.11A and Fig. 11B is a view showing an example of a process of manufacturing an electronic device by transferring a semiconductor device onto a heterogeneous semiconductor substrate via a separate transfer substrate;

[0040] Fig.12 is a plan view showing an example of an electrode arrangement of a semiconductor device according to another embodiment; and

[0041] Fig.13A and Fig. 13B It is shown in the included Fig.12 A view showing an example of a conductor pattern for electrically connecting a semiconductor device in an electronic device of the semiconductor device shown. DETAILED DESCRIPTION

[0042] Now will refer to the embodiment in detail, examples of which are shown in the accompanying drawings, wherein the same reference numerals always represent the same elements. In this respect, the current embodiment may have different forms and should not be construed as being limited to the description set forth herein. Therefore, the following only describes the embodiment to explain various aspects by referring to the accompanying drawings. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. Statements such as "at least one of ..." modify the entire column of elements when following a column of elements, rather than modifying individual elements in the list.

[0043] Hereinafter, a semiconductor device and an electronic device including the semiconductor device will be described in detail with reference to the accompanying drawings. In the following drawings, the same reference numerals represent the same elements, and for ease of description, the size of each element in the drawings may be exaggerated. In addition, the embodiments described below are merely illustrative, and various modifications may be made from these embodiments.

[0044] Hereinafter, when an element is referred to as being "on," "over," or "above" another element, it may be directly on the other element in contact with the other element, or indirectly on or above the other element without contacting the other element. Unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" as used herein are intended to include the plural forms as well. In addition, it will be understood that when a part is referred to as "comprising" another element, unless otherwise described, additional elements may not be excluded, but may also be included.

[0045] The use of the term "the" and similar reference terms may refer to both singular and plural statements. Unless an order is specifically stated or stated to the contrary, the operations constituting the method may be performed in any suitable order and are not necessarily limited to the order specified.

[0046] In addition, the term “… device / unit” or “module” used herein refers to a unit that processes at least one operation function, which can be implemented as hardware or software, or as a combination of hardware and software.

[0047] The wiring connections or connecting means between elements shown in the drawings illustratively represent functional connections and / or physical or circuit connections, and in actual devices they may present various types of alternative or additional functional, physical or circuit connections.

[0048] All examples or illustrative terms are used only to explain the technical ideas in detail, and the scope of the present disclosure is not limited by the examples or illustrative terms unless limited by the claims.

[0049] Figure 1 is a plan view showing an example of an electrode arrangement of a semiconductor device according to an embodiment, Figure 2A It is along Figure 1 A schematic cross-sectional view of the structure of the semiconductor device taken along line AA' of Figure 2B It is along Figure 1 A schematic cross-sectional view of the structure of the semiconductor device taken along line BB' of Figure 2C It is along Figure 1 1 is a schematic cross-sectional view of the structure of the semiconductor device taken along the line CC' of FIG. 1 to illustrate the arrangement relationship between the plurality of source / drain electrodes 105a, 105b, 105c and 105d, the plurality of conductive layers 107a, 107b, 107c and 107d, the plurality of source / drain electrodes 109a, 109b, 109c and 109d, the gate 110 and the gate electrode 111 (all of which will be described below), Figure 1 It is shown assuming that the gate insulating layer 106 and the passivation layer 108 (which will be described below) are transparent for the convenience of description. However, the gate insulating layer 106 and the passivation layer 108 do not actually need to be transparent.

[0050] Reference Figure 1 , Figure 2A , Figure 2B and Figure 2C According to an embodiment, a semiconductor device 100 may include: a substrate 101; a buffer layer 102 provided on the substrate 101; a channel layer 103 provided on the buffer layer 102; a barrier layer 104 provided on the channel layer 103; a plurality of source / drain electrodes 105a, 105b, 105c and 105d provided on the barrier layer 104; a gate insulating layer 106 provided to cover a surface of the channel layer 103 and a surface of the barrier layer 104; a gate 110 provided on the gate insulating layer 106; a plurality of conductive layers 107a, 107b, 107c and 107d provided on the gate insulating layer 106; 06 to be electrically connected to the multiple source / drain electrodes 105a, 105b, 105c and 105d respectively; a passivation layer 108 is provided to cover the gate insulating layer 106, the gate 110 and the multiple conductive layers 107a, 107b, 107c and 107d to protect the semiconductor device 100; multiple source / drain electrodes 109a, 109b, 109c and 109d are provided to be electrically connected to the multiple conductive layers 107a, 107b, 107c and 107d respectively through the passivation layer 108; and a gate electrode 111 is provided to be electrically connected to the gate 110 through the passivation layer 108.

[0051] The semiconductor device 100 may include a Group III-V semiconductor device including a Group III-V semiconductor material. For example, the semiconductor device 100 may include a high electron mobility transistor (HEMT).

[0052] The substrate 101 may be a growth substrate for manufacturing the semiconductor device 100 . Figure 2A The substrate 101 shown can be removed before the fluid self-assembly (FSA) transfer of the semiconductor device 100 described below. To this end, the substrate 101 may include a material that can be easily separated from the buffer layer 102 by using a chemical stripping method or a laser stripping method. For example, the substrate 101 may include at least one of sapphire and silicon (Si), but is not limited thereto. The substrate 101 may also be various other materials that can be chemically stripped or laser stripped. When the substrate 101 is separated using a chemical stripping or laser stripping method, the lower surface of the semiconductor device 100 (i.e., the lower surface of the buffer layer 102) can be in a very smooth and flat state.

[0053] The buffer layer 102 may be provided to prevent the crystallinity of the channel layer 103 from being degraded by alleviating the difference in lattice constant and thermal expansion coefficient between the substrate 101 and the channel layer 103. The buffer layer 102 may have a single-layer or multi-layer structure including one or more materials selected from group III-V materials (e.g., nitrides including at least one of aluminum (Al), gallium (Ga), and indium (In)). The buffer layer 102 may be Al x In y Ga 1-x-y N(0≤x≤1, 0≤y≤1, x+y≤1). The buffer layer 102 may have a single layer or multilayer structure including at least one of aluminum nitride (AlN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum indium nitride (AlInN), and aluminum gallium indium nitride (AlGaInN). In addition, if necessary, a seed layer for growing the buffer layer 102 may be further provided between the substrate 101 and the buffer layer 102.

[0054] The channel layer 103 may be a layer forming a channel between the source and the drain, and may include a material capable of generating a two-dimensional electron gas (2DEG) therein. The channel layer 103 may have a single layer or a multilayer including one or more materials selected from III-V group materials (e.g., nitrides including at least one of Al, Ga, and In). The channel layer 103 may be Al x In y Ga 1-x-y N (0≤x≤1, 0≤y≤1, x+y≤1). For example, the channel layer 103 may include at least one material among GaN, AlN, indium nitride (InN), InGaN, AlGaN, AlInN, and aluminum indium gallium nitride (AlInGaN). The channel layer 103 may be an undoped layer or a layer doped with impurities. The thickness of the channel layer 103 may be several hundred nm or less.

[0055] The barrier layer 104 may include a III-V semiconductor material different from the semiconductor material of the channel layer 103. For example, the barrier layer 104 may be different from the channel layer 103 in at least one of polarization characteristics, energy band gap, and lattice constant. The barrier layer 104 may include a material having a larger energy band gap than the energy band gap of the channel layer 103. For example, the barrier layer 104 may have a multilayer structure including one or more materials selected from III-V semiconductor materials (e.g., nitrides including at least one of Al, Ga, and In). The barrier layer 104 may be, for example, Al x In y Ga 1-x-y N (0≤x≤1, 0≤y≤1, x+y≤1), and may include at least one material among GaN, InN, AlGaN, AlInN, InGaN, AlN, and AlInGaN. The energy band gap of the barrier layer 104 may be adjusted by the composition ratio of Al and / or In.

[0056] The barrier layer 104 may be doped with specific impurities. The impurities may be p-type dopants that can provide holes. For example, magnesium (Mg) may be used as a p-type dopant. The doping concentration of the barrier layer 104 may be set to obtain a predetermined threshold voltage and on-resistance.

[0057] The barrier layer 104 may have a relatively larger band gap than the band gap of the channel layer 103, and may have an electric susceptibility higher than the electric susceptibility of the channel layer 103. Therefore, the barrier layer 104 may induce 2DEG in the channel layer 103, and the channel layer 103 may have a relatively low electric susceptibility. In this regard, the barrier layer 104 may also be referred to as a channel supply layer or a 2DEG supply layer. 2DEG may be formed in a region of the channel layer 103 below the interface between the channel layer 103 and the barrier layer 104. 2DEG exhibits very high electron mobility.

[0058] Therefore, the region of the channel layer 103 facing the barrier layer 104 becomes a drift region. The drift region may be a region formed in the channel layer 103 between the source and the drain, and may be a region where carrier movement occurs when a potential difference is generated between the source and the drain. The carrier movement in the drift region may be allowed / blocked or controlled according to the magnitude of the voltage applied to the gate 110.

[0059] exist Figure 2A , the barrier layer 104 is shown as a single layer, but may include a plurality of layers. The barrier layer 104 may include, for example, a plurality of layers having different energy band gaps, and the plurality of layers may be arranged such that the energy band gap of a layer closer to the channel layer 103 among the plurality of layers is larger.

[0060] The plurality of source / drain electrodes 105a, 105b, 105c, and 105d including a conductive metal may be provided on the upper surface of the barrier layer 104 and spaced apart from each other. Figure 1 , four source / drain electrodes 105a, 105b, 105c, and 105d are shown. For example, the semiconductor device 100 may include a first source / drain electrode 105a, a second source / drain electrode 105b, a third source / drain electrode 105c, and a fourth source / drain electrode 105d. However, the number of source / drain electrodes 105a, 105b, 105c, and 105d is not limited thereto, and three or more source / drain electrodes may be selected.

[0061] The upper surface of the barrier layer 104 may have a square shape. The first to fourth source / drain electrodes 105a, 105b, 105c, and 105d may be respectively arranged in four quadrant regions on the upper surface of the barrier layer 104. For example, the first source / drain electrode 105a, the second source / drain electrode 105b, the third source / drain electrode 105c, and the fourth source / drain electrode 105d may be respectively arranged in the first quadrant region, the second quadrant region, the third quadrant region, and the fourth quadrant region on the upper surface of the barrier layer 104.

[0062] In addition, if Figure 1As shown, the first to fourth source / drain electrodes 105a, 105b, 105c and 105d may be arranged to avoid the central region, the regions near the four vertices and the region between two adjacent quadrant regions on the upper surface of the barrier layer 104. For example, the first source / drain electrode 105a may be arranged to cover the region on the first quadrant region of the upper surface of the barrier layer 104, except for the central region on the upper surface of the barrier layer 104, the region near the vertices of the first quadrant region, the boundary region between the first quadrant region and the fourth quadrant region, and the boundary region between the first quadrant region and the second quadrant region. The second source / drain electrode 105b may be arranged to cover the region on the second quadrant region of the upper surface of the barrier layer 104, except for the central region on the upper surface of the barrier layer 104, the region near the vertices of the second quadrant region, the boundary region between the second quadrant region and the third quadrant region, and the boundary region between the second quadrant region and the first quadrant region. The third source / drain 105c may be arranged to cover an area on the third quadrant region of the upper surface of the barrier layer 104, except for a central area on the upper surface of the barrier layer 104, an area near the apex of the third quadrant region, a boundary area between the third quadrant region and the second quadrant region, and a boundary area between the third quadrant region and the fourth quadrant region. The fourth source / drain 105d may be arranged to cover an area on the fourth quadrant region of the upper surface of the barrier layer 104, except for a central area on the upper surface of the barrier layer 104, an area near the apex of the fourth quadrant region, a boundary area between the fourth quadrant region and the first quadrant region, and a boundary area between the fourth quadrant region and the third quadrant region.

[0063] In addition, two adjacent sources / drains among the first to fourth source / drains 105a, 105b, 105c and 105d may be rotationally symmetrical with respect to the boundary between them. For example, the first source / drain 105a and the fourth source / drain 105d may have a shape that is rotationally symmetrical with respect to the boundary between the first quadrant region and the fourth quadrant region. The first source / drain 105a and the second source / drain 105b may have a shape that is rotationally symmetrical with respect to the boundary between the first quadrant region and the second quadrant region. The second source / drain 105b and the third source / drain 105c may have a shape that is rotationally symmetrical with respect to the boundary between the second quadrant region and the third quadrant region. The third source / drain 105c and the fourth source / drain 105d may have a shape that is rotationally symmetrical with respect to the boundary between the third quadrant region and the fourth quadrant region. Furthermore, the first to fourth source / drains 105 a , 105 b , 105 c , and 105 d may have rotationally symmetrical shapes with respect to the center of the semiconductor device 100 when viewed from the top.

[0064] The gate insulating layer 106 may be provided to cover the upper surface of the barrier layer 104. The gate insulating layer 106 may include, for example, silicon oxide (SiO 2 ), hafnium oxide (HfO x ) and aluminum oxide (Al 2 O 3 ) is at least one oxide material, but is not limited thereto. The gate insulating layer 106 may extend to cover a portion of the sidewalls of the barrier layer 104, the sidewalls of the channel layer 103, and the sidewalls of the buffer layer 102. In addition, the gate insulating layer 106 may be provided to cover the sidewalls and upper surfaces of the first to fourth source / drain electrodes 105a, 105b, 105c, and 105d. For electrical connection between the conductive layers 107a, 107b, 107c, and 107d to be described below and the first to fourth source / drain electrodes 105a, 105b, 105c, and 105d, as Figure 2A As shown, the gate insulating layer 106 may be removed from a portion of the first to fourth source / drain electrodes 105a, 105b, 105c, and 105d. For example, a portion of the upper surface of the first to fourth source / drain electrodes 105a, 105b, 105c, and 105d may be exposed and not covered by the gate insulating layer 106. However, the remaining areas of the upper surfaces of the first to fourth source / drain electrodes 105a, 105b, 105c, and 105d may be covered by the gate insulating layer 106, as shown in FIG. Figure 2B shown.

[0065] A gate 110 including a conductive metal may be provided on the gate insulating layer 106. Figure 1As shown, when viewed from the top, the gate 110 may be arranged on the upper surface of the gate insulating layer 106 without overlapping the first to fourth source / drain electrodes 105a, 105b, 105c, and 105d. In addition, the gate 110 may include a central gate 110e arranged in the central portion of the semiconductor device 100 or in the central portion of the upper surface of the gate insulating layer 106, and a plurality of branch gates 110a, 110b, 110c, and 110d extending from the central gate 110e to between two adjacent source / drain electrodes among the first to fourth source / drain electrodes 105a, 105b, 105c, and 105d. For example, the gate 110 may include: a first branch gate 110a, extending in a serpentine curve from the central gate 110e to between the first source / drain 105a and the second source / drain 105b or along the boundary between the first quadrant region and the second quadrant region; a second branch gate 110b, extending in a serpentine curve from the central gate 110e to between the second source / drain 105b and the third source / drain 105c or along the boundary between the second quadrant region and the third quadrant region; a third branch gate 110c, extending in a serpentine curve from the central gate 110e to between the third source / drain 105c and the fourth source / drain 105d or along the boundary between the third quadrant region and the fourth quadrant region; and a fourth branch gate 110d, extending in a serpentine curve from the central gate 110e to between the first source / drain 105a and the fourth source / drain 105d or along the boundary between the first quadrant region and the fourth quadrant region. A width of each of the first to fourth branch gates 110 a , 110 b , 110 c , and 110 d may be smaller than a width of the central gate 110 e .

[0066] When the first to fourth branch gates 110a, 110b, 110c, and 110d have a meandering shape, the surface area of ​​each of the first to fourth branch gates 110a, 110b, 110c, and 110d can be larger than when the first to fourth branch gates 110a, 110b, 110c, and 110d have a straight line shape. Therefore, the current injection efficiency can be improved, and thus the operating characteristics of the semiconductor device 100 can be improved. In addition, even when the semiconductor device 100 is manufactured to a small size with a side length of 100 μm or less, the operating characteristics of the semiconductor device 100 are not deteriorated.

[0067] Reference Figure 1 and Figure 2C , an end portion of each of the first to fourth branch gates 110a, 110b, 110c, and 110d of the gate 110 may laterally protrude further than the sidewalls of the gate insulating layer 106, the barrier layer 104, and the channel layer 103. For example, Figure 2CAs shown, one end of the second branch gate 110b may extend along the surface of the gate insulating layer 106 to face the sidewall of the barrier layer 104 and the sidewall of the channel layer 103. Figure 2C In the cross-sectional view of FIG. 1 , only the end of the second branch gate 110b can be seen, but like the second branch gate 110b, the ends of the first branch gate 110a, the third branch gate 110c, and the fourth branch gate 110d can also extend along the surface of the gate insulating layer 106 to face the sidewalls of the barrier layer 104 and the channel layer 103. Because the gate 110 including the first to fourth branch gates 110a, 110b, 110c, and 110d extends to the sidewalls of the barrier layer 104 and the channel layer 103 without directly contacting the barrier layer 104, the on / off control performance of the semiconductor device 100 due to the gate 110 can be further improved.

[0068] In addition, the plurality of conductive layers 107a, 107b, 107c, and 107d including a conductive metal may be provided on the upper surface of the gate insulating layer 106. The plurality of conductive layers 107a, 107b, 107c, and 107d may be spaced apart from each other. When viewed from the top, the plurality of conductive layers 107a, 107b, 107c, and 107d may be arranged in an area near four vertices of the upper surface of the gate insulating layer 106 without overlapping the gate 110 including the central gate 110e and the first to fourth branch gates 110a, 110b, 110c, and 110d. For example, the first conductive layer 107a may be arranged in the vertex region of the first quadrant region on the upper surface of the gate insulating layer 106, the second conductive layer 107b may be arranged in the vertex region of the second quadrant region on the upper surface of the gate insulating layer 106, the third conductive layer 107c may be arranged in the vertex region of the third quadrant region on the upper surface of the gate insulating layer 106, and the fourth conductive layer 107d may be arranged in the vertex region of the fourth quadrant region on the upper surface of the gate insulating layer 106.

[0069] The first to fourth conductive layers 107a, 107b, 107c, and 107d may be electrically connected to corresponding source / drain electrodes among the first to fourth source / drain electrodes 105a, 105b, 105c, and 105d. For example, the first conductive layer 107a may be electrically connected to the first source / drain electrode 105a, the second conductive layer 107b may be electrically connected to the second source / drain electrode 105b, the third conductive layer 107c may be electrically connected to the third source / drain electrode 105c, and the fourth conductive layer 107d may be electrically connected to the fourth source / drain electrode 105d.

[0070] Reference Figure 2A, the fourth conductive layer 107d may extend to contact a portion of the upper surface of the fourth source / drain 105d that is exposed and not covered by the gate insulating layer 106, and the third conductive layer 107c may extend to contact a portion of the upper surface of the third source / drain 105c that is exposed and not covered by the gate insulating layer 106. Similarly, the first conductive layer 107a and the second conductive layer 107b may extend to contact a portion of the first source / drain 105a and a portion of the second source / drain 105b, respectively. When viewed from the top, the first to fourth conductive layers 107a, 107b, 107c, and 107d may overlap with the corresponding source / drain in the region contacting the corresponding source / drain among the first to fourth source / drain 105a, 105b, 105c, and 105d, respectively.

[0071] The passivation layer 108 may include SiO 2 , HfO x and Al 2 O 3 At least one oxide material thereof, but not limited thereto. The passivation layer 108 may be provided to cover the gate insulating layer 106, the gate 110, and the first to fourth conductive layers 107a, 107b, 107c, and 107d. In addition, the passivation layer 108 may extend along the surface of the gate insulating layer 106 to cover a portion of the sidewalls of the barrier layer 104, the sidewalls of the channel layer 103, and the sidewalls of the buffer layer 102.

[0072] The plurality of source / drain electrodes 109a, 109b, 109c, and 109d and the gate electrode 111 may be provided through the passivation layer 108 and electrically connected to the first to fourth conductive layers 107a, 107b, 107c, and 107d and the gate 110, respectively, under the passivation layer 108. For example, the first source / drain electrode 109a may be provided through the passivation layer 108 and electrically connected to the first conductive layer 107a, the second source / drain electrode 109b may be provided through the passivation layer 108 and electrically connected to the second conductive layer 107b, the third source / drain electrode 109c may be provided through the passivation layer 108 and electrically connected to the third conductive layer 107c, and the fourth source / drain electrode 109d may be provided through the passivation layer 108 and electrically connected to the fourth conductive layer 107d. The first to fourth source / drain electrodes 109a, 109b, 109c, and 109d may be electrically connected to corresponding sources / drains among the first to fourth source / drain electrodes 105a, 105b, 105c, and 105d through the first to fourth conductive layers 107a, 107b, 107c, and 107d, respectively. In other words, the first source / drain electrode 109a may be electrically connected to the first source / drain 105a through the first conductive layer 107a, the second source / drain electrode 109b may be electrically connected to the second source / drain 105b through the second conductive layer 107b, the third source / drain electrode 109c may be electrically connected to the third source / drain 105c through the third conductive layer 107c, and the fourth source / drain electrode 109d may be electrically connected to the fourth source / drain 105d through the fourth conductive layer 107d. In addition, a gate electrode 111 may be provided to pass through the passivation layer 108 and be electrically connected to the gate 110.

[0073] The semiconductor device 100 having the above structure can be manufactured into a small size with a side length of 100 μm or less. The semiconductor device 100 having such a small size can be transferred in large quantities to another semiconductor substrate or a heat dissipation substrate having a large area by FSA transfer. To this end, the semiconductor device 100 can have a symmetrical electrode arrangement structure suitable for FSA transfer.

[0074] Figure 3 yes Figure 1 FIG. 1 is a schematic plan view of an electrode arrangement structure of a semiconductor device 100 shown in FIG. Figure 3, when viewed from the top, the gate electrode 111 may be arranged at a central region of the semiconductor device 100 or a central region of the passivation layer 108. In addition, when viewed from the top, two source / drain electrodes diagonally facing each other among the first to fourth source / drain electrodes 109a, 109b, 109c, and 109d may be arranged at the same distance from the center of the semiconductor device 100, the center of the passivation layer 108, or the center of the gate electrode 111. For example, the first source / drain electrode 109a and the third source / drain electrode 109c facing each other in a first diagonal direction may be arranged at a first distance d1 from the center of the semiconductor device 100, the center of the passivation layer 108, or the center of the gate electrode 111, and the second source / drain electrode 109b and the fourth source / drain electrode 109d facing each other in a second diagonal direction intersecting the first diagonal direction may be arranged at a second distance d2 from the center of the semiconductor device 100, the center of the passivation layer 108, or the center of the gate electrode 111.

[0075] In addition, source / drain electrodes that do not diagonally face each other among the first to fourth source / drain electrodes 109a, 109b, 109c, and 109d may be arranged at different distances from the center of the semiconductor device 100, the center of the passivation layer 108, or the center of the gate electrode 111. For example, a first distance d1 from the center of the semiconductor device 100, the center of the passivation layer 108, or the center of the gate electrode 111 to the first source / drain electrode 109a or the third source / drain electrode 109c may be different from a second distance d2 from the center of the semiconductor device 100, the center of the passivation layer 108, or the center of the gate electrode 111 to the second source / drain electrode 109b or the fourth source / drain electrode 109d. In this regard, it can be seen that the first to fourth source / drain electrodes 109a, 109b, 109c, and 109d and the gate electrode 111 have a symmetrical arrangement structure in a diagonal direction relative to the center of the semiconductor device 100, the center of the passivation layer 108, or the center of the gate electrode 111 when viewed from the top.

[0076] Figure 4 1 is a plan view showing an example of the shape of the gate 110 in the semiconductor device 100 according to another embodiment. Figure 1 , the first to fourth branch gates 110a, 110b, 110c and 110d of the gate 110 have been shown to extend from the central gate 110e in a meandering curve, but the shapes of the first to fourth branch gates 110a, 110b, 110c and 110d are not limited thereto. Figure 4 In another embodiment, the first to fourth branch gates 110 a , 110 b , 110 c , and 110 d may extend in straight lines.

[0077] FIG. 5A to FIG. 5L It shows the manufacturing Figure 1A diagram illustrating an example of a process for a semiconductor device 100 is shown.

[0078] Reference Figure 5A , a buffer layer 102, a channel layer 103 and a barrier layer 104 may be sequentially grown on the upper surface of the substrate 101. The substrate 101 may include at least one of sapphire and Si, but is not limited thereto. The buffer layer 102 may include, for example, at least one of AlN, GaN, AlGaN, InGaN, AlInN and AlGaInN, and the channel layer 103 may include, for example, at least one material among GaN, AlN, InN, InGaN, AlGaN, AlInN and AlInGaN. The barrier layer 104 may include at least one material among GaN, InN, AlGaN, AlInN, InGaN, AlN and AlInGaN having a larger band gap than the band gap of the channel layer 103. Although for ease of description, Figure 5A The process of manufacturing a single semiconductor device 100 is shown, but in fact, multiple semiconductor devices 100 can be manufactured at one time on a large-area substrate 101. After growing the barrier layer 104, a mesa structure can be formed by partially etching the barrier layer 104 and the channel layer 103 to isolate from the area where other adjacent semiconductor devices are to be formed. The barrier layer 104 and the channel layer 103 retained after etching can be completely separated from the barrier layer 104 and the channel layer 103 in the area where other adjacent semiconductor devices are to be formed. During the etching process, the upper surface of the buffer layer 102 can also be partially removed, and a portion of the upper surface of the buffer layer 102 can be exposed to the outside along the edge.

[0079] Reference Figure 5B and Figure 5C , first to fourth source / drain electrodes 105a, 105b, 105c and 105d that may be spaced apart from each other may be formed on the upper surface of the barrier layer 104. Figure 5C As shown, the first to fourth source / drain electrodes 105a, 105b, 105c, and 105d may be arranged in the first quadrant region, the second quadrant region, the third quadrant region, and the fourth quadrant region on the upper surface of the barrier layer 104, respectively. In addition, the first to fourth source / drain electrodes 105a, 105b, 105c, and 105d may be arranged to avoid the central region, the regions near the four vertices, and the region between two adjacent quadrant regions on the upper surface of the barrier layer 104. For example, the first to fourth source / drain electrodes 105a, 105b, 105c, and 105d may be formed by depositing a conductive metal to completely cover the barrier layer 104, and then patterning the conductive metal into Figure 5C To be formed in the form shown.

[0080] Reference Figure 5D, a gate insulating layer 106 may be formed to cover the barrier layer 104 and the first to fourth source / drain electrodes 105a, 105b, 105c, and 105d. For example, the gate insulating layer 106 may be formed by depositing SiO 2 , HfO x and Al 2 O 3 The gate insulating layer 106 may be formed to cover the sidewalls of the barrier layer 104 , the sidewalls of the channel layer 103 , and the exposed upper surface of the buffer layer 102 .

[0081] Reference Figure 5E , a plurality of openings 106h can be formed through the gate insulating layer 106 by etching a portion of the gate insulating layer 106 covering the first to fourth source / drain electrodes 105a, 105b, 105c, and 105d. A portion of the upper surface of each of the first to fourth source / drain electrodes 105a, 105b, 105c, and 105d can be exposed to the outside through the plurality of openings 106h of the gate insulating layer 106. Although Figure 5E Only the third source / drain 105c and the fourth source / drain 105d are shown, but the openings 106h may also be formed on the upper surfaces of the first source / drain 105a and the second source / drain 105b, respectively.

[0082] Reference Fig. 5F and Figure 5G , the first to fourth conductive layers 107a, 107b, 107c and 107d (which may be spaced apart from each other) and the gate 110 may be simultaneously formed on the upper surface of the gate insulating layer 106. Figure 5G As shown, the first to fourth conductive layers 107a, 107b, 107c and 107d may be arranged in the vertex region of the first quadrant region, the vertex region of the second quadrant region, the vertex region of the third quadrant region and the vertex region of the fourth quadrant region on the upper surface of the gate insulating layer 106, respectively. A portion of each of the first to fourth conductive layers 107a, 107b, 107c and 107d may extend over the opening 106h of the gate insulating layer 106 to be electrically connected to the corresponding source / drain among the first to fourth source / drain 105a, 105b, 105c and 105d. Therefore, the first to fourth conductive layers 107a, 107b, 107c and 107d may contact the corresponding source / drain among the first to fourth source / drain 105a, 105b, 105c and 105d through the opening 106h.

[0083] The gate 110 may be formed to have a central gate 110e and first to fourth branch gates 110a, 110b, 110c, and 110d extending from the central gate 110e. The central gate 110e may be formed in the central portion of the upper surface of the gate insulating layer 106, and the first to fourth branch gates 110a, 110b, 110c, and 110d may be formed to extend between two adjacent source / drain electrodes among the first to fourth source / drain electrodes 105a, 105b, 105c, and 105d. When viewed from the top, the central gate 110e and the first to fourth branch gates 110a, 110b, 110c, and 110d may be formed not to overlap with the first to fourth conductive layers 107a, 107b, 107c, and 107d.

[0084] For example, the first to fourth conductive layers 107a, 107b, 107c and 107d, the central gate 110e and the first to fourth branch gates 110a, 110b, 110c and 110d can be formed by depositing a conductive metal to completely cover the gate insulating layer 106 and then patterning the conductive metal as follows: Figure 5G Therefore, the first to fourth conductive layers 107a, 107b, 107c and 107d and the gate 110 may be formed of the same conductive metal material at the same time.

[0085] Reference Figure 5H , a portion of the edge of the buffer layer 102 may be further etched to further isolate it from the area where other adjacent semiconductor devices are to be formed. During this process, the edge of the gate insulating layer 106 may also be partially etched. Thus, the edge region of the buffer layer 102 may have a stepped shape. The outermost edge region of the buffer layer 102 may not be covered by the gate insulating layer 106, and the inner edge region inside the outermost edge region may be covered by the gate insulating layer 106.

[0086] Reference Fig.5I The passivation layer 108 may be formed to cover the gate insulating layer 106, the gate 110, and the first to fourth conductive layers 107a, 107b, 107c, and 107d. The passivation layer 108 may be formed by depositing, for example, SiO 2 , HfO x and Al 2 O 3 The passivation layer 108 may be formed along the surface of the gate insulating layer 106 to cover the sidewalls of the barrier layer 104 , the sidewalls of the channel layer 103 , and the edge region of the buffer layer 102 .

[0087] Reference Figure 5J, an opening 108h that completely passes through the passivation layer 108 can be formed by etching a portion of the passivation layer 108 that covers the first to fourth conductive layers 107a, 107b, 107c, and 107d. A portion of the upper surface of the first to fourth conductive layers 107a, 107b, 107c, and 107d can be exposed to the outside through the opening 108h of the passivation layer 108. Figure 5J Only one opening 108h exposing the fourth conductive layer 107d is shown in FIG. 1 , but the opening 108h may also be formed on the upper surfaces of the first to third conductive layers 107a, 107b, and 107c. The position of the opening 108h may be the same as that of the reference Figure 3 The positions of the first to fourth source / drain electrodes 109 a , 109 b , 109 c , and 109 d are described to be the same.

[0088] Reference Figure 5K , the first to fourth source / drain electrodes 109a, 109b, 109c, and 109d can be formed by filling the opening 108h of the passivation layer 108 with a conductive metal. Figure 5K Only the fourth source / drain electrode 109d is shown in the figure, but the first to third source / drain electrodes 109a, 109b and 109c may be formed simultaneously to fill the opening 108h of the passivation layer 108. Portions of the first to fourth source / drain electrodes 109a, 109b, 109c and 109d may also protrude above the upper surface of the passivation layer 108 and extend laterally along the upper surface of the passivation layer 108.

[0089] Reference Figure 5L , the plurality of semiconductor devices 100 may be separated from each other by further etching the substrate 101 .

[0090] The semiconductor device 100 can be used, for example, as a power amplification element or switch in a high-power RF system including a radar system and a communication system, and various other electronic devices. As described above, the semiconductor device 100 can be a III-V semiconductor device including a III-V semiconductor material. In addition, an electronic device to which the semiconductor device 100 will be applied can be manufactured on a IV semiconductor substrate (such as Si). Since it may be difficult to directly grow both a III-V semiconductor device and a IV semiconductor device on a IV semiconductor substrate, the semiconductor device 100 can be transferred to a IV semiconductor substrate by using an FSA transfer method.

[0091] 6A to 6F It is shown that by Figure 1 The illustrated diagram is a diagram of an example of a process in which a semiconductor device 100 is integrated on a heterogeneous semiconductor substrate to manufacture an electronic device.

[0092] Reference Fig. 6A, the electronic device 200 may include a first substrate 201, a second substrate 202 provided on an upper surface of the first substrate 201, and a first semiconductor device 200TR on the second substrate 202. The first substrate 201 may be a silicon-on-insulator (SOI) substrate including a semiconductor layer 201a and an insulating layer 201b provided on an upper surface of the semiconductor layer 201a. The second substrate 202 may include a first semiconductor material. For example, the first semiconductor material may include a Group IV semiconductor material such as Si or germanium. The semiconductor layer 201a and the second substrate 202 may be, for example, a Group IV semiconductor substrate including a Group IV semiconductor material such as Si or germanium. The insulating layer 201b may include, for example, SiO 2 Or silicon nitride (SiN). Fig. 6A , it is shown that the electronic device 200 can be formed on the SOI substrate, and the electronic device 200 can be manufactured by using a bulk silicon substrate instead of the SOI substrate. For example, the electronic device 200 can include only the second substrate 202 without including the first substrate 201.

[0093] The first semiconductor device 200TR may be a field effect transistor. For example, the first semiconductor device 200TR may include a source region 203 arranged on the second substrate 202, a drain region 204 arranged on the second substrate 202 and spaced apart from the source region 203, a channel layer 205 between the source region 203 and the drain region 204, a gate insulating layer 208 provided on the upper surface of the channel layer 205, a gate electrode 209 provided on the upper surface of the gate insulating layer 208, a source electrode 206 provided on the upper surface of the source region 203, and a drain electrode 207 provided on the upper surface of the drain region 204. The source region 203 and the drain region 204 may be formed by doping the upper portion of the second substrate 202. The first semiconductor device 200TR may be a group IV semiconductor device provided on a group IV semiconductor substrate and including a group IV semiconductor material.

[0094] Reference Figure 6B , the groove 202h may be concavely formed by partially etching a portion of the upper surface of the second substrate 202 adjacent to the first semiconductor device 200TR. In this case, the insulating layer 201b of the first substrate 201 may be used as an etching stop layer. The upper surface of the insulating layer 201b of the first substrate 201 may be partially etched through the groove 202h.

[0095] Reference Figure 6C , an insulating layer 210 may be formed to cover the first semiconductor device 200TR, the upper surface of the second substrate 202, and the inner wall and bottom surface of the groove 202h. The insulating layer 210 may include an insulating material having a hydrophilic property. The insulating layer 210 may be formed by depositing, for example, SiO 2 , HfOx and Al 2 O 3 The at least one oxide material is formed to a uniform thickness. The inner wall of the groove 202h may be the inside of the second substrate 202 exposed by the groove 202h, and the bottom surface of the groove 202h may be the upper surface of the insulating layer 201b exposed by the groove 202h.

[0096] In addition, a portion of the insulating layer 210 may be etched so that the upper surfaces of the source electrode 206, the drain electrode 207, and the gate electrode 209 of the first semiconductor device 200TR may be partially exposed. For example, a plurality of openings 210h that completely pass through the insulating layer 210 may be formed by etching the portion of the insulating layer 210 that covers the source electrode 206, the drain electrode 207, and the gate electrode 209.

[0097] Reference Fig.6D , you can transfer Figure 1 The semiconductor device 100 shown is transferred into the groove 202h. Hereinafter, the semiconductor device 100 will be referred to as the second semiconductor device 100 to identify it with the first semiconductor device 200TR. The second semiconductor device 100 may include a second semiconductor material different from the first semiconductor material. For example, the second semiconductor material may include a III-V semiconductor material such as AlN, GaN, AlGaN, InGaN, AlInN, and AlGaInN. Before FSA transfer, the semiconductor device 100 may be preliminarily removed from the groove 202h by using a chemical lift-off or laser lift-off method. Figure 1 The second semiconductor device 100 shown removes the substrate 101. Thus, the lower surface of the second semiconductor device 100 becomes the lower surface of the buffer layer 102. The lower surface of the buffer layer 102 separated by using a chemical stripping or laser stripping method can have a very smooth and flat surface and can have a hydrophilic property. On the contrary, the upper surface of the second semiconductor device 100 on which the gate electrode 111 and the first to fourth source / drain electrodes 109a, 109b, 109c and 109d are formed can have a hydrophobic property. Therefore, during the FSA transfer process, when the buffer layer 102 of the second semiconductor device 100 faces the bottom surface of the groove 202h, the second semiconductor device 100 can be easily disposed in the groove 202h. However, when the gate electrode 111 and the first to fourth source / drain electrodes 109a, 109b, 109c and 109d face the bottom surface of the groove 202h, the second semiconductor device 100 can be easily separated from the groove 202h. Therefore, the second semiconductor device 100 may be transferred such that the gate electrode 111 and the first to fourth source / drain electrodes 109 a , 109 b , 109 c , and 109 d of the second semiconductor device 100 face the outside of the groove 202 h .

[0098] Reference Fig. 6E , a passivation layer 211 may be formed to cover the first semiconductor device 200TR and the second semiconductor device 100. The passivation layer 211 may be formed to completely fill the inside of the groove 202h. Thereafter, a portion of the passivation layer 211 may be etched so that the upper surfaces of the source electrode 206, the drain electrode 207, and the gate electrode 209 of the first semiconductor device 200TR and the upper surfaces of the gate electrode 111 and the first to fourth source / drain electrodes 109a, 109b, 109c, and 109d of the second semiconductor device 100 may be exposed. For example, a plurality of openings 211h that completely pass through the passivation layer 211 may be formed by etching portions of the passivation layer 211 that cover the source electrode 206, the drain electrode 207, and the gate electrode 209 of the first semiconductor device 200TR and the gate electrode 111 and the first to fourth source / drain electrodes 109a, 109b, 109c, and 109d of the second semiconductor device 100. Although in Fig. 6E The opening 211h for exposing the gate electrode 209 of the first semiconductor device 200TR is not shown in the figure, but may be Fig. 6E An opening 211 h exposing the gate electrode 209 of the first semiconductor device 200TR is formed at a different position in the illustrated cross section.

[0099] Reference Fig. 6F , a plurality of electrode pads 212, 213, 215, and 216 may be formed by filling the plurality of openings 211h of the passivation layer 211 with a conductive metal. Fig. 6F The electrode pad electrically connected to the gate electrode 209 of the first semiconductor device 200TR is not shown in the figure, but the electrode pad electrically connected to the gate electrode 209 of the first semiconductor device 200TR may be formed on the same Fig. 6F The plurality of electrode pads 212 , 213 , 215 , and 216 may protrude above the upper surface of the passivation layer 211 and extend laterally along the upper surface of the passivation layer 211 .

[0100] Figure 7 2 is a plan view showing an example of the arrangement of a plurality of electrode pads included in the resulting electronic device 200. Figure 7 , the electronic device 200 may include a first electrode pad 212 electrically connected to the source electrode 206 of the first semiconductor device 200TR, a second electrode pad 213 electrically connected to the drain electrode 207, and a third electrode pad 214 electrically connected to the gate electrode 209. Figure 7As shown by the dotted line in the plan view of FIG. 2 , the gate electrode 209 of the first semiconductor device 200TR may have a first portion 209a extending in the first direction between the source electrode 206 and the drain electrode 207 and a second portion 209b extending in a second direction perpendicular to the first direction. Therefore, the gate electrode 209 of the first semiconductor device 200TR may have a "T" shape. The third electrode pad 214 may be arranged to contact the second portion 209b of the gate electrode 209.

[0101] The electronic device 200 may further include a plurality of fourth electrode pads 215 electrically connected to one of the first source / drain electrode 109a and the third source / drain electrode 109c of the second semiconductor device 100, a plurality of fifth electrode pads 216 electrically connected to one of the second source / drain electrode 109b and the fourth source / drain electrode 109d of the second semiconductor device 100, and a sixth electrode pad 217 electrically connected to the gate electrode 111 of the second semiconductor device 100. For example, the four fourth electrode pads 215 may be positioned at a second distance d2 from the center of the sixth electrode pad 217 in the diagonal direction, and the four fifth electrode pads 216 may be positioned at a first distance d1 from the center of the sixth electrode pad 217 in the diagonal direction. Therefore, during the FSA transfer process, regardless of the rotation direction of the second semiconductor device 100, each of the first source / drain electrode 109a and the third source / drain electrode 109c of the second semiconductor device 100 can be electrically connected to any one of the four fourth electrode pads 215, and each of the second source / drain electrode 109b and the fourth source / drain electrode 109d can be electrically connected to any one of the four fifth electrode pads 216.

[0102] FIG. 8A to FIG. 8C It shows that Figure 1 FIG. 1 is a diagram showing an example of a process of transferring the second semiconductor device 100FSA to a foreign semiconductor substrate.

[0103] Reference Fig. 8A , the electronic device 200 to which the second semiconductor device 100 is to be transferred may be mounted on the transfer head 300. The electronic device 200 may include a plurality of grooves 202h, and a plurality of second semiconductor devices 100 may be respectively disposed in the plurality of grooves 202h. The plurality of second semiconductor devices 100 may be directly sprayed on the electronic device 200 after the liquid L is supplied to the grooves 202h of the electronic device 200, or the plurality of second semiconductor devices 100 may be included in the liquid L and supplied to the electronic device 200.

[0104] The liquid L supplied to the groove 202h can be any type of liquid as long as the liquid does not corrode or damage the second semiconductor device 100 and the electronic device 200. The liquid L can be supplied to the groove 202h by using various methods, such as a spraying method, a dripping method, an inkjet dot method, or a method of flowing the liquid L into the electronic device 200. The liquid L may include, for example, one or more combinations of a group including water, ethanol, alcohol, polyol, ketone, halocarbon, acetone, flux, and an organic solvent. The organic solvent may include, for example, isopropyl alcohol (IPA). The supply amount of the liquid L may be adjusted differently to fit into the groove 202h or overflow from the groove 202h.

[0105] The plurality of second semiconductor devices 100 may be directly sprayed on the electronic device 200 without any other liquid, or may be included in the liquid L such as a suspension and supplied to the electronic device 200. As a method of supplying the second semiconductor devices 100 included in the suspension, various methods may be used, such as a spraying method, a dropping method of dropping the liquid as droplets, an inkjet dot method of ejecting the liquid like a printing method, or a method of flowing the suspension into the electronic device 200.

[0106] Reference Figure 8B , after the plurality of second semiconductor devices 100 are supplied onto the electronic device 200, scanning may be performed to align the plurality of second semiconductor devices 100. For example, the absorber 310 may scan the upper surface of the electronic device 200. According to the scanning, the absorber 310 contacts the electronic device 200 and passes through the plurality of grooves 202h, and thus the second semiconductor devices 100 may be moved into the grooves 202h and absorb the liquid L in the grooves 202h. The absorber 310 may be sufficient as long as the absorber is a material that can absorb the liquid L, and its shape and structure are not limited. The absorber 310 may include, for example, fabric, tissue, polyester fiber, paper, or a wiper.

[0107] The absorber 310 can scan the electronic device 200 while pressing the electronic device 200 with appropriate pressure. Scanning can be performed by various methods, such as a sliding method, a rotation method, a translational motion method, a reciprocating motion method, a rolling method, a rotation method and / or a friction method of the absorber 310. Scanning can include both regular methods and irregular methods. Scanning can be performed by moving the transfer head 300 instead of moving the absorber 310. In addition, scanning can be performed by the cooperation between the absorber 310 and the transfer head 300.

[0108] Reference Figure 8C, after the absorber 310 scans the electronic device 200, the second semiconductor device 100 that does not fill the groove 202h and remains on the upper surface of the electronic device 200 can be reused. The above-described process can be repeated until the second semiconductor device 100 is disposed in all the grooves 202h. As described above, by using the FSA transfer method, a large number of second semiconductor devices 100 can be aligned in a large-area electronic device 200.

[0109] As described above, the lower surface of the buffer layer 102 of the second semiconductor device 100 may be very smooth and flat and may have a hydrophilic property. In addition, the bottom surface of the groove 202h may be very smooth and flat and may have a hydrophilic property. FIG. 8A to FIG. 8C During the FSA transfer process shown, when the buffer layer 102 of the second semiconductor device 100 faces the bottom surface of the groove 202h, the second semiconductor device 100 can be easily disposed and fixed in the groove 202h by van der Waals force. On the contrary, when the first to fourth source / drain electrodes 109a, 109b, 109c and 109d face the bottom surface of the groove 202h, the second semiconductor device 100 can be easily separated from the groove 202h during the scanning process. When the scanning process is repeated, only the second semiconductor device 100 remains in the groove 202h, wherein the buffer layer 102 faces the bottom surface of the groove 202h. The remaining second semiconductor devices 100 can be reused while remaining on the upper surface of the electronic device 200.

[0110] exist Fig. 6F After the illustrated process, a conductive line for electrically connecting to the second semiconductor device 100 in the electronic apparatus 200 may be further formed. 9A to 9C FIG. 2 is a diagram showing a method for communicating with an electronic device 200 according to an embodiment of the present invention. Figure 1 A view showing examples of various conductive line patterns to which the second semiconductor device 100 is electrically connected is shown. 9A to 9C is a schematic diagram of the resulting connection between the first to fourth source / drain electrodes 109a, 109b, 109c and 109d and the gate electrode 111 of the second semiconductor device 100 and the wire. 9A to 9C The wires shown in the figure can actually be connected with Figure 7 The fourth to sixth electrode pads 215 , 216 , and 217 are shown to be in direct contact with and indirectly connected to the first to fourth source / drain electrodes 109 a , 109 b , 109 c , and 109 d and the gate electrode 111 .

[0111] Reference Fig.9A, the electronic device 200 may include a first wire 225, a second wire 226, and a third wire 227. The first to third wires 225, 226, and 227 may be electrically connected to the second semiconductor device 100 so that the second semiconductor device 100 operates normally regardless of the rotation direction of the second semiconductor device 100 during the transfer process. For example, the first wire 225 and the second wire 226 may be arranged on opposite sides of the second semiconductor device 100 to face each other. The first wire 225 may include two arms 225a and 225b, which extend in a straight line toward the second semiconductor device 100 to be connected to any one of the second source / drain electrode 109b and the fourth source / drain electrode 109d located at a second distance d2 from the center of the second semiconductor device 100. The second wire 226 may include two arms 226a and 226b extending in a straight line toward the second semiconductor device 100 to be connected to any one of the first source / drain electrode 109a and the third source / drain electrode 109c located at a first distance d1 from the center of the second semiconductor device 100. In this case, the interval between the two arms 225a and 225b of the first wire 225 may be greater than the interval between the two arms 226a and 226b of the second wire 226.

[0112] The third conductive line 227 may be arranged to face one of the two sides of the second semiconductor device 100 that do not face the first conductive line 225 and the second conductive line 226. The third conductive line 227 may include one arm 227a extending in a straight line toward the center of the second semiconductor device 100 to be connected to the gate electrode 111. The extension direction of the arm 227a of the third conductive line 227 may be perpendicular to the extension directions of the arms 225a and 225b of the first conductive line 225 and the extension directions of the arms 226a and 226b of the second conductive line 226.

[0113] Reference Fig. 9B, the electronic device 200 may include a first wire 228, a second wire 229, and a third wire 227. The first wire 228 and the second wire 229 may be arranged on opposite sides of the second semiconductor device 100 to face each other and may have the same shape. The first wire 228 may include two arms 228a and 228b bent to connect to any two adjacent source / drain electrodes among the first to fourth source / drain electrodes 109a, 109b, 109c, and 109d, and the second wire 229 may include two arms 229a and 229b bent to connect to the other two source / drain electrodes among the first to fourth source / drain electrodes 109a, 109b, 109c, and 109d, and the other two source / drain electrodes may not be connected to the first wire 228 and may be adjacent to each other. For example, the two arms 228a and 228b of the first wire 228 and the two arms 229a and 229b of the second wire 229 can have a shape bent at 90 degrees to extend straightly toward the second semiconductor device 100, thereby connecting to any one of the second source / drain electrode 109b and the fourth source / drain electrode 109d located at a second distance d2 from the center of the second semiconductor device 100, and then connecting to any one of the first source / drain electrode 109a and the third source / drain electrode 109c located at a first distance d1 from the center of the second semiconductor device 100.

[0114] Reference Fig. 9C , the electronic device 200 may include a first conductive line 230, a second conductive line 231, and a third conductive line 227. The first conductive line 230 may include two arms 230a and 230b extending in a straight line toward the center of the second semiconductor device 100 to be connected to both the second source / drain electrode 109b and the fourth source / drain electrode 109d located at a second distance d2 from the center of the second semiconductor device 100. The second conductive line 231 may include one arm 231a bent to be connected to both the first source / drain electrode 109a and the third source / drain electrode 109c located at a first distance d1 from the center of the second semiconductor device 100. For example, the arm 231a of the second conductive line 231 may have a shape bent twice at 90 degrees each time to surround three sides of the arm 227a of the third conductive line 227 between the two arms 230a and 230b of the first conductive line 230.

[0115] Fig.10 is a circuit diagram showing an example of an equivalent circuit of the electronic device 200 according to an embodiment. Fig.10, the source electrode 206 of the first semiconductor device 200TR may be electrically connected to the gate electrode 111 of the second semiconductor device 100, and the drain electrode 207 of the first semiconductor device 200TR may be electrically connected to any two of the first to fourth source / drain electrodes 109a, 109b, 109c, and 109d of the second semiconductor device 100. In addition, the gate electrode 209 of the first semiconductor device 200TR may be connected to a separate gate line GL, and the source electrode 206 of the first semiconductor device 200TR may be connected to a separate source line SL. The other two source / drain electrodes of the first to fourth source / drain electrodes 109a, 109b, 109c, and 109d of the second semiconductor device 100 that are not connected to the drain electrode 207 of the first semiconductor device 200TR may be connected to a separate drain line DL.

[0116] As described above, the second semiconductor device 100 may be a HEMT, which may generally have a normally-on characteristic. In other words, even if no voltage is applied to the gate electrode 111, current flows through the channel between two adjacent source / drain electrodes, and when a voltage is applied to the gate electrode 111, the second semiconductor device 100 may be turned off. Fig.10 When connected as shown, the electronic device 200 can have a normally-off characteristic. In this case, when a voltage higher than or equal to the threshold voltage is applied through the gate line GL, current can flow between the source line SL and the drain line DL. Therefore, the electronic device 200 can be used as, for example, a cascode HEMT.

[0117] Fig.10 The equivalent circuit of the electronic device 200 shown is only one example of various electronic devices that can be formed by combining III-V semiconductor devices and IV semiconductor devices on one substrate. Fig.10 In addition to the cascode HEMTs shown, the electronic device 200 may further include circuits or devices that perform additional functions. For example, the electronic device 200 may be a radar system or a communication system that includes a plurality of cascode HEMTs.

[0118] exist 6A to 6F In the embodiment, it has been described that the groove 202h can be formed in the second substrate 202 of the electronic device 200, Figure 1 The second semiconductor device 100 shown may be directly transferred to the electronic apparatus 200. However, the second semiconductor device 100 may be transferred to the electronic apparatus 200 by using a transfer substrate after the second semiconductor device 100 is first aligned on a separate transfer substrate. Fig.11A and Fig. 11B is shown by transferring the Figure 1A diagram showing an example of a process in which the second semiconductor device 100 is transferred to a foreign semiconductor substrate to manufacture an electronic device.

[0119] Reference Fig.11A , a transfer substrate 400 including a plurality of grooves 400h may be mounted on FIG. 8A to FIG. 8C Thereafter, similar to the transfer head 300 of reference FIG. 8A to FIG. 8C According to the FSA transfer process described above, the second semiconductor device 100 may be aligned in the plurality of grooves 400h of the transfer substrate 400. In this case, the second semiconductor device 100 may be aligned in the grooves 400h so that the gate electrode 111 and the first to fourth source / drain electrodes 109a, 109b, 109c, and 109d of the second semiconductor device 100 face the outside of the grooves 400h.

[0120] Reference Fig. 11B , the second semiconductor device 100 may be transferred to the upper surface on which the first semiconductor device 200TR is formed of the second substrate 202 of the electronic device 200. For example, the transfer substrate 400 may be arranged on the electronic device 200 so that the gate electrode 111 and the first to fourth source / drain electrodes 109a, 109b, 109c, and 109d of the second semiconductor device 100 face the upper surface of the second substrate 202. Thereafter, the transfer substrate 400 may be separated from the electronic device 200 having the second semiconductor device 100 retained.

[0121] In this case, no groove may be formed in the second substrate 202 of the electronic device 200, and thus the second substrate 202 may have a flat upper surface. A plurality of electrode pads 232 may be pre-formed on the upper surface of the second substrate 202. The second semiconductor device 100 may be fixed and electrically connected to the plurality of electrode pads 232 by, for example, solder bumps. Fig. 11B , it is shown that the second semiconductor device 100 can be fixed to only one electrode pad 232. However, a plurality of electrode pads may be further arranged at the same Fig. 11B The cross-section of the semiconductor device 100 is different from that of the cross-section of the semiconductor device 100 , and a second semiconductor device 100 can be fixed by the plurality of electrode pads.

[0122] So far, an example has been described in which the first semiconductor device 200TR including the first semiconductor material is a field effect transistor and the electronic device 200 is a cascode HEMT, but the first semiconductor device 200TR and the electronic device 200 are not necessarily limited thereto. For example, the first semiconductor device including the first semiconductor material may be a light emitting device or various sensor devices other than a field effect transistor. In addition, the electronic device 200 may be implemented as a radar system, a LiDAR system, or a communication system including a HEMT and a light emitting device or various sensor devices.

[0123] Furthermore, it has been described that when viewed from the top Figure 1 The semiconductor device 100 shown may have a square shape. In addition, it has been described that the semiconductor device 100 may include four source / drain electrodes. However, the semiconductor device may have a rectangular shape or may have three source / drain electrodes. Fig.12 is a plan view showing an example of an electrode arrangement of a semiconductor device according to another embodiment.

[0124] Reference Fig.12 , the semiconductor device 100' may include a first source / drain 105a', a second source / drain 105b', and a third source / drain 105c' extending in a first direction. The first to third source / drains 105a', 105b', and 105c' may be arranged sequentially in a second direction perpendicular to the first direction. Therefore, the second source / drain 105b' may be between the first source / drain 105a' and the third source / drain 105c' in the second direction. In addition, the gate 110' of the semiconductor device 100' may include a first branch gate 110a' extending in the first direction between the first source / drain 105a' and the second source / drain 105b', and a second branch gate 110b' extending in the first direction between the second source / drain 105b' and the third source / drain 105c'. Fig.12 In the figure, for the convenience of description, it is shown that the first to third source / drain electrodes 105a', 105b' and 105c' and the gate electrode 110' may be on the same plane. FIG. 2A to FIG. 2C As described above, the first to third source / drain electrodes 105 a ′, 105 b ′, and 105 c ′ may be disposed on the barrier layer 104 , and the gate 110 ′ may be disposed on the gate insulating layer 106 .

[0125] In reference FIG. 2A to FIG. 2COn the passivation layer 108 described, two first source / drain electrodes 109a' may be arranged on both sides of the first source / drain 105a' and may be electrically connected to the first source / drain 105a' through the passivation layer 108. One second source / drain electrode 109b' may be arranged on the passivation layer 108 on one side of the second source / drain 105b' and may be electrically connected to the second source / drain 105b' through the passivation layer 108. In addition, two third source / drain electrodes 109c' may be arranged on the passivation layer 108 on both sides of the third source / drain 105c' and may be electrically connected to the third source / drain 105c' through the passivation layer 108. In addition, one gate electrode 111 may be arranged on the passivation layer 108 on one side of the gate 110' and may be electrically connected to the gate 110' through the passivation layer 108. The gate electrode 111 and the second source / drain electrode 109 b ′ may be arranged at opposite sides of the semiconductor device 100 ′ in the first direction to face each other.

[0126] Fig.13A and Fig. 13B It is shown that Fig.12 FIG. 2 is a diagram showing an example of a conductive line pattern in an electronic device 200 of a semiconductor device 100 ′ for electrical connection with the semiconductor device 100 ′. Fig.13A and Fig. 13B The electronic device 200 may include a first wire 233, a second wire 234, a third wire 235, and a fourth wire 236. The first wire 233 and the fourth wire 236 may be arranged to face the two long sides of the semiconductor device 100', and the second wire 234 and the third wire 235 may be arranged to face the two short sides of the semiconductor device 100'.

[0127] When the semiconductor device 100' is transferred to the electronic device 200 by using the FSA transfer method, the semiconductor device 100' can be arranged in two different directions. Fig.13A As shown, the gate electrode 111 may be located at the top in the figure, and the second source / drain electrode 109b' may be located at the bottom in the figure, or as shown in FIG. Fig. 13B As shown, the second source / drain electrode 109b' may be located at the top, and the gate electrode 111 may be located at the bottom. Fig.13A In the case of, the first wire 233 can be connected to the first source / drain electrode 109a', and the fourth wire 236 can be connected to the third source / drain electrode 109c'. In addition, the second wire 234 can be connected to the gate electrode 111, and the third wire 235 can be connected to the second source / drain electrode 109b'. Fig. 13BIn the case of, the first wire 233 can be connected to the third source / drain electrode 109c', and the fourth wire 236 can be connected to the first source / drain electrode 109a'. In addition, the second wire 234 can be connected to the second source / drain electrode 109b', and the third wire 235 can be connected to the gate electrode 111.

[0128] In this case, the first source / drain 105a' and the third source / drain 105c' may be used as Fig.10 Source as shown. Fig.13A or Fig. 13B In the semiconductor device 100 ′ shown, the second conductive line 234 may be connected to the gate line and the third conductive line 235 may be connected to the drain line, or the second conductive line 234 may be connected to the drain line and the third conductive line 235 may be connected to the gate line.

[0129] The aforementioned semiconductor device and the electronic device including the semiconductor device have been described with reference to the embodiments shown in the accompanying drawings, but these are merely examples, and it should be understood that various modifications and other equivalent embodiments may be made by a person skilled in the art. Therefore, the disclosed embodiments should be considered in an illustrative sense rather than a restrictive sense. The scope of the present disclosure is indicated in the claims, rather than in the foregoing description, and all differences within the equivalent range should be interpreted as being included within the scope of the present disclosure.

[0130] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

[0131] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0089050 filed in the Korean Intellectual Property Office on July 10, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: a channel layer comprising a first III-V semiconductor material; a barrier layer provided on an upper surface of the channel layer, the barrier layer comprising a second III-V semiconductor material different from the first III-V semiconductor material; a plurality of source / drain electrodes spaced apart from each other on the upper surface of the barrier layer; A gate insulating layer covering the upper surface of the barrier layer and the upper surfaces of the plurality of source / drain electrodes; A gate electrode is provided on the upper surface of the gate insulating layer, and the gate electrode does not overlap with the plurality of source electrodes / drains; A plurality of source / drain electrodes electrically connected to corresponding source / drain electrodes among the plurality of source / drain electrodes; as well as a gate electrode electrically connected to the gate, The plurality of source / drain electrodes are arranged in a diagonally symmetrical manner.

2. The semiconductor device according to claim 1, wherein the plurality of source / drain electrodes comprises: a first source / drain provided on a first quadrant of the upper surface of the barrier layer; a second source / drain provided on a second quadrant of the upper surface of the barrier layer; a third source / drain provided on a third quadrant of the upper surface of the barrier layer; as well as A fourth source / drain is provided on a fourth quadrant of the upper surface of the barrier layer. 3 . The semiconductor device according to claim 2 , wherein the first source / drain, the second source / drain, the third source / drain, and the fourth source / drain do not cover a central region of the upper surface of the barrier layer.

4. The semiconductor device according to claim 3, wherein the first source / drain and the fourth source / drain have rotationally symmetric shapes with respect to a boundary between the first quadrant and the fourth quadrant, wherein the first source / drain and the second source / drain have rotationally symmetric shapes with respect to a boundary between the first quadrant and the second quadrant, wherein the second source / drain and the third source / drain have rotationally symmetric shapes with respect to a boundary between the second quadrant and the third quadrant, and The third source / drain and the fourth source / drain have rotationally symmetric shapes with respect to a boundary between the third quadrant and the fourth quadrant.

5. The semiconductor device according to claim 2, further comprising: a first conductive layer provided on the upper surface of the gate insulating layer and electrically connected to the first source / drain; a second conductive layer provided on the upper surface of the gate insulating layer and electrically connected to the second source / drain; a third conductive layer provided on the upper surface of the gate insulating layer and electrically connected to the third source / drain; as well as A fourth conductive layer is provided on the upper surface of the gate insulating layer and is electrically connected to the fourth source / drain.

6. The semiconductor device according to claim 5, wherein the first conductive layer is in a vertex region of the first quadrant on the upper surface of the gate insulating layer, wherein the second conductive layer is in a vertex region of the second quadrant on the upper surface of the gate insulating layer, wherein the third conductive layer is in a vertex region of the third quadrant on the upper surface of the gate insulating layer, and The fourth conductive layer is in a vertex region of the fourth quadrant on the upper surface of the gate insulating layer.

7. The semiconductor device according to claim 5, wherein the gate insulating layer comprises a plurality of openings, the plurality of openings exposing a portion of an upper surface of each of the first source / drain, the second source / drain, the third source / drain, and the fourth source / drain, and The first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer are respectively in contact with the first source / drain, the second source / drain, the third source / drain and the fourth source / drain through the plurality of openings.

8. The semiconductor device according to claim 2, wherein the plurality of source / drain electrodes comprises: a first source / drain electrode electrically connected to the first source / drain; a second source / drain electrode electrically connected to the second source / drain; a third source / drain electrode electrically connected to the third source / drain; as well as A fourth source / drain electrode is electrically connected to the fourth source / drain.

9. The semiconductor device according to claim 8, wherein the gate electrode is in a central portion of the semiconductor device, wherein the first source / drain electrode and the third source / drain electrode face each other in a first diagonal direction and are spaced a first distance from the center of the gate electrode, wherein the second source / drain electrode and the fourth source / drain electrode face each other in a second diagonal direction and are a second distance away from the center of the gate electrode, and The second diagonal direction intersects with the first diagonal direction, and the second distance is different from the first distance.

10. The semiconductor device according to claim 1, wherein the gate comprises: a central gate arranged in a central portion of the upper surface of the gate insulating layer; as well as A plurality of branch gates extend between two adjacent source / drains among the plurality of source / drains. The semiconductor device according to claim 10 , wherein each of the plurality of branch gates has a meandering curve shape. 12 . The semiconductor device according to claim 10 , wherein each of the plurality of branch gates has a straight line shape. 13 . The semiconductor device according to claim 10 , wherein the gate insulating layer covers a sidewall of the barrier layer and a sidewall of the channel layer. 14 . The semiconductor device according to claim 13 , wherein each of the plurality of branch gates extends along a surface of the gate insulating layer to face the sidewall of the barrier layer and the sidewall of the channel layer.

15. The semiconductor device according to claim 1, further comprising a passivation layer configured to cover the gate insulating layer and the gate, The gate electrode and the plurality of source / drain electrodes pass through the passivation layer.

16. The semiconductor device according to claim 1, wherein the plurality of source / drains include a first source / drain, a second source / drain, and a third source / drain extending in a first direction, The first source / drain, the second source / drain and the third source / drain are arranged in sequence in a second direction perpendicular to the first direction, The gate comprises: a first branch gate extending between the first source / drain and the second source / drain in the first direction; as well as A second branch gate extends between the second source / drain and the third source / drain in the first direction.

17. An electronic device comprising: a substrate comprising a first semiconductor material; A first semiconductor device is provided on the substrate; as well as a second semiconductor device provided on the substrate and comprising a second semiconductor material different from the first semiconductor material, The second semiconductor device comprises: a channel layer comprising a first III-V semiconductor material; a barrier layer provided on an upper surface of the channel layer, the barrier layer comprising a second III-V semiconductor material different from the first III-V semiconductor material; a plurality of source / drain electrodes spaced apart from each other on the upper surface of the barrier layer; A gate insulating layer covering the upper surface of the barrier layer and the upper surfaces of the plurality of source / drain electrodes; A gate electrode is provided on the upper surface of the gate insulating layer, and the gate electrode does not overlap with the plurality of source electrodes / drains; a plurality of source / drain electrodes electrically connected to corresponding source / drain electrodes among the plurality of source / drain electrodes; and a gate electrode electrically connected to the gate, and The plurality of source / drain electrodes are arranged in a diagonally symmetrical manner. 18 . The electronic apparatus according to claim 17 , wherein the first semiconductor device is one of a transistor, a light emitting device, and a sensor device.

19. The electronic device of claim 17, wherein the substrate comprises a recessed groove in an upper surface of the substrate, and wherein the second semiconductor device is provided in the groove so that the gate electrode and the plurality of source / drain electrodes face the outside of the groove. 20 . The electronic device according to claim 17 , wherein the gate electrode and the plurality of source / drain electrodes face an upper surface of the substrate.

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