A silicon carbide planar gate MOSFET device and a manufacturing method thereof

Abstract

The present invention relates to a silicon carbide planar gate MOSFET device and a manufacturing method thereof in the field of semiconductor technology. The device comprises a substrate, a drain electrode formed on one end surface of the substrate, an epitaxial layer formed on the other end surface of the substrate, a current diffusion layer formed above the epitaxial layer, an epitaxial well region formed above the epitaxial layer, a first source contact region formed in the epitaxial well region, and a second source contact region formed in the epitaxial well region. A source electrode is also arranged on the second source contact region, and the source electrode is also arranged in contact with a part of the first source contact region. A planar gate is arranged on the current diffusion layer and the epitaxial well region. A first base region and a second base region are arranged in the current diffusion layer. The first base region is entirely arranged in the second base region, or the first base region is partially arranged in the second base region. The device can reduce the oscillation in the device shutdown process while accelerating the device shutdown speed, reduce the switching loss and electromagnetic interference of the device, and solve the problem that the traditional device cannot balance the switching speed and the switching oscillation.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a silicon carbide planar gate MOSFET device and a manufacturing method thereof. Background Art

[0002] In recent years, silicon carbide MOSFETs have been widely studied, and motor drive systems based on SiC MOSFETs have been widely used in many fields such as new energy vehicles, rail transportation, and aerospace. Switching loss is one of the important indicators of power MOSFETs, which directly affects the efficiency of devices and systems. SiC MOSFETs have relatively low switching losses due to their fast switching speed. However, considering the parasitic parameters in the circuit, faster switching speeds will aggravate electromagnetic interference (EMI), resulting in significant voltage and current overshoots and oscillations. This will have a negative impact on power electronic systems in practical applications, and in extreme cases will cause system damage. During the MOSFET shutdown process, a smaller gate-drain capacitance Cgd will speed up the shutdown speed, thereby reducing losses, but at the same time will increase voltage overshoots and oscillations, increasing EMI. Therefore, switching loss and electromagnetic interference often cause conflicts in device design, and corresponding trade-offs need to be made.

[0003] The traditional SiC planar gate MOSFET cell structure is as follows: Figure 1 As shown, a trade-off needs to be made between switching speed and switching oscillation. If the switching speed is fast, the switching oscillation will become larger; if the switching oscillation is reduced, the switching speed will also be reduced accordingly. On the other hand, because traditional silicon carbide materials have greatly improved the switching speed of MOSFET, it causes larger switching oscillation during the switching process, which in turn causes greater electromagnetic interference. Summary of the invention

[0004] In view of the shortcomings in the prior art, the present invention provides a silicon carbide planar gate MOSFET device and a manufacturing method thereof, which solves the problem that the traditional silicon carbide planar gate MOSFET device cannot balance the switching speed and the switching oscillation.

[0005] In order to solve the above technical problems, the present invention is solved by the following technical solutions:

[0006] A silicon carbide planar gate MOSFET device, comprising a substrate, a drain electrode formed on one end surface of the substrate, an epitaxial layer formed on the other end surface of the substrate, a current diffusion layer formed above the epitaxial layer, an epitaxial well region formed above the epitaxial layer, a first source contact region formed in the epitaxial well region, and a second source contact region formed in the epitaxial well region, wherein the current diffusion layer is arranged in contact with the epitaxial well region, and the current diffusion layer and the epitaxial well region are located on the same surface, the first source contact region is arranged in contact with the second source contact region, and the first source contact region and the second source contact region are located on the same surface, a source electrode is further arranged on the second source contact region, and the source electrode The electrode is also arranged in contact with a portion of the first source contact region, a planar gate is also arranged on the current diffusion layer and the epitaxial well region, the planar gate is also in contact with a portion of the first source contact region, and the planar gate is not arranged in contact with the source electrode, a first base region and a second base region are arranged in the current diffusion layer, and the first base region is entirely arranged in the second base region, or the first base region is partially arranged in the second base region, the substrate, the epitaxial layer, the current diffusion layer, the first source contact region and the first base region are all of the first doping type, the epitaxial well region, the second source contact region and the second base region are all of the second doping type, and the first doping type and the second doping type are opposite doping types.

[0007] Optionally, when the first base region is entirely disposed in the second base region, lower surfaces of the first base region and the second base region are not lower than a lower surface of a current diffusion layer, and an upper surface of the first base region is not higher than an upper surface of the second base region.

[0008] Optionally, the second base region is embedded in the current diffusion layer, and a side wall of the second base region is in contact with the epitaxial well region; the first base region is embedded in the second base region, and a side wall of the first base region is in contact with the epitaxial well region.

[0009] Optionally, the lower surface of the second base region and the lower surface of the first base region are both arranged in contact with the epitaxial layer.

[0010] Optionally, the lower surface of the second base region is arranged in contact with the epitaxial layer, and the lower surface of the first base region is arranged not in contact with the epitaxial layer.

[0011] Optionally, the lower surface of the second base region is not in contact with the epitaxial layer, and the lower surface of the first base region is in contact with the current diffusion layer.

[0012] Optionally, the second base region is embedded in the current diffusion layer, and the side wall of the second base region is in contact with the epitaxial well region, the lower surface of the second base region is in contact with the epitaxial layer, the first base region is embedded in the second base region, and the lower surface of the first base region is in contact with the epitaxial layer, and the side wall of the first base region is in contact with the second base region.

[0013] Optionally, the second base region is embedded in the current diffusion layer, and the side wall of the second base region is in contact with the epitaxial well region, the lower surface of the second base region is in contact with the epitaxial layer, the first base region is embedded in the second base region, and the second base region is arranged around the first base region.

[0014] Optionally, there are more than two groups of first base regions embedded in the second base region, the more than two groups of the first base regions are arranged in a polygonal shape, and the more than two groups of the first base regions are arranged at intervals in the second base region, or the more than two groups of the first base regions are arranged continuously in the second base region.

[0015] Optionally, the polygonal shape of the first base region is a rectangle, and more than two groups of the first base regions are arranged at intervals in the second base region.

[0016] Optionally, the polygon in which the first base regions are arranged is a triangle, and more than two groups of the first base regions are continuously arranged in the second base region.

[0017] Optionally, when the first base region is partially disposed in the second base region, an upper surface of the first base region is not higher than an upper surface of the second base region.

[0018] Optionally, the second base region is embedded in the current diffusion layer, and a side wall of the second base region is in contact with the epitaxial well region, and a lower surface of the second base region is not in contact with the epitaxial layer.

[0019] Optionally, a side wall of the first base region partially disposed in the second base region is disposed in contact with the epitaxial well region, and a lower surface of the first base region is disposed in contact with the epitaxial layer.

[0020] Optionally, the second base region is embedded in the current diffusion layer, and the side wall of the second base region is in contact with the epitaxial well region, the lower surface of the second base region and the lower surface of the first base region are both in contact with the epitaxial layer, and the first base region is partially embedded in the epitaxial well region and in contact with the epitaxial well region.

[0021] Optionally, the structure formed by the first base region and the second base region is provided in one group or two groups.

[0022] Optionally, when there are two groups of structures formed by the first base region and the second base region, the structures formed by the two groups of the first base region and the second base region are arranged to be the same or different.

[0023] Optionally, when the structures formed by the two groups of the first base regions and the second base regions are set to be the same, the structures formed by the two groups of the first base regions and the second base regions are respectively set close to the side walls of the current diffusion layer, and are symmetrically arranged at intervals in the current diffusion layer; when the structures formed by the two groups of the first base regions and the second base regions are set to be different, the structures formed by the two groups of the first base regions and the second base regions are respectively set close to the side walls of the current diffusion layer, and are arranged at intervals in the current diffusion layer.

[0024] Optionally, the direction of the current diffusion layer toward the epitaxial layer is the first direction; the direction of the current diffusion layer toward the epitaxial well region and perpendicular to the first direction is the second direction; the direction perpendicular to the plane formed by the first direction and the second direction is the third direction, and the cross-sectional view of the silicon carbide planar gate MOSFET device on the plane formed by the second direction and the third direction is a polygon.

[0025] Optionally, when the cross-sectional view is rectangular, the second source contact regions are continuously distributed in the third direction.

[0026] Optionally, when the cross-sectional view is rectangular, the second source contact regions are distributed in segments and at intervals in the third direction.

[0027] Optionally, the first base region and the second base region are continuously distributed in the third direction.

[0028] Optionally, the second base regions are distributed continuously in the third direction, and the first base regions are distributed in segmented intervals in the third direction.

[0029] Optionally, the first base region and the second base region are distributed in segments and at intervals in the third direction.

[0030] Optionally, when the cross-sectional view is a square, the first base region and the second base region are arranged to surround the epitaxial well region in the cross-sectional view, and the first base region and the second base region are both continuously distributed.

[0031] Optionally, when the cross-sectional view is a square, the first base region and the second base region are arranged to surround the epitaxial well region in the cross-sectional view, and the second base region is continuously distributed, and the first base region is segmented and spaced apart.

[0032] Optionally, when the cross-sectional view is a square, the first base region and the second base region are arranged to surround the epitaxial well region in the cross-sectional view, and the first base region and the second base region are both distributed in segmented intervals.

[0033] Optionally, when the cross-sectional view is a hexagon, the first base region and the second base region are arranged to surround the epitaxial well region in the cross-sectional view, and the first base region and the second base region are both continuously distributed.

[0034] Optionally, when the cross-sectional view is hexagonal, the first base region and the second base region are arranged to surround the epitaxial well region in the cross-sectional view, and the second base region is continuously distributed, and the first base region is segmented and spaced apart.

[0035] Optionally, when the cross-sectional view is a hexagon, the first base region and the second base region are arranged to surround the epitaxial well region in the cross-sectional view, and the first base region and the second base region are both distributed in segmented intervals.

[0036] A silicon carbide planar gate MOSFET device, comprising a substrate, a drain electrode formed on one end surface of the substrate, an epitaxial layer formed on the other end surface of the substrate, a current diffusion layer formed above the epitaxial layer, an epitaxial well region formed on the current diffusion layer, wherein the sidewall and the lower surface of the epitaxial well region are both arranged in contact with the current diffusion layer, a first source contact region formed in the epitaxial well region and a second source contact region formed in the epitaxial well region, wherein the first source contact region is arranged in contact with the second source contact region, and the first source contact region and the second source contact region are located on the same surface, a source electrode is also arranged on the second source contact region, and the source electrode is also in contact with a portion of the The first source contact region is arranged in contact with the first source contact region, a planar gate is also arranged on the current diffusion layer and the epitaxial well region, the planar gate is also in contact with part of the first source contact region, the planar gate is not arranged in contact with the source electrode, a first base region and a second base region are arranged in the current diffusion layer, and the first base region is entirely arranged in the second base region, or the first base region is partially arranged in the second base region, the substrate, the epitaxial layer, the current diffusion layer, the first source contact region and the first base region are all of the first doping type, the epitaxial well region, the second source contact region and the second base region are all of the second doping type, and the first doping type and the second doping type are opposite doping types.

[0037] Optionally, the direction of the current diffusion layer toward the epitaxial layer is the first direction; the direction of the current diffusion layer toward the epitaxial well region and perpendicular to the first direction is the second direction; the direction perpendicular to the plane formed by the first direction and the second direction is the third direction, and the cross-sectional view of the silicon carbide planar gate MOSFET device on the plane formed by the second direction and the third direction is a polygon.

[0038] Optionally, the structure formed by the first base region and the second base region is provided in one group or two groups.

[0039] Optionally, when there are two groups of structures formed by the first base region and the second base region, the two groups of structures formed by the first base region and the second base region are respectively arranged close to the side walls of the current diffusion layer and are symmetrically arranged at intervals in the current diffusion layer.

[0040] Optionally, the upper surface of the first base region is not higher than the upper surface of the second base region, the second base region is embedded in the current diffusion layer, and the side wall of the second base region is in contact with the side wall of the epitaxial well region, and the first base region is embedded in the second base region, and the side wall of the first base region is in contact with the side wall of the epitaxial well region.

[0041] A method for manufacturing a silicon carbide planar gate MOSFET device, the method for manufacturing a silicon carbide planar gate MOSFET device as described in any one of the above, comprising the following steps:

[0042] An epitaxial layer is grown on the surface of the substrate, wherein the doping concentration of the epitaxial layer is 1×10 15 ~1×10 17 cm -3 ;

[0043] A second base region, a portion of the epitaxial well region and a portion of the current diffusion layer are formed in the epitaxial layer by photolithography and ion implantation, and a first base region is formed in the second base region by high-energy ion implantation, wherein the first base region and the second base region are both doped with a concentration of 1×10 15 ~1×10 20 cm -3 Semiconductor materials;

[0044] Continue to grow the epitaxial layer, and form a current diffusion layer and an epitaxial well region by ion implantation, wherein the doping concentration of the current diffusion layer is 1×10 15 ~1×10 18 cm -3 The doping concentration of the epitaxial well region is 1×10 16 ~1×10 19 cm -3 ;

[0045] A first source contact region and a second source contact region are formed by ion implantation on the surface of the epitaxial well region, wherein the implantation of the first source contact region uses a self-aligned process, and the doping concentrations of the first source contact region and the second source contact region are both 1×10 18 ~1×10 20 cm -3 ;

[0046] After the ion implantation, an activation annealing treatment is performed, and a gate dielectric is formed on the device surface by any one of high temperature oxidation, chemical vapor deposition, physical vapor deposition or atomic layer deposition processes, followed by NO interface annealing treatment;

[0047] Depositing an N-type polysilicon gate on the surface of the gate dielectric, and etching the N-type polysilicon gate and the gate dielectric to remove excess polysilicon and the gate dielectric;

[0048] Ohmic contacts are made on the surface and back of the device, gate dielectric is filled around the polysilicon gate, a drain electrode is prepared on the back of the substrate by sputtering, evaporation or annealing, and a source electrode is prepared on the first source contact area and the second source contact area.

[0049] A method for manufacturing a silicon carbide planar gate MOSFET device, the method for manufacturing a silicon carbide planar gate MOSFET device as described in any one of the above, comprising the following steps:

[0050] An epitaxial layer is grown on the surface of the substrate, wherein the doping concentration of the epitaxial layer is 1×10 15 ~1×10 17 cm -3 ;

[0051] A current diffusion layer and an epitaxial well region are formed in the epitaxial layer by ion implantation, wherein the doping concentration of the current diffusion layer is 1×10 15 ~1×10 18 cm -3 The doping concentration of the epitaxial well region is 1×10 16 ~1×10 19 cm -3 ;

[0052] A first base region and a second base region are formed in the current diffusion layer by high energy ion implantation, wherein the first base region and the second base region are both doped with a concentration of 1×10 15 ~1×10 20 cm -3 Semiconductor materials;

[0053] A first source contact region and a second source contact region are formed by ion implantation on the surface of the epitaxial well region, wherein the implantation of the first source contact region uses a self-aligned process, and the doping concentrations of the first source contact region and the second source contact region are both 1×10 18 ~1×10 20 cm -3 ;

[0054] After the ion implantation, an activation annealing treatment is performed, and a gate dielectric is formed on the device surface by any one of high temperature oxidation, chemical vapor deposition, physical vapor deposition or atomic layer deposition processes, followed by NO interface annealing treatment;

[0055] Depositing an N-type polysilicon gate on the surface of the gate dielectric, and etching the N-type polysilicon gate and the gate dielectric;

[0056] Remove excess polysilicon and gate dielectric;

[0057] Ohmic contacts are made on the surface and back of the device, gate dielectric is filled around the polysilicon gate, a drain electrode is prepared on the back of the substrate by sputtering, evaporation or annealing, and a source electrode is prepared on the first source contact area and the second source contact area.

[0058] A method for manufacturing a silicon carbide planar gate MOSFET device, the method for manufacturing a silicon carbide planar gate MOSFET device as described in any one of the above, comprising the following steps:

[0059] An epitaxial layer is grown on the surface of the substrate, wherein the doping concentration of the epitaxial layer is 1×10 15 ~1×10 17 cm -3 ;

[0060] A first base region, a portion of a second base region, a portion of a current diffusion layer and a portion of an epitaxial well region are formed in the epitaxial layer by ion implantation, wherein the doping concentration of the current diffusion layer is 1×10 15 ~1×10 18 cm -3 The doping concentration of the epitaxial well region is 1×10 16 ~1×10 19 cm -3 The first base region and the second base region both have a doping concentration of 1×10 15 ~1×10 20 cm -3 Semiconductor materials;

[0061] Continue to grow the epitaxial layer, and form the remaining second base region, part of the current diffusion layer and part of the epitaxial well region by ion implantation;

[0062] Continue to grow the epitaxial layer, and form the remaining current diffusion layer and the remaining epitaxial well region by ion implantation;

[0063] A first source contact region and a second source contact region are formed by ion implantation on the surface of the epitaxial well region, wherein the implantation of the first source contact region uses a self-aligned process, and the doping concentrations of the first source contact region and the second source contact region are both 1×10 18 ~1×10 20 cm -3 ;

[0064] After the ion implantation, an activation annealing treatment is performed, and a gate dielectric is formed on the device surface by any one of high temperature oxidation, chemical vapor deposition, physical vapor deposition or atomic layer deposition processes, followed by NO interface annealing treatment;

[0065] Depositing an N-type polysilicon gate on the surface of the gate dielectric, and etching the N-type polysilicon gate and the gate dielectric;

[0066] Remove excess polysilicon and gate dielectric;

[0067] Ohmic contacts are made on the surface and back of the device, gate dielectric is filled around the polysilicon gate, a drain electrode is prepared on the back of the substrate by sputtering, evaporation or annealing, and a source electrode is prepared on the first source contact area and the second source contact area.

[0068] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0069] 1. By introducing a first base region and a second base region with an opposite doping type to the first base region, when the device is just turned off, the drain-source voltage V ds Due to the existence of the second base region, the overlapping area between the gate and the drain is smaller than that of the traditional device, so the gate-drain capacitance C gd smaller, thus through a smaller C gd The dV / dt at the early stage of device shutdown is increased, which makes the device turn off faster and reduces the shutdown loss at this stage; when the device enters the end of the shutdown transient, the drain-source voltage V ds The gate-drain capacitance C increases significantly because the first base region depletes the second base region, and the second base region is depleted, so the overlapping area between the gate and the drain increases. gd Significantly increased, dV / dt is small, reducing the overshoot and oscillation of the voltage and current of the device, and reducing the EMI of the device;

[0070] 2. By introducing the second base region, the shielding effect on the gate dielectric is more obvious, and the electric field peak of the gate dielectric is reduced compared with traditional devices;

[0071] 3. By introducing the second base region into the current diffusion layer, the short-circuit current flow position is changed, the short-circuit peak current is reduced, and the short-circuit withstand time is increased, thereby increasing the short-circuit capability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0073] Figure 1 Schematic diagram of the cell structure of a conventional SiC planar gate MOSFET;

[0074] Figure 2A schematic diagram of a cell structure of a silicon carbide planar gate MOSFET device proposed in the first embodiment;

[0075] Figure 3 A comparison diagram of the on-capacitance versus voltage of a silicon carbide planar gate MOSFET device and a conventional silicon carbide planar gate MOSFET device proposed in the first embodiment;

[0076] Figure 4 A comparison diagram of the drain-source voltage variation over time of a silicon carbide planar gate MOSFET device proposed in the first embodiment and a conventional silicon carbide planar gate MOSFET device;

[0077] Figure 5 A schematic diagram of a cell structure of a silicon carbide planar gate MOSFET device proposed in the second embodiment;

[0078] Figure 6 A schematic diagram of a cell structure of a silicon carbide planar gate MOSFET device proposed in the third embodiment;

[0079] Figure 7 A schematic diagram of a cell structure of a silicon carbide planar gate MOSFET device proposed in the fourth embodiment;

[0080] Figure 8 A schematic diagram of a cell structure of a silicon carbide planar gate MOSFET device proposed in the fifth embodiment;

[0081] Fig. 9 A schematic diagram of a cell structure of a silicon carbide planar gate MOSFET device proposed in the sixth embodiment;

[0082] Fig.10 A schematic diagram of a cell structure of a silicon carbide planar gate MOSFET device proposed in the seventh embodiment;

[0083] Fig.11 A schematic diagram of a cell structure of a silicon carbide planar gate MOSFET device proposed in the eighth embodiment;

[0084] Fig.12 A schematic diagram of a cell structure of a silicon carbide planar gate MOSFET device proposed in the ninth embodiment;

[0085] Fig.13 A schematic diagram of a cell structure of a silicon carbide planar gate MOSFET device proposed in the tenth embodiment;

[0086] Fig.14 A schematic diagram of a cell structure of a silicon carbide planar gate MOSFET device proposed in the eleventh embodiment;

[0087] Fig.15This is a schematic diagram of the structure of a silicon carbide planar gate MOSFET device proposed in the twelfth embodiment, wherein: Fig.15 (a) is a schematic diagram of a cell structure of a silicon carbide planar gate MOSFET device proposed in the twelfth embodiment. Fig.15 (b) in the equation is Fig.15 (a) is the cross-sectional view at A-A', Fig.15 (c) in the equation is Fig.15 (a) Cross-sectional view at BB';

[0088] Fig.16 This is a schematic diagram of the structure of a silicon carbide planar gate MOSFET device proposed in the thirteenth embodiment, wherein: Fig.16 (a) is a schematic diagram of a cell structure of a silicon carbide planar gate MOSFET device proposed in the thirteenth embodiment. Fig.16 (b) in the equation is Fig.16 (a) is the cross-sectional view at A-A', Fig.16 (c) in the equation is Fig.16 (a) Cross-sectional view at BB';

[0089] Fig.17 This is a schematic diagram of the structure of a silicon carbide planar gate MOSFET device proposed in the fourteenth embodiment, wherein: Fig.17 (a) is a schematic diagram of a cell structure of a silicon carbide planar gate MOSFET device proposed in the fourteenth embodiment. Fig.17 (b) in the equation is Fig.17 (a) is the cross-sectional view at A-A', Fig.17 (c) in the equation is Fig.17 (a) Cross-sectional view at BB';

[0090] Fig.18 This is a schematic diagram of the structure of a silicon carbide planar gate MOSFET device proposed in the fifteenth embodiment, wherein: Fig.18 (a) is a schematic diagram of a cell structure of a silicon carbide planar gate MOSFET device proposed in the fifteenth embodiment. Fig.18 (b) in the equation is Fig.18 (a) is the cross-sectional view at A-A', Fig.18 (c) in the equation is Fig.18 (a) Cross-sectional view at BB';

[0091] Fig.19 This is a schematic diagram of the structure of a silicon carbide planar gate MOSFET device proposed in the sixteenth embodiment, wherein: Fig.19 (a) is a schematic diagram of a cell structure of a silicon carbide planar gate MOSFET device proposed in the sixteenth embodiment. Fig.19(b) in the equation is Fig.19 (a) is the cross-sectional view at A-A', Fig.19 (c) in the equation is Fig.19 (a) Cross-sectional view at BB';

[0092] Fig. 20 Schematic diagram of the structure of a silicon carbide planar gate MOSFET device proposed in the seventeenth embodiment, wherein: Fig. 20 (a) is a schematic diagram of a cell structure of a silicon carbide planar gate MOSFET device proposed in the seventeenth embodiment. Fig. 20 (b) in the equation is Fig. 20 (a) is the cross-sectional view at A-A', Fig. 20 (c) in the equation is Fig. 20 (a) Cross-sectional view at BB';

[0093] Fig.21 Schematic diagram of the structure of a silicon carbide planar gate MOSFET device proposed in the eighteenth embodiment, wherein: Fig.21 (a) is a schematic diagram of a cell structure of a silicon carbide planar gate MOSFET device proposed in the eighteenth embodiment. Fig.21 (b) in the equation is Fig.21 (a) is the cross-sectional view at A-A', Fig.21 (c) in the equation is Fig.21 (a) Cross-sectional view at BB';

[0094] Fig. 22 This is a schematic diagram of the structure of a silicon carbide planar gate MOSFET device proposed in the nineteenth embodiment, wherein: Fig. 22 (a) is a schematic diagram of a cell structure of a silicon carbide planar gate MOSFET device proposed in the nineteenth embodiment. Fig. 22 (b) in the equation is Fig. 22 (a) is the cross-sectional view at A-A', Fig. 22 (c) in the equation is Fig. 22 (a) Cross-sectional view at BB';

[0095] Fig.23 This is a schematic diagram of the structure of a silicon carbide planar gate MOSFET device proposed in the twenty-first embodiment, wherein: Fig.23 (a) is a schematic diagram of a cell structure of a silicon carbide planar gate MOSFET device proposed in this embodiment 20. Fig.23 (b) in the equation is Fig.23 (a) is the cross-sectional view at A-A', Fig.23 (c) in the equation is Fig.23 (a) Cross-sectional view at BB';

[0096] Fig.24 Schematic diagram of the structure of a silicon carbide planar gate MOSFET device proposed in the twenty-first embodiment, wherein: Fig.24 (a) is a schematic diagram of a cell structure of a silicon carbide planar gate MOSFET device proposed in the twenty-first embodiment. Fig.24 (b) in the equation is Fig.24 (a) is the cross-sectional view at A-A', Fig.24 (c) in the equation is Fig.24 (a) Cross-sectional view at BB';

[0097] Fig.25 A schematic diagram of a cell structure of a silicon carbide planar gate MOSFET device proposed in Embodiment 22;

[0098] Fig.26 This is a manufacturing flow chart of a silicon carbide planar gate MOSFET device proposed in the twenty-third embodiment;

[0099] Fig. 27 This is a manufacturing flow chart of a silicon carbide planar gate MOSFET device proposed in the twenty-fourth embodiment;

[0100] Fig.28 This is a manufacturing flow chart of a silicon carbide planar gate MOSFET device proposed in the twenty-fifth embodiment.

[0101] Figure numerals: 1. drain electrode; 2. source electrode; 3. gate electrode; 4. gate dielectric; 5. substrate; 6. epitaxial layer; 7. epitaxial well region; 8. current diffusion layer; 9. first source contact region; 10. second source contact region; 11. first base region; 12. second base region. DETAILED DESCRIPTION

[0102] The present invention is further described in detail below in conjunction with embodiments. The following embodiments are for explanation of the present invention but the present invention is not limited to the following embodiments.

[0103] Embodiment 1

[0104] like Figure 2As shown, a silicon carbide planar gate MOSFET device includes a substrate 5, a drain electrode 1 formed on one end surface of the substrate 5, an epitaxial layer 6 formed on the other end surface of the substrate 5, a current diffusion layer 8 formed above the epitaxial layer 6, an epitaxial well region 7 formed above the epitaxial layer 6, a first source contact region 9 formed in the epitaxial well region 7, and a second source contact region 10 formed in the epitaxial well region 7, wherein the current diffusion layer 8 is arranged in contact with the epitaxial well region 7, and the current diffusion layer 8 and the epitaxial well region 7 are located on the same surface, and the first The source contact region 9 is arranged in contact with the second source contact region 10, and the first source contact region 9 and the second source contact region 10 are located on the same surface. A source electrode 2 is also arranged on the second source contact region 10, and the source electrode 2 is also arranged in contact with a portion of the first source contact region 9. A planar gate is also arranged on the current diffusion layer 8 and the epitaxial well region 7, and the planar gate is also in contact with a portion of the first source contact region 9. The planar gate is not arranged in contact with the source electrode 2, wherein the planar gate includes a gate electrode 3 and a gate dielectric 4, and the gate electrode 3 is formed on the gate dielectric 4.

[0105] like Figure 2 As shown, the path of the dotted arrow is the conduction current path of the device in the forward conduction state, and the direction of the arrow is the direction of the current. In this embodiment, a positive voltage of 10~20V is applied to the gate electrode 3, a positive voltage of 0~20V is applied to the drain electrode 1, and the source electrode 2 is grounded. In this state, the device forms a channel under the planar gate, and the current flows from the drain through the substrate 5, the epitaxial layer 6, the current diffusion layer 8, the channel, the first source contact area 9 in sequence, and finally flows to the source electrode 2.

[0106] Furthermore, in the present embodiment, a first base region 11 and a second base region 12 are arranged in the current diffusion layer 8, and the first base region 11 is entirely arranged in the second base region 12, or the first base region 11 is partially arranged in the second base region 12, wherein the substrate 5, the epitaxial layer 6, the current diffusion layer 8, the first source contact region 9 and the first base region 11 are all of the first doping type, the epitaxial well region 7, the second source contact region 10 and the second base region 12 are all of the second doping type, and the first doping type and the second doping type are opposite doping types.

[0107] It should be noted that, in this embodiment, the first doping type and the second doping type are opposite doping types, which means that when the first doping type is N-type doping, the second doping type is P-type doping; conversely, when the first doping type is P-type doping, the second doping type is N-type doping.

[0108] Thus, by introducing the first base region 11 and the second base region 12 having the opposite doping type to the first base region 11, when the device is just turned off, the drain-source voltage V ds The existence of the second base region 12 makes the overlapping area between the gate and the drain smaller, so that the gate-drain capacitance C gdSmaller, and smaller gate-drain capacitance C gd The dV / dt in the early stage of device shutdown is increased, making it have a faster shutdown speed and reducing the shutdown loss in this stage. dV / dt represents the first-order derivative of voltage with respect to time, and is also expressed as the slope of the voltage curve in the voltage change image, which is used to indicate the switching speed.

[0109] like Figure 3 As shown, when the drain voltage is 0~700V, the device is just turned off. At this time, it can be seen from the figure that the gate-drain capacitance of the silicon carbide planar gate MOSFET device proposed in this embodiment is much lower than the gate-drain capacitance of the traditional device. Therefore, the switching speed of the device in this embodiment is faster than that of the traditional device.

[0110] On the other hand, by introducing the second base region 12, the shielding effect on the gate dielectric 4 is more obvious. Compared with the traditional device, the electric field peak of the gate dielectric 4 is reduced. Specifically, since the second base region 12 is of the second type of doping, which is opposite to the doping type of the current diffusion layer 8, it will attract a part of the electric field lines not to point to the gate but to point to the second base region 12, thereby achieving a better shielding effect on the gate dielectric 4. Due to the better shielding effect, the peak electric field of the gate dielectric 4 is reduced.

[0111] When the device enters the end of the turn-off transient, the drain-source voltage V ds The gate-drain capacitance C increases significantly, and since the first base region 11 has a depletion effect on the second base region 12, the second base region 12 is depleted, so the overlapping area between the gate and the drain increases, which leads to the gate-drain capacitance C gd The dV / dt is relatively small, which ultimately reduces the overshoot and oscillation of the voltage and current of the device and reduces the electromagnetic interference EMI of the device.

[0112] like Figure 4 As shown in the figure, when the device enters the end of the turn-off transient, the drain-source voltage of the silicon carbide planar gate MOSFET device proposed in this embodiment and the traditional device changes with time. It can be seen from the dotted ellipse part circled in the figure that the switching speed of the device of this embodiment is faster; it can be seen from the dotted box part circled in the figure that the switching oscillation of this embodiment is smaller, and thus the electromagnetic interference generated is smaller.

[0113] It should be noted that the overlapping area between the gate and the drain in this embodiment refers to the area where the gate is directly projected on the drain, which can also be understood as the area where the gate is exposed to the drain. Figure 1 As shown, in the conventional device, since no structure is provided in the current diffusion layer 8, the gate is completely exposed to the drain, so the overlapping area between the gate and the drain is large; and as shown in FIG. Figure 2As shown, in this embodiment, due to the presence of the second base region 12, the first base region 11 is of the first doping type, and the second base region 12 is of the second doping type, which is opposite to the doping type of the first base region 11 and has a counter-effect on shielding the electric field. Therefore, the overlapping area between the gate and the drain is equivalent to only the part located between the two second base regions 12, so that when the device is just turned off, the overlapping area between the gate and the drain is smaller, thereby weakening the shielding effect on the gate dielectric 4.

[0114] In summary, from the perspective of the entire shutdown process, the shutdown loss and electromagnetic interference of the device proposed in this embodiment are significantly reduced.

[0115] On the other hand, by introducing the second base region 12 in the current diffusion layer 8, the short-circuit current flow position is also changed, the short-circuit peak current is reduced, and the short-circuit withstand time is increased, thereby increasing the short-circuit capability of the device. Specifically, the current of traditional devices flows from the drain through the substrate 5, the epitaxial layer 6, the current diffusion layer 8, the channel, the first source contact area 9, and finally flows to the source; while in the present application, due to the presence of the second base region 12, the channel is reduced when the current flows through the current diffusion layer, resulting in an increase in the resistance of the current diffusion layer, reducing the saturation current of the device, thereby reducing the short-circuit peak current, and due to the reduction in the short-circuit peak current, the temperature rise of the device is slowed down, thereby increasing the short-circuit withstand time.

[0116] Furthermore, in the present embodiment, the structure formed by the first base region 11 and the second base region 12 is provided with two groups, and the structures formed by the two groups of the first base region 11 and the second base region 12 are provided identically, and the structures formed by the two groups of the first base region 11 and the second base region 12 are respectively provided close to the sidewalls of the current diffusion layer 8, and are symmetrically provided in the current diffusion layer 8, and the first base region 11 and the second base region 12 are both provided with a doping concentration of 1×10 15 ~1×10 20 cm -3 semiconductor materials.

[0117] Among them, when the first base region 11 is entirely arranged in the second base region 12, since the upper surface of the first base region 11 is higher than the upper surface of the second base region 12, the shielding effect of the second base region 12 will be affected and exhausted in advance. Therefore, in this embodiment, the lower surfaces of the first base region 11 and the second base region 12 are arranged not lower than the lower surface of the current diffusion layer 8, and the upper surface of the first base region 11 is not higher than the upper surface of the second base region 12. Specifically, the second base region 12 is embedded in the current diffusion layer 8, and the side wall of the second base region 12 is in contact with the epitaxial well region 7. The first base region 11 is embedded in the second base region 12, and the side wall of the first base region 11 is in contact with the epitaxial well region 7. The lower surface of the second base region 12 and the lower surface of the first base region 11 are both in contact with the epitaxial layer 6.

[0118] In this embodiment, the doping concentration of the current diffusion layer 8 may be equal to or higher than the doping concentration of the epitaxial layer 6. Specifically, the doping concentration of the substrate 5 is set to 1×10 18 ~1×10 20 cm -3 ; The doping concentration of epitaxial layer 6 is set to 1×10 15 ~1×10 17 cm -3 ; The doping concentration of the epitaxial well region 7 is 1×10 16 ~1×10 19 cm -3 ; The doping concentration of the current diffusion layer 8 is 1×10 15 ~1×10 18 cm -3 The doping concentration of the first source contact region 9 and the second source contact region 10 is 1×10 18 ~1×10 20 cm -3 .

[0119] In this embodiment, the epitaxial layer 6 is made of N-type semiconductor material as an example. At this time, the first base region 11 has a doping concentration of 1×10 15 ~1×10 20 cm -3 The second base region 12 is an N-type semiconductor material with a doping concentration of 1×10 15 ~1×10 20 cm -3 The doping concentration of the first base region 11 may be higher than the doping concentration of the epitaxial layer 6, and the doping concentration of the second base region 12 may be equal to or different from the doping concentration of the first base region 11.

[0120] Furthermore, when the length of the first base region 11 in the second base region 12 is greater than or equal to the length of the second base region 12, the shielding effect of the second base region 12 on the gate will be weakened. When the device operates at a lower voltage, the gate-drain capacitance will not maintain a small value, which will affect the switching speed of the device. Therefore, in this embodiment, the first base region 11 is entirely or partially arranged in the second base region 12, so that the length of the first base region 11 in the second base region 12 is less than the length of the second base region 12, thereby ensuring the switching speed of the device.

[0121] Embodiment 2

[0122] like Figure 5 As shown, the difference between this embodiment and the first embodiment is that when the first base region 11 is entirely disposed in the second base region 12 , the lower surface of the second base region 12 is disposed in contact with the epitaxial layer 6 , and the lower surface of the first base region 11 is not disposed in contact with the epitaxial layer 6 .

[0123] In this embodiment, the first base region 11 is arranged to be in contact with only the epitaxial well region 7 and the second base region 12 , but not in direct contact with the epitaxial layer 6 , thereby increasing the process window of the depth of the first base region 11 .

[0124] Embodiment 3

[0125] like Figure 6 As shown, the difference between this embodiment and the first embodiment is that when the first base region 11 is entirely disposed in the second base region 12 , the lower surface of the second base region 12 is not in contact with the epitaxial layer 6 , and the lower surface of the first base region 11 is in contact with the current diffusion layer 8 .

[0126] In this embodiment, the second base region 12 is not in contact with the epitaxial layer 6, the lower surface of the first base region 11 is in contact with the current diffusion layer 8, and the lower surface of the first base region 11 coincides with the lower surface of the second base region 12. As a result, compared with the first embodiment, the first base region 11 and the second base region 12 of this embodiment are closer to the gate, thereby better reducing the electric field of the gate dielectric 4 and having a better inhibitory effect on the short circuit of the device.

[0127] Embodiment 4

[0128] like Figure 7 As shown, the difference between this embodiment and the first embodiment is that, when the first base region 11 is entirely disposed in the second base region 12, the second base region 12 is embedded in the current diffusion layer 8, and the side wall of the second base region 12 is in contact with the epitaxial well region 7, and the lower surface of the second base region 12 is in contact with the epitaxial layer 6, and the first base region 11 is embedded in the second base region 12, and the lower surface of the first base region 11 is in contact with the epitaxial layer 6, and the side wall of the first base region 11 is in contact with the second base region 12.

[0129] In this embodiment, the first base region 11 is configured to be in contact only with the second base region 12 and the epitaxial layer 6, so that the first base region 11 is not in direct contact with the epitaxial well region 7, thereby avoiding a high electric field strength in the device.

[0130] Embodiment 5

[0131] like Figure 8 As shown, the difference between this embodiment and the first embodiment is that when the first base region 11 is entirely disposed in the second base region 12, the second base region 12 is embedded in the current diffusion layer 8, and the side wall of the second base region 12 is disposed in contact with the epitaxial well region 7, the lower surface of the second base region 12 is disposed in contact with the epitaxial layer 6, the first base region 11 is embedded in the second base region 12, and the second base region 12 is disposed around the first base region 11.

[0132] In this embodiment, the first base region 11 is structurally arranged to be in contact with the second base region 12 only, so that the first base region 11 is not in direct contact with the epitaxial well region 7, thereby avoiding high electric field strength in the device. At the same time, compared with the fourth embodiment, since the first base region 11 may not be in direct contact with the epitaxial layer 6, the process window of the depth of the first base region 11 is increased.

[0133] Embodiment 6

[0134] The difference between this embodiment and the first embodiment is that there are more than two groups of first base regions 11 embedded in the second base region 12, the more than two groups of first base regions 11 are arranged in a polygonal shape, and the more than two groups of first base regions 11 are arranged at intervals in the second base region 12, or the more than two groups of first base regions 11 are arranged continuously in the second base region 12.

[0135] Specifically, Fig. 9 As shown, in this embodiment, the polygonal shape of the first base region 11 is a rectangle, and more than two groups of first base regions 11 are arranged in the second base region 12 at intervals.

[0136] On the one hand, in this embodiment, by introducing the first base region 11 and the second base region 12 having the opposite doping type to the first base region 11, when the device is just turned off, the drain-source voltage V ds Due to the presence of the second base region 12, the overlapping area between the gate and the drain is smaller than that of the conventional device, so the gate-drain capacitance C gd smaller, thus through a smaller C gd The dV / dt at the early stage of device shutdown is increased, which makes the device turn off faster and reduces the shutdown loss at this stage; when the device enters the end of the shutdown transient, the drain-source voltage V ds The gate-drain capacitance C increases significantly. Due to the depletion effect of the first base region 11 on the second base region 12, the second base region 12 is depleted, so the overlapping area between the gate and the drain increases, resulting in a gate-drain capacitance C gd The dV / dt is significantly increased, and the dV / dt is small, which reduces the overshoot and oscillation of the voltage and current of the device and reduces the EMI of the device; on the other hand, by introducing the second base region 12, the shielding effect of the gate dielectric 4 is more obvious, and the electric field peak of the gate dielectric 4 is reduced compared with the traditional device; at the same time, by introducing the second base region 12 in the current diffusion layer 8, the short-circuit current flow position is changed, the short-circuit peak current is reduced, and the short-circuit withstand time is increased, thereby increasing the short-circuit capability of the device.

[0137] Embodiment 7

[0138] The difference between this embodiment and the first embodiment is that there are more than two groups of first base regions 11 embedded in the second base region 12, the more than two groups of first base regions 11 are arranged in a polygonal shape, and the more than two groups of first base regions 11 are arranged at intervals in the second base region 12, or the more than two groups of first base regions 11 are arranged continuously in the second base region 12.

[0139] Specifically, Fig.10 As shown, in this embodiment, the polygonal shape of the first base region 11 is a triangle, and more than two groups of first base regions 11 are continuously arranged in the second base region 12 .

[0140] On the one hand, in this embodiment, by introducing the first base region 11 and the second base region 12 having the opposite doping type to the first base region 11, when the device is just turned off, the drain-source voltage V ds Due to the presence of the second base region 12, the overlapping area between the gate and the drain is smaller than that of the conventional device, so the gate-drain capacitance C gd smaller, thus through a smaller C gd The dV / dt at the early stage of device shutdown is increased, which makes the device turn off faster and reduces the shutdown loss at this stage; when the device enters the end of the shutdown transient, the drain-source voltage V ds The gate-drain capacitance C increases significantly. Due to the depletion effect of the first base region 11 on the second base region 12, the second base region 12 is depleted, so the overlapping area between the gate and the drain increases, resulting in a gate-drain capacitance C gd The dV / dt is significantly increased, and the dV / dt is small, which reduces the overshoot and oscillation of the voltage and current of the device and reduces the EMI of the device; on the other hand, by introducing the second base region 12, the shielding effect of the gate dielectric 4 is more obvious, and the electric field peak of the gate dielectric 4 is reduced compared with the traditional device; at the same time, by introducing the second base region 12 in the current diffusion layer 8, the short-circuit current flow position is changed, the short-circuit peak current is reduced, and the short-circuit withstand time is increased, thereby increasing the short-circuit capability of the device.

[0141] Embodiment 8

[0142] like Fig.11 As shown, the difference between this embodiment and embodiment 1 is that when the first base region 11 is partially disposed in the second base region 12, the upper surface of the first base region 11 is not higher than the upper surface of the second base region 12. Specifically, the second base region 12 is embedded in the current diffusion layer 8, and the side wall of the second base region 12 is in contact with the epitaxial well region 7, and the lower surface of the second base region 12 is not in contact with the epitaxial layer 6. The side wall of the first base region 11 partially disposed in the second base region 12 is in contact with the epitaxial well region 7, and the lower surface of the first base region 11 is in contact with the epitaxial layer 6.

[0143] In the arrangement of this embodiment, the second base region 12 is not in contact with the epitaxial layer 6 , thereby increasing the process window of the depth of the second base region 12 compared with the first embodiment.

[0144] Embodiment 9

[0145] like Fig.12 As shown, the difference between this embodiment and the eighth embodiment is that when the first base region 11 is partially disposed in the second base region 12, the second base region 12 is embedded in the current diffusion layer 8, and the side wall of the second base region 12 is in contact with the epitaxial well region 7, the lower surface of the second base region 12 and the lower surface of the first base region 11 are both in contact with the epitaxial layer 6, and the first base region 11 is partially embedded in the epitaxial well region 7 and in contact with the epitaxial well region 7.

[0146] In this embodiment, when the first base region 11 is partially arranged in the second base region 12, the first base region 11 is extended in the second dimension so that a part of the first base region 11 is arranged in the second base region 12 and the other part is arranged in the epitaxial well region 7. The structural arrangement of this embodiment can increase the process window of the device design while achieving the same effect as the first embodiment, thereby reducing the process difficulty to a certain extent.

[0147] Embodiment 10

[0148] like Fig.13 As shown, the difference between this embodiment and the first embodiment is that the structure formed by the first base region 11 and the second base region 12 in this embodiment is provided in a group.

[0149] Compared with the first embodiment, this embodiment only sets a group of structures consisting of the first base region 11 and the second base region 12, which can achieve the same effect as the first embodiment. Compared with the first embodiment, the number of ion implantations can be reduced, making the process simpler.

[0150] Embodiment 11

[0151] The difference between this embodiment and the first embodiment is that the structures formed by the two groups of first base regions 11 and second base regions 12 in this embodiment are set differently. The structures formed by the two groups of first base regions 11 and second base regions 12 are respectively set close to the side walls of the current diffusion layer 8 and are spaced apart in the current diffusion layer 8.

[0152] like Fig.14 As shown, in this embodiment, the structure formed by one group of the first base regions 11 and the second base regions 12 is set to the same structure as that of the first embodiment, and the structure formed by the other group of the first base regions 11 and the second base regions 12 is set to the same structure as that of the ninth embodiment, thereby forming two groups of first base regions 11 and second base regions 12 with different structures.

[0153] Compared with the first embodiment, the present embodiment has a different structure formed by two groups of first base regions 11 and second base regions 12, so that when processing one group of the first base regions 11 and the second base regions 12, the process window of the device is increased, thereby reducing the process difficulty to a certain extent.

[0154] Embodiment 12

[0155] The difference between this embodiment and the first embodiment is that this embodiment further designs the third dimension of the silicon carbide planar gate MOSFET device. Specifically, this embodiment sets the direction of the current diffusion layer 8 toward the epitaxial layer 6 as the first direction; the direction of the current diffusion layer 8 toward the epitaxial well region 7 and perpendicular to the first direction is the second direction; the direction perpendicular to the plane formed by the first direction and the second direction is the third direction, wherein the third direction here is the aforementioned third dimension, and the cross-sectional view of the silicon carbide planar gate MOSFET device on the plane formed by the second direction and the third direction is a polygon.

[0156] Specifically, Fig.15 As shown, in this embodiment, the cross-sectional view is set to a rectangle. At this time, the first base region 11 and the second base region 12 are continuously distributed in the third direction, and the second source contact region 10 is continuously distributed in the third direction.

[0157] In this embodiment, the first base region 11 and the second base region 12 are continuously distributed in the third direction, and the second source contact region 10 is continuously distributed in the third direction, thereby increasing the range of the second base region 12 and enhancing the shielding effect of the second base region 12 on the gate dielectric 4. At the same time, due to the depletion effect of the first base region 11 on the second base region 12, the second base region 12 is depleted, so that the overlapping area between the gate and the drain becomes larger, resulting in a gate-drain capacitance C gd The dV / dt is significantly increased, which reduces the overshoot and oscillation of the voltage and current of the device and reduces the EMI of the device.

[0158] Embodiment 13

[0159] like Fig.16 As shown, the difference between this embodiment and the twelfth embodiment is that the second source contact regions 10 of this embodiment are distributed in sections and intervals in the third direction.

[0160] In this embodiment, the second source contact regions 10 are arranged in segments and intervals in the third direction, thereby increasing the contact area between the first source contact region 9 and the source electrode 2 and reducing the contact resistance thereof, compared with the twelfth embodiment.

[0161] Embodiment 14

[0162] like Fig.17As shown, the difference between this embodiment and the twelve embodiment is that when the cross-sectional view is set to a rectangle and the second source contact region 10 is continuously distributed in the third direction, the second base region 12 of this embodiment is continuously distributed in the third direction, and the first base region 11 is distributed in segments and intervals in the third direction.

[0163] In this embodiment, the first base regions 11 are arranged in segmented and spaced distributions in the third direction, thereby increasing the range of the second base regions 12 and enhancing the shielding effect of the second base regions 12 on the gate dielectric 4 .

[0164] Embodiment 15

[0165] like Fig.18 As shown, the difference between this embodiment and the twelfth embodiment is that when the cross-sectional view is set to a rectangle and the second source contact region 10 is continuously distributed in the third direction, the first base region 11 and the second base region 12 of this embodiment are both distributed in segments in the third direction.

[0166] In this embodiment, the first base region 11 and the second base region 12 are evenly distributed in segments in the third direction, thereby increasing the range of the current diffusion layer 8, reducing the resistance of the current diffusion layer 8, reducing the on-resistance of the device, and further reducing the conduction loss of the device during operation.

[0167] Embodiment 16

[0168] like Fig.19 As shown, the difference between this embodiment and embodiment twelfth is that this embodiment sets the cross-sectional view to be a square, and at this time, the first base region 11 and the second base region 12 are set to surround the epitaxial well region 7 in the cross-sectional view, and the first base region 11 and the second base region 12 are both continuously distributed.

[0169] Compared with the twelfth embodiment, the present embodiment obtains a square unit cell design by setting the cross-section to a square, thereby increasing the area of ​​the current diffusion layer 8 of the unit cell, reducing the specific on-resistance, and reducing the conduction loss of the device.

[0170] Embodiment 17

[0171] like Fig. 20 As shown, the difference between this embodiment and embodiment sixteen is that after the cross-sectional view is set to a square, the first base region 11 and the second base region 12 of this embodiment are set to surround the epitaxial well region 7 in the cross-sectional view, and the second base region 12 is continuously distributed, and the first base region 11 is segmented and spaced.

[0172] Compared with the sixteenth embodiment, the present embodiment increases the range of the second base region 12 by distributing the first base region 11 in sections and intervals, thereby enhancing the shielding effect of the second base region 12 on the gate dielectric 4 .

[0173] Embodiment 18

[0174] like Fig.21 As shown, the difference between this embodiment and embodiment sixteen is that after the cross-sectional view is set to a square, the first base region 11 and the second base region 12 of this embodiment are set to surround the epitaxial well region 7 in the cross-sectional view, and the first base region 11 and the second base region 12 are both distributed in segmented intervals.

[0175] Compared with the sixteenth embodiment, the first base region 11 and the second base region 12 are distributed in segments, thereby increasing the range of the current diffusion layer 8 and reducing the resistance of the current diffusion layer 8, thereby reducing the on-resistance of the device and further reducing the conduction loss of the device during operation.

[0176] Embodiment 19

[0177] like Fig. 22 As shown, the difference between this embodiment and embodiment twelfth is that this embodiment sets the cross-sectional view to be a hexagon. At this time, the first base region 11 and the second base region 12 of this embodiment are set to surround the epitaxial well region 7 in the cross-sectional view, and the first base region 11 and the second base region 12 are both continuously distributed.

[0178] In this embodiment, the area of ​​the current diffusion layer 8 of the unit cell is increased by setting the hexagonal unit cell, the specific on-resistance is reduced, and the conduction loss of the device is reduced.

[0179] Embodiment 20

[0180] like Fig.23 As shown, the difference between this embodiment and Embodiment 19 is that after the cross-sectional view is set to a hexagon, the first base region 11 and the second base region 12 of this embodiment are set to surround the epitaxial well region 7 in the cross-sectional view, and the second base region 12 is continuously distributed, and the first base region 11 is segmented and spaced.

[0181] In this embodiment, the first base region 11 is arranged to be distributed in segments and intervals, thereby increasing the range of the second base region 12 and further enhancing the shielding effect of the second base region 12 on the gate dielectric 4 .

[0182] Embodiment 21

[0183] like Fig.24 As shown, the difference between this embodiment and the nineteenth embodiment is that after the cross-sectional view is set to a hexagon, the first base region 11 and the second base region 12 of this embodiment are set to surround the epitaxial well region 7 in the cross-sectional view, and the first base region 11 and the second base region 12 are both distributed in segmented intervals.

[0184] In this embodiment, the first base region 11 and the second base region 12 are both distributed in segments, thereby increasing the range of the current diffusion layer 8 and reducing the resistance of the power diffusion layer, thereby reducing the on-resistance of the device and further reducing the conduction loss of the device during operation.

[0185] Embodiment 22

[0186] like Fig.25 As shown, a silicon carbide planar gate MOSFET device includes a substrate 5, a drain electrode 1 formed on one end surface of the substrate 5, an epitaxial layer 6 formed on the other end surface of the substrate 5, a current diffusion layer 8 formed on the epitaxial layer 6, an epitaxial well region 7 formed on the current diffusion layer 8, and the sidewall and the lower surface of the epitaxial well region 7 are both arranged in contact with the current diffusion layer 8, a first source contact region 9 formed in the epitaxial well region 7 and a second source contact region 10 formed in the epitaxial well region 7, the first source contact region 9 is arranged in contact with the second source contact region 10, and the first source contact region 9 and the second source contact region 10 are located on the same surface, and a source electrode 2 is also arranged on the second source contact region 10, and the source electrode 2 It is also arranged in contact with part of the first source contact area 9, a planar gate is also arranged on the current diffusion layer 8 and the epitaxial well area 7, the planar gate is also in contact with part of the first source contact area 9, the planar gate is not arranged in contact with the source electrode 2, a first base area 11 and a second base area 12 are arranged in the current diffusion layer 8, and the first base area 11 is entirely arranged in the second base area 12, or the first base area 11 is partially arranged in the second base area 12, the substrate 5, the epitaxial layer 6, the current diffusion layer 8, the first source contact area 9 and the first base area 11 are all of the first doping type, the epitaxial well area 7, the second source contact area 10, and the second base area 12 are all of the second doping type, and the first doping type and the second doping type are opposite doping types.

[0187] The direction of the current diffusion layer 8 toward the epitaxial layer 6 is the first direction; the direction of the current diffusion layer 8 toward the epitaxial well region 7 and perpendicular to the first direction is the second direction; the direction perpendicular to the plane formed by the first direction and the second direction is the third direction, and the cross-sectional view of the silicon carbide planar gate MOSFET device on the plane formed by the second direction and the third direction is a polygon.

[0188] The structure formed by the first base region 11 and the second base region 12 is provided in one group or two groups.

[0189] When there are two groups of structures formed by the first base region 11 and the second base region 12 , the two groups of structures formed by the first base region 11 and the second base region 12 are respectively arranged close to the sidewalls of the current diffusion layer 8 , and are symmetrically arranged in the current diffusion layer 8 .

[0190] The upper surface of the first base region 11 is not higher than the upper surface of the second base region 12. The second base region 12 is embedded in the current diffusion layer 8, and the side wall of the second base region 12 is in contact with the side wall of the epitaxial well region 7. The first base region 11 is embedded in the second base region 12, and the side wall of the first base region 11 is in contact with the side wall of the epitaxial well region 7.

[0191] In this embodiment, the current diffusion layer 8 extends to below the epitaxial well region 7. Compared with the first embodiment, the current diffusion layer 8 in this embodiment has a larger range, which reduces the resistance of the current diffusion layer 8. At the same time, in this embodiment, the epitaxial well region 7 is separated from the epitaxial layer 6 by the current diffusion layer 8, which facilitates the diffusion of current, reduces the on-resistance of the device, and further reduces the conduction loss of the device during operation.

[0192] Embodiment 23

[0193] like Fig.26 As shown, a method for manufacturing a silicon carbide planar gate MOSFET device is used to manufacture the silicon carbide planar gate MOSFET device as described in any one of Embodiments 1 to 22, comprising the following steps:

[0194] S1. An epitaxial layer 6 is grown on the surface of the substrate 5, wherein the doping concentration of the epitaxial layer 6 is 1×10 15 ~1×10 17 cm -3 ;

[0195] S2, forming a second base region 12, a portion of the epitaxial well region 7 and a portion of the current diffusion layer 8 in the epitaxial layer 6 by photolithography and ion implantation, and forming a first base region 11 in the second base region 12 by high-energy ion implantation, wherein the first base region 11 and the second base region 12 are both doped with a concentration of 1×10 15 ~1×10 20 cm -3 Semiconductor materials;

[0196] S3, continue to grow the epitaxial layer 6, and form the current diffusion layer 8 and the epitaxial well region 7 by ion implantation, wherein the doping concentration of the current diffusion layer 8 is 1×10 15 ~1×10 18 cm -3 , the doping concentration of the epitaxial well region 7 is 1×10 16 ~1×10 19 cm -3 ;

[0197] S4, forming a first source contact region 9 and a second source contact region 10 on the surface of the epitaxial well region 7 by ion implantation, wherein the implantation of the first source contact region 9 uses a self-aligned process, and the doping concentrations of the first source contact region 9 and the second source contact region 10 are both 1×10 18~1×10 20 cm -3 ;

[0198] S5, after the ion implantation, an activation annealing treatment is performed, and a gate dielectric 4 is formed on the device surface by any one of high temperature oxidation, chemical vapor deposition, physical vapor deposition or atomic layer deposition processes, and then a NO interface annealing treatment is performed;

[0199] S6, depositing an N-type polysilicon gate on the surface of the gate dielectric 4, and etching the N-type polysilicon gate and the gate dielectric 4;

[0200] S7, removing excess polysilicon and gate dielectric 4, wherein the N-type polysilicon gate in this embodiment is the gate electrode 3 in Embodiments 1 to 22;

[0201] S8. Make ohmic contacts on the surface and back of the device, fill the gate dielectric 4 around the polysilicon gate, prepare the drain electrode 1 on the back of the substrate 5 by sputtering, evaporation or annealing, and prepare the source electrode 2 on the first source contact area 9 and the second source contact area 10.

[0202] Embodiment 24

[0203] like Fig. 27 As shown, a method for manufacturing a silicon carbide planar gate MOSFET device is used to manufacture the silicon carbide planar gate MOSFET device as described in any one of Embodiments 1 to 22, comprising the following steps:

[0204] S1. An epitaxial layer 6 is grown on the surface of the substrate 5, wherein the doping concentration of the epitaxial layer 6 is 1×10 15 ~1×10 17 cm -3 ;

[0205] S2, forming a current diffusion layer 8 and an epitaxial well region 7 in the epitaxial layer 6 by ion implantation, wherein the doping concentration of the current diffusion layer 8 is 1×10 15 ~1×10 18 cm -3 , the doping concentration of the epitaxial well region 7 is 1×10 16 ~1×10 19 cm -3 ;

[0206] S3, forming a first base region 11 and a second base region 12 in the current diffusion layer 8 by high energy ion implantation, wherein the first base region 11 and the second base region 12 are both doped with a concentration of 1×10 15 ~1×10 20 cm -3 Semiconductor materials;

[0207] S4, forming a first source contact region 9 and a second source contact region 10 on the surface of the epitaxial well region 7 by ion implantation, wherein the implantation of the first source contact region 9 uses a self-aligned process, and the doping concentrations of the first source contact region 9 and the second source contact region 10 are both 1×10 18 ~1×10 20 cm -3 ;

[0208] S5, after the ion implantation, an activation annealing treatment is performed, and a gate dielectric 4 is formed on the device surface by any one of high temperature oxidation, chemical vapor deposition, physical vapor deposition or atomic layer deposition processes, and then a NO interface annealing treatment is performed;

[0209] S6, depositing an N-type polysilicon gate on the surface of the gate dielectric 4, and etching the N-type polysilicon gate and the gate dielectric 4;

[0210] S7, removing excess polysilicon and gate dielectric, wherein the N-type polysilicon gate in this embodiment is the gate electrode 3 in Embodiments 1 to 22;

[0211] S8. Make ohmic contacts on the surface and back of the device, fill the gate dielectric 4 around the polysilicon gate, prepare the drain electrode 1 on the back of the substrate 5 by sputtering, evaporation or annealing, and prepare the source electrode 2 on the first source contact area 9 and the second source contact area 10.

[0212] Embodiment 25

[0213] like Fig.28 As shown, a method for manufacturing a silicon carbide planar gate MOSFET device is used to manufacture a silicon carbide planar gate MOSFET device as any one of Embodiments 1 to 22, comprising the following steps:

[0214] S1. An epitaxial layer 6 is grown on the surface of the substrate 5, wherein the doping concentration of the epitaxial layer 6 is 1×10 15 ~1×10 17 cm -3 ;

[0215] S2, forming the first base region 11, part of the second base region 12, part of the current diffusion layer 8 and part of the epitaxial well region 7 in the epitaxial layer 6 by ion implantation, wherein the doping concentration of the current diffusion layer 8 is 1×10 15 ~1×10 18 cm -3 , the doping concentration of the epitaxial well region 7 is 1×10 16 ~1×10 19 cm -3 The first base region 11 and the second base region 12 are both doped with a concentration of 1×10 15 ~1×10 20cm -3 Semiconductor materials;

[0216] S3, continue to grow the epitaxial layer 6, and form the remaining second base region 12, part of the current diffusion layer 8 and part of the epitaxial well region 7 by ion implantation;

[0217] S4, continue to grow the epitaxial layer 6, and form the remaining current diffusion layer 8 and the remaining epitaxial well region 7 by ion implantation;

[0218] S5. Form a first source contact region 9 and a second source contact region 10 on the surface of the epitaxial well region 7 by ion implantation, wherein the implantation of the first source contact region 9 uses a self-aligned process, and the doping concentrations of the first source contact region 9 and the second source contact region 10 are both 1×10 18 ~1×10 20 cm -3 ;

[0219] S6, after the ion implantation, an activation annealing treatment is performed, and a gate dielectric 4 is formed on the device surface by any one of high temperature oxidation, chemical vapor deposition, physical vapor deposition or atomic layer deposition processes, and then a NO interface annealing treatment is performed;

[0220] S7, depositing an N-type polysilicon gate on the surface of the gate dielectric 4, and etching the N-type polysilicon gate and the gate dielectric 4;

[0221] S8, removing excess polysilicon and gate dielectric 4, wherein the N-type polysilicon gate in this embodiment is the gate electrode 3 in Embodiments 1 to 22;

[0222] S9. Make ohmic contacts on the surface and back of the device, fill the gate dielectric 4 around the polysilicon gate, prepare the drain electrode 1 on the back of the substrate 5 by sputtering, evaporation or annealing, and prepare the source electrode 2 on the first source contact area 9 and the second source contact area 10.

[0223] The above is only a preferred embodiment of the present invention, and is not any formal or substantial limitation of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and supplements without departing from the method of the present invention, and these improvements and supplements should also be regarded as the protection scope of the present invention. Any technician familiar with this profession, without departing from the spirit and scope of the present invention, can make some changes, modifications and evolutions of the technical content disclosed above, which are equivalent embodiments of the present invention; at the same time, any changes, modifications and evolutions of any equivalent changes made to the above embodiments based on the essential technology of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A silicon carbide planar gate MOSFET device, characterized in that: The present invention comprises a substrate, a drain electrode formed on one end surface of the substrate, an epitaxial layer formed on the other end surface of the substrate, a current diffusion layer formed on the epitaxial layer, an epitaxial well region formed on the epitaxial layer, a first source contact region formed in the epitaxial well region, and a second source contact region formed in the epitaxial well region, wherein the current diffusion layer is arranged in contact with the epitaxial well region, and the current diffusion layer and the epitaxial well region are located on the same surface, the first source contact region is arranged in contact with the second source contact region, and the first source contact region and the second source contact region are located on the same surface, a source electrode is also arranged on the second source contact region, and the source electrode is also connected to a part of the first source The contact areas are arranged in contact with each other, a planar gate is also arranged on the current diffusion layer and the epitaxial well area, the planar gate is also in contact with part of the first source contact area, the planar gate is arranged without contact with the source electrode, a first base area and a second base area are arranged in the current diffusion layer, and the first base area is entirely arranged in the second base area, or the first base area is partially arranged in the second base area, the substrate, the epitaxial layer, the current diffusion layer, the first source contact area and the first base area are all of the first doping type, the epitaxial well area, the second source contact area and the second base area are all of the second doping type, and the first doping type and the second doping type are opposite doping types.

2. A silicon carbide planar gate MOSFET device according to claim 1, characterized in that: When the first base region is entirely disposed in the second base region, lower surfaces of the first base region and the second base region are not lower than a lower surface of the current diffusion layer, and an upper surface of the first base region is not higher than an upper surface of the second base region.

3. A silicon carbide planar gate MOSFET device according to claim 2, characterized in that: The second base region is embedded in the current diffusion layer, and the sidewall of the second base region is in contact with the epitaxial well region. The first base region is embedded in the second base region, and the sidewall of the first base region is in contact with the epitaxial well region.

4. A silicon carbide planar gate MOSFET device according to claim 3, characterized in that: The lower surface of the second base region and the lower surface of the first base region are both arranged in contact with the epitaxial layer.

5. A silicon carbide planar gate MOSFET device according to claim 3, characterized in that: The lower surface of the second base region is disposed in contact with the epitaxial layer, and the lower surface of the first base region is disposed not in contact with the epitaxial layer.

6. A silicon carbide planar gate MOSFET device according to claim 3, characterized in that: The lower surface of the second base region is not in contact with the epitaxial layer, and the lower surface of the first base region is in contact with the current diffusion layer.

7. A silicon carbide planar gate MOSFET device according to claim 2, characterized in that: The second base region is embedded in the current diffusion layer, and the side wall of the second base region is in contact with the epitaxial well region, the lower surface of the second base region is in contact with the epitaxial layer, the first base region is embedded in the second base region, and the lower surface of the first base region is in contact with the epitaxial layer, and the side wall of the first base region is in contact with the second base region.

8. A silicon carbide planar gate MOSFET device according to claim 2, characterized in that: The second base region is embedded in the current diffusion layer, and the side wall of the second base region is in contact with the epitaxial well region, the lower surface of the second base region is in contact with the epitaxial layer, the first base region is embedded in the second base region, and the second base region surrounds the first base region.

9. A silicon carbide planar gate MOSFET device according to any one of claims 4 to 8, characterized in that: There are more than two groups of first base regions embedded in the second base region, the more than two groups of the first base regions are arranged in a polygonal shape, and the more than two groups of the first base regions are arranged at intervals in the second base region, or the more than two groups of the first base regions are arranged continuously in the second base region.

10. A silicon carbide planar gate MOSFET device according to claim 9, characterized in that: The polygonal shape of the first base region is a rectangle, and more than two groups of the first base regions are arranged in the second base region at intervals.

11. The silicon carbide planar gate MOSFET device according to claim 9, characterized in that: The polygonal shape of the first base region is a triangle, and more than two groups of the first base regions are continuously arranged in the second base region.

12. The silicon carbide planar gate MOSFET device according to claim 1, characterized in that: When the first base region is partially disposed in the second base region, an upper surface of the first base region is not higher than an upper surface of the second base region.

13. A silicon carbide planar gate MOSFET device according to claim 12, characterized in that: The second base region is embedded in the current diffusion layer, and the sidewall of the second base region is in contact with the epitaxial well region, and the lower surface of the second base region is not in contact with the epitaxial layer.

14. A silicon carbide planar gate MOSFET device according to claim 13, characterized in that: A side wall of the first base region partially disposed in the second base region is disposed in contact with the epitaxial well region, and a lower surface of the first base region is disposed in contact with the epitaxial layer.

15. The silicon carbide planar gate MOSFET device according to claim 12, characterized in that: The second base region is embedded in the current diffusion layer, and the side wall of the second base region is in contact with the epitaxial well region. The lower surface of the second base region and the lower surface of the first base region are both in contact with the epitaxial layer. The first base region is partially embedded in the epitaxial well region and in contact with the epitaxial well region.

16. A silicon carbide planar gate MOSFET device according to any one of claims 10, 11, 14 and 15, characterized in that: The structure formed by the first base region and the second base region is provided in one group or two groups.

17. A silicon carbide planar gate MOSFET device according to claim 16, characterized in that: When there are two groups of structures formed by the first base region and the second base region, the structures formed by the two groups of the first base region and the second base region are arranged to be the same or different.

18. A silicon carbide planar gate MOSFET device according to claim 17, characterized in that: When the structures formed by the two groups of the first base regions and the second base regions are set to be the same, the structures formed by the two groups of the first base regions and the second base regions are respectively set close to the side walls of the current diffusion layer, and are symmetrically arranged at intervals in the current diffusion layer; when the structures formed by the two groups of the first base regions and the second base regions are set to be different, the structures formed by the two groups of the first base regions and the second base regions are respectively set close to the side walls of the current diffusion layer, and are arranged at intervals in the current diffusion layer.

19. A silicon carbide planar gate MOSFET device according to claim 18, characterized in that: The direction of the current diffusion layer toward the epitaxial layer is the first direction; the direction of the current diffusion layer toward the epitaxial well region and perpendicular to the first direction is the second direction; the direction perpendicular to the plane formed by the first direction and the second direction is the third direction, and the cross-sectional view of the silicon carbide planar gate MOSFET device on the plane formed by the second direction and the third direction is a polygon.

20. A silicon carbide planar gate MOSFET device according to claim 19, characterized in that: When the cross-sectional view is rectangular, the second source contact regions are continuously distributed in the third direction.

21. The silicon carbide planar gate MOSFET device according to claim 19, characterized in that: When the cross-sectional view is rectangular, the second source contact regions are distributed in sections and at intervals in the third direction.

22. A silicon carbide planar gate MOSFET device according to claim 20 or 21, characterized in that: The first base region and the second base region are continuously distributed in the third direction.

23. A silicon carbide planar gate MOSFET device according to claim 20 or 21, characterized in that: The second base regions are distributed continuously in the third direction, and the first base regions are distributed segmented and spaced in the third direction.

24. A silicon carbide planar gate MOSFET device according to claim 20 or 21, characterized in that: The first base region and the second base region are evenly distributed in sections and at intervals in the third direction.

25. The silicon carbide planar gate MOSFET device according to claim 19, characterized in that: When the cross-sectional view is a square, the first base region and the second base region are arranged to surround the epitaxial well region in the cross-sectional view, and the first base region and the second base region are both continuously distributed.

26. A silicon carbide planar gate MOSFET device according to claim 19, characterized in that: When the cross-sectional view is a square, the first base region and the second base region are arranged to surround the epitaxial well region in the cross-sectional view, and the second base region is continuously distributed, and the first base region is segmented and spaced apart.

27. A silicon carbide planar gate MOSFET device according to claim 19, characterized in that: When the cross-sectional view is a square, the first base region and the second base region are arranged to surround the epitaxial well region in the cross-sectional view, and the first base region and the second base region are both distributed in segments.

28. A silicon carbide planar gate MOSFET device according to claim 19, characterized in that: When the cross-sectional view is a hexagon, the first base region and the second base region are arranged to surround the epitaxial well region in the cross-sectional view, and the first base region and the second base region are continuously distributed.

29. The silicon carbide planar gate MOSFET device according to claim 19, characterized in that: When the cross-sectional view is hexagonal, the first base region and the second base region are arranged to surround the epitaxial well region in the cross-sectional view, and the second base region is continuously distributed, and the first base region is segmented and spaced.

30. A silicon carbide planar gate MOSFET device according to claim 19, characterized in that: When the cross-sectional view is a hexagon, the first base region and the second base region are arranged to surround the epitaxial well region in the cross-sectional view, and the first base region and the second base region are both distributed in segmented intervals.

31. A silicon carbide planar gate MOSFET device, characterized in that: The invention comprises a substrate, a drain electrode formed on one end surface of the substrate, an epitaxial layer formed on the other end surface of the substrate, a current diffusion layer formed above the epitaxial layer, an epitaxial well region formed on the current diffusion layer, wherein the sidewall and the lower surface of the epitaxial well region are both arranged in contact with the current diffusion layer, a first source contact region formed in the epitaxial well region and a second source contact region formed in the epitaxial well region, wherein the first source contact region is arranged in contact with the second source contact region, and the first source contact region and the second source contact region are located on the same surface, and a source electrode is also arranged on the second source contact region, and the source electrode is also in contact with a portion of the first source contact region A planar gate is also arranged on the current diffusion layer and the epitaxial well region, the planar gate is also in contact with a portion of the first source contact region, the planar gate is arranged without contact with the source electrode, a first base region and a second base region are arranged in the current diffusion layer, and the first base region is entirely arranged in the second base region, or the first base region is partially arranged in the second base region, the substrate, the epitaxial layer, the current diffusion layer, the first source contact region and the first base region are all of the first doping type, the epitaxial well region, the second source contact region and the second base region are all of the second doping type, and the first doping type and the second doping type are opposite doping types.

32. A silicon carbide planar gate MOSFET device according to claim 31, characterized in that: The direction of the current diffusion layer toward the epitaxial layer is the first direction; the direction of the current diffusion layer toward the epitaxial well region and perpendicular to the first direction is the second direction; the direction perpendicular to the plane formed by the first direction and the second direction is the third direction, and the cross-sectional view of the silicon carbide planar gate MOSFET device on the plane formed by the second direction and the third direction is a polygon.

33. A silicon carbide planar gate MOSFET device according to claim 32, characterized in that: The structure formed by the first base region and the second base region is provided in one group or two groups.

34. A silicon carbide planar gate MOSFET device according to claim 33, characterized in that: When there are two groups of structures formed by the first base region and the second base region, the two groups of structures formed by the first base region and the second base region are respectively arranged close to the sidewalls of the current diffusion layer and are symmetrically arranged at intervals in the current diffusion layer.

35. A silicon carbide planar gate MOSFET device according to claim 34, characterized in that: The upper surface of the first base region is not higher than the upper surface of the second base region, the second base region is embedded in the current diffusion layer, and the side wall of the second base region is in contact with the side wall of the epitaxial well region, the first base region is embedded in the second base region, and the side wall of the first base region is in contact with the side wall of the epitaxial well region.

36. A method for manufacturing a silicon carbide planar gate MOSFET device, characterized in that: The manufacturing method is used to manufacture a silicon carbide planar gate MOSFET device as claimed in claim 1 or claim 31, comprising the following steps: An epitaxial layer is grown on the surface of the substrate, wherein the doping concentration of the epitaxial layer is 1×10 15 ~1×10 17 cm -3 ; A second base region, a portion of the epitaxial well region and a portion of the current diffusion layer are formed in the epitaxial layer by photolithography and ion implantation, and a first base region is formed in the second base region by high-energy ion implantation, wherein the first base region and the second base region are both doped with a concentration of 1×10 15 ~1×10 20 cm -3 Semiconductor materials; Continue to grow the epitaxial layer, and form a current diffusion layer and an epitaxial well region by ion implantation, wherein the doping concentration of the current diffusion layer is 1×10 15 ~1×10 18 cm -3 The doping concentration of the epitaxial well region is 1×10 16 ~1×10 19 cm -3 ; A first source contact region and a second source contact region are formed by ion implantation on the surface of the epitaxial well region, wherein the implantation of the first source contact region uses a self-aligned process, and the doping concentrations of the first source contact region and the second source contact region are both 1×10 18 ~1×10 20 cm -3 ; After the ion implantation, an activation annealing treatment is performed, and a gate dielectric is formed on the device surface by any one of high temperature oxidation, chemical vapor deposition, physical vapor deposition or atomic layer deposition processes, followed by NO interface annealing treatment; Depositing an N-type polysilicon gate on the surface of the gate dielectric, and etching the N-type polysilicon gate and the gate dielectric; Remove excess polysilicon and gate dielectric; Ohmic contacts are made on the surface and back of the device, gate dielectric is filled around the polysilicon gate, a drain electrode is prepared on the back of the substrate by sputtering, evaporation or annealing, and a source electrode is prepared on the first source contact area and the second source contact area.

37. A method for manufacturing a silicon carbide planar gate MOSFET device, characterized in that: The manufacturing method is used to manufacture a silicon carbide planar gate MOSFET device as claimed in claim 1 or claim 31, comprising the following steps: An epitaxial layer is grown on the surface of the substrate, wherein the doping concentration of the epitaxial layer is 1×10 15 ~1×10 17 cm -3 ; A current diffusion layer and an epitaxial well region are formed in the epitaxial layer by ion implantation, wherein the doping concentration of the current diffusion layer is 1×10 15 ~1×10 18 cm -3 The doping concentration of the epitaxial well region is 1×10 16 ~1×10 19 cm -3 ; A first base region and a second base region are formed in the current diffusion layer by high energy ion implantation, wherein the first base region and the second base region are both doped with a concentration of 1×10 15 ~1×10 20 cm -3 Semiconductor materials; A first source contact region and a second source contact region are formed by ion implantation on the surface of the epitaxial well region, wherein the implantation of the first source contact region uses a self-aligned process, and the doping concentrations of the first source contact region and the second source contact region are both 1×10 18 ~1×10 20 cm -3 ; After the ion implantation, an activation annealing treatment is performed, and a gate dielectric is formed on the device surface by any one of high temperature oxidation, chemical vapor deposition, physical vapor deposition or atomic layer deposition processes, followed by NO interface annealing treatment; Depositing an N-type polysilicon gate on the surface of the gate dielectric, and etching the N-type polysilicon gate and the gate dielectric; Remove excess polysilicon and gate dielectric; Ohmic contacts are made on the surface and back of the device, gate dielectric is filled around the polysilicon gate, a drain electrode is prepared on the back of the substrate by sputtering, evaporation or annealing, and a source electrode is prepared on the first source contact area and the second source contact area.

38. A method for manufacturing a silicon carbide planar gate MOSFET device, characterized in that: The manufacturing method is used to manufacture a silicon carbide planar gate MOSFET device as claimed in claim 1 or claim 31, comprising the following steps: An epitaxial layer is grown on the surface of the substrate, wherein the doping concentration of the epitaxial layer is 1×10 15 ~1×10 17 cm -3 ; A first base region, a portion of a second base region, a portion of a current diffusion layer and a portion of an epitaxial well region are formed in the epitaxial layer by ion implantation, wherein the doping concentration of the current diffusion layer is 1×10 15 ~1×10 18 cm -3 The doping concentration of the epitaxial well region is 1×10 16 ~1×10 19 cm -3 The first base region and the second base region both have a doping concentration of 1×10 15 ~1×10 20 cm -3 Semiconductor materials; Continue to grow the epitaxial layer, and form the remaining second base region, part of the current diffusion layer and part of the epitaxial well region by ion implantation; Continue to grow the epitaxial layer, and form the remaining current diffusion layer and the remaining epitaxial well region by ion implantation; A first source contact region and a second source contact region are formed by ion implantation on the surface of the epitaxial well region, wherein the implantation of the first source contact region uses a self-aligned process, and the doping concentrations of the first source contact region and the second source contact region are both 1×10 18 ~1×10 20 cm -3 ; After the ion implantation, an activation annealing treatment is performed, and a gate dielectric is formed on the device surface by any one of high temperature oxidation, chemical vapor deposition, physical vapor deposition or atomic layer deposition processes, followed by NO interface annealing treatment; Depositing an N-type polysilicon gate on the surface of the gate dielectric, and etching the N-type polysilicon gate and the gate dielectric; Remove excess polysilicon and gate dielectric; Ohmic contacts are made on the surface and back of the device, gate dielectric is filled around the polysilicon gate, a drain electrode is prepared on the back of the substrate by sputtering, evaporation or annealing, and a source electrode is prepared on the first source contact area and the second source contact area.

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