Semiconductor device and method of manufacturing the same

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. A semiconductor device includes: a first layer formed of silicon carbide of a first conductivity type; a second layer formed of silicon carbide of a second conductivity type on the first layer; a third layer formed of silicon carbide of the first conductivity type on the second layer; a plurality of stripe-shaped groove structures are formed from one side of the third layer to the first layer; wherein, in a transverse cross-sectional view, the groove structure is provided with a first bending part formed at the bottom part, and a second bending part formed between the bottom part and the side part.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to semiconductor devices and methods for manufacturing the same. Background Art

[0002] Patent document 1 (Japanese Patent Laid-Open No. 2023-013100) discloses a trench MOSFET. Trench MOSFET can increase the cell (component unit of the element) density per unit area and increase the current density per unit area, thereby reducing costs.

[0003] However, in a trench MOSFET, the electric field is concentrated at the bottom corners of the trench structure. Therefore, insulation breakdown may occur at the bottom corners of the trench structure. Summary of the invention

[0004] The present disclosure is made to solve the above-mentioned problems. An object of the present disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device that can suppress electric field concentration in a trench structure.

[0005] In a first aspect, an embodiment of the present disclosure provides a semiconductor device, including:

[0006] A first layer formed of first conductivity type silicon carbide;

[0007] a second layer, on the first layer, of first conductivity type silicon carbide formed;

[0008] a third layer, formed on the second layer, of second conductivity type silicon carbide; and

[0009] a plurality of groove structures formed in a stripe shape from one side of the third layer to the first layer;

[0010] The groove structure includes, in a transverse cross-sectional view, a first curved portion formed at a bottom portion, and a second curved portion formed between the bottom portion and a side portion.

[0011] In some of these embodiments,

[0012] The curvature radius of the first curved portion is greater than the curvature radius of the second curved portion.

[0013] In some embodiments, the radius of curvature of the first curved portion is 1.5 to 3 times the radius of curvature of the second curved portion.

[0014] In some of these embodiments,

[0015] The groove structure has a third curved portion in a transverse cross-sectional view.

[0016] The third curved portion is formed between the first curved portion and the second curved portion, and a curvature radius gradually decreases from a curvature of the first curved portion to a curvature of the second curved portion as moving from the first curved portion toward the second curved portion.

[0017] In some of these embodiments,

[0018] In the groove structure, the side portion is inclined in such a manner that an upper portion of the groove becomes wider.

[0019] In some of these embodiments,

[0020] The groove structure has a longitudinal curved portion in a longitudinal cross-sectional view, and the longitudinal curved portion is formed at an end portion and has a curvature radius greater than a curvature radius of the second curved portion.

[0021] In some of these embodiments,

[0022] The first layer, the second layer and the third layer are mainly formed of 4H silicon carbide,

[0023] The longitudinal direction of the groove structure is parallel to the (11-20) plane, (1-210) plane or (-2110) plane of the 4H silicon carbide hexagonal crystal, and the (11-20) plane, (1-210) plane or (-2110) plane is perpendicular to the main surface of the substrate formed by the first layer, the second layer and the third layer.

[0024] In some of these embodiments,

[0025] The first layer, the second layer and the third layer are mainly formed of 4H silicon carbide,

[0026] The longitudinal direction of the groove structure is parallel to the (1-100) plane, (10-10) plane or (0-110) plane of the 4H silicon carbide hexagonal crystal, and the (1-100) plane, (10-10) plane or (0-110) plane is perpendicular to the main surface of the substrate formed by the first layer, the second layer and the third layer.

[0027] In some of these embodiments,

[0028] The first layer is a drain layer and a drift layer, the second layer is a plurality of body layers, and the third layer is a plurality of source layers and are respectively formed on a side of the corresponding body layer away from the drain layer; and the first conductivity type is N type, and the second conductivity type is P type;

[0029] or

[0030] The first layer is a collector layer and a drift layer, the second layer is a plurality of main layers, and the third layer is a plurality of emitter layers; and the first conductivity type is P type, and the second conductivity type is N type.

[0031] In a second aspect, a method for manufacturing a semiconductor device is provided in this embodiment, comprising:

[0032] A first etching mask forming step, for a substrate formed of a first layer, a second layer, and a third layer, forming a first oxide film on the third layer, and forming a plurality of first stripe-shaped grooves with inclined sides on the first oxide film, thereby forming a first etching mask, wherein the first layer is formed of first conductive type silicon carbide, the second layer is formed of second conductive type silicon carbide on the first layer, and the third layer is formed of first conductive type silicon carbide on the second layer;

[0033] a second etching mask forming step, after the first etching mask forming step, forming a second oxide film on the first etching mask, forming a plurality of stripe-shaped second grooves with inclined sides and multi-stage curved bottoms at the positions of the plurality of stripe-shaped first grooves, thereby forming a second etching mask; and

[0034] The trench structure forming step is to anisotropically etch the substrate after the second etching mask forming step, thereby forming a plurality of stripe-shaped trench structures with inclined sides and multi-level complete bottoms in the range from the third layer side to the first layer.

[0035] According to the present disclosure, the electric field concentration of the trench structure can be suppressed by forming the first bent portion at the bottom of the trench structure and the second bent portion between the bottom and the side.

[0036] The details of one or more embodiments of the present disclosure are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings described herein are used to provide further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application.

[0038] Figure 1 This is a cross-sectional view of a main part of the semiconductor device in the first embodiment.

[0039] Figure 2 Schematic diagram showing a crystal plane of a 4H silicon carbide crystal used in the semiconductor device in the first embodiment.

[0040] Figure 3 This is a schematic diagram showing the crystal plane of the 4H silicon carbide crystal used in the semiconductor device in Embodiment 1, viewed from the (0001) plane side.

[0041] Figure 4 This is a cross-sectional view in the lateral direction of the trench structure of the semiconductor device in the first embodiment.

[0042] Figure 5 This is a cross-sectional view in the longitudinal direction of the trench structure of the semiconductor device in the first embodiment.

[0043] Figure 6 This is a schematic diagram for explaining the method for manufacturing the semiconductor device in the first embodiment.

[0044] Figure 7 This is a schematic diagram for explaining the method for manufacturing the semiconductor device in the first embodiment.

[0045] Figure 8 This is a schematic diagram for explaining a method for forming a trench structure of a semiconductor device in the first embodiment.

[0046] Fig. 9 This is a schematic diagram for explaining a method for forming a trench structure of a semiconductor device in the first embodiment.

[0047] Fig.10 Schematic diagram showing the optical image intensity distribution of a line and space pattern used to manufacture the semiconductor device in Embodiment 1.

[0048] Fig.11 This is a schematic diagram showing a sensitivity curve of a positive resist used for manufacturing the semiconductor device in the first embodiment.

[0049] Fig.12 1 and 2 are cross-sectional views of trench structures of the semiconductor device in Embodiment 1 and the first and second comparative examples.

[0050] Fig.13 This is a schematic diagram showing the electric field distribution near the trench structure of the semiconductor device in the first embodiment.

[0051] Fig.14 Schematic diagram showing the electric field distribution near the trench structure of the first comparative example.

[0052] Fig.15 Schematic diagram showing the electric field distribution near the trench structure of the second comparative example.

[0053] Fig.16 1 is a schematic diagram showing the comparison results of the electric field intensity near the trench structure between the semiconductor device in Embodiment 1 and the first comparative example and the second comparative example.

[0054] In the figure: 1. semiconductor device, 2. drain layer, 3. drift layer, 4. main layer, 5. source layer, 6. main contact layer, 7. gate insulating layer, 8. gate electrode layer, 9. interlayer insulating layer, 10. source electrode layer, 11. wiring electrode layer, 12. drain electrode layer, 13. first bend, 14. second bend, 15. third bend, 16. longitudinal bend, 17. first silicon dioxide film (first oxide film), 18. first anti-etching agent, 19. second silicon dioxide film (second oxide film), 20. second anti-etching agent, 21. bend, 22. bend. DETAILED DESCRIPTION

[0055] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0056] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "a", "a", "the", "these" and the like in this application do not represent quantitative restrictions, and they can be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether directly or indirectly. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, "A and / or B" can mean: A exists alone, A and B exist at the same time, and B exists alone. Usually, the character " / " indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0057] Implementation 1:

[0058] Figure 1 This is a cross-sectional view of a main part of the semiconductor device in the first embodiment.

[0059] exist Figure 1In the embodiment, the semiconductor device 1 is a trench-type silicon carbide MOSFET. The semiconductor device 1 includes a drain layer 2, a drift layer 3, a plurality of body layers 4, a plurality of source layers 5, a plurality of body contact layers 6, a plurality of gate insulating layers 7, a plurality of gate electrode layers 8, a plurality of interlayer insulating layers 9, a plurality of source electrode layers 10, a wiring electrode layer 11, and a drain electrode layer 12. The plurality of trench structures T are arranged along the Figure 1 The depth direction is formed into stripes. Figure 1 In the figure, only one of each of the plurality of gate insulating layers 7 , the plurality of gate electrode layers 8 , the plurality of interlayer insulating layers 9 , and the plurality of trench structures T is shown.

[0060] The drain layer 2 is formed of first conductivity type silicon carbide. + For example, the drain layer 2 is formed with nitrogen as an impurity. The drift layer 3 is formed as a first layer on the first surface ( Figure 1 The drift layer 3 is formed of first conductivity type silicon carbide, and its impurity concentration is lower than that of the drain layer 2. For example, the drift layer 3 is an n-type layer.

[0061] A plurality of body layers 4 are formed as the second layer on the upper side of the drift layer 3. The plurality of body layers 4 are formed of second conductive type silicon carbide. For example, the plurality of body layers 4 are p-type layers. A plurality of source layers 5 are formed as the third layer on the upper side of the plurality of body layers 4. The plurality of source layers 5 are formed of first conductive type silicon carbide, and the impurity concentration thereof is higher than that of the drift layer 3. For example, the plurality of source layers 5 are n-type layers. + The plurality of body contact layers 6 are respectively formed on the upper side of the plurality of body layers 4. In each body layer 4, the body contact layer 6 is surrounded by the source layer 5. The plurality of body contact layers 6 are formed of second conductivity type silicon carbide, and the impurity concentration thereof is higher than that of the plurality of body layers 4. For example, the plurality of body contact layers 6 are p + Type layer.

[0062] In the adjacent main layer 4, multiple gate insulating layers 7 are formed inside the multiple stripe-shaped trench structures T from the source layer 5 side to the drift layer 3. For example, the multiple gate insulating layers 7 are silicon dioxide. For example, the multiple gate insulating layers 7 are formed of aluminum oxide. Inside each trench structure T, multiple gate electrode layers 8 are formed on the multiple gate insulating layers 7.

[0063] A plurality of interlayer insulating layers 9 are formed to cover the plurality of gate electrode layers 8, respectively. A plurality of source electrode layers 10 are formed corresponding to the plurality of main body layers 4, respectively. The source electrode layer 10 is formed to contact the source layer 5. The source electrode layer 10 may also be formed across the main body contact layer 6. The wiring electrode layer 11 is formed to cover the plurality of source electrode layers 10. The drain electrode layer 12 is formed on the second surface ( Figure 1 on the lower surface of the ).

[0064] Next, use Figure 2 and Figure 3 , the formation direction of the trench structure T is explained.

[0065] Figure 2 Schematic diagram showing a crystal plane of a 4H silicon carbide crystal used in the semiconductor device in the first embodiment. Figure 3 This is a schematic diagram showing the crystal plane of the 4H silicon carbide crystal used in the semiconductor device in Embodiment 1, viewed from the (0001) plane side.

[0066] The drain layer 2 and the drift layer 3 are mainly made of 4H silicon carbide to form a substrate. 4H silicon carbide is a hexagonal crystal. Figure 2 As shown in (a), the main surface of the hexagonal crystal is the (0001) Si plane. The trench structure T is formed so that its longitudinal direction is parallel to the plane perpendicular to the main surface. Figure 2 As shown in (b), the trench structure T is formed so that its longitudinal direction is parallel to the (11-20) plane or the (1-100) plane of the crystal orientation.

[0067] Figure 3 (a) shows the (11-20) plane and the (1-100) plane as well as the (1-210) plane and the (-2110) plane. Figure 3 (b) shows the (1-100) plane as well as the (10-10) plane and the (0-110) plane. Figure 3 (c) shows the orientation plane used to confirm the substrate orientation. Hexagonal crystals are 6-fold symmetric. Figure 3 In (a), the (1-210) plane or the (-2110) plane can also be used as the longitudinal direction of the trench structure T. Figure 3 In (b), the (10-10) plane or the (0-110) plane may be used as the longitudinal direction of the trench structure T.

[0068] In the case of 4H silicon carbide, hexagonal crystals can also be epitaxially grown at an inclination of 4 degrees or 8 degrees. Therefore, the (10-10) plane, (0-110) plane, (1-210) plane and (-2110) plane of the 4H silicon carbide cubic crystal are slightly different from the angles in the top view. For example, in the top view of the cubic crystal, the angle between the (1-210) plane and the (-2110) plane is 30 degrees. On the contrary, when epitaxial growth is performed at an inclination of 4 degrees, in the top view of the substrate, the angle between the (1-210) plane and the (-2110) plane is 29.94 degrees. Including this error and other manufacturing errors, the longitudinal direction of the groove structure T is roughly parallel to any one of the planes. The deviation of the longitudinal direction of the groove structure T from any one of the planes is preferably within ±0.2 degrees.

[0069] like Figure 3As shown in (c), the orientation plane is substantially consistent with the (1-100) plane. Due to manufacturing errors, the angle between the orientation plane and the (1-100) plane may be offset by ±5 degrees. The longitudinal direction of the groove structure T is set in consideration of this offset. Specifically, the angle between the longitudinal direction of the groove structure T and the orientation plane is set to any one of the following: between -5 degrees and 5 degrees, between 25 degrees and 35 degrees, between 55 degrees and 65 degrees, between 85 degrees and 95 degrees, between 115 degrees and 125 degrees, and between 145 degrees and 155 degrees.

[0070] Next, use Figure 4 and Figure 5 , the details of the trench structure T are described.

[0071] Figure 4 This is a cross-sectional view in the lateral direction of the trench structure of the semiconductor device in the first embodiment. Figure 5 This is a cross-sectional view in the longitudinal direction of the trench structure of the semiconductor device in the first embodiment.

[0072] like Figure 4 As shown, in the transverse cross-sectional view of the groove structure T, the side is inclined to widen the upper part of the groove. In the transverse cross-sectional view of the groove structure T, the bottom has a multi-level curvature. For example, a first bend 13, a second bend 14 and a third bend 15 are formed. The first bend 13 is formed at the bottom center of the groove structure T. The second bend 14 is formed between the bottom and the side of the groove structure T. The third bend 15 is formed between the first bend 13 and the second bend 14. The third bend 15 is continuously connected to the first bend 13 and the second bend 14. The radius of curvature of the first bend 13 is greater than the radius of curvature of the second bend 14. For example, the radius of curvature of the first bend 13 is 1.5 to 3 times the radius of curvature of the second bend 14. As it moves from the first bend 13 toward the second bend 14, the radius of curvature of the third bend 15 gradually decreases from the radius of curvature of the first bend 13 to the curvature of the second bend.

[0073] like Figure 5 As shown, in the longitudinal cross-sectional view of the groove structure T, a pair of longitudinal bends 16 are formed. The pair of longitudinal bends 16 are formed at the bottom ends of the longitudinal direction of the groove structure T. The curvature radius of the longitudinal bend 16 is greater than the curvature radius of the second bend 14.

[0074] Next, use Figure 6 and Figure 7 , a method for manufacturing the semiconductor device 1 is described.

[0075] Figure 6 and Figure 7 is a schematic diagram for explaining the method for manufacturing a semiconductor device in Embodiment 1. Figure 6 and Figure 7 In the present invention, the upper surface of the semiconductor device 1 during the manufacturing process is set as the first surface. The lower surface of the semiconductor device 1 during the manufacturing process is set as the second surface.

[0076] First, if Figure 6 As shown in (a), a drain layer forming step is performed. In the drain layer forming step, a drain layer 2 is formed. Then, as Figure 6 As shown in (b), a drift layer forming step is performed. In the drift layer forming step, the drift layer 3 is formed by epitaxial growth.

[0077] Then, if Figure 6 As shown in (c), a main body layer forming step, a source layer forming step, and a main body contact layer forming step are performed. In the main body layer forming step, a plurality of main body layers 4 are formed. For example, the plurality of main body layers 4 are formed by ion implantation with aluminum as an impurity. In the source layer forming step, a plurality of source layers 5 are formed. For example, the plurality of source layers 5 are formed by ion implantation with nitrogen as an impurity. In the main body contact layer forming step, a plurality of main body contact layers 6 are formed. For example, the plurality of main body contact layers 6 are formed by ion implantation with aluminum as an impurity.

[0078] Then, if Figure 6 As shown in (d), a groove structure forming step, a carbon film forming step, a high temperature annealing step, and a carbon film removing step are performed. In the groove structure forming step, a plurality of groove structures T are formed. In the carbon film forming step, a carbon film is formed so as to completely cover the first surface side of the semiconductor device 1 during manufacturing. In the high temperature annealing step, the annealing treatment is performed in a high temperature atmosphere. In the carbon film removing step, the carbon film is removed.

[0079] Then, if Figure 6 As shown in (e), a gate insulating layer forming step is performed. In the gate insulating layer forming step, first, an oxide film is formed by thermal oxidation so as to completely cover the first surface side of the semiconductor device 1 during the manufacturing process. Then, the oxide film is nitrided. Then, a resist pattern is formed. Then, the oxide film is etched. Then, the resist pattern is removed. In this way, a plurality of gate insulating layers 7 are formed.

[0080] Then, if Figure 7 As shown in (a), a gate electrode layer forming step is performed. In the gate electrode layer forming step, first, a polysilicon film is formed by CVD so as to completely cover the first surface side of the semiconductor device 1 during the manufacturing process. Then, a resist pattern is formed. Then, the polysilicon film is etched. Then, the resist pattern is removed. In this way, a plurality of gate electrode layers 8 are formed. Then, as shown in FIG. Figure 7As shown in (b), an interlayer insulating layer forming step is performed. In the interlayer insulating layer forming step, first, a silicon dioxide film is formed by a CVD method so as to completely cover the first surface side of the semiconductor device 1 during the manufacturing process. Then, a resist pattern is formed. Then, the silicon dioxide film is etched. Then, the resist pattern is removed. In this way, a plurality of interlayer insulating layers 9 are formed.

[0081] Then, if Figure 7 As shown in (c), a source electrode layer forming step is performed. In the source electrode layer forming step, first, a metal film of Ni, Ti, etc. is formed by sputtering so as to completely cover the first surface side of the semiconductor device 1 during the manufacturing process. Then, a resist pattern is formed. Then, the metal film is etched. Then, the resist pattern is removed. Then, an ohmic reaction layer is formed by rapid thermal annealing (RTA). In this way, a plurality of source electrode layers 10 are formed. Then, as shown in FIG. Figure 7 As shown in (d), a wiring electrode layer forming step is performed. In the wiring electrode layer forming step, first, a metal film such as Al, AlSi, etc. is formed by a sputtering method so as to completely cover the first surface side of the semiconductor device 1 during the manufacturing process. Then, a resist pattern is formed. Then, the metal film is etched. Then, the resist pattern is removed. In this way, the wiring electrode layer 11 is formed.

[0082] Then, if Figure 7 As shown in (e), a drain electrode layer forming step is performed. In the drain electrode layer forming step, first, a metal film such as Ni or Ti is formed by a sputtering method so as to completely cover the second surface side of the semiconductor device 1 during the manufacturing process. Then, an ohmic reaction layer is formed by laser annealing or rapid thermal annealing (RTA). In this way, the drain electrode layer 12 is formed.

[0083] Next, use Figure 8 and Fig. 9 , a method for forming the trench structure T is described.

[0084] Figure 8 and Fig. 9 This is a schematic diagram for explaining a method for forming a trench structure of a semiconductor device in Embodiment 1. During the manufacturing process, the upper surface of the structure is set as the first surface. During the manufacturing process, the lower surface of the structure is set as the second surface.

[0085] First, if Figure 8As shown in (a), as part of the first etching mask forming step, a first silicon dioxide film forming step and a first resist film coating step are performed. In the first silicon dioxide film forming step, a first silicon dioxide film (first oxide film) 17 is formed so as to completely cover the first surface side of the semiconductor device 1 during manufacturing. In the first resist film coating step, a first resist 18 is coated so as to completely cover the first surface side of the semiconductor device 1 during manufacturing. Then, as shown in FIG. Figure 8 As shown in (b), as part of the first etching mask forming process, a first resist pattern forming process is performed. In the first resist pattern forming process, a first resist pattern is formed by exposure and development. In this way, a plurality of stripe-shaped openings are formed in the first resist pattern.

[0086] Then, if Figure 8 As shown in (c), as part of the first etching mask forming process, a first resist pattern tilting forming process is performed. In the first resist pattern tilting forming process, the side portions of the plurality of openings of the first resist pattern are tilted by heat shrinking or reflowing. Then, as shown in FIG. Figure 8 As shown in (d), as part of the first etching mask forming process, a first anisotropic etching process is performed. In the first anisotropic etching process, the first silicon dioxide film 17 is subjected to reactive ion etching using the first resist 18 as a mask. At this time, the selection ratio of the first silicon dioxide film 17 to the first resist 18 is approximately 1:1. In this way, a plurality of first stripe-shaped grooves with inclined side portions are formed in the first silicon dioxide film 17. Then, as part of the first etching mask forming process, as shown in FIG. Figure 8 As shown in (e), a first resist removal step is performed. In the first resist removal step, the first resist 18 is removed. Thus, the first silicon dioxide film 17 is exposed as a first etching mask.

[0087] Then, if Figure 8 As shown in (f), as part of the second etching mask forming process, a second silicon dioxide film forming process is performed. In the second silicon dioxide film forming process, a second silicon dioxide film (second oxide film) 19 is formed so as to completely cover the first surface side of the semiconductor device 1 during the manufacturing process. In this way, at the positions of the plurality of stripe-shaped first grooves of the first etching mask, a plurality of stripe-shaped second grooves with inclined sides are formed in the second silicon dioxide film 19. Then, as shown in FIG. Fig. 9 As shown in (a), as part of the second etching mask forming process, a second resist film coating process is performed. In the second resist film coating process, the second resist 20 is coated so as to completely cover the first surface side of the semiconductor device 1 during manufacturing. Then, as shown in FIG. Fig. 9As shown in (b), a second resist pattern forming step is performed as a part of the second etching mask forming step.

[0088] Here, use Fig.10 and Fig.11 The second resist pattern is formed by optical lithography using an optical stepper. Fig.10 The optical image intensity distribution of the line and space pattern is shown. At the appropriate focus position, the optical image intensity of the light-irradiated part becomes high, while the optical image intensity is almost zero in the lower part of the pattern with the pattern width W. However, when exposed in a defocused state, its optical image intensity is lower than that obtained at the appropriate focus position. Fig.11 The sensitivity curve of the positive resist is shown. This pattern shows the residual resist film after the assumed optically infinite area is exposed and developed within a certain development time. The thickness of the resist film decreases as the exposure amount increases. When the exposure amount is F, the resist film thickness is 0. That is, if the exposure amount is less than F, the resist film remains. This state is called underexposure. In addition, even if the development time is shortened, the resist film remains. This state is called underdevelopment. If the exposure amount is less than F, the resist film will remain. This state is called underdevelopment. Fig.10 Adjust the exposure intensity of E to Fig.11 At the F position in the middle, it can be seen that in the case of defocus, the exposure is insufficient and the resist film remains even at the position where the light is irradiated. Fig.11 As shown, there are also resists G and H having different sensitivity characteristics. By appropriately selecting these resists, the shape of the resist residual film can be changed. As described above, by combining one or more of underexposure, underdevelopment, defocusing, and resist type selection, a plurality of grooves are formed in the second resist pattern, and the sides of the plurality of grooves are inclined in such a way that the upper portion of the groove is widened, and the bottom has a multi-level curvature.

[0089] Then, if Fig. 9 As shown in (c), as part of the second etching mask forming process, a second anisotropic etching process is performed. In the second anisotropic etching process, the second silicon dioxide film 19 is subjected to reactive ion etching using the second resist 20 as a mask. At this time, the selection ratio of the second silicon dioxide film 19 to the second resist 20 is approximately 1:1. In this way, a plurality of stripe-shaped second grooves are formed in the second silicon dioxide film 19, the sides of the grooves are inclined, and the bottom has a multi-level curvature. Then, as shown in FIG. Fig. 9 As shown in (d), a second resist removal step is performed as a part of the second etching mask forming step. In the second resist removal step, the second resist 20 is removed. Thus, the second silicon dioxide film 19 is exposed as a second etching mask.

[0090] Then, if Fig. 9 As shown in (e), as part of the trench structure forming process, a third anisotropic etching process is performed. In the third anisotropic etching process, the drift layer 3, the main layer 4 and the source layer 5 are reactively ion etched using the first silicon dioxide film 17 and the second silicon dioxide film 19 as masks. At this time, the selection ratio of silicon carbide constituting the drift layer 3, the main layer 4 and the source layer 5 to silicon dioxide constituting the first silicon dioxide film 17 and the second silicon dioxide film 19 is approximately 1:1. In this way, a plurality of stripe-shaped trench structures T are formed, whose sides are inclined and whose bottoms have multi-level curvatures. Then, as shown in FIG. Fig. 9 As shown in (f), as a part of the trench structure forming process, a silicon dioxide film removing process is performed. In the silicon dioxide film removing process, the first silicon dioxide film 17 and the second silicon dioxide film 19 are removed simultaneously. Thus, a plurality of stripe-shaped trench structures T are exposed.

[0091] Next, use Figures 12 to 16 , the electric field distribution on the surface of the groove portion is described.

[0092] Fig.12 1 and 2 are cross-sectional views of trench structures of the semiconductor device in Embodiment 1 and the first and second comparative examples. Fig.13 This is a schematic diagram showing the electric field distribution near the trench structure of the semiconductor device in the first embodiment. Fig.14 Schematic diagram showing the electric field distribution near the trench structure of the first comparative example. Fig.15 Schematic diagram showing the electric field distribution near the trench structure of the second comparative example. Fig.16 1 is a schematic diagram showing the comparison results of the electric field intensity near the trench structure between the semiconductor device in Embodiment 1 and the first comparative example and the second comparative example.

[0093] Fig.12 (a) shows a trench structure T of the semiconductor device 1 in the first embodiment. Fig.12 (b) shows the trench structure of the first comparative example. Fig.12 (c) shows the trench structure of the second comparative example.

[0094] like Fig.12 As shown in (a), the trench structure T of the semiconductor device 1 in the first embodiment includes: Figure 4 The first curved portion 13, the second curved portion 14 and the third curved portion 15 are identical. For example, the first curved portion 13 has a curvature radius of 2.55 μm. For example, the second curved portion 14 has a curvature radius of 1.41 μm. The curvature radius of the central portion of the third curved portion 15 is 2.02 μm.

[0095] like Fig.12 (b) shows that in the first comparative example, the trench structure has: Fig.12(a) The same curved portion 21 as the second curved portion 14. The groove structure does not have: Fig.12 In (a), the first curved portion 13 and the third curved portion 15 are the same curved portion. For example, the curvature radius of the curved portion 21 is 1.41 μm.

[0096] like Fig.12 As shown in (c), in the second comparative example, the groove structure has a bent portion 22 formed at the same Fig.12 (a) is the same position as the first bend 13. This groove structure does not have: Fig.12 In (a), the second curved portion 14 and the third curved portion 15 are the same curved portion. The curvature radius of the curved portion 22 is greater than the curvature radius of the first curved portion 13. For example, the curvature radius of the curved portion 22 is 2.83 μm.

[0097] like Fig.13 As shown, in the trench structure T of the semiconductor device 1 of Embodiment 1, the electric field strength is almost uniform in all regions including the bottom and the side. For example, when a voltage of 1650 V is applied, the electric field strength is about 2.6 MV / cm to 2.7 MV / cm.

[0098] like Fig.14 As shown, in the trench structure of the first comparative example, the electric field is maximum near the bent portion 21. For example, when a voltage of 1650 V is applied, the electric field intensity is approximately 2.8 MV / cm to 2.9 MV / cm.

[0099] like Fig.15 As shown, in the trench structure of the second comparative example, the electric field is maximum near the bent portion 22. For example, when a voltage of 1650 V is applied, the electric field intensity is approximately 2.9 MV / cm to 3.0 MV / cm.

[0100] exist Fig.16 In the figure, the horizontal axis is the position of the center of the groove structure surface in the lateral direction (μm). The vertical axis is the electric field strength (MV / cm). A represents the electric field strength distribution of the groove structure T of the semiconductor device 1 in embodiment 1. B represents the electric field strength distribution of the groove structure of the first comparative example. C represents the electric field strength distribution of the groove structure of the second comparative example. D is the insulation breakdown electric field strength of 4H silicon carbide (2.8MV / cm). Fig.16 As shown, only the electric field intensity distribution A of the trench structure T of the semiconductor device 1 in the first embodiment is lower than the dielectric breakdown electric field intensity D of 4H silicon carbide in the entire region.

[0101] According to the first embodiment described above, the bottom of the trench structure T has a multi-level curvature in a transverse cross-sectional view. The trench structure T includes at least the first curved portion 13 and the second curved portion 14. Therefore, electric field concentration in the trench structure T can be suppressed.

[0102] In addition, the curvature radius of the first curved portion 13 is larger than the curvature radius of the second curved portion 14. Therefore, the electric field concentration in the trench structure T can be suppressed more reliably.

[0103] In addition, the curvature radius of the first curved portion 13 is 1.5 to 3 times the curvature radius of the second curved portion 14. Therefore, the electric field concentration in the trench structure T can be suppressed more reliably.

[0104] In addition, in the transverse cross-sectional view of the trench structure T, the curvature radius of the third curved portion 15 gradually decreases from the first curved portion 13 toward the second curved portion 14. Therefore, the electric field concentration in the trench structure T can be suppressed more reliably.

[0105] In addition, the side portion is inclined in the transverse cross-sectional view of the trench structure T. Therefore, it is easy to form the trench structure T in which the electric field concentration is suppressed.

[0106] In addition, the longitudinal curved portion 16 is formed in the longitudinal cross-sectional view of the trench structure T. Therefore, even at the end portion of the longitudinal bottom of the trench structure T, the electric field concentration can be suppressed.

[0107] In addition, the longitudinal direction of the trench structure T is parallel to the (11-20) plane, (1-210) plane or (-2110) plane of the 4H silicon carbide hexagonal crystal. Therefore, electric field concentration is suppressed and channel mobility can be improved.

[0108] In addition, the longitudinal direction of the trench structure T is parallel to the (1-100) plane, (10-10) plane, or (0-110) plane of the 4H silicon carbide hexagonal crystal. Therefore, electric field concentration is suppressed and channel mobility can be improved.

[0109] In addition, if the substrate is of the notch type, the line perpendicular to the line connecting the notch to the center of the substrate is regarded as the orientation plane. In this case, the angle between the longitudinal direction of the groove structure T and the orientation plane can be set to any of the following: between -5 degrees and 5 degrees, between 25 degrees and 35 degrees, between 55 degrees and 65 degrees, between 85 degrees and 95 degrees, between 115 degrees and 125 degrees, and between 145 degrees and 155 degrees. In this case, the channel mobility can also be improved.

[0110] In addition, in the transverse cross-sectional view of the trench structure T, a third curved portion 15 may be partially provided between the first curved portion 13 and the second curved portion 14. In this case, the radius of curvature of the third curved portion 15 should be smaller than the radius of curvature of the first curved portion 13 and larger than the radius of curvature of the second curved portion 14. In this case, the electric field concentration in the trench structure T can also be suppressed.

[0111] Alternatively, the first conductivity type may be the p-type and the second conductivity type may be the n-type. In this case, the electric field concentration in the trench structure T can be suppressed.

[0112] In addition, the semiconductor device 1 may also be an IGBT. In this case, the drain layer 2 may be formed as a P + The source electrode layer 5 can be set as an emission layer. The source electrode layer 10 can be set as an emission electrode layer. The drain electrode layer 12 can be set as a collector electrode layer.

[0113] Although some aspects of at least one embodiment have been described above, it should be understood that various changes, modifications and improvements may be easily conceived by those skilled in the art. The changes, modifications and improvements involved are intended to become part of this disclosure and are intended to be within the scope of this disclosure.

[0114] It should be understood that the implementation of the method and apparatus described herein is not limited to the details of the structure and arrangement of the components described in the above description or illustrated in the accompanying drawings. The method and apparatus can be implemented in other embodiments and implemented or executed in various ways.

[0115] The specific embodiments are provided herein only by way of example and are not meant to be limiting.

[0116] The expressions and terms used in this disclosure are for illustrative purposes only and should not be considered as limiting. The use of "includes," "having," "having," "comprising," and variations thereof as used herein means the inclusion of the following listed items, their equivalents, and additional items.

[0117] Reference to "or" may be interpreted as one or more of any terms recited using "or", as well as interpretation of all terms.

[0118] References to front, back, left, right, top, bottom, up, down, horizontal, vertical, inside and outside are for convenience of description. Such references do not mean that the constituent elements of the present disclosure are limited to any particular position or spatial orientation. Therefore, the above description and drawings are only for illustration.

[0119] In addition, it is needless to say that the present disclosure is not limited to the embodiments described above, but includes all embodiments that can achieve the purpose of the present invention.

[0120] The term "embodiment" in this disclosure refers to specific features, structures, or characteristics described in conjunction with the embodiment that may be included in at least one embodiment of the present application. The appearance of this phrase in various locations in the specification does not necessarily mean the same embodiment, nor does it mean that it is mutually exclusive with other embodiments and is independent or optional. It is clearly or implicitly understood by those of ordinary skill in the art that the embodiments described in this application can be combined with other embodiments without conflict.

[0121] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of patent protection. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the attached claims.

Claims

1. A semiconductor device, characterized in that: include: A first layer formed of first conductivity type silicon carbide; a second layer, on which second conductivity type silicon carbide is formed, on the first layer; a third layer, on the second layer, formed of first conductivity type silicon carbide; as well as a plurality of groove structures formed in a stripe shape from one side of the third layer to the first layer; The groove structure includes, in a transverse cross-sectional view, a first curved portion formed at a bottom portion, and a second curved portion formed between the bottom portion and a side portion.

2. The semiconductor device according to claim 1, wherein: A curvature radius of the first curved portion is greater than a curvature radius of the second curved portion.

3. The semiconductor device according to claim 2, wherein: The curvature radius of the first curved portion is 1.5 to 3 times the curvature radius of the second curved portion.

4. The semiconductor device according to claim 1 or 2, characterized in that: The groove structure has a third curved portion in a transverse cross-sectional view. The third curved portion is formed between the first curved portion and the second curved portion, and a curvature radius gradually decreases from a curvature of the first curved portion to a curvature of the second curved portion as moving from the first curved portion toward the second curved portion.

5. The semiconductor device according to claim 1 or 2, characterized in that: In the groove structure, the side portion is inclined in such a manner that an upper portion of the groove becomes wider.

6. The semiconductor device according to claim 1 or 2, characterized in that: The groove structure has a longitudinal curved portion in a longitudinal cross-sectional view, and the longitudinal curved portion is formed at an end portion and has a curvature radius greater than a curvature radius of the second curved portion.

7. The semiconductor device according to claim 1 or 2, characterized in that: The first layer, the second layer and the third layer are mainly formed of 4H silicon carbide, The longitudinal direction of the groove structure is parallel to the (11-20) plane, (1-210) plane or (-2110) plane of the 4H silicon carbide hexagonal crystal, and the (11-20) plane, (1-210) plane or (-2110) plane is perpendicular to the main surface of the substrate formed by the first layer, the second layer and the third layer.

8. The semiconductor device according to claim 1 or 2, characterized in that: The first layer, the second layer and the third layer are mainly formed of 4H silicon carbide, The longitudinal direction of the groove structure is parallel to the (1-100) plane, (10-10) plane or (0-110) plane of the 4H silicon carbide hexagonal crystal, and the (1-100) plane, (10-10) plane or (0-110) plane is perpendicular to the main surface of the substrate formed by the first layer, the second layer and the third layer.

9. The semiconductor device according to claim 1, wherein: The first layer is a drain layer and a drift layer, the second layer is a plurality of body layers, and the third layer is a plurality of source layers and are respectively formed on a side of the corresponding body layer away from the drain layer; and the first conductivity type is N type, and the second conductivity type is P type; or The first layer is a collector layer and a drift layer, the second layer is a plurality of main layers, and the third layer is a plurality of emitter layers; and the first conductivity type is a P type, and the second conductivity type is an N type.

10. A method for manufacturing a semiconductor device, characterized in that: include: A first etching mask forming step, for a substrate formed of a first layer, a second layer, and a third layer, forming a first oxide film on the third layer, and forming a plurality of first stripe-shaped grooves with inclined sides on the first oxide film, thereby forming a first etching mask, wherein the first layer is formed of first conductive type silicon carbide, the second layer is formed of second conductive type silicon carbide on the first layer, and the third layer is formed of first conductive type silicon carbide on the second layer; a second etching mask forming step, after the first etching mask forming step, forming a second oxide film on the first etching mask, forming a plurality of stripe-shaped second grooves with inclined sides and multi-stage curved bottoms at the positions of the plurality of stripe-shaped first grooves, thereby forming a second etching mask; and The trench structure forming step is to anisotropically etch the substrate after the second etching mask forming step, thereby forming a plurality of stripe-shaped trench structures with inclined sides and multi-level complete bottoms in the range from the third layer side to the first layer.

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