A layout of a power semiconductor device

Abstract

The present application discloses a power semiconductor device, which has a substrate layer, an epitaxial layer, a well region, a source region, and a well contact region. The epitaxial layer has an upper surface of the epitaxial layer and a lower surface of the epitaxial layer, wherein the lower surface of the epitaxial layer is in contact with the substrate layer. The well region is distributed in the epitaxial layer and is strip-shaped in a first direction on the upper surface of the epitaxial layer. The source region is distributed in the well region and is strip-shaped in the first direction on the upper surface of the epitaxial layer. The well contact region is distributed in the epitaxial platform region between the well regions, and the sidewalls are in contact with the sidewalls of adjacent well regions. In the present application, the well contact region is distributed in the epitaxial platform region between the well regions, reducing the size of the power semiconductor device and lowering the on-resistance of the power semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a layout and structure of a power semiconductor device. Background Art

[0002] Figure 1 The cross-sectional view of a conventional MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device 100 is shown. As Figure 1 shown, the MOSFET device 100 includes a semiconductor layer 111 and a gate structure 112 located above the semiconductor layer 111. The gate structure 112 includes a polysilicon gate 112a and an insulating layer 112b wrapping the polysilicon gate 112a. The semiconductor layer 111 includes a substrate layer 101, an epitaxial layer 102 located above the substrate layer 101, a well region 103 located within the epitaxial layer 102, adjacent source regions 104 and well contact regions 105 located within the well region 103. Meanwhile, a metal layer is covered on the lower surface of the semiconductor layer 111, that is, the surface of the substrate layer 101 of the device, as a drain electrode 106, and a metal layer is covered on the upper surface of the semiconductor layer 111, that is, the exposed surfaces such as the source region 104, as a source electrode 107. In the MOSFET device 100, as Figure 1 shown, the size of the cell in this cross-section is L = Lohmic + 2Lgs + 2Loverlap + 2Lch + Ljfet. Currently, the lengths of each part have reached the limit of the current process capabilities, and it is difficult to further reduce the cell size of the device, resulting in the on-resistance of the device not being able to be further reduced. Summary of the Invention

[0003] This application provides a power semiconductor device. By placing the well contact region in a partial epitaxial platform region of a strip-shaped cell, the cell size of the device is reduced, thereby further reducing the on-resistance of the device.

[0004] According to an embodiment of the present application, a power semiconductor device is provided, including: a substrate layer; an epitaxial layer having an upper surface and a lower surface of the epitaxial layer, wherein the lower surface of the epitaxial layer is in contact with the substrate layer; a well region distributed in the epitaxial layer and strip-shaped in a first direction on the upper surface of the epitaxial layer; a source region distributed in the well region and strip-shaped in the first direction on the upper surface of the epitaxial layer; and a well contact region distributed in the epitaxial platform region between the well regions.

[0005] For the power semiconductor device according to an embodiment of the present application, the epitaxial platform region between the well regions is strip-shaped, and a plurality of the well contact regions are distributed in the strip-shaped epitaxial platform region, and the plurality of well contact regions are equidistantly distributed in the first direction.

[0006] A power semiconductor device according to an embodiment of the present application, wherein the epitaxial platform region between the well regions is strip-shaped, and a plurality of the well contact regions are distributed in the strip-shaped epitaxial platform region, and the distance between adjacent well contact regions in the first direction is 0.5 μm or more.

[0007] A power semiconductor device according to an embodiment of the present application, wherein the width of the well contact region in the second direction on the upper surface of the epitaxial layer is greater than the width of the epitaxial platform region, and the second direction is perpendicular to the first direction.

[0008] A power semiconductor device according to an embodiment of the present application, wherein the width of the well contact region in the second direction on the upper surface of the epitaxial layer is equal to the width of the epitaxial platform region, and the second direction is perpendicular to the first direction.

[0009] A power semiconductor device according to an embodiment of the present application, wherein the width of the well contact region in the second direction on the upper surface of the epitaxial layer is greater than the width of the epitaxial platform region, the second direction is perpendicular to the first direction, and the well contact region extends in the second direction until the sidewall of the well contact region meets the sidewall of the source region.

[0010] A power semiconductor device according to an embodiment of the present application, a power semiconductor device according to an embodiment of the present application, wherein the well contact regions of adjacent epitaxial platform regions are distributed on a straight line in the second direction on the upper surface of the epitaxial layer, and the second direction is perpendicular to the first direction.

[0011] A power semiconductor device according to an embodiment of the present application, wherein the well contact regions of adjacent epitaxial platform regions are distributed on different straight lines in the second direction on the upper surface of the epitaxial layer, and the second direction is perpendicular to the first direction.

[0012] In some embodiments, the aforementioned power semiconductor device further includes: a gate oxide layer located on the epitaxial layer; and a gate electrode layer located on the gate oxide layer and covering the gate oxide layer; wherein, the gate oxide layer and the gate electrode layer cover a part of the source region and cover other regions except the well contact region and a certain region around the well contact region.

[0013] In some embodiments, the aforementioned power semiconductor device further includes: a drain electrode layer covering the surface of the substrate layer, the surface of the substrate layer being opposite and parallel to the surface of the substrate layer covering the epitaxial layer; and a source electrode layer located above the upper surface of the epitaxial layer, isolated from a part of the upper surface region of the epitaxial layer by an interlayer dielectric layer, and connected to the well contact region and the source region exposed on the upper surface of the epitaxial layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Through the following description of the embodiments of the present application with reference to the drawings, the above and other objects, features and advantages of the present application will become clearer:

[0015] Figure 1 Shows a cross-sectional view of a conventional MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device 100;

[0016] Figure 2 Is a schematic plan view of a partial region of a power semiconductor device 200 according to an embodiment of the present application;

[0017] Figure 3 Is along according to an embodiment of the present application Figure 2 Schematic diagram of the first cross-section 300 of the power semiconductor device 200 along the AA' line in;

[0018] Figure 4 Is along according to an embodiment of the present application Figure 2 Schematic diagram of the second cross-section 400 of the power semiconductor device 200 along the BB' line in;

[0019] Figure 5 Shows a schematic plan view of a partial region of a power semiconductor device 500 according to an embodiment of the present application;

[0020] Figure 6 Is along according to an embodiment of the present application Figure 5 Schematic diagram of the second cross-section 600 of the power semiconductor device 500 along the BB' line in;

[0021] Figure 7 Is a schematic plan view of a partial region of a power semiconductor device 700 according to another embodiment of the present application;

[0022] Figure 8 Is along according to an embodiment of the present application Figure 7 Schematic diagram of the second cross-section 800 of the power semiconductor device 700 along the BB' line in;

[0023] Figure 9 Is a schematic plan view of a partial region of a power semiconductor device 900 according to another embodiment of the present application;

[0024] Figure 10 Is along according to an embodiment of the present application Figure 9 Schematic diagram of the second cross-section 1000 of the power semiconductor device 900 along the BB' line in;

[0025] Figure 11 Is a schematic plan view of a partial region of a power semiconductor device 1100 according to another embodiment of the present application;

[0026] Figure 12Schematic diagram of a second cross-section 1200 of a power semiconductor device 1100 along line BB' in Figure 11 in accordance with an embodiment of the present application. Detailed Description of the Invention

[0027] Specific embodiments of the present application will be described in detail below. It should be noted that the embodiments described here are only for illustrative purposes and are not intended to limit the present application. In the following description, a large number of specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to those of ordinary skill in the art that: these specific details do not have to be employed to practice the present application. In other instances, well-known circuits, materials, or methods have not been specifically described in order to avoid obscuring the present application.

[0028] Throughout the specification, references to "one embodiment", "an embodiment", "one example" or "an example" mean that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present application. Thus, the phrases "in one embodiment", "in an embodiment", "one example" or "an example" appearing throughout the specification do not necessarily all refer to the same embodiment or example. Additionally, the specific features, structures, or characteristics may be combined in any suitable combination and / or sub-combination in one or more embodiments or examples. Further, those of ordinary skill in the art will understand that the drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale. Like reference numerals denote like elements. The term "and / or" used herein includes any and all combinations of one or more of the associated listed items. The drawings are not drawn to scale and are for illustrative purposes only. For clarity, unless otherwise stated, the same elements have been designated by corresponding reference numerals in different drawings.

[0029] The terms "having", "including", "comprising", "containing", etc. are open-ended, and these terms indicate the presence of the stated structure, element, or feature, but do not exclude additional elements or features.

[0030] When describing the structure of a device, when a layer or a region is referred to as being "above" or "over" another layer or another region, it may mean directly above the other layer or the other region, or there may be other layers or regions between it and the other layer or the other region. And if the device is flipped, this layer or this region will be "below" or "beneath" the other layer or the other region.

[0031] If in order to describe the situation of being directly above another layer or another region, the expressions "directly on top of..." or "on top of... and adjacent thereto" will be used herein.

[0032] In this text, the relative doping concentration is illustrated by indicating "-" or "+" beside the doping type "n" or "p". For example, "n-" indicates that the doping concentration is lower than that of the "n" doped region, and the "n" doped region has a higher doping concentration than the "n-" doped region. Doped regions with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" type doped regions may have the same or different absolute doping concentrations.

[0033] In the embodiments of the present application, each semiconductor layer or region has a first conductivity type or a second conductivity type. The first conductivity type refers to one of n-type or p-type, and the second conductivity type is the other one. That is to say, the semiconductor layer with the first conductivity type can be an n-type semiconductor layer or a p-type semiconductor layer. When the semiconductor layer with the first conductivity type is an n-type semiconductor layer, the semiconductor layer with the second conductivity type is a p-type semiconductor layer. The n-type semiconductor layer is formed by doping n-type impurities in the semiconductor layer. The n-type impurities can be pentavalent elements such as phosphorus, arsenic, nitrogen, etc. The p-type semiconductor layer is formed by doping p-type impurities in the semiconductor layer. The p-type impurities can be trivalent elements such as boron, indium, gallium, aluminum, etc.

[0034] Figure 2 FIG. is a plan view of a partial region of a power semiconductor device 200 according to an embodiment of the present application. It should be understood that Figure 2 only a partial planar structure of the power semiconductor device 200 on one of its horizontal planes is shown, which does not represent the overall structure of the power semiconductor device 200. As Figure 2 shown, a single cell 208 of the power semiconductor device 200 includes an epitaxial platform region 202, a well region 203, a source region 204, and a well contact region 205. The epitaxial platform region 202, the well region 203, and the source region 204 are strip-shaped and are longitudinally parallelly distributed along a first direction (the y direction as shown in the figure). Among them, the well region 203 is distributed on both sides of the epitaxial platform region 202, the source region 204 is distributed in the well region 203, and the well contact region 205 is distributed in a partial region of the epitaxial platform region 202 of the strip-shaped cell 208 and is distributed along the same straight line in the first direction. There is a certain interval between adjacent well contact regions 205 that are distributed along the same straight line.

[0035] In Figure 2 the embodiment, a single cell 208 of the power semiconductor device 200 includes an epitaxial platform region 202 and well regions 203 distributed on both sides of the epitaxial platform region 202. The well regions 203 are shared between adjacent cells. And the source region 204 and the well contact region 205 distributed in the epitaxial platform region 202 are distributed in the well region 203. The well contact region 205 is embedded in the epitaxial platform region 202 in the longitudinal direction of the epitaxial platform region 202 and is distributed on the same straight line as the epitaxial platform region 202.

[0036] Figure 2 The embodiment shows a partial area of the upper surface 209 of the epitaxial layer of the power semiconductor device 200. The actual power semiconductor device 200 is composed of a plurality of cells 208. On the layout composed of a plurality of cells, a plurality of well contact regions 205 are distributed in an epitaxial platform region 202. In some embodiments, the well contact regions 205 in an epitaxial platform region 202 are equally spaced. In some embodiments, the pitch h1 between adjacent well contact regions 205 in the strip-shaped epitaxial platform region 202 is at least 0.5 μm or more.

[0037] Figure 2 Each partition shown is a structure on the horizontal plane 209 of the epitaxial layer of the power semiconductor device 200, for example, the upper surface of the epitaxial layer. Among them Figure 2 The region between the upper and lower dashed lines covering the well contact region 205 is the region of the source electrode layer 207 covering this horizontal plane. To show the structure of each region on this horizontal plane, other structures covering this horizontal plane are not drawn in the figure, but only the position of the source electrode layer 207 is indicated by a dashed line. Therefore, the region between the two dashed lines in the figure represents the position of the source electrode layer, not the actual source electrode layer. In Figure 2 the embodiment, to ensure that the source electrode layer 207 does not cover the epitaxial platform region 202 and cause the device to become a fixed resistor, the source electrode layer 207 maintains a certain distance from the epitaxial platform region 202 in the first direction.

[0038] Figure 3 is a schematic diagram of a first cross-section 300 of the power semiconductor device 200 along the Figure 2 AA' line in accordance with an embodiment of the present application. The first cross-section 300 is parallel to the second direction, that is, Figure 2 the x direction shown, and perpendicular to the first direction, that is, Figure 2 the y direction shown. As Figure 3As shown, the power semiconductor device 200 includes: a substrate layer 201, an epitaxial layer 219, well regions 203, source regions 204, a gate oxide layer 214, a gate electrode layer 212, an interlayer dielectric layer 213, a source electrode layer 207, and a drain electrode layer 206. The epitaxial layer 219 is located above the first surface of the substrate layer 201, and the drain electrode layer 206 covers the second surface of the substrate layer 201, and the first surface and the second surface face away from each other and are parallel. The epitaxial layer 219 has an epitaxial layer upper surface 209 and an epitaxial layer lower surface 210 that face away from each other and are parallel. Among them, the lower surface 210 of the epitaxial layer 219 covers the first surface of the substrate layer 201, and the epitaxial layer upper surface 209 is covered by the gate oxide layer 214 on the first cross-section 300. The epitaxial layer includes a plurality of well regions 203 that extend from the epitaxial layer upper surface 209 into the epitaxial layer. The plurality of well regions 203 are isolated by an epitaxial platform region 202 and have substantially the same spacing. It should be understood that the epitaxial platform region 202 is a part of the epitaxial layer 219. The source regions 204 are located in each well region 203 and extend from the epitaxial layer upper surface 209 into the well region, and the bottom of the source region 204 does not reach the bottom of the well region 203, that is, the distance from the bottom of the well region 203 to the epitaxial layer upper surface 209 is greater than the distance from the bottom of the source region 204 to the epitaxial layer upper surface 209. The well regions 203 and the source regions 204 are both exposed to the epitaxial layer upper surface 209. The gate oxide layer 214 covers the epitaxial layer upper surface 209 and isolates the gate electrode layer 212 thereon from the underlying epitaxial layer upper surface 209. The interlayer dielectric layer 213 covers the upper part of the gate electrode layer 212, and the source electrode layer 207 is located above the interlayer dielectric layer 213, and the gate electrode layer 212 and the source electrode layer 207 are isolated by the interlayer dielectric layer 213.

[0039] In one embodiment, the gate oxide layer 214 is silicon dioxide and has a thickness between 5 and 200 nanometers. In other embodiments, the gate oxide layer 214 may also include other insulating materials such as silicon nitride and aluminum nitride. The interlayer dielectric layer 213 may be the same insulating material as the gate oxide layer 214 or may be other different insulating materials. The thickness of the interlayer dielectric layer 213 is much greater than the thickness of the gate oxide layer 214.

[0040] In one embodiment, the epitaxial layer 219 is of a single conductivity type and has a substantially uniform concentration. In some embodiments, the epitaxial layer 219 includes multiple semiconductor layers with different doping concentrations. For example, the epitaxial layer 219 may include a first semiconductor layer with a first doping concentration and a second semiconductor layer with a second doping concentration. The first semiconductor layer is located in a region below the well region and at a certain distance from the bottom of the well region, and the second semiconductor layer is located above the first semiconductor layer, and the first doping concentration is less than the second doping concentration. In other embodiments, the epitaxial layer 219 may also be composed of more semiconductor layers with different doping concentrations.

[0041] In one embodiment, the substrate layer 201, the epitaxial layer 219, and the source region 204 have a first doping type, and the well region 203 and the well contact region 205 have a second doping type. In one embodiment, the first doping type is n-type doping, and the second doping type is p-type doping. It should be understood that in other embodiments, the first doping type may be p-type doping and the second doping type may be n-type doping. In one embodiment, the doping concentration of the well contact region 205 is greater than that of the well region 203, and the doping concentration of the substrate layer 201 is greater than that of the epitaxial layer 219.

[0042] As can be seen from Figure 3 , in the first cross-section 300, there is no well contact region 205. Thus, the size of a single cell of the power semiconductor device 200 is L = Ls + 2Lch + Ljfet. Compared with the prior art, since the well contact region 205 is located in the epitaxial platform region 202 and does not overlap with the source region 204 in size in the second direction (such as the Figure 2 -shown x direction), that is, the well contact region 205 is not included in the first cross-section 300, and thus the ohmic contact region (the contact between the source electrode layer and the well contact region and the source region) is not included either. Therefore, in the second direction, that is, the length direction perpendicular to the source region, there is no need to have an ohmic contact region, a certain overlap region between the gate oxide layer and the source region, and the thickness of the sidewall of the interlayer dielectric layer as shown in Figure 1 . That is, the sizes Lohmic, Loverlap, and Lgs are reduced. Further, since there is no need for an ohmic contact, the width of the source region can also be greatly reduced, and thus the size of the device can be greatly reduced, enabling the semiconductor device 200 to have a smaller device area.

[0043] Figure 4 FIG. 400 is a schematic diagram of a second cross-section of the power semiconductor device 200 along the BB' line according to an embodiment of the present application. As shown in Figure 2 , the second cross-section 400 includes a substrate layer 201, an epitaxial layer 219, a well region 203, a source region 204, a well contact region 205, a source electrode layer 207, and a drain electrode layer 206. In the second cross-section 400, since the well region 203, the source region 204, and the well contact region 205 exposed on the upper surface 209 of the epitaxial layer are all electrically connected to the source potential of the device, the source electrode layer 207 can cover the entire end region of the cell and be in direct contact with the well region 203, the source region 204, and the well contact region 205. That is, in the second cross-section 400, the gate oxide layer 214 and the gate electrode layer 212 are not distributed. Combining Figure 4 As shown, on the second cross-section 400, there are included a substrate layer 201, an epitaxial layer 219, a well region 203, a source region 204, a well contact region 205, a source electrode layer 207, and a drain electrode layer 206. In the second cross-section 400, since the well region 203, the source region 204, and the well contact region 205 exposed on the upper surface 209 of the epitaxial layer are all electrically connected to the source potential of the device, the source electrode layer 207 can cover the entire end region of the cell and be in direct contact with the well region 203, the source region 204, and the well contact region 205. That is, in the second cross-section 400, the gate oxide layer 214 and the gate electrode layer 212 are not distributed. Combining Figure 2Looking at the longitudinal direction of the cell 208, that is, in a part of the strip-shaped epitaxial platform region 202, the well contact region 205 is distributed, and this region is used to connect the well contact region 205 and the source region 204 to the source electrode layer 207. Therefore, the gate oxide layer 214 and the gate electrode layer 212 are not distributed in this end region. In other embodiments, the source electrode layer 207 can also be selectively contacted with the well region 203, the source region 204, the well contact region 205, or any combination thereof through the interlayer dielectric layer isolation.

[0044] On the second cross-section 400, the well contact region 205 is located in the epitaxial platform region 202, and the sidewalls are connected to the sidewalls of the well regions 203 on both sides. The top of the well contact region 205 is exposed on the upper surface 209 of the epitaxial layer, and the bottom is shallower than the bottom of the well region 203, that is, the distance from the bottom of the well contact region 205 to the upper surface 209 of the epitaxial layer is less than the distance from the bottom of the well region 203 to the upper surface 209 of the epitaxial layer. In some embodiments, the depth of the well contact region 205 can also be greater than or equal to the depth of the well region 203.

[0045] Figure 5 A plan view of a partial region of a power semiconductor device 500 according to an embodiment of the present application is shown. It should be understood that Figure 5 Only a partial planar structure of the power semiconductor device 500 on one of the horizontal planes is shown, which does not represent the overall structure of the power semiconductor device 500. As Figure 5 shown, as Figure 5 shown, a single cell 508 of the power semiconductor device 500 includes an epitaxial platform region 202, a well region 203, a source region 204, and a well contact region 205. The epitaxial platform region 202, the well region 203, and the source region 204 are strip-shaped and are longitudinally distributed in parallel along the first direction (the y direction as shown in the figure). Among them, the well region 203 is distributed on both sides of the epitaxial platform region 202, the source region 204 is distributed in the well region 203, and the well contact region 205 is distributed in a part of the epitaxial platform region 202. There is a certain interval h1 between adjacent well contact regions 205 that are distributed along the same straight line in the first direction. In some embodiments, this interval is at least 0.5 μm.

[0046] In Figure 5 the embodiment, different from Figure 2 the embodiment, the gate oxide layer and the gate electrode layer extend along the first direction into a part of the well region in the two end regions of the cell 508, covering the part of the well regions at both ends, thereby increasing the current density of the device. The source electrode layer 207 covers a part of the well contact region 205 and the source region 204 at both ends of the cell 508 on the upper surface of the epitaxial layer, as shown by the dotted line box in the figure, rather than as Figure 2As shown, they are connected into a strip in the second direction. The area where the source electrode layer 207 is disconnected in the second direction is covered by the gate oxide layer and the gate electrode layer, and in order to prevent short - circuiting between the gate electrode layer and the source electrode layer, they are isolated by an inter - layer dielectric layer.

[0047] The first cross - section of the power semiconductor device 500 along the line AA’ is as Figure 3 shown, and will not be elaborated here.

[0048] Figure 6 For a power semiconductor device 500 according to an embodiment of the present application along Figure 5 is a schematic diagram of a second cross - section 600 of the power semiconductor device 500 along the line BB’ in Figure 6 shown. As Figure 4 shown, the second cross - section 600 includes a substrate layer 201, an epitaxial layer 219, a well region 203, a well contact region 205, a gate oxide layer 214, a gate electrode layer 212, an inter - layer dielectric layer 213, a source electrode layer 207, and a drain electrode layer 206. On the second cross - section 600, compared with the second cross - section 400 as

[0049] In Figures 2 - 6 the embodiment, the well contact regions 205 are distributed at both ends of the cell 208. In other embodiments, the well contact regions 205 can be distributed at any position of the epitaxial platform region 202, overlapping or partially overlapping with the epitaxial platform region 202 or having the same central axis. And, the well contact regions 205 do not need to be distributed in each strip - shaped epitaxial platform region 202. Those of ordinary skill in the art can, under the inspiration of the disclosure of the present invention, select the distribution of the well contact regions 205 in the epitaxial platform region 202 as needed. When the well contact regions 205 are not distributed in each strip - shaped epitaxial platform region 202, or the well contact regions 205 are staggeredly distributed in the second direction, rather than in a straight line as in Figures 2 - 6 the embodiment, the cells in the second cross - section do not all have well contact regions 205 in adjacent two well regions. The second cross - section referred to in the embodiments of the present invention refers to the cross - section of at least one cross - section including a well contact region 205.

[0050] Figure 7 is a partial - plane schematic diagram of a part of a power semiconductor device 700 according to another embodiment of the present application. It should be understood that Figure 7 only shows a partial - plane structure of the power semiconductor device 700 on one of its horizontal planes and does not represent the overall structure of the power semiconductor device 700. As Figure 7As shown, a single cell 708 of the power semiconductor device 700 includes an epitaxial platform region 202, a well region 203, a source region 204, and a well contact region 205. The epitaxial platform region 202, the well region 203, and the source region 204 are strip-shaped and are parallelly distributed longitudinally along a first direction (the y direction as shown in the figure). Among them, the well region 203 is distributed on both sides of the epitaxial platform region 202, and the source region is distributed in the well region 203.

[0051] Different from Figure 2 and Figure 5 the embodiment is that, in Figure 7 the embodiment, the well contact regions 205 located in different epitaxial platform regions 202 are staggeredly distributed in a second direction, that is, the well contact regions 205 in adjacent epitaxial platform regions 202 are arranged on different straight lines.

[0052] In Figure 7 the embodiment, the first cross-section along the AA' line has the same structure as the first cross-section 300 of the power semiconductor device 200. Therefore, for the sake of simplicity of description, it will not be elaborated here.

[0053] Figure 8 Schematic diagram of a second cross-section 800 of the power semiconductor device 700 along the Figure 7 BB' line in accordance with an embodiment of the present application. As Figure 8 shown, the second cross-section 800 includes: a substrate layer 201, an epitaxial layer 219, a well region 203, a source region 204, a well contact region 205, a gate oxide layer 214, a gate electrode layer 212, an interlayer dielectric layer 213, a source electrode layer 207, and a drain electrode layer 206. Different from Figure 6 the above, due to the staggered distribution of the well contact regions 205, on the second cross-section 800, the epitaxial platform regions 202 between some well regions 203 do not have well contact regions 205, and the epitaxial platform regions 202 without well contact regions are covered by the gate oxide layer 214 and the gate electrode layer 212.

[0054] Figure 9 Schematic plan view of a partial region of a power semiconductor device 900 in accordance with another embodiment of the present application. It should be understood that Figure 9 only a partial planar structure of the power semiconductor device 900 on one of its horizontal planes is shown, and it does not represent the overall structure of the power semiconductor device 900. As Figure 9 shown, a single cell 908 of the power semiconductor device 900 includes an epitaxial platform region 202, a well region 203, a source region 204, and a well contact region 905. The epitaxial platform region 202, the well region 203, and the source region 204 are strip-shaped and are parallelly distributed longitudinally along a first direction (the y direction as shown in the figure). Among them, the well region 203 is distributed on both sides of the epitaxial platform region 202, and the source region is distributed in the well region 203.

[0055] different from Figure 2 the embodiment, in Figure 9 the embodiment, the width of the well contact region 905 in the second direction is greater than the width of the epitaxial platform region 202.

[0056] In some embodiments, it is possible to Figure 5 and Figure 7 on the basis of the embodiment, make the width of the well contact region greater than the width of the epitaxial platform region 202.

[0057] In Figure 9 the embodiment, the first cross-section along the line AA' has the same structure as the first cross-section 300 of the power semiconductor device 200. Therefore, for the sake of simplicity of description, it will not be elaborated here.

[0058] Figure 10 Schematic diagram of the second cross-section 1000 of the power semiconductor device 900 along the Figure 9 BB' line in an embodiment of the present application. As Figure 10 shown, the second cross-section 1000 includes: a substrate layer 201, an epitaxial layer 219, a well region 203, a source region 204, a well contact region 205, a source electrode layer 207, and a drain electrode layer 206. Different from Figure 4 the embodiment, since the width of the well contact region 905 is greater than the width of the epitaxial platform region 202, on the second cross-section 1000, the well contact region 905 extends to the well regions 203 on both sides of the epitaxial platform region 202.

[0059] Figure 11 Schematic plan view of a partial region of the power semiconductor device 1100 according to another embodiment of the present application. It should be understood that Figure 11 only shows the partial planar structure of the power semiconductor device 1100 on one of the horizontal planes and does not represent the overall structure of the power semiconductor device 1100. As Figure 11 shown, a single cell 1108 of the power semiconductor device 1100 includes an epitaxial platform region 202, a well region 203, a source region 204, and a well contact region 1105. The epitaxial platform region 202, the well region 203, and the source region 204 are strip-shaped and are longitudinally parallelly distributed along the first direction (the y direction as shown in the figure). Among them, the well region 203 is distributed on both sides of the epitaxial platform region 202, and the source region 204 is distributed in the well region 203.

[0060] different from Figure 9 the embodiment, in Figure 11In the embodiment, the well contact region 1105 is further extended and widened in the second direction until it extends to the sidewall of the source region 204. That is to say, the well contact region 1105 is distributed along the second direction in the end region of the cell and is disconnected at the source region 204, so that the source region 204 can be connected to the source electrode layer 207. Figure 11 The well contact region 1105 shown is in contact with the sidewall of the source region 204. In some embodiments, the well contact region 1105 can also extend into a partial region of the source region 204, as long as the region where the source region 204 remains can be in contact with the source electrode layer 207.

[0061] In some embodiments, it is possible to Figure 7 On the basis of the embodiment, make the width of the well contact region greater than the width of the epitaxial platform region 202 and extend to the sidewall of the source region 204 or into the interior of the source region 204 in the second direction.

[0062] In Figure 11 the embodiment, the first cross-section along the line AA' has the same structure as the first cross-section 300 of the power semiconductor device 200. Therefore, for the sake of simplicity of description, it will not be elaborated here.

[0063] Figure 12 FIG. is a schematic diagram of a second cross-section 1200 of the power semiconductor device 1100 along the Figure 11 line BB' in an embodiment of the present application. As Figure 12 shown, the second cross-section 1200 includes: a substrate layer 201, an epitaxial layer 219, a well region 203, a source region 204, a well contact region 1105, a gate oxide layer 214, a gate electrode layer 212, an interlayer dielectric layer 213, a source electrode layer 207, and a drain electrode layer 206. Different from Figure 10 the embodiment, the width of the well contact region 1105 is further increased, and in the second direction, the sidewall of the well contact region 1105 is in contact with the sidewall of the source region 204.

[0064] In the foregoing embodiments, the well region 203, the well contact region 205, and the source region 204 all vertically extend from the surface of the epitaxial layer into its interior. Among them, in the direction perpendicular to the upper surface 209 of the epitaxial layer, the distance from the upper surface 209 of the epitaxial layer to the bottom of the well region 203 is the depth of the well region 203. In the direction perpendicular to the upper surface 209 of the epitaxial layer, the distance from the upper surface 209 of the epitaxial layer to the bottom of the well contact region 205 is the depth of the well contact region 205. In the direction perpendicular to the upper surface 209 of the epitaxial layer, the distance from the upper surface 209 of the epitaxial layer to the bottom of the source region 204 is the depth of the source region 204. In some embodiments, the depth of the well region 203 is greater than the depths of the source region 204 and the well contact region 205. In some embodiments, the depth of the source region 204 is the same as the depth of the well contact region 205. In some embodiments, the depth of the well contact region 205 is greater than the depth of the source region 204.

[0065] The embodiment of the present application shows a schematic structural diagram of a single epitaxial layer. In some embodiments, the epitaxial layer may include multiple epitaxial layers with different doping concentrations. In these embodiments, the well region 203 may be disposed in the uppermost epitaxial layer, that is, the epitaxial layer closest to the source electrode layer 207.

[0066] The present application takes a MOSFET device as an example to elaborate on the inventive principle. It should be understood that the present invention is equally applicable to power semiconductor devices of other structures, such as IGBTs, etc. Those of ordinary skill in the art can make improvements based on the device layout of the present application as needed after reading the present application and apply them to devices of other structures or types.

[0067] The embodiments of the present application can be used not only for devices with silicon as the semiconductor substrate layer but also for devices with wide bandgap materials, such as SiC and GaN, etc., as the semiconductor substrate layer.

[0068] According to the embodiments of the present application as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. The present specification selects and specifically describes these embodiments to better explain the principle and practical application of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A power semiconductor device, comprising: A substrate layer; An epitaxial layer having an upper surface and a lower surface of the epitaxial layer, wherein the lower surface of the epitaxial layer is in contact with the substrate layer; Well regions distributed in the epitaxial layer, strip-shaped in a first direction on the upper surface of the epitaxial layer, separating the portion of the epitaxial layer near the upper surface of the epitaxial layer into strip-shaped epitaxial platform regions; Source regions distributed in the well regions, strip-shaped in a first direction on the upper surface of the epitaxial layer; And Well contact regions distributed in the epitaxial platform regions between the well regions, two opposite sidewalls of the well contact regions being in contact with the epitaxial platform regions in the first direction respectively; Wherein other regions of the epitaxial platform regions except the well contact regions are covered with a gate oxide layer and a gate electrode layer.

2. The power semiconductor device according to claim 1, wherein the epitaxial platform regions between the well regions are strip-shaped, and a plurality of the well contact regions are distributed in the strip-shaped epitaxial platform regions, and the plurality of well contact regions are equidistantly distributed in the first direction.

3. The power semiconductor device according to claim 1, wherein the epitaxial platform regions between the well regions are strip-shaped, and a plurality of the well contact regions are distributed in the strip-shaped epitaxial platform regions, and the distance between adjacent well contact regions in the first direction is more than 0.5 μm.

4. The power semiconductor device according to claim 1, wherein the width of the well contact region in a second direction on the upper surface of the epitaxial layer is greater than the width of the epitaxial platform region, and the second direction is perpendicular to the first direction.

5. The power semiconductor device according to claim 1, wherein the width of the well contact region in a second direction on the upper surface of the epitaxial layer is equal to the width of the epitaxial platform region, and the second direction is perpendicular to the first direction.

6. The power semiconductor device according to claim 1, wherein the width of the well contact region in a second direction on the upper surface of the epitaxial layer is greater than the width of the epitaxial platform region, the second direction is perpendicular to the first direction, and the well contact region extends in the second direction until the sidewall of the well contact region is in contact with the sidewall of the source region.

7. The power semiconductor device according to claim 1, wherein the well contact regions of adjacent epitaxial platform regions are distributed on a straight line in a second direction on the upper surface of the epitaxial layer, and the second direction is perpendicular to the first direction.

8. The power semiconductor device according to claim 1, wherein the well contact regions of adjacent epitaxial platform regions are distributed on different straight lines in a second direction on the upper surface of the epitaxial layer, and the second direction is perpendicular to the first direction.

9. The power semiconductor device according to any one of claims 1-8, further comprising: A gate oxide layer located on the epitaxial layer; And A gate electrode layer located on the gate oxide layer, covering the gate oxide layer; Wherein, the gate oxide layer and the gate electrode layer cover a part of the source region area and cover other regions except the well contact regions and a certain area around the well contact regions.

10. The power semiconductor device according to any one of claims 1-8, further comprising: A drain electrode layer covering the surface of the substrate layer, the surface of the substrate layer being opposite and parallel to the surface of the substrate layer covering the epitaxial layer; And The source electrode layer is located above the upper surface of the epitaxial layer, and is isolated from a partial upper surface area of the epitaxial layer by an interlayer dielectric layer, and is connected to the well contact region and the source region exposed on the upper surface of the epitaxial layer.

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