An anisotropic dielectric layer transistor and method of fabrication
By employing a low-symmetry dielectric layer and an armchair crystal stack with conductive channels in a two-dimensional semiconductor electronic device, the problem of anisotropic control of conductive channels was solved, and the electrical performance of the device was improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-11
- Publication Date
- 2026-03-27
AI Technical Summary
In two-dimensional semiconductor electronic devices, the anisotropy of the conductive channel is difficult to control, and the dangling bonds and disordered states on the surface of traditional dielectric materials affect electrical performance.
A dielectric layer and conductive channel with a low-symmetry C2 rotational symmetry crystal structure are stacked along the crystal direction of the armchair to form anisotropy. The dielectric layer thickness is 10nm to 100nm, the conductive channel thickness is 1nm to 20nm, and it is combined with an ohmic contact metal electrode and a protective layer.
Anisotropic control of the conductive channel is achieved, reducing leakage current and improving electrical performance, exhibiting low leakage current, high on/off ratio, small subthreshold swing and high anisotropic conductivity.
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Figure CN119317161B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the technical field of semiconductor devices, and more particularly relates to an anisotropic dielectric layer transistor and a preparation method. BACKGROUND
[0002] With the continuous miniaturization of silicon-based field effect transistors according to Moore's Law, the electrical performance decline caused by the short channel effect is difficult to meet the growing demand for chips. Two-dimensional semiconductor materials have become the ideal channel material for the next generation of integrated circuit chips due to their atomic-level thickness, high carrier mobility, and suppression of short channel effects. However, after the integration of two-dimensional semiconductor channel materials with traditional dielectric materials (SiO2), the dangling bonds and disordered states on the surface of the dielectric material will affect the electrical performance of the two-dimensional semiconductor channel material, making it difficult to exhibit intrinsic excellent performance.
[0003] Compared with traditional oxide dielectric materials, the surface of van der Waals structure dielectric material presents atomic-level flatness without dangling bonds, and is considered as an ideal dielectric layer that is compatible with two-dimensional semiconductor channel materials. After screening and exploration, a series of van der Waals dielectric layers have been developed, such as hexagonal boron nitride (h-BN), calcium fluoride (CaF2), strontium titanate (SrTiO3), and antimony oxide (Sb2O3). With further research, it is found that these van der Waals dielectric layers all belong to high-symmetry crystal structures, and the intrinsic isotropy is difficult to further realize the anisotropic regulation of two-dimensional semiconductor channels. Therefore, the development of low-crystal-symmetry van der Waals dielectric layers not only provides new degrees of freedom for the performance regulation of two-dimensional semiconductor electronic devices, but also facilitates the design and development of new multifunctional electronic devices. SUMMARY
[0004] In view of the above defects or improvement needs of the prior art, the present application provides an anisotropic dielectric layer transistor and a preparation method, which solves the problem that the anisotropy of the conductive channel in the two-dimensional semiconductor electronic device is difficult to regulate.
[0005] To achieve the above-mentioned purpose, according to one aspect of the present application, an anisotropic dielectric layer transistor is provided, which comprises a substrate, a gate, a source electrode, a drain electrode, a conductive channel and a dielectric layer. The substrate serves as a carrier for the conductive channel. The dielectric layer is stacked above the conductive channel, and the dielectric layer and the conductive channel have the same armchair crystal direction. The source electrode and the drain electrode are arranged on both sides of the conductive channel. The gate is arranged on the dielectric layer. The dielectric layer has a low-symmetry crystal structure and is anisotropic in the horizontal plane.
[0006] Further preferably, the dielectric layer is made of a material with a C2 rotational symmetry crystal structure.
[0007] Further preferably, the material of the dielectric layer is one of gallium indium sulfide, molybdenum oxide, vanadium oxychloride, bismuth selenide and bromide chromium sulfide.
[0008] Further preferably, the thickness of the dielectric layer is 10nm-100nm.
[0009] Further preferably, the dielectric constant of the dielectric layer is greater than 10.
[0010] Further preferably, the conductive channel is a material with C3 rotational symmetry, and the thickness is 1nm-20nm.
[0011] Further preferably, the material with C3 rotational symmetry is molybdenum sulfide, molybdenum selenide, molybdenum telluride, tungsten sulfide, tungsten selenide or graphene.
[0012] Further preferably, the gate, source electrode and drain electrode each include two layers, one is a metal electrode capable of realizing ohmic contact with the conductive channel, and the other is a protective layer for avoiding oxidation of the metal electrode, the thickness of the metal electrode is 5nm-10nm, and the thickness of the protective layer is 50nm-100nm.
[0013] Further preferably, the substrate is an insulating rigid or flexible substrate.
[0014] According to another aspect of the present application, a preparation method of the above-mentioned anisotropic dielectric layer transistor is provided, and the preparation method comprises the following steps:
[0015] Respectively preparing the conductive channel and the dielectric layer;
[0016] Respectively detecting the crystal direction of the conductive channel and the dielectric layer, then stacking the dielectric layer and the conductive channel along the armchair crystal direction and placing them on the substrate;
[0017] Respectively arranging the source electrode and the drain electrode on both sides of the conductive channel, and arranging the gate on the dielectric layer, so as to obtain the required transistor.
[0018] Overall, compared with the prior art, the above technical scheme conceived by the present application has the following beneficial effects:
[0019] 1. The present application adopts a dielectric layer with low-symmetry crystal structure, which is anisotropic in the horizontal plane, so that the anisotropy of the conductive channel is regulated, because the anisotropic dielectric layer and the conductive channel are stacked and contacted along the armchair crystal direction, and under the action of symmetry coupling, the isotropy of the conductive channel is destroyed, and anisotropy is generated, so as to regulate the anisotropy of the conductive channel.
[0020] 2. The dielectric layer of the present application adopts a material with C2 rotational symmetry crystal structure, because the material with C2 rotational symmetry can have a symmetry coupling effect with the conductive channel with C3 rotational symmetry, and then produce C1 symmetry with lower symmetry, i.e. anisotropy;
[0021] 3. The dielectric layer adopted in the present application has a thickness of 10 nm to 100 nm, too thin to easily cause electric leakage, and too thick to have a small capacitance, which affects the regulation performance of the dielectric layer, and the conductive channel has a thickness of 1 nm to 20 nm, too thick to make the dielectric layer difficult to regulate the anisotropy of the conductive channel;
[0022] 4. The anisotropic dielectric layer transistor provided by the present application, under the regulation of the dielectric layer, not only reduces the leakage current and improves the electrical performance of the conductive channel, but also induces the channel material to produce obvious anisotropic electrical response due to the low-symmetry lattice of the transistor, so that the transistor has good electrical performance, including low leakage current (<10 -12 A), high on-off ratio (>10 6 ), small sub-threshold swing (71.6 mV dec -1 ) and high anisotropic conductance ratio (>10 6 ). BRIEF DESCRIPTION OF DRAWINGS
[0023] Figure 1 is a structure schematic diagram of an anisotropic dielectric layer transistor constructed according to the preferred embodiment of the present application;
[0024] Figure 2 is a capacitance measurement and dielectric constant extraction curve of a capacitor with a dielectric layer of GaInS3 according to the preferred embodiment of the present application;
[0025] Figure 3 is an anisotropic characterization of the dielectric layer of GaInS3 according to the preferred embodiment of the present application, wherein (a) is the polarized optical absorption spectrum of GaInS3 at different wavelengths, and (b) is the extracted polar coordinate diagram of optical absorption at a wavelength of 370 nm;
[0026] Figure 4 is an anisotropic optical characterization of the MoS2 / GaInS3 heterojunction constructed according to the preferred embodiment 1 of the present application, wherein (a) is an optical photo of the MoS2 / GaInS3 heterojunction, wherein the number 1 represents a region with only MoS2, and the number 2 represents a region of the MoS2 / GaInS3 heterojunction; (b) is the photoluminescence (PL) polar coordinate data of the region with only MoS2; and (c) is the PL polar coordinate data of the region of the MoS2 / GaInS3 heterojunction;
[0027] Figure 5(a) is the transfer characteristic output curve, (b) is the extracted sub-threshold swing curve;
[0028] Figure 6 is the conductance curve extracted in different directions of the transistor constructed according to the preferred embodiment 1 of the present application. DETAILED DESCRIPTION
[0029] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not used to limit the present application. In addition, the technical features involved in each embodiment of the present application described below can be combined with each other as long as they do not conflict with each other.
[0030] As shown in Figure 1 An anisotropic dielectric layer-based field effect transistor includes an insulating substrate, a conductive channel material, a dielectric layer, a gate and source-drain electrodes.
[0031] In an embodiment of the present application, the dielectric layer is a planar anisotropic, i.e. a low-symmetry crystal structure, which has in-plane anisotropic physical properties. Among the seven crystal systems, four crystal systems (cubic, tetragonal and hexagonal crystal systems) are in-plane isotropic, and three crystal systems (orthorhombic, monoclinic and triclinic crystal systems) are low-symmetry and exhibit in-plane anisotropy.
[0032] In an embodiment of the present application, the thickness of the conductive channel material is 1 nm to 20 nm. If the conductive channel is too thick, it is difficult to induce anisotropy. The thickness of the anisotropic structure of the dielectric layer is 10 nm to 100 nm. The anisotropic structure of the dielectric layer can maintain high capacitance at this thickness and improve the gate control performance.
[0033] In an embodiment of the present application, the dielectric layer is C2 rotationally symmetric gallium indium sulfide GaInS3, which is an orthorhombic crystal system with a space group of Cmc21. The element ratio in GaInS3 can be adjusted, and the range is Ga 1-x In 1+x S3(x = 0-0.4).
[0034] In an embodiment of the present application, the dielectric layer is C2 rotationally symmetric molybdenum oxide MoO3, which is an orthorhombic crystal system with a space group of Pnma.
[0035] In an embodiment of the present application, the dielectric layer is C2 rotationally symmetric vanadium oxychloride VOCl, which is an orthorhombic crystal system with a space group of Pmmn.
[0036] In one embodiment of the present application, the dielectric layer is C2 rotationally symmetric bismuth selenide oxide Bi2SeO5, which is an orthorhombic system and has a space group of Abm2.
[0037] In one embodiment of the present application, the dielectric layer is C2 rotationally symmetric bromide chromium sulfide CrSBr, which is an orthorhombic system and has a space group of Pmmn.
[0038] Theoretically, the dielectric layer with C2 symmetry can regulate the anisotropy of the channel.
[0039] In one embodiment of the present application, the dielectric constant of the dielectric layer is greater than 10, and the high dielectric constant has good gate regulation capability.
[0040] In one embodiment of the present application, the conductive channel material is MoS2, MoSe2, MoTe2, WS2, WSe2, graphene, etc. The above channel materials are two-dimensional materials and have isotropy. The thickness of the conductive channel is 1 nm to 20 nm. The thickness of the channel is too high to induce anisotropy.
[0041] In one embodiment of the present application, the substrate is a Si / SiO2 insulating substrate.
[0042] In one embodiment of the present application, the source electrode, the drain electrode and the gate electrode are selected from metal electrodes in ohmic contact with the channel material, including two layers, one layer is a metal electrode capable of achieving ohmic contact with the conductive channel, and the other layer is a protective layer to avoid oxidation of the metal electrode. The thickness of the metal electrode is 5 nm to 10 nm, and the thickness of the protective layer is 50 nm to 100 nm. For example, Bi / Au, In / Au, Sb / Au, Ti / Au, etc., wherein Au is used as the protective layer. The preparation method of the anisotropic dielectric layer transistor is as follows:
[0043] (1) preparing the dielectric layer and the conductive channel material; the preparation methods of the dielectric layer and the conductive channel are both existing methods, for example, the mechanical peeling or chemical vapor deposition method is used to prepare the dielectric layer.
[0044] (2) detecting the crystal direction of the conductive channel and the dielectric layer respectively, and then stacking the dielectric layer and the conductive channel along the armchair crystal direction on the substrate;
[0045] (3) preparing the source and drain metal electrodes on the conductive channel material and preparing the gate on the dielectric layer, thereby obtaining the field effect transistor.
[0046] The present application will be further described below with reference to specific embodiments.
[0047] Embodiment 1
[0048] MoS2 is prepared as the conductive channel by mechanical exfoliation method, with a thickness of ~1 nm, and GaInS3 with C2 rotational symmetry is prepared as the dielectric layer material, with a thickness of ~40 nm and a dielectric constant of ~12;
[0049] The crystal direction of the dielectric layer and the conductive channel is measured, the conductive channel is transferred to the insulating substrate of the 300 nm SiO2 / Si wafer by using PDMS, and then the dielectric layer is transferred to the conductive channel, so as to ensure that the dielectric layer and the conductive channel are stacked along the armchair crystal direction;
[0050] The source electrode and the drain electrode are deposited on both sides of the conductive channel by using a coating instrument, and the gate electrode is deposited on the dielectric layer, the material of the source electrode and the drain electrode is Ti / Au, with a thickness of 10 nm / 50 nm, the material of the gate electrode is Ti / Au, with a thickness of 10 nm / 50 nm, and the deposition rate is 0.1 A / s;
[0051] Example 2
[0052] MoSe2 is prepared as the conductive channel by mechanical exfoliation method, with a thickness of ~1 nm, and MoO3 with C2 rotational symmetry is prepared as the dielectric layer material, with a thickness of ~30 nm and a dielectric constant of ~30;
[0053] The crystal direction of the dielectric layer and the conductive channel is measured, the conductive channel is transferred to the above-mentioned substrate by using PDMS, and then the dielectric layer is transferred to the conductive channel, so as to ensure that the dielectric layer and the conductive channel are stacked along the armchair crystal direction;
[0054] The source electrode and the drain electrode are deposited on both sides of the conductive channel by using a coating instrument, and the gate electrode is deposited on the dielectric layer, the material of the source electrode and the drain electrode is Bi / Au, with a thickness of 5 / 50 nm, the material of the gate electrode is Bi / Au, with a thickness of 5 / 50 nm, and the deposition rate is 0.1 A / s;
[0055] Example 3
[0056] MoTe2 is prepared as the conductive channel by mechanical exfoliation method, with a thickness of ~3 nm, and VOCl with C2 rotational symmetry is prepared as the dielectric layer material, with a thickness of ~35 nm and a dielectric constant of ~11;
[0057] The channel material and the dielectric layer are transferred to the substrate by using the method in Examples 1-2;
[0058] The gate electrode is deposited on the dielectric layer by using the method in Examples 1-2, the material of the source electrode and the drain electrode is In / Au, with a thickness of 10 nm / 50 nm, the material of the gate electrode is In / Au, with a thickness of 10 nm / 50 nm, and the deposition rate is 0.1 A / s;
[0059] Example 4
[0060] WS2 was prepared as the conductive channel by mechanical exfoliation with a thickness of ~1 nm and GaInS3 was prepared as the dielectric layer material with C2 rotational symmetry with a thickness of ~55 nm and a dielectric constant of ~12;
[0061] The channel material and the dielectric layer were transferred to a substrate using the method in Example 1-2;
[0062] The materials of the gate, source electrode and drain electrode were deposited on the dielectric layer using the method in Example 1-2, Bi / Au with a thickness of 10 nm / 50 nm, and the material of the gate was Bi / Au with a thickness of 10 nm / 50 nm, and the deposition rate was 0.1 A / s;
[0063] Example 5
[0064] WSe2 was prepared as the conductive channel by mechanical exfoliation with a thickness of ~5 nm and Bi2SeO5 was prepared as the dielectric layer material with C2 rotational symmetry with a thickness of ~10 nm and a dielectric constant of ~12;
[0065] The channel material and the dielectric layer were transferred to a substrate using the method in Example 1-2;
[0066] The materials of the gate, source electrode and drain electrode were deposited on the dielectric layer using the method in Example 1-2, In / Au with a thickness of 5 nm / 50 nm, and the material of the gate was In / Au with a thickness of 5 nm / 50 nm, and the deposition rate was 0.1 A / s;
[0067] Example 6
[0068] Graphene was prepared as the conductive channel by mechanical exfoliation with a thickness of ~1 nm and CrSBr was prepared as the dielectric layer material with C2 rotational symmetry with a thickness of ~45 nm and a dielectric constant of ~18;
[0069] The channel material and the dielectric layer were transferred to a substrate using the method in Example 1-2;
[0070] The materials of the gate, source electrode and drain electrode were deposited on the dielectric layer using the method in Example 1-2, In / Au with a thickness of 5 nm / 50 nm, and the material of the gate was In / Au with a thickness of 5 nm / 50 nm, and the deposition rate was 0.1 A / s;
[0071] Example 7
[0072] WSe2 was prepared as the conductive channel by mechanical exfoliation with a thickness of ~5 nm, and GaInS3 with C2 rotational symmetry was prepared as the dielectric layer material with a thickness of ~100 nm and a dielectric constant of ~12;
[0073] The channel material and the dielectric layer were transferred to the substrate by the method in Example 1-2;
[0074] The materials of the gate, source electrode and drain electrode were deposited on the dielectric layer by the method in Example 1-2, which were Ti / Au with a thickness of 5 nm / 50 nm, and the material of the gate was Ti / Au with a thickness of 5 nm / 50 nm, and the deposition rate was 0.1 A / s;
[0075] Example 8
[0076] MoTe2 was prepared as the conductive channel by mechanical exfoliation with a thickness of ~10 nm, and GaInS3 with C2 rotational symmetry was prepared as the dielectric layer material with a thickness of ~65 nm and a dielectric constant of ~12;
[0077] The channel material and the dielectric layer were transferred to the substrate by the method in Example 1-2;
[0078] The materials of the gate, source electrode and drain electrode were deposited on the dielectric layer by the method in Example 1-2, which were Bi / Au with a thickness of 5 nm / 50 nm, and the material of the gate was Bi / Au with a thickness of 5 nm / 50 nm, and the deposition rate was 0.1 A / s;
[0079] Example 9
[0080] WSe2 was prepared as the conductive channel by mechanical exfoliation with a thickness of ~15 nm, and GaInS3 with C2 rotational symmetry was prepared as the dielectric layer material with a thickness of ~70 nm and a dielectric constant of ~12;
[0081] The channel material and the dielectric layer were transferred to the substrate by the method in Example 1-2;
[0082] The materials of the gate, source electrode and drain electrode were deposited on the dielectric layer by the method in Example 1-2, which were Bi / Au with a thickness of 8 nm / 100 nm, and the material of the gate was Bi / Au with a thickness of 9 nm / 100 nm, and the deposition rate was 0.1 A / s;
[0083] Example 10
[0084] MoS2 was prepared as the conductive channel by mechanical exfoliation with a thickness of ~20 nm, and CrSBr with C2 rotational symmetry was prepared as the dielectric layer material with a thickness of ~50 nm and a dielectric constant of ~19;
[0085] The channel material and dielectric layer are transferred to the substrate using the method in Example 1-2;
[0086] The materials of the gate, source and drain electrodes are Ti / Au with thickness of 10 nm / 100 nm, and the material of the gate is Ti / Au with thickness of 10 nm / 100 nm, and the deposition rate is 0.1 nm / s, 0.1 nm / s and 0.1 nm / s, respectively, on the dielectric layer using the method in Example 1-2;
[0087] Figure 2 The capacitance measurement and the extracted dielectric constant curve of the capacitor with GaInS3 as the dielectric layer. As shown in the schematic diagram and the optical photograph, the capacitor with Ti-Au / GaInS3 / Au structure is prepared to test the capacitance of GaInS3. In the voltage range of -3 to 3 V and the frequency range of 1 kHz to 1 MHz, GaInS3 exhibits a stable capacitance value of ~1.2 pF, and its relative dielectric constant is further extracted to be ~12.0, which is much larger than that of the traditional dielectric layer SiO2 (~4.0) and two-dimensional BN (~5.0).
[0088] Figure 3 The anisotropy characterization of GaInS3 as the dielectric layer. The in-plane anisotropic absorption of the dielectric layer GaInS3 is analyzed by polarized optical absorption spectrum. According to the absorption spectrum at the wavelength of 300-800 nm, it can be observed that GaInS3 has obvious angle-dependent absorption in the ultraviolet band, and by extraction fitting, the anisotropic absorption ratio of GaInS3 at the wavelength of 370 nm is ~1.5, which proves that GaInS3 has in-plane anisotropy.
[0089] Figure 4 The characterization of the anisotropy of the conductive channel material after the conductive channel material and the dielectric layer material are stacked along the armchair crystal direction in Example 1. As shown in (a) of Figure 4 the optical microscope photograph of the heterojunction of MoS2 and GaInS3 stacked along the armchair direction. Figure 4 (b) of is the polarized photoluminescence (PL) data collected in the area numbered 1 (i.e., only MoS2); Figure 4 (c) of is the polarized PL data collected in the area numbered 2 (i.e., the area where MoS2 and GaInS3 are stacked). According to the comparison, when MoS2 and GaInS3 are stacked along the armchair direction, there will be obvious anisotropic optical response.
[0090] Figure 5 The transfer characteristic output curve and subthreshold swing curve of the anisotropic dielectric layer transistor in Example 1. Under the modulation of the GaInS3 dielectric layer, the MoS2 transistor exhibits excellent electrical performance, such as low drain current (<10 -12 A), high on-off ratio (>106 ), small subthreshold swing (71.6 mV dec -1 ).
[0091] Figure 6 Figure 1 is a transfer characteristic output curve of the anisotropic dielectric layer transistor in each direction in Example 1. Under the regulation of the GaInS3 dielectric layer of the anisotropic structure, the conductance ratio of the MoS2 transistor in the armchair direction (AC) and zigzag direction (ZZ) is as high as 10 6 , which is much higher than the anisotropy ratio reported by the current two-dimensional material.
[0092] Those skilled in the art will easily understand that the above description is only the preferred embodiment of the present application, and is not intended to limit the present application, and any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. An anisotropic dielectric layer transistor, characterized by, The transistor comprises a substrate, a gate, a source electrode, a drain electrode, a conductive channel and a dielectric layer, the substrate serves as a carrier of the conductive channel, the dielectric layer is stacked above the conductive channel, the dielectric layer and the conductive channel have the same chiral crystal direction, the source electrode and the drain electrode are arranged on both sides of the conductive channel, and the gate is arranged on the dielectric layer, wherein the dielectric layer has a low-symmetry crystal structure and is anisotropic in a horizontal plane. The dielectric layer employs a material having C 2 a material of a rotationally symmetric crystal structure; The conductive channel is a material with C 3 rotational symmetry, with a thickness of 1 nm to 20 nm, C 2 rotational symmetry material can be coupled with C 3 rotational symmetry of the conductive channel symmetry, and then produce a lower symmetry C 1 symmetry, i.e. anisotropy.
2. A transistor of claim 1 wherein the anisotropic dielectric layer is formed of a material having a dielectric constant of at least 10. The material of the dielectric layer is one of gallium indium sulfide, molybdenum oxide, chlorovanadium oxide, bismuth selenium oxide and bromide chromium sulfide.
3. A transistor of an anisotropic dielectric layer as claimed in claim 1 or 2, characterized in that The thickness of the dielectric layer is 10-100 nm.
4. A transistor of an anisotropic dielectric layer as claimed in claim 1 or 2, characterized in that The dielectric constant of the dielectric layer is greater than 10.
5. A transistor of claim 4, wherein the anisotropic dielectric layer is formed of a material selected from the group consisting of: SiO2, Si3N4, Al2O3, and HfO2. The C 3The material of the rotational symmetry is molybdenum sulfide, molybdenum selenide, molybdenum telluride, tungsten sulfide, tungsten selenide or graphene.
6. A transistor of an anisotropic dielectric layer as claimed in claim 1 or 2, characterized in that The gate, the source electrode and the drain electrode each comprise two layers, one layer is a metal electrode capable of realizing ohmic contact with the conductive channel, and the other layer is a protective layer for preventing oxidation of the metal electrode, the thickness of the metal electrode is 5-10 nm, and the thickness of the protective layer is 50-100 nm.
7. A transistor of an anisotropic dielectric layer as claimed in claim 1 or 2, characterized in that The substrate is an insulating rigid or flexible substrate.
8. A method of fabricating the anisotropic dielectric layer transistor according to any one of claims 1 to 7, characterized by, The preparation method comprises the following steps: Preparation of the conductive channel and the dielectric layer respectively; Detection of the crystal direction of the conductive channel and the dielectric layer respectively, then stacking the dielectric layer and the conductive channel along the chiral crystal direction and placing them on the substrate; Arrangement of the source electrode and the drain electrode on both sides of the conductive channel respectively, and arrangement of the gate on the dielectric layer, thereby obtaining the required transistor.