Light emitting diode capable of improving etching uniformity and preparation method thereof

Abstract

The embodiment of the invention provides a light emitting diode capable of improving etching uniformity and a preparation method thereof, and belongs to the technical field of semiconductors. The preparation method comprises the steps that an epitaxial lamination layer is formed on a substrate, the substrate is provided with a center area and a first annular area which are connected, and the first annular area is located on the periphery of the center area; the epitaxial laminated layer is etched to form a plurality of light-emitting structures arranged in an array mode, the light-emitting structures are located in the center area and the first annular area, and a cutting channel is formed between every two adjacent light-emitting structures; removing the light-emitting structure in the first annular region; and cracking the substrate along the cutting channels to obtain a plurality of light-emitting diodes. According to the embodiment of the invention, the etching uniformity of the LED can be improved, and the uniformity of the light-emitting effect of the LED is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a light emitting diode with improved etching uniformity and a preparation method thereof. Background Art

[0002] Light Emitting Diode (LED) has been widely used in various light source fields such as backlight, lighting, and landscaping due to its small size, long service life, rich colors, and low energy consumption.

[0003] In the related art, the preparation method of LED includes: forming an epitaxial stack on a substrate, wherein the epitaxial stack includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked in sequence; etching the epitaxial stack to form a plurality of light-emitting structures, wherein a cutting path is formed between adjacent light-emitting structures; and finally, the substrate is split along the cutting path to obtain a plurality of LEDs.

[0004] However, due to the etching load effect generated during the etching process, the etching gas consumption is greater than the supply in the central area of ​​the substrate where the patterns are dense, and the etching gas consumption is less than the supply in the edge area of ​​the substrate where the patterns are sparse. This will cause the etching rate of the edge area to be greater than the etching rate of the central area during the etching of the epitaxial stack, and the etching depth of the light-emitting structure in the edge area to be greater than the etching depth of the light-emitting structure in the central area, thereby affecting the etching uniformity of the LED and the uniformity of the LED's light-emitting effect. Summary of the invention

[0005] The embodiment of the present disclosure provides a light-emitting diode with improved etching uniformity and a method for manufacturing the same, which can improve the etching uniformity of the LED and improve the uniformity of the light-emitting effect of the LED. The technical solution is as follows:

[0006] On the one hand, a method for preparing a light-emitting diode is provided, comprising: forming an epitaxial stack on a substrate, the substrate having a connected central region and a first annular region, the first annular region being located at the periphery of the central region; etching the epitaxial stack to form a plurality of light-emitting structures arranged in an array, the plurality of light-emitting structures being located at the central region and the first annular region, and cutting paths being formed between adjacent light-emitting structures; removing the light-emitting structures in the first annular region; and scratching the substrate along the cutting paths to obtain a plurality of the light-emitting diodes.

[0007] Optionally, the ratio of the width of the first annular area to the center distance between two adjacent light-emitting structures is 3 to 5.

[0008] Optionally, a width of the first annular region is 30 μm to 150 μm.

[0009] Optionally, the epitaxial stack includes a first semiconductor layer, a light emitting layer, and a second semiconductor layer stacked in sequence, the first semiconductor layer includes a first sublayer, a second sublayer, and a third sublayer stacked in sequence in a direction away from the substrate, and the growth temperature of the second sublayer is greater than the growth temperature of the first sublayer and the growth temperature of the third sublayer.

[0010] Optionally, a difference between a growth temperature of the second sublayer and a growth temperature of the first sublayer is 200°C to 400°C, and a difference between a growth temperature of the second sublayer and a growth temperature of the third sublayer is 200°C to 400°C.

[0011] Optionally, the growth temperature of the second sub-layer is 1400°C to 1600°C.

[0012] Optionally, the thickness of the first sub-layer is 2.4 μm to 2.6 μm, the thickness of the second sub-layer is 0.4 μm to 0.6 μm, and the thickness of the third sub-layer is 0.4 μm to 0.6 μm.

[0013] Optionally, before etching the epitaxial stack, the method further comprises: forming a transparent conductive layer on the second semiconductor layer.

[0014] Optionally, each of the light-emitting structures has a table extending from a surface of the second semiconductor layer away from the light-emitting layer toward the first semiconductor layer. After removing the light-emitting structure in the first annular area, the method further includes: forming a first connecting electrode on each of the table surfaces of the light-emitting structures.

[0015] On the other hand, a light emitting diode is provided, wherein the light emitting diode is prepared by any one of the above-mentioned preparation methods.

[0016] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:

[0017] In the disclosed embodiment, the substrate has a central region and a first annular region connected to each other, the first annular region is located at the periphery of the central region, the epitaxial stack is first etched to form a plurality of light-emitting structures arranged in an array, the plurality of light-emitting structures are located in the central region and the first annular region, a cutting path is formed between adjacent light-emitting structures, the light-emitting structures in the first annular region are removed, and finally the substrate is scratched along the cutting path to obtain a plurality of LEDs. In this way, the light-emitting structures in the first annular region at the edge of the substrate that are unevenly etched due to the etching load effect can be removed, so that the etching of the plurality of LEDs obtained by scratching is more uniform, which is conducive to improving the etching uniformity of the LEDs and improving the uniformity of the light-emitting effect of the LEDs. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 is a flow chart of a method for preparing an LED provided by an embodiment of the present disclosure;

[0020] Figure 2 is a flow chart of another method for preparing an LED provided by an embodiment of the present disclosure;

[0021] Figure 3 is a top view of an LED manufacturing process provided by an embodiment of the present disclosure;

[0022] Figure 4 is a schematic diagram of the structure of an LED provided by an embodiment of the present disclosure;

[0023] Figure 5 is a schematic structural diagram of a first semiconductor layer provided by an embodiment of the present disclosure;

[0024] Figure 6 It is a top view of an LED manufacturing process provided by an embodiment of the present disclosure.

[0025] Reference numerals:

[0026] 10: substrate; 10a: central area; 10b: first annular area; 10c: second annular area; 11: first substrate; 20: light-emitting structure; 201: cutting path; 21: first semiconductor layer; 211: first sublayer; 212: second sublayer; 213: third sublayer; 22: light-emitting layer; 23: second semiconductor layer; 24: table; 30: transparent conductive layer; 40: first connecting electrode; 41: second connecting electrode; 50: first passivation layer; 51: first through hole; 52: second through hole; 60: first pad electrode; 61: second pad electrode; 70: second passivation layer. DETAILED DESCRIPTION

[0027] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0028] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity restriction, but indicate that there is at least one. Words such as "include" and similar words mean that the elements or objects appearing before "include" include the elements or objects listed after "include" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0029] The present disclosure provides a method for preparing an LED, which is applicable to LEDs of various sizes or types such as mini-LEDs and micro-LEDs. The preparation method is exemplarily described below with reference to the accompanying drawings.

[0030] Figure 1 FIG. 1 is a flow chart of a method for preparing an LED provided by an embodiment of the present disclosure. Figure 1 As shown, the preparation method comprises:

[0031] In step S1001 , an epitaxial stack is formed on a substrate.

[0032] The substrate has a central region and a first annular region connected to each other, and the first annular region is located at the periphery of the central region.

[0033] In step S1002, the epitaxial stack is etched to form a plurality of light emitting structures arranged in an array.

[0034] A plurality of light emitting structures are located in the central area and the first annular area, and cutting paths are formed between adjacent light emitting structures.

[0035] In step S1003 , the light-emitting structure in the first annular region is removed.

[0036] In step S1004, the substrate is cleaved along the dicing lines to obtain a plurality of light emitting diodes.

[0037] In the disclosed embodiment, the substrate has a central region and a first annular region connected to each other, the first annular region is located at the periphery of the central region, the epitaxial stack is first etched to form a plurality of light-emitting structures arranged in an array, the plurality of light-emitting structures are located in the central region and the first annular region, a cutting path is formed between adjacent light-emitting structures, the light-emitting structures in the first annular region are removed, and finally the substrate is scratched along the cutting path to obtain a plurality of LEDs. In this way, the light-emitting structures in the first annular region at the edge of the substrate that are unevenly etched due to the etching load effect can be removed, so that the etching of the plurality of LEDs obtained by scratching is more uniform, which is conducive to improving the etching uniformity of the LEDs and improving the uniformity of the light-emitting effect of the LEDs.

[0038] Figure 2 FIG. 1 is a flow chart of another method for preparing an LED provided by an embodiment of the present disclosure. Figure 2 As shown, the preparation method includes.

[0039] In step S2001, an epitaxial stack is formed on a substrate.

[0040] Figure 3 FIG. 1 is a top view of an LED manufacturing process provided by an embodiment of the present disclosure. Figure 3 As shown, the substrate 10 has a central region 10a and a first annular region 10b connected to each other, and the first annular region 10b is located at the periphery of the central region 10a.

[0041] Exemplarily, the shape of the central region 10a is a rectangle, the shape of the first annular region 10b is a rectangular ring, and the central region 10a is concentric with the first annular region 10b.

[0042] Figure 4 Schematic diagram of the structure of an LED provided by an embodiment of the present disclosure. Figure 4 As shown, the epitaxial stack includes a first semiconductor layer 21, a light emitting layer 22 and a second semiconductor layer 23 which are stacked in sequence.

[0043] Optionally, the substrate 10 may be a patterned sapphire substrate having a plurality of protrusions arranged in an array on its surface.

[0044] Figure 5 Schematic diagram of the structure of a first semiconductor layer provided by an embodiment of the present disclosure. Figure 5 As shown, the first semiconductor layer 21 includes a first sublayer 211, a second sublayer 212 and a third sublayer 213 which are sequentially stacked in a direction away from the substrate.

[0045] Optionally, the growth temperature of the second sub-layer 212 is greater than the growth temperature of the first sub-layer 211 and the growth temperature of the third sub-layer 213 .

[0046] Since the density of the film layer grown at high temperature is good, the first semiconductor layer 21 is composed of the first sublayer 211 grown at low temperature, the second sublayer 212 grown at high temperature, and the third sublayer 213 grown at low temperature, so that the density of the first semiconductor layer 21 can be better, and the first sublayer 211 and the third sublayer 213 grown at low temperature can ensure the overall growth quality of the first semiconductor layer 21. The improved density of the first semiconductor layer 21 can reduce the reaction rate of the first semiconductor layer 21 during chemical etching, and can reduce the probability of uneven etching morphology of the first semiconductor layer 21 due to uneven etching rates in different regions during chemical etching, thereby improving etching uniformity.

[0047] Exemplarily, the growth temperature of the first sub-layer 211 and the growth temperature of the third sub-layer 213 are the same.

[0048] Optionally, the difference between the growth temperature of the second sublayer 212 and the growth temperature of the first sublayer 211 is 200°C to 400°C, and the difference between the growth temperature of the second sublayer 212 and the growth temperature of the third sublayer 213 is 200°C to 400°C.

[0049] If the difference between the growth temperature of the second sublayer 212 and the growth temperatures of the first sublayer 211 and the third sublayer 213 is too small, it may be difficult to improve the compactness of the first semiconductor layer 21; if the difference between the growth temperature of the second sublayer 212 and the growth temperature of the first sublayer 211 and the third sublayer 213 is too large, the quality of the first semiconductor layer 21 may deteriorate. When the difference between the growth temperature of the second sublayer 212 and the growth temperature of the first sublayer 211 and the third sublayer 213 is within this range, the compactness of the first semiconductor layer 21 can be improved while ensuring the good quality of the first semiconductor layer 21, the reaction rate of the first semiconductor layer 21 during chemical etching can be reduced, and the probability of uneven etching can be reduced.

[0050] For example, the difference between the growth temperature of the second sub-layer 212 and the growth temperature of the first sub-layer 211 may be 200° C., 300° C., 400° C., or the like.

[0051] For example, the difference between the growth temperature of the second sub-layer 212 and the growth temperature of the third sub-layer 213 may be 200° C., 300° C., 400° C., or the like.

[0052] Optionally, the growth temperature of the second sublayer 212 is 1400° C. to 1600° C. When the growth temperature of the second sublayer 212 is within this range, the compactness of the second sublayer 212 can be effectively improved, and the growth quality of the second sublayer 212 can be improved.

[0053] By way of example, the growth temperature of the second sub-layer 212 may be 1400° C., 1500° C., or 1600° C., etc.

[0054] Optionally, the growth temperature of the first sub-layer 211 and the third sub-layer 213 are both 1200° C. to 1400° C.

[0055] It should be noted that the temperature ranges of the first sublayer 211 , the second sublayer 212 and the third sublayer 213 have overlapping parts, and it is sufficient to ensure that the growth temperature of the second sublayer 212 is greater than the growth temperatures of the first sublayer 211 and the third sublayer 213 .

[0056] Optionally, the first sub-layer 211 has a thickness of 2.4 μm to 2.6 μm.

[0057] By way of example, the thickness of the first sub-layer 211 may be 2.4 μm, 2.5 μm, or 2.6 μm.

[0058] Optionally, the second sub-layer 212 has a thickness of 0.4 μm to 0.6 μm.

[0059] By way of example, the thickness of the second sub-layer 212 may be 0.4 μm, 0.5 μm, or 0.6 μm.

[0060] Optionally, the third sub-layer 213 has a thickness of 0.4 μm to 0.6 μm.

[0061] By way of example, the thickness of the third sub-layer 213 may be 0.4 μm, 0.5 μm, or 0.6 μm.

[0062] When the thickness of the first sublayer 211 , the second sublayer 212 , and the third sublayer 213 is within this range, the compactness of the first semiconductor layer 21 can be effectively improved, and the quality of the first semiconductor layer 21 can be ensured to be good.

[0063] Optionally, the first semiconductor layer 21 may be an N-type GaN layer, and the second semiconductor layer 23 may be a P-type GaN layer.

[0064] Exemplarily, the first semiconductor layer 21 is a Si-doped GaN layer, and the second semiconductor layer 23 is a Mg-doped GaN layer.

[0065] Optionally, the light-emitting layer 22 is a multi-quantum well layer, including multiple pairs of InGaN layers and GaN layers stacked alternately. Different materials can be selected for the light-emitting layer 22 according to the different light-emitting wavelength ranges of the LED. For example, the light-emitting layer 22 of the blue-green LED can use multiple pairs of InGaN layers and GaN layers stacked alternately; the light-emitting layer 22 of the red LED can use multiple pairs of AlGaInP quantum barrier layers and AlGaInP quantum well layers stacked alternately, wherein the Al component content of the AlGaInP quantum barrier layer is greater than the Al component content of the AlGaInP quantum well layer.

[0066] Exemplarily, the light emitting layer 22 includes 3 to 8 pairs of InGaN layers and GaN layers stacked alternately, for example, 5 pairs of InGaN layers and GaN layers stacked alternately, and of course other pairs are also possible, which is not limited in the present disclosure.

[0067] Optionally, before growing the first semiconductor layer 21 , a buffer layer may be formed on the substrate 10 .

[0068] Optionally, the buffer layer may be a GaN buffer layer or an AlN buffer layer.

[0069] In step S2002, a plurality of mesas extending from a surface of the second semiconductor layer away from the light emitting layer toward the first semiconductor layer are formed in the epitaxial stack.

[0070] Illustratively, a photoresist structure can be obtained on the surface of the second semiconductor layer away from the light-emitting layer by processes such as photoresist coating, exposure, and development, and the surface of the second semiconductor layer away from the light-emitting layer can be etched using the photoresist structure as a mask by inductively coupled plasma (ICP) etching and other methods. The etching depth extends from the surface of the second semiconductor layer away from the light-emitting layer to the first semiconductor layer. After removing the photoresist structure, multiple mesas (MESA) exposing the first semiconductor layer are formed.

[0071] In step S2003 , a transparent conductive layer is formed on the second semiconductor layer.

[0072] like Figure 4 As shown, the transparent conductive layer 30 is located on the surface of the second semiconductor layer 23 away from the light emitting layer 22 .

[0073] Optionally, the transparent conductive layer 30 may be an indium tin oxide (ITO) layer. ITO has good transmittance and low resistivity, so it can ensure the light emitting effect of the LED, and also facilitate carrier conduction and improve carrier injection efficiency.

[0074] Exemplarily, an initial ITO layer can be deposited on the entire surface of the second semiconductor layer 23, and a photoresist structure can be obtained on the initial ITO layer through processes such as photoresist coating, exposure, and development. The initial ITO layer is etched by ITO etching solution using the photoresist structure as a mask, and a transparent conductive layer 30 is formed after removing the photoresist structure.

[0075] In step S2004, the epitaxial stack is etched to form a plurality of light emitting structures arranged in an array.

[0076] like Figure 4 As shown, each light emitting structure 20 has a mesa 24 .

[0077] Optionally, ICP etching can be used to perform deep etching (isolation, ISO) on the epitaxial stack from the surface of the second semiconductor layer away from the light-emitting layer to form a plurality of light-emitting structures arranged in an array. Figure 3 As shown, a plurality of light emitting structures 20 are located in the central area 10 a and the first annular area 10 b , and cutting paths 201 are formed between adjacent light emitting structures 20 .

[0078] Exemplarily, the plurality of light emitting structures 20 are arranged in an array along row and column directions, and the row direction is parallel to the flat side of the substrate 10 .

[0079] Optionally, the ratio of the width W of the first annular region 10b to the center distance D of two adjacent light emitting structures 20 is 3 to 5. Here, the width W of the first annular region 10b is the width in any arrangement direction of the light emitting structures 20, and the center distance D of two adjacent light emitting structures 20 is the distance between the center points of the two adjacent light emitting structures 20 in the same direction as the width W.

[0080] like Figure 3 As shown, the width W is the width of the first annular region 10b in the row direction, and the center distance D is the distance between the center points of two adjacent light-emitting structures 20 in the row direction. If the ratio of the width W of the first annular region 10b to the center distance D of the two adjacent light-emitting structures 20 is too small, the etching load effect may have a greater impact on the etching uniformity of the light-emitting structure 20 in the central region 10a; if the ratio of the width W of the first annular region 10b to the center distance D of the two adjacent light-emitting structures 20 is too large, too many light-emitting structures 20 will be removed in the subsequent process, resulting in a waste of materials and an increase in production costs.

[0081] The ratio of the width W of the first annular region 10b to the center distance D of two adjacent light-emitting structures 20 is within this range, which is conducive to removing the light-emitting structure 20 that is greatly affected by the etching load effect in the first annular region 10b at the edge of the substrate 10 in the subsequent steps, thereby effectively improving the etching uniformity of the LED, improving the uniformity of the light-emitting effect of the LED, and reducing material waste.

[0082] For example, the ratio of the width W of the first annular region 10 b to the center distance D between two adjacent light emitting structures 20 may be 3, 4, 5, or the like.

[0083] Optionally, the width W of the first annular region 10b is 30 μm to 150 μm. In this way, the light emitting structure 20 in the first annular region 10b is the light emitting structure 20 that is greatly affected by the etching load effect, and the etching depth is greatly different from that of the light emitting structure 20 in the central region 10a, and the number of light emitting structures 20 that are less affected by the etching load effect to be removed in subsequent steps is reduced. Thus, while reducing production costs, the etching uniformity of the LED is effectively improved.

[0084] Exemplarily, the width W of the first annular region 10 b may be 30 μm to 50 μm. For example, the width W of the first annular region 10 b may be 30 μm, 40 μm, or 50 μm.

[0085] like Figure 3 As shown, the substrate 10 further has a second annular region 10c, which is located at the periphery of the first annular region 10b and connected to the first annular region 10b.

[0086] In the embodiment of the present disclosure, the epitaxial stack located in the second annular region 10 c is not patterned.

[0087] In step S2005 , the light-emitting structure in the first annular region is removed.

[0088] Figure 6 FIG. 1 is a top view of an LED manufacturing process provided by an embodiment of the present disclosure. Figure 3 and Figure 6 As shown, the light emitting structure 20 in the first annular region 10 b may be removed by an etching process, and only the light emitting structure 20 in the central region 10 a is retained.

[0089] In the related art, the light-emitting structure on the substrate is not divided into regions. After the epitaxial stack is formed on the substrate, the light-emitting structure obtained by etching the epitaxial stack in the rectangular region at the center of the substrate is used to make LEDs. That is, in the related art, the substrate is only divided into a central region where the epitaxial stack is patterned, and an edge region where the epitaxial stack is not patterned. This will cause the etching depth of the light-emitting structure in the edge region to be greater than the etching depth of the light-emitting structure in the central region, thereby affecting the etching uniformity of the LED.

[0090] In the embodiment of the present disclosure, the light emitting structure 20 in the first annular region 10b is removed after the light emitting structure 20 is formed. This not only removes the light emitting structure 20 in the first annular region 10b that is unevenly etched due to the etching load effect, thereby improving the etching uniformity of the LED, but also reduces the waste of materials caused by forming film layers such as electrodes on the unevenly etched light emitting structure 20 in subsequent steps, which is beneficial to reducing production costs.

[0091] In step S2006, first connecting electrodes are formed on the mesas of each light emitting structure.

[0092] like Figure 4 As shown, a photoresist structure can be obtained on the surface of the product obtained in step S2005 through processes such as photoresist coating, exposure, and development. A connecting electrode layer is formed by using the photoresist structure as a mask through an electron beam evaporation process and a stripping process. The connecting electrode layer includes a first connecting electrode 40, which is located on the table 24 and connected to the first semiconductor layer 21.

[0093] Optionally, the connection electrode layer further includes a second connection electrode 41, the second connection electrode 41 is insulated from the first connection electrode 40, and the second connection electrode 41 is located on a surface of the transparent conductive layer 30 away from the light emitting structure 20 and connected to the transparent conductive layer 30. This facilitates the subsequently formed pad electrode layer to form a reliable electrical connection with the light emitting structure 20 through the connection electrode layer, and helps improve the carrier injection efficiency.

[0094] In other embodiments, the connection electrode layer may include only the first connection electrode 40 , and the subsequent pad electrode layer may be electrically connected to the light emitting structure 20 through the first connection electrode 40 and the transparent conductive layer 30 , which is not limited in the present disclosure.

[0095] Optionally, the material of the connection electrode layer includes a Cr layer, and the Cr layer is located on the surface of the connection electrode layer closest to the light emitting structure 20. That is, the Cr layer of the first connection electrode 40 is connected to the first semiconductor layer 21, and the Cr layer of the second connection electrode 41 is connected to the transparent conductive layer 30. The Cr layer has high adhesion, which can make the connection electrode layer stably connected, reduce the probability of the connection electrode layer falling off, and improve the reliability of the LED.

[0096] Optionally, the thickness of the Cr layer is less than or equal to 100 angstroms. In this way, the absorption of light by the Cr layer in the connecting electrode layer can be reduced, ensuring a high luminous efficiency of the LED.

[0097] For example, the thickness of Cr may be 50 angstroms, 70 angstroms, 90 angstroms, etc.

[0098] In step S2007 , a first passivation layer is formed on the connection electrode layer.

[0099] like Figure 4 As shown, the first passivation layer 50 covers the connection electrode layer and the transparent conductive layer 30, and the first passivation layer 50 has a first through hole 51 exposing the first connection electrode 40 and a second through hole 52 exposing the second connection electrode 41. Here, covering means covering both the surface of the film layer and the side wall of the film layer. Figure 4The first passivation layer 50 covers both the surface of the connecting electrode layer away from the light emitting structure 20 and the surface of the transparent conductive layer 30, and also covers the side walls of the connecting electrode layer and the side walls of the transparent conductive layer 30, that is, the first passivation layer 50 covers the first connecting electrode 40, the second connecting electrode 41 and the transparent conductive layer 30 below.

[0100] Optionally, the first passivation layer 50 may be a distributed Bragg reflection (DBR) layer. The DBR layer has a high reflectivity to light, which can reduce the absorption of light by the first passivation layer 50, thereby improving the light extraction efficiency of the LED.

[0101] Exemplarily, the DBR layer includes a plurality of SiO 2 Layers and multiple TiO 2 The number of cycles of the DBR layer may be 20 to 50. For example, the DBR layer may include 30 SiO layers alternately stacked periodically. 2 layer and 30 TiO 2 In addition, DBR can also play a passivation role, protecting the exposed surfaces of the LED, reducing the impact of mechanical damage or chemical corrosion on the LED, and ensuring the reliability of the LED.

[0102] In other embodiments, the first passivation layer 50 may be SiO 2 Layer, Al 2 O 3 At least one of a Si layer, a SiN layer or a SiON layer. These materials have good protection and can better protect the LED, and these materials have good light transmittance and can reduce the light absorption effect of the first passivation layer 50 and improve the light extraction efficiency of the LED.

[0103] By way of example, the thickness of the first passivation layer 50 may be 30,000 angstroms.

[0104] Exemplarily, an initial first passivation layer can be deposited on the entire surface of the connecting electrode layer, and a photoresist structure can be obtained on the initial first passivation layer through processes such as photoresist coating, exposure, and development. The initial first passivation layer is etched using the photoresist structure as a mask through a buffered oxide etching (BOE) process or an ICP etching method, and the first passivation layer 50 is formed after removing the photoresist structure.

[0105] In step S2008 , a pad electrode layer is formed on the first passivation layer.

[0106] like Figure 4As shown, the pad electrode layer is located on the surface of the first passivation layer 50 away from the light emitting structure 20, and the pad electrode layer includes a first pad electrode 60 and a second pad electrode 61. The first pad electrode 60 is connected to the first connection electrode 40 through the first through hole 51, and the second pad electrode 61 is connected to the second connection electrode 41 through the second through hole 52.

[0107] Optionally, the material of the pad electrode layer includes a first Ti layer, a first Al layer, a second Ti layer, a second Al layer, a third Ti layer and an Au layer stacked in sequence in a direction away from the connecting electrode layer. In this way, the pad electrode layer can be guaranteed to have good adhesion and conductivity, which is not only conducive to the stable connection between the pad electrode layer and the connecting electrode layer, but also reduces the probability of the pad electrode layer falling off, improves the reliability of the LED, and is also conducive to carrier injection.

[0108] Exemplarily, the thickness of the first Ti layer and the second Ti layer is 100 angstroms to 300 angstroms. For example, the thickness of the first Ti layer and the second Ti layer may both be 200 angstroms.

[0109] Exemplarily, the thickness of the first Al layer and the second Al layer is 9000 angstroms to 11000 angstroms. For example, the thickness of the first Al layer and the second Al layer may both be 10000 angstroms.

[0110] Illustratively, the thickness of the third Ti layer is 500 angstroms to 1500 angstroms. For example, the thickness of the third Ti layer may be 1000 angstroms.

[0111] Exemplarily, the thickness of the Au layer is 9000 angstroms to 11000 angstroms. For example, the thickness of the Au layer may be 10000 angstroms.

[0112] For example, a photoresist structure may be obtained on the first passivation layer 50 through processes such as photoresist coating, exposure, and development, and the pad electrode layer may be formed through an electron beam evaporation process and a stripping process using the photoresist structure as a mask.

[0113] In step S2009 , a second passivation layer is formed on the first passivation layer.

[0114] like Figure 4 As shown, the second passivation layer 70 covers the light emitting structure 20 and the first passivation layer 50 , and the second passivation layer 70 has a through hole exposing the first pad electrode 60 and the second pad electrode 61 .

[0115] Optionally, the second passivation layer 70 may be SiO 2 Layer, Al 2 O 3 At least one of a SiN layer, a SiON layer, or a SiO2 layer.

[0116] Exemplarily, an initial second passivation layer can be deposited on the entire surface of the first passivation layer 50, and a photoresist structure can be obtained on the initial second passivation layer through processes such as photoresist coating, exposure, and development. The initial second passivation layer is etched using the photoresist structure as a mask through a BOE process or an ICP etching method, and the second passivation layer 70 is formed after removing the photoresist structure.

[0117] Optionally, after step S2009 , the substrate 10 may be polished and thinned.

[0118] In step S2010, the substrate is cleaved along the dicing lines to obtain a plurality of light emitting diodes.

[0119] like Figure 4 As shown, the substrate 10 can be cleaved along the dicing lines by a cleaving process to cleave the substrate 10 into a plurality of first substrates 11 to obtain a plurality of LEDs.

[0120] The present disclosure also provides an LED, which uses Figure 1 or Figure 2 Prepared by the preparation method in.

[0121] Optionally, the structure, material and thickness of the LED refer to Figures 1 to 6 The detailed description of the related embodiments is omitted here.

[0122] The above description does not limit the present disclosure in any form. Although the present disclosure has been disclosed as above through the embodiments, it is not used to limit the present disclosure. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure still falls within the scope of the technical solution of the present disclosure.

Claims

1. A method for preparing a light emitting diode, characterized in that: include: An epitaxial stack is formed on a substrate (10), wherein the substrate (10) has a connected central region and a first annular region, wherein the first annular region is located at the periphery of the central region; Etching the epitaxial stack to form a plurality of light-emitting structures (20) arranged in an array, wherein the plurality of light-emitting structures (20) are located in the central area and the first annular area, and a cutting path (201) is formed between adjacent light-emitting structures (20); removing the light-emitting structure (20) in the first annular region; The substrate (10) is cut along the cutting path (201) to obtain a plurality of the light-emitting diodes.

2. The preparation method according to claim 1, characterized in that: The ratio of the width of the first annular area to the center distance between two adjacent light-emitting structures (20) is 3 to 5.

3. The preparation method according to claim 2, characterized in that: The width of the first annular region is 30 μm to 150 μm.

4. The preparation method according to claim 1, characterized in that: The epitaxial stack comprises a first semiconductor layer (21), a light-emitting layer (22) and a second semiconductor layer (23) which are stacked in sequence, the first semiconductor layer (21) comprises a first sublayer (211), a second sublayer (212) and a third sublayer (213) which are stacked in sequence in a direction away from the substrate (10), and the growth temperature of the second sublayer (212) is greater than the growth temperature of the first sublayer (211) and the growth temperature of the third sublayer (213).

5. The preparation method according to claim 4, characterized in that: The difference between the growth temperature of the second sublayer (212) and the growth temperature of the first sublayer (211) is 200°C to 400°C, and the difference between the growth temperature of the second sublayer (212) and the growth temperature of the third sublayer (213) is 200°C to 400°C.

6. The preparation method according to claim 5, characterized in that: The growth temperature of the second sub-layer (212) is 1400°C to 1600°C.

7. The preparation method according to any one of claims 4 to 6, characterized in that: The thickness of the first sublayer (211) is 2.4 μm to 2.6 μm, the thickness of the second sublayer (212) is 0.4 μm to 0.6 μm, and the thickness of the third sublayer (213) is 0.4 μm to 0.6 μm.

8. The preparation method according to any one of claims 1 to 6, characterized in that: Before etching the epitaxial stack, the method further comprises: A transparent conductive layer (30) is formed on the second semiconductor layer (23).

9. The preparation method according to any one of claims 4 to 6, characterized in that: Each of the light emitting structures (20) has a mesa (24) extending from a surface of the second semiconductor layer (23) away from the light emitting layer (22) toward the first semiconductor layer (21), and after removing the light emitting structure (20) in the first annular region, the method further comprises: A first connecting electrode (40) is formed on each of the mesas (24) of the light-emitting structures (20).

10. A light emitting diode, characterized in that: The light emitting diode is prepared by the preparation method according to any one of claims 1 to 9.

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