Light-emitting element array, display device, and method for manufacturing display device

Abstract

A light emitting element array, a display device, and a method of manufacturing the display device are provided. The light emitting element array includes: a base substrate; a plurality of light-emitting elements, each of which includes a light-emitting element rod including a third semiconductor layer, a second semiconductor layer, a light-emitting layer, and a first semiconductor layer sequentially stacked on the base substrate, and an insulating layer surrounding the light-emitting element rod; and a connection electrode disposed on the first semiconductor layer of each of the plurality of light emitting elements, in which a length of the connection electrode in the horizontal direction is greater than a length of the light emitting element in the horizontal direction, and the connection electrode surrounds a side surface of the first semiconductor layer and a side surface of the light emitting layer.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0089828 filed in the Korean Intellectual Property Office on July 11, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The embodiments relate to a light emitting element array, a display device, and a method of manufacturing the display device. Background Art

[0003] Light emitting diodes (LEDs) are characterized by their low power consumption and environmental friendliness. These advantages have led to growing industrial demand. Light emitting elements are used not only in lighting devices or LCD backlights, but also in light emitting element display devices. For example, display devices using micro-unit light emitting elements are being developed. When manufacturing a micro-light emitting element display device, the micro-light emitting element needs to be transferred to a substrate. Summary of the invention

[0004] Aspects and features of the embodiments provide a method of depositing a connection electrode of a light emitting element without a patterning process using a photomask, a light emitting element array formed by the method, and a display device.

[0005] However, aspects of the disclosure are not limited to the aspects set forth herein. The above and other aspects of the disclosure will become more apparent to those skilled in the art to which the disclosure pertains by referring to the detailed description of the disclosure given below.

[0006] According to an embodiment, a light emitting element array may include: a base substrate; a plurality of light emitting elements, each of the plurality of light emitting elements including a light emitting element rod including a third semiconductor layer, a second semiconductor layer, a light emitting layer and a first semiconductor layer sequentially stacked on the base substrate, and an insulating layer surrounding the light emitting element rod; and a connecting electrode disposed on the first semiconductor layer of each of the plurality of light emitting elements, wherein a length of the connecting electrode in a horizontal direction may be greater than a length of the light emitting element in a horizontal direction, and the connecting electrode may surround a side surface of the first semiconductor layer and a side surface of the light emitting layer.

[0007] The connection electrode may include a first portion disposed on the first semiconductor layer and a second portion disposed on a side surface of the light emitting element bar, and the first portion of the connection electrode may protrude upward.

[0008] The length of the second portion of the connection electrode in the horizontal direction may be changed according to the height of the second portion.

[0009] A length of the second portion of the connection electrode in the horizontal direction may be substantially constant according to a height of the second portion.

[0010] The connection electrode may include a first portion disposed on the first semiconductor layer and a second portion disposed on a side surface of the light emitting element bar, the first portion of the connection electrode may have a flat upper surface, and a length of the second portion of the connection electrode in a horizontal direction may vary according to a height of the second portion.

[0011] The connection electrode may include a first portion disposed on the first semiconductor layer and a second portion disposed on a side surface of the light emitting element bar, the first portion of the connection electrode may have a flat upper surface, and a length of the second portion of the connection electrode in a horizontal direction may be substantially constant according to a height of the second portion.

[0012] Each of the plurality of light emitting elements may have at least one of a circular shape, a hexagonal shape, and a rectangular shape in a plan view.

[0013] According to an embodiment, a display device may include: a substrate including a pixel electrode; a plurality of light emitting elements, each of the plurality of light emitting elements including a light emitting element rod including a first semiconductor layer, a light emitting layer, and a second semiconductor layer sequentially stacked on the pixel electrode of the substrate, and an insulating layer surrounding the light emitting element rod; a connecting electrode disposed between the pixel electrode and the plurality of light emitting elements; and a common electrode disposed on the plurality of light emitting elements, wherein a length of the connecting electrode in a horizontal direction is greater than a length of the light emitting element in a horizontal direction, and the connecting electrode may surround a side surface of the first semiconductor layer and a side surface of the light emitting layer.

[0014] The connection electrode may include a first portion disposed on the first semiconductor layer and a second portion disposed on a side surface of the light emitting element bar, and a length of the second portion of the connection electrode in a horizontal direction may be changed according to a height of the second portion.

[0015] The connection electrode may include a first portion disposed on the first semiconductor layer and a second portion disposed on a side surface of the light emitting element bar, and a length of the second portion of the connection electrode in a horizontal direction may be substantially constant according to a height of the second portion.

[0016] Each of the plurality of light emitting elements may have at least one of a circular shape, a hexagonal shape, and a rectangular shape in a plan view.

[0017] The connection electrode may include at least one of gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and titanium (Ti).

[0018] According to an embodiment, a method for manufacturing a light emitting element may include the following steps: forming a light emitting element bar including a third semiconductor layer, a second semiconductor layer, a light emitting layer, and a first semiconductor layer sequentially stacked on a base substrate; forming an insulating layer surrounding the light emitting element bar; and forming a connecting electrode having a length greater than a length of the light emitting element in a horizontal direction and surrounding a portion of a side surface of the base substrate on which the light emitting element bar is formed.

[0019] The step of forming the connection electrode may be performed by at least one of an electron beam evaporation method, a sputtering method, and a molecular beam epitaxy (MBE) method.

[0020] The connection electrode may surround a side surface of the first semiconductor layer and a side surface of the light emitting layer.

[0021] The method may further include the steps of aligning a light emitting element having a connection electrode formed thereon on a substrate having a pixel electrode formed thereon; bonding the connection electrode to the pixel electrode; removing the base substrate and the third semiconductor layer; and forming a common electrode on the light emitting element.

[0022] The connection electrode may include a first portion disposed on the first semiconductor layer and a second portion disposed on a side surface of the light emitting element bar, and a length of the second portion in a horizontal direction may be changed according to a height of the second portion.

[0023] The connection electrode may include a first portion disposed on the first semiconductor layer and a second portion disposed on a side surface of the light emitting element bar, and a length of the second portion of the connection electrode in a horizontal direction may be substantially constant according to a height of the second portion.

[0024] The light emitting element may have at least one of a circular shape, a hexagonal shape, and a rectangular shape in a plan view.

[0025] The connection electrode may include at least one of gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and titanium (Ti).

[0026] The display device according to the embodiment can improve the exposure point.

[0027] In addition, light emission efficiency can be improved by forming a connection electrode around the light emitting layer of the light emitting element.

[0028] However, the disclosed effects are not limited to the above-mentioned effects, and various other effects are included in the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a diagram showing an exposure method used in a manufacturing process of a light emitting element array.

[0030] Figure 2 1 is a schematic plan view showing a superposition region of an exposure region in a manufacturing process of a light emitting element array.

[0031] Figure 3 is a schematic plan view of a light emitting element array according to the embodiment.

[0032] Figure 4 is a schematic plan view of a light emitting element array according to another embodiment.

[0033] Figure 5 is a schematic plan view of a light emitting element array according to another embodiment.

[0034] Figure 6 According to the embodiment along Figure 3 A schematic cross-sectional view taken along line AA'.

[0035] Figures 7 to 9 According to another embodiment, Figure 3 A schematic cross-sectional view taken along line AA'.

[0036] Fig.10 is a schematic plan view of a display device according to an embodiment.

[0037] Fig.11 is a schematic layout diagram of a display substrate circuit of a display device according to an embodiment.

[0038] Fig.12 is a schematic diagram of an equivalent circuit of a pixel of a display device according to an embodiment.

[0039] Fig.13 is a schematic diagram of an equivalent circuit of a pixel of a display device according to another embodiment.

[0040] Fig.14 is a schematic diagram of an equivalent circuit of a pixel of a display device according to another embodiment.

[0041] Fig.15 is a schematic cross-sectional view of a display device according to an embodiment.

[0042] Fig.16 According to the embodiment Fig.15 An enlarged schematic diagram of region B is shown in FIG.

[0043] Fig.17 is a schematic plan view showing a light emitting area of ​​a display device.

[0044] Fig.18 According to another embodiment Fig.15 An enlarged schematic diagram of region B is shown in FIG.

[0045] Fig.19 is a graph showing reflectivity of a connection electrode according to an embodiment.

[0046] Fig. 20 This is a SEM photograph of the light-emitting element according to the example, taken with a scanning electron microscope.

[0047] Fig.21 is a flowchart showing steps of a method of manufacturing a display device according to an embodiment.

[0048] Fig. 22 , Fig.23 , Fig.24 , Fig.25 , Fig.26 , Fig. 27 , Fig.28 and Fig.29 It is shown Fig.21 Diagram of the steps.

[0049] Fig.30 2 is a diagram schematically showing an example of a virtual reality device including a display device according to an embodiment.

[0050] Fig.31 is an exemplary diagram schematically illustrating a smart device including a display device according to an embodiment.

[0051] Fig.32 is a diagram schematically showing an example of a vehicle including a display device according to an embodiment.

[0052] Fig.33 is a diagram schematically showing an example of a transparent display device including a display device according to an embodiment. DETAILED DESCRIPTION

[0053] Embodiments will now be described more fully below with reference to the accompanying drawings. However, embodiments may be provided in different forms and should not be construed as limiting. Throughout the disclosure, the same reference numerals represent the same components. In the accompanying drawings, the thickness of layers and regions may be exaggerated for clarity.

[0054] In order to describe the disclosed embodiments, some of the parts (components) that are not related to the description may not be provided.

[0055] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Conversely, when an element is referred to as being “directly on” another element, there may be no intervening elements present.

[0056] In addition, the phrase "in a plan view" means when viewing the object portion from above, and the phrase "in a cross-sectional view" means when viewing a schematic cross-section taken by vertically cutting the object portion from the side. The term "overlapping with..." or "overlapping" means that the first object can be above or below or on the side of the second object, and vice versa. In addition, the term "overlapping with..." can include stacking, stacking, facing or facing, extending on..., covering or partially covering, or any other suitable term as will be appreciated and understood by a person of ordinary skill in the art. The expression "not overlapping with..." can include meanings such as "separated from..." or "offset from..." or "offset from..." and any other suitable equivalents as will be appreciated and understood by a person of ordinary skill in the art. The terms "facing" and "facing" can mean that the first object can be directly or indirectly opposite to the second object. In the case where a third object is placed between the first object and the second object, although the first object and the second object still face each other, the first object and the second object can be understood to be indirectly opposite to each other.

[0057] For ease of description, spatially relative terms "below", "under", "lower", "above", "on", etc. may be used herein to describe the relationship between one element or assembly and another element or assembly as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, the spatially relative terms are intended to also encompass different orientations of the device in use or in operation. For example, in a case where the device shown in the drawings is flipped, a device positioned "below" or "below" another device may be placed "above" the other device. Thus, the schematic term "below" may include both a lower position and an upper position. The device may also be oriented in other directions, and thus the spatially relative terms may be interpreted differently depending on the orientation.

[0058] When an element is referred to as being "connected" or "coupled" to another element, the element may be "directly connected" or "directly coupled" to the other element, or "indirectly connected" or "indirectly coupled" to the other element with one or more intervening elements interposed therebetween. It will also be understood that when the terms "comprises," "having," "including," and / or variations thereof are used, they may indicate the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0059] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, these elements should not be limited by these terms. To facilitate description and explanation thereof, these terms are used to distinguish one element from another. For example, when discussing a "first element" in the description, it may be named "second element" or "third element," and the "second element" and "third element" may be named in a similar manner without departing from the teachings herein.

[0060] As used herein, the terms "about" or "approximately" are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and errors associated with the measurement of the particular quantity (e.g., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0061] In the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or" for the purpose of its meaning and interpretation. For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunction or a disjunction sense and may be understood to be equivalent to "and / or". In the specification and claims, the phrase "at least one of..." is intended to include the meaning of "at least one of the group selected from..." for the purpose of its meaning and interpretation. For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0062] Unless otherwise defined or implied, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined in the specification.

[0063] When manufacturing the light emitting element, a connection electrode to be described later may be formed by a mask process.

[0064] The mask process may include the following processes.

[0065] First, a metal film may be deposited on the entire surface of a substrate by chemical vapor deposition (CVD) or sputtering to form a deposited film.

[0066] Then, the surface of the deposited film formed on the substrate may be cleaned, a photoresist may be coated, and a specific pattern shape may be formed through an exposure and development process using a mask.

[0067] Then, using the patterned photoresist film as a mask, the deposited film can be etched to form a specific pattern, and then the patterned photoresist film can be removed to complete the mask process.

[0068] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0069] Figure 1 This is a diagram showing an exposure method used in a manufacturing process of a light emitting element array. Figure 2 1 is a schematic plan view showing overlapping regions of shot regions in a manufacturing process of a light emitting element array.

[0070] In an embodiment, the connection electrode BOL of the light emitting element LE may be formed by performing a mask process.

[0071] For example, the mask process may be performed by depositing a mask on a substrate, applying a photoresist film, and performing an exposure process according to a pattern of the mask. At this time, due to the disadvantage that the manufacturing cost increases as the exposure lens becomes larger, the mask process will not be completed in a single exposure. Therefore, a partitioned exposure may be performed.

[0072] In the embodiments, the entire surface of the substrate to be exposed is referred to as a field, and a specific region where a specific pattern is transferred using one exposure through a reticle is referred to as an exposure region.

[0073] Reference Figure 1 , the field FLE may require exposure areas EXA1, EXA2, EXA3, EXA4, EXA5, and EXA6. The mask MK may include a pattern MP. The size of the mask MK may be the same as the size of the exposure area.

[0074] Reference Figure 2, a first exposure may be performed on a first exposure area EXA1 on the left side of a field FLE having a specific width, and then a second exposure may be performed on a second exposure area EXA2 adjacent to the first exposure area EXA1. In the case where the mask MK (e.g., MK1 and MK2) repeatedly exposes the field FLE, an overlapping area OVA may appear where adjacent exposure areas EXA1 and EXA2 overlap each other. For example, the mask MK (e.g., MK1 and MK2) may be a negative photoresist mask. For example, the photoresist may be a chemical substance whose properties change in response to light (e.g., photosensitization). The negative photoresist may be characterized by dissolving unilluminated areas. Therefore, the mask MK (e.g., MK1 and MK2) for the negative photoresist may block light in a portion where the pattern MP (e.g., MP1-1 and MP1-2) is to be formed.

[0075] An abnormal pattern MP1 - 2 having a size different from that of the normal pattern MP1 - 1 may appear in the overlap area OVA.

[0076] For example, abnormal patterns MP1-2 may be generated in the case where exposures are not precisely aligned due to distortions such as transfer, rotation, twist, etc. For example, discontinuity between two exposures may cause a stitch defect on the screen of a corresponding display device.

[0077] Therefore, in the embodiment, a photoresist patterning method using the mask MK may not be employed in the manufacturing process of the light emitting element array, and a front deposition method may be used.

[0078] Figure 3 is a schematic plan view of a light emitting element array according to the embodiment. Figure 4 is a schematic plan view of a light emitting element array according to another embodiment. Figure 5 is a schematic plan view of a light emitting element array according to another embodiment. Figure 6 According to the embodiment along Figure 3 A schematic cross-sectional view taken along line AA'. Figures 7 to 9 According to another embodiment, Figure 3 A schematic cross-sectional view taken along line AA'.

[0079] Although the light emitting element LE according to the embodiment has been described as a micro light emitting diode display device (eg, a micro light emitting diode display device or a nano light emitting diode display device) including a micro light emitting diode (eg, a micro light emitting diode or a nano light emitting diode), the embodiment is not limited thereto.

[0080] Reference Figure 3According to an embodiment, the light emitting elements LE may be arranged on the base substrate BSUB in the first direction DR1 and the second direction DR2. The light emitting elements LE may be spaced apart from each other at equal intervals.

[0081] The base substrate BSUB may have a rectangular planar shape. However, the planar shape of the base substrate BSUB is not limited thereto, and may have a polygonal, circular, elliptical, or irregular planar shape other than a rectangular shape.

[0082] The base substrate BSUB can be a sapphire substrate (Al 2 O 3 ) or a silicon wafer including silicon. However, the embodiment is not limited thereto, and in the embodiment, a case where the base substrate BSUB is a sapphire substrate will be described as an example.

[0083] The light emitting element LE may be a vertical light emitting diode element extending longitudinally in the third direction DR3. For example, the length of the light emitting element LE in the third direction DR3 may be longer than the length (or width / diameter) of the light emitting element LE in the horizontal direction. The length (or width / diameter) in the horizontal direction refers to the length (or width / diameter) in the first direction DR1 or the length (or width / diameter) in the second direction DR2.

[0084] The light emitting element LE may have a circular planar shape. Figure 4 As shown in , the light emitting element LE may have a hexagonal planar shape, and as Figure 5 As shown in , the light emitting element LE may have a quadrilateral planar shape.

[0085] However, the embodiment is not limited thereto. For example, the light emitting element LE may have a polygonal shape such as a triangle, a quadrangle, a pentagon, a hexagon, and an octagon, an ellipse, or an irregular plane shape.

[0086] Reference Figures 3 to 5 The planar shape of the connection electrode BOL can be formed according to the planar shape of the light emitting element LE. For example, when the planar shape of the light emitting element LE is circular, the planar shape of the connection electrode BOL can also be circular, when the planar shape of the light emitting element LE is hexagonal, the planar shape of the connection electrode BOL can also be hexagonal, and when the planar shape of the light emitting element LE is square, the planar shape of the connection electrode BOL can also be square.

[0087] The connection electrode BOL may be disposed on an upper surface of the light emitting element LE.

[0088] Diameter W of the connecting electrode BOL B Can be larger than the diameter W of the light emitting element LE L .

[0089] Reference Figure 6 , the light emitting element LE may be a micro light emitting diode element. The light emitting element LE may include a third semiconductor layer USE, a second semiconductor layer SEM2, a light emitting layer MQW, a first semiconductor layer SEM1, an insulating layer INS, and a connecting electrode BOL in a thickness direction (e.g., a third direction DR3) of the base substrate BSUB. The third semiconductor layer USE, the second semiconductor layer SEM2, the light emitting layer MQW, and the first semiconductor layer SEM1 may be sequentially stacked in the third direction DR3. For ease of description, the third semiconductor layer USE, the second semiconductor layer SEM2, the light emitting layer MQW, and the first semiconductor layer SEM1 stacked in the third direction DR3 are referred to as light emitting element rods LER.

[0090] The light emitting element LE may have a cylindrical shape, a disk shape, or a rod shape whose height is longer than its diameter. However, the light emitting element LE is not limited thereto, and the light emitting element LE may have a shape such as a rod, a wire, a tube, a polygonal column shape such as a regular hexahedron, a cuboid, or a hexagonal column, or a shape extending in one direction but having a partially inclined outer surface.

[0091] The third semiconductor layer USE may be disposed on the base substrate BSUB. The third semiconductor layer USE may be undoped.

[0092] The second semiconductor layer SEM2 may be disposed on the third semiconductor layer USE. The second semiconductor layer SEM2 may be an n-type semiconductor. The second semiconductor layer SEM2 may include a semiconductor having a chemical formula of Al x Ga y In 1-x-y N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) semiconductor material. For example, the second semiconductor layer SEM2 may be any one or more of n-type doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The second semiconductor layer SEM2 may be doped with an n-type dopant, and the n-type dopant may be Si, Ge, Se, or Sn. For example, the second semiconductor layer SEM2 may be n-GaN doped with n-type Si. The thickness of the second semiconductor layer SEM2 may be in the range of about 2 μm to about 4 μm, but the embodiment is not limited thereto.

[0093] The light emitting layer MQW may emit light by recombining electron-hole pairs according to an electrical signal applied through the first and second semiconductor layers SEM1 and SEM2. The light emitting layer MQW may emit first light (eg, light in a blue band) having a central wavelength range of about 450 nm to about 495 nm.

[0094] The light emitting layer MQW may include a single quantum well structure or a multi-quantum well structure. In the case where the light emitting layer MQW includes a material having a multi-quantum well structure, it may be a stacked structure having well layers and barrier layers alternately stacked with each other. For example, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but the embodiment is not limited thereto. The thickness of each of the well layers may be about 1 nm to about 4 nm, and the thickness of the barrier layer may be about 3 nm to about 10 nm.

[0095] The light emitting layer MQW may have a structure in which a semiconductor material having a large energy band gap and a semiconductor material having a small energy band gap are alternately stacked with each other, and may include other Group 3 to Group 5 semiconductor materials according to the wavelength band of the emitted light. The light emitted from the light emitting layer MQW is not limited to the first light (e.g., light in the blue band), and in some cases, a second light (e.g., light in the green band) or a third light (e.g., light in the red band) may also be emitted. In an embodiment, in the case where the semiconductor material included in the light emitting layer MQW includes indium, the color of the emitted light may vary according to the amount of indium. For example, in the case where the content of indium is about 15%, light in the blue band may be emitted, in the case where the content of indium is about 25%, light in the green band may be emitted, and in the case where the content of indium is about 35% or more, light in the red band may be emitted.

[0096] The first semiconductor layer SEM1 may be doped with a first conductive type dopant such as Mg, Zn, Ca, Sr, or Ba. For example, the first semiconductor layer SEM1 may be p-GaN doped with p-type Mg. The first semiconductor layer SEM1 may have a thickness of about 30 nm to about 200 nm, but the embodiment is not limited thereto.

[0097] In another embodiment, a superlattice layer may be disposed between the second semiconductor layer SEM2 and the light emitting layer MQW. The superlattice layer may be a layer that relieves stress between the second semiconductor layer SEM2 and the light emitting layer MQW. For example, the superlattice layer may be formed of InGaN or GaN. The thickness of the superlattice layer may be about 50 nm to about 200 nm. In another example, the superlattice layer may be omitted.

[0098] In another embodiment, an electron blocking layer may be further provided between the first semiconductor layer SEM1 and the light emitting layer MQW. The electron blocking layer may be a layer for suppressing or preventing excessive electrons from flowing into the light emitting layer MQW. For example, the electron blocking layer may be p-AlGaN doped with p-type Mg. The thickness of the electron blocking layer may be about 10 nm to about 50 nm. In another example, the electron blocking layer may be omitted.

[0099] The insulating layer INS may surround the side surface (eg, the outer peripheral surface) of the light emitting element rod LER. The insulating layer INS may surround the light emitting element rod LER.

[0100] The insulating layer INS may insulate the light emitting element LE from the outside. The insulating layer INS may be disposed (e.g., directly disposed) on the outer peripheral surfaces of the third semiconductor layer USE, the second semiconductor layer SEM2, the light emitting layer MQW, and the first semiconductor layer SEM1 to surround them. In an embodiment, the insulating layer INS may surround the entire outer peripheral surfaces of the third semiconductor layer USE, the second semiconductor layer SEM2, the light emitting layer MQW, and the first semiconductor layer SEM1.

[0101] The insulating layer INS may expose both ends (eg, opposite ends) of the light emitting element LE.

[0102] The insulating layer INS may include an inorganic insulating material (such as silicon oxide (SiO x )、Silicon Nitride(SiN x ), silicon oxynitride (SiO x N y )、Alumina(Al x O y ) or aluminum nitride (AlN). The thickness of the insulating layer INS may be about 0.1 μm, but the embodiment is not limited thereto.

[0103] The connection electrode BOL may be disposed on the light emitting element LE. In an embodiment, the connection electrode BOL may be disposed on the first semiconductor layer SEM1. The connection electrode BOL may surround side surfaces of the first semiconductor layer SEM1 and the light emitting layer MQW.

[0104] The connection electrode BOL may include a first portion BOL-1 disposed on the first semiconductor layer SEM1 and a second portion BOL-2 surrounding side surfaces of the first semiconductor layer SEM1 and the light emitting layer MQW. The first portion BOL-1 and the second portion BOL-2 may have an upwardly convex shape.

[0105] The height of the second portion BOL-2 may be in the range of about 1 μm to about 2 μm, but the embodiment is not limited thereto. The height of the second portion BOL-2 refers to the length of the light emitting element rod LER in the third direction DR3.

[0106] The thickness of the second portion BOL-2 may vary according to the height. For example, the middle portion of the second portion BOL-2 may be formed to be the thickest. In another embodiment, the second portion BOL-2 may be formed to be thinner toward the bottom.

[0107] In another embodiment, referring to Figures 7 to 9, at least a portion of the first portion BOL-1 and / or at least a portion of the second portion BOL-2 may have a flat shape. Figure 7 As shown in , the first portion BOL-1 may have a flat shape, and the second portion BOL-2 may have an upwardly convex shape. Figure 8 As shown in , the first portion BOL-1 may have an upwardly convex shape, and the second portion BOL-2 may have a flat shape. Fig. 9 As shown in , both the first portion BOL- 1 and the second portion BOL- 2 may have a flat shape.

[0108] The connection electrode BOL may include a conductive material and is used to transmit a light emitting signal from the outside (e.g., a pixel electrode) to the light emitting element LE. The connection electrode BOL may include at least one of gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and titanium (Ti). For example, the connection electrode BOL may include a 9:1 alloy, an 8:2 alloy, or a 7:3 alloy of gold and tin, or may include an alloy of copper, silver, and tin (e.g., SAC305).

[0109] Figures 6 to 9 The side surface of the light emitting element LE shown in FIG. 4 may make an angle of 90 degrees or more with a portion of the base substrate BSUB on which the light emitting element LE is not disposed.

[0110] Fig.10 is a schematic plan view of a display device according to an embodiment.

[0111] Reference Fig.10 The display device 10 according to the embodiment can be applied to various consumer electronic products or IoT devices (such as smart phones, cellular phones, tablet PCs, personal digital assistants (PDAs), portable multimedia players (PMPs), televisions, game devices, watch-type electronic devices, head-mounted displays, monitors of personal computers, laptop computers, car navigation, car dashboards, digital cameras, video cameras, external billboards, billboards, medical devices, inspection devices, refrigerators, washing machines, etc.). A television is described herein as an example of the display device 10, and the television may have a high resolution or an ultra-high resolution (such as HD, UHD, 4K, 8K, etc.).

[0112] For example, in the following drawings, the first direction DR1 refers to the horizontal direction of the display device 10, the second direction DR2 refers to the vertical direction of the display device 10, and the third direction DR3 refers to the thickness direction of the display device 10. For example, "left", "right", "top", and "bottom" refer to directions when the display device 10 is viewed from a plane. For example, "right" refers to one side of the first direction DR1, "left" refers to the other side of the first direction DR1, "top" refers to one side of the second direction DR2, and "bottom" refers to the other side of the second direction DR2. In addition, "up" refers to a first side of the third direction DR3, and "down" refers to a second side of the third direction DR3.

[0113] The display device 10 according to the embodiment may have a square shape in a plan view. In the case where the display device 10 is a television, it may have a rectangular shape with a long side arranged in a transverse direction. However, the embodiment is not limited thereto, and the long side may be arranged in a longitudinal direction, and the long side may be rotatably mounted so that the long side may be variably arranged in a horizontal direction or a vertical direction. The display device 10 may also have a circular shape or an elliptical shape.

[0114] The display device 10 may include a display area DPA and a non-display area NDA. The display area DPA may be an effective area for displaying an image. The display area DPA may have a square shape similar to the overall shape of the display device 10 in a plan view, but the embodiment is not limited thereto.

[0115] The display area DPA may include pixels PX. The pixels PX may be arranged in a matrix orientation. The shape of each pixel PX may be a rectangle or a square in a plan view, but the embodiment is not limited thereto, and may also be a rhombus shape with each side tilted toward one side of the display device 10. The pixel PX may include a plurality of color pixels PX. For example, the pixel PX may include a first color pixel PX of red, a second color pixel PX of green, and a third color pixel PX of blue, but the embodiment is not limited thereto. Each color pixel PX may be arranged in a stripe type or a pentile type (e.g., PenTile ® ) are arranged alternately.

[0116] The non-display area NDA may be disposed at the periphery of the display area DPA. The non-display area NDA may completely or partially surround (or surround) the display area DPA. The display area DPA may be in a square shape, and the non-display area NDA may be arranged adjacent to four sides of the display area DPA. The non-display area NDA may include a frame of the display device 10.

[0117] A driving circuit or a driving element for driving the display area DPA may be disposed in the non-display area NDA. Figure 1The non-display area NDA disposed adjacent to the lower side of the display device 10 may have a pad (also called a "pad" or "solder pad") portion disposed on the display substrate of the display device 10, and the external device EXD may be mounted on the pad electrode of the pad portion. Examples of the external device EXD include a connection film, a printed circuit board, a driver chip DIC, a connector, a wiring connection film, etc. Figure 1 In the non-display area NDA (a left side in the figure) adjacent to the display substrate 10, a scan driving unit SDR formed (for example, directly formed) on the display substrate of the display device 10 may be disposed.

[0118] Fig.11 is a schematic layout diagram of a display substrate circuit of a display device according to an embodiment.

[0119] Reference Fig.11 , a plurality of lines may be disposed on the substrate. The plurality of lines may include a scan line SCL, a sensing signal line SSL, a data line DTL, a reference voltage line RVL, a first power line ELVDL, and the like.

[0120] The scan line SCL and the sensing signal line SSL may extend in the first direction DR1. The scan line SCL and the sensing signal line SSL may be connected (e.g., electrically connected) to a scan driving unit SDR. The scan driving unit SDR may include a driving circuit. The scan driving unit SDR may be disposed on one side of the non-display area NDA on the display substrate, but may also be disposed on multiple sides (e.g., opposite sides) of the non-display area NDA. The scan driving unit SDR may be connected (e.g., electrically connected) to a signal connection line CWL, and at least one end of the signal connection line CWL may be connected (e.g., electrically connected) to an external device (e.g., a display device) through a pad WPD_CW formed in the non-display area NDA. Fig.10 in the .

[0121] The data line DTL and the reference voltage line RVL may extend in a second direction DR2 crossing the first direction DR1. The first power line ELVDL may include a portion extending in the second direction DR2. The first power line ELVDL may also include a portion extending in the first direction DR1. The first power line ELVDL may have a mesh structure, but the embodiment is not limited thereto.

[0122] The wiring pad WPD may be disposed at at least one end of the data line DTL, the reference voltage line RVL, and the first power line ELVDL. Each wiring pad WPD may be disposed in the pad area PDA of the non-display area NDA. In an embodiment, a wiring pad WPD_DT for the data line DTL (hereinafter referred to as a "data pad"), a wiring pad WPD_RV for the reference voltage line RVL (hereinafter referred to as a "reference voltage pad"), and a wiring pad WPD_ELVD for the first power line ELVDL (hereinafter referred to as a "first power pad") may be disposed in the pad area PDA of the non-display area NDA. In another example, the data pad WPD_DT, the reference voltage pad WPD_RV, and the first power pad WPD_ELVD may be disposed in different non-display areas NDA. As described above, Fig.10 The external device EXD in the embodiment may be mounted on the wiring pad WPD. The external device EXD may be mounted on the wiring pad WPD through an anisotropic conductive film, ultrasonic bonding, or the like.

[0123] Each pixel PX in the display area DPA may include a pixel driving circuit. The above wiring may pass through each pixel PX or around each pixel PX, and apply a driving signal to each pixel driving circuit. The pixel driving circuit may include a transistor and a capacitor. The number of transistors and capacitors in each pixel driving circuit may vary. Hereinafter, a pixel driving circuit will be described by taking a 3T1C structure including three transistors and one capacitor as an example, but the embodiment is not limited thereto, and various other modified pixel structures (such as a 2T1C structure, a 7T1C structure, and a 6T1C structure) may be applied.

[0124] Fig.12 is a schematic diagram of an equivalent circuit of a pixel of a display device according to an embodiment.

[0125] Reference Fig.12 , each pixel PX of the display device according to the embodiment may further include three transistors DTR, STR1 and STR2 and one capacitor CST for storage, in addition to the light emitting element LE.

[0126] The light emitting element LE may emit light in response to current supplied through the driving transistor DTR. The light emitting element LE may be implemented as an inorganic light emitting diode, an organic light emitting diode, a micro light emitting diode, a nano light emitting diode, or the like.

[0127] A first electrode (e.g., an anode electrode) of the light emitting element LE may be connected (e.g., electrically connected) to a source electrode of the driving transistor DTR, and a second electrode (e.g., a cathode electrode) may be connected (e.g., electrically connected) to a second power line ELVSL supplied with a low potential voltage (e.g., a second power supply voltage) lower than a high potential voltage (e.g., a first power supply voltage) of the first power line ELVDL.

[0128] The driving transistor DTR may adjust a current flowing from the first power line ELVDL supplied with the first power voltage to the light emitting element LE according to a voltage difference between the gate electrode and the source electrode. The gate electrode of the driving transistor DTR may be connected (e.g., electrically connected) to the first electrode of the first transistor STR1, the source electrode of the driving transistor DTR may be connected (e.g., electrically connected) to the first electrode of the light emitting element LE, and the drain electrode of the driving transistor DTR may be connected (e.g., electrically connected) to the first power line ELVDL to which the first power voltage is applied.

[0129] The first transistor STR1 may be turned on by a scan signal of the scan line SCL to connect (e.g., electrically connect) the data line DTL to the gate electrode of the drive transistor DTR. The gate electrode of the first transistor STR1 may be connected (e.g., electrically connected) to the scan line SCL, the first electrode of the first transistor STR1 may be connected (e.g., electrically connected) to the gate electrode of the drive transistor DTR, and the second electrode of the first transistor STR1 may be connected (e.g., electrically connected) to the data line DTL.

[0130] The second transistor STR2 may be turned on by a sensing signal of the sensing signal line SSL to connect the initialization voltage line VIL to the source electrode of the driving transistor DTR. A gate electrode of the second transistor STR2 may be connected (e.g., electrically connected) to the sensing signal line SSL, a first electrode of the second transistor STR2 may be connected (e.g., electrically connected) to the initialization voltage line VIL, and a second electrode of the second transistor STR2 may be connected (e.g., electrically connected) to the source electrode of the driving transistor DTR.

[0131] In an embodiment, a first electrode of each of the first transistor STR1 and the second transistor STR2 may be a source electrode, and a second electrode may be a drain electrode, but the embodiment is not limited thereto, and may be vice versa.

[0132] The capacitor CST may be formed between the gate electrode and the source electrode of the driving transistor DTR. The capacitor CST may store a difference voltage between the gate voltage and the source voltage of the driving transistor DTR.

[0133] The driving transistor DTR and the first and second transistors STR1 and STR2 may be formed as thin film transistors. Fig.12 The driving transistor DTR and the first and second transistors STR1 and STR2 are described as n-type MOSFETs (e.g., metal oxide semiconductor field effect transistors), but the embodiment is not limited thereto. For example, the driving transistor DTR and the first and second transistors STR1 and STR2 may be p-type MOSFETs, or some may be n-type MOSFETs and others may be p-type MOSFETs.

[0134] Fig.13 is a schematic diagram of an equivalent circuit of a pixel of a display device according to another embodiment.

[0135] Reference Fig.13 The first electrode of the light emitting element LE may be connected (eg, electrically connected) to the first electrode of the fourth transistor STR4 and the second electrode of the sixth transistor STR6, and the second electrode may be connected (eg, electrically connected) to the second power line ELVSL. A parasitic capacitor Cel may be formed between the first electrode and the second electrode of the light emitting element LE.

[0136] Each pixel PX may include a driving transistor DTR, a switching element, and a capacitor CST. The switching element includes first to sixth transistors STR1, STR2, STR3, STR4, STR5, and STR6.

[0137] For example, the first transistor STR1 may include first sub-transistors ST1-1 and ST1-2 connected in series with each other. The first transistor STR1 may be turned on by a scan signal written to the scan line GWL to connect the driving transistor DTR with a diode. The second transistor STR2 may be turned on by a scan signal written to the scan line GWL to electrically connect the data line DTL to the drain electrode of the driving transistor DTR. For example, the third transistor STR3 may include third sub-transistors ST3-1 and ST3-2 connected in series with each other. The third transistor STR3 may be turned on by an initialization signal of the initialization scan line GIL so that the gate electrode of the driving transistor DTR may be electrically connected to the initialization voltage line VIL. The fourth transistor STR4 may be turned on by a control signal of the control scan line GCL so that the light emitting element LE may be electrically connected to the initialization voltage line VIL. The fifth transistor STR5 and the sixth transistor STR6 may be turned on by an emission control signal of the emission control scan line EL so that current may flow into the light emitting element LE through the driving transistor DTR.

[0138] The driving transistor DTR may include a gate electrode, a first electrode (ie, a source electrode), and a second electrode (ie, a drain electrode). The driving transistor DTR controls a drain-source current (hereinafter, referred to as a "driving current") flowing between the first electrode and the second electrode based on a data voltage applied to the gate electrode.

[0139] The capacitor CST may be formed between the gate electrode of the driving transistor DTR and the first power line ELVDL. One electrode of the capacitor CST may be connected (eg, electrically connected) to the gate electrode of the driving transistor DTR, and the other electrode of the capacitor CST may be connected (eg, electrically connected) to the first power line ELVDL.

[0140] In the case where the first electrode of each of the first to sixth transistors STR1, STR2, STR3, STR4, STR5, and STR6 and the driving transistor DTR is a source electrode, the second electrode may be a drain electrode. In another example, in the case where the first electrode of each of the first to sixth transistors STR1, STR2, STR3, STR4, STR5, and STR6 and the driving transistor DTR is a drain electrode, the second electrode may be a source electrode.

[0141] The active layer of each of the first to sixth transistors STR1, STR2, STR3, STR4, STR5, and STR6 and the driving transistor DTR may be formed of any one of polysilicon, amorphous silicon, and an oxide semiconductor. In the case where the semiconductor layer of each of the first to sixth transistors STR1, STR2, STR3, STR4, STR5, and STR6 and the driving transistor DTR is formed of polysilicon, the process for forming it may be a low temperature polysilicon (LTPS) process.

[0142] For example, in Fig.13 , the first to sixth transistors STR1 , STR2 , STR3 , STR4 , STR5 , and STR6 and the driving transistor DTR may be described centering on p-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), but the embodiment is not limited thereto and may be formed as n-type MOSFETs.

[0143] Furthermore, a first power supply voltage of the first power supply line ELVDL, a second power supply voltage of the second power supply line ELVSL, and an initialization voltage of the initialization voltage line VIL may be set by considering characteristics of the driving transistor DTR, characteristics of the light emitting element LE, and the like.

[0144] Fig.14 is a schematic diagram of an equivalent circuit of a pixel of a display device according to another embodiment.

[0145] Fig.14 Examples and Fig.13The embodiment of FIG. 1 is different in that the driving transistor DTR, the second transistor STR2, the fourth transistor STR4, the fifth transistor STR5 and the sixth transistor STR6 are formed as p-type MOSFETs, and the first transistor STR1 and the third transistor STR3 are formed as n-type MOSFETs.

[0146] Reference Fig.14 The active layer of each of the driving transistor DTR, the second transistor STR2, the fourth transistor STR4, the fifth transistor STR5 and the sixth transistor STR6 formed as a p-type MOSFET can be formed of polysilicon, and the active layer of each of the first transistor STR1 and the third transistor STR3 formed as an n-type MOSFET can be formed of an oxide semiconductor.

[0147] Fig.14 Examples and Fig.13 The embodiment of is different in that the gate electrode of the second transistor STR2 and the gate electrode of the fourth transistor STR4 are connected (eg, electrically connected) to the write scan line GWL, and the gate electrode of the first transistor STR1 is connected (eg, electrically connected) to the control scan line GCL. Fig.14 In the embodiment, the first transistor STR1 and the third transistor STR3 can be formed as n-type MOSFETs, so that a scan signal with a gate high voltage can be applied to the control scan line GCL and the initialization scan line GIL. On the other hand, since the second transistor STR2, the fourth transistor STR4, the fifth transistor STR5, and the sixth transistor STR6 are formed as p-type MOSFETs, a scan signal with a gate low voltage can be applied to the write scan line GWL and the emission control scan line EL.

[0148] It should be noted that the schematic diagram of the equivalent circuit of the pixel according to the above-mentioned embodiment is not limited to Figure 12 to Figure 14 The schematic diagram of the equivalent circuit of the pixel according to the embodiment can be composed of Figure 12 to Figure 14 Other known circuit structures used by those skilled in the art besides the embodiments shown in FIG.

[0149] Fig.15 is a schematic cross-sectional view of a display device according to an embodiment. Fig.16 According to the embodiment Fig.15 An enlarged schematic diagram of region B is shown in FIG. Fig.17 is a schematic plan view showing a light emitting area of ​​a display device. Fig.18 According to another embodiment Fig.15 An enlarged schematic diagram of region B is shown in FIG.

[0150] Reference Fig.15, the display device 10 may include a display substrate 100 , and a wavelength control unit 200 and a color filter layer CFL disposed on the display substrate 100 .

[0151] The display substrate 100 may include a substrate 110 and a light emitting element portion LEP disposed on the substrate 110. The substrate 110 may be an insulating substrate. The substrate 110 may include a transparent material. For example, the substrate 110 may include a transparent insulating material (such as glass, quartz, etc.). The substrate 110 may be a rigid substrate. However, the substrate 110 is not limited thereto and may include plastic (such as polyimide, etc.). For example, the substrate 110 may have a flexible property to be twisted, bent, folded, or curled. The light emitting areas EA1, EA2, and EA3 and the non-light emitting area NEA may be defined on the substrate 110.

[0152] The switching elements T1, T2, and T3 may be disposed on the substrate 110. In an embodiment, the first switching element T1 may be disposed in the first light emitting area EA1 of the substrate 110, the second switching element T2 may be disposed in the second light emitting area EA2, and the third switching element T3 may be disposed in the third light emitting area EA3. However, the embodiment is not limited thereto, and in other embodiments, at least one of the first switching element T1, the second switching element T2, and the third switching element T3 may be disposed in the non-light emitting area NEA.

[0153] In an embodiment, the first switching element T1, the second switching element T2 and the third switching element T3 may each be a thin film transistor including amorphous silicon, polycrystalline silicon or an oxide semiconductor. For example, there may be a signal line (e.g., a gate line, a data line, a power line, etc.) further disposed on the substrate 110, and the signal line transmits a signal to each of the switching elements T1, T2 and T3.

[0154] Each of the switching elements T1, T2, and T3 may include a semiconductor layer 65, a gate electrode 75, a source electrode 85a, and a drain electrode 85b. For example, a buffer layer 60 may be disposed on the substrate 110. The buffer layer 60 may be disposed to cover the upper surface of the substrate 110. The buffer layer 60 may include silicon nitride, silicon oxide, or silicon oxynitride, and may be a single layer or a double layer thereof.

[0155] The semiconductor layer 65 may be disposed on the buffer layer 60. The semiconductor layer 65 may form a channel of each of the switching elements T1, T2, and T3. The semiconductor layer 65 may include amorphous silicon, polycrystalline silicon, or an oxide semiconductor. In an example, the oxide semiconductor may include, for example, a binary compound (AB) containing indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. x ), ternary compounds (AB x C y ) or quaternary compounds (ABx C y D z In an embodiment, the semiconductor layer 65 may include indium gallium zinc oxide (IGZO).

[0156] The gate insulating layer 70 may be disposed on the semiconductor layer 65. The gate insulating layer 70 may include a silicon compound, a metal oxide, etc. For example, the gate insulating layer 70 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. In an embodiment, the gate insulating layer 70 may include silicon oxide.

[0157] The gate electrode 75 may be disposed on the gate insulating layer 70. The gate electrode 75 may overlap the semiconductor layer 65. The gate electrode 75 may include a conductive material. The gate electrode 75 may include a metal oxide (such as ITO, IZO, ITZO, In 2 O 3 ) or a metal such as copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg), or nickel (Ni). For example, the gate electrode 75 may be formed of a Cu / Ti double layer in which an upper layer of copper is stacked on a lower layer of titanium, but the embodiment is not limited thereto.

[0158] The first interlayer insulating layer 80 and the second interlayer insulating layer 82 may be disposed on the gate electrode 75. The first interlayer insulating layer 80 may be disposed (e.g., directly disposed) on the gate electrode 75, and the second interlayer insulating layer 82 may be disposed (e.g., directly disposed) on the first interlayer insulating layer 80. The first interlayer insulating layer 80 and the second interlayer insulating layer 82 may each include an inorganic insulating material (such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, zinc oxide, etc.). However, the embodiment is not limited thereto, and the second interlayer insulating layer 82 may include an organic insulating material capable of flattening the step portion below.

[0159] The source electrode 85a and the drain electrode 85b may be disposed on the second interlayer insulating layer 82. The source electrode 85a and the drain electrode 85b may be connected (e.g., electrically connected) to the semiconductor layer 65 through contact holes penetrating the first interlayer insulating layer 80, the second interlayer insulating layer 82, and the gate insulating layer 70, respectively. The source electrode 85a and the drain electrode 85b may include a metal oxide (e.g., ITO, IZO, ITZO, In 2 O 3 ) or metals such as copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg), and nickel (Ni). For example, the source electrode 85a and the drain electrode 85b may be formed of a Cu / Ti double layer in which an upper layer of copper is stacked on a lower layer of titanium, but the embodiment is not limited thereto.

[0160] The first planarization layer 120 may be disposed on the first switching element T1, the second switching element T2, and the third switching element T3. The first planarization layer 120 may include an organic material. For example, the first planarization layer 120 may include an acrylic resin, an epoxy resin, an imide resin, an ester resin, etc. In an embodiment, the first planarization layer 120 may include a positive photosensitive material or a negative photosensitive material.

[0161] The pixel connection electrode 125 may be disposed on the first planarization layer 120. The pixel connection electrode 125 may be disposed to correspond to each of the first switching element T1, the second switching element T2, and the third switching element T3, and may be connected (e.g., electrically connected) to them. The pixel connection electrode 125 may connect the pixel electrodes PE1, PE2, and PE3 described later to the above-mentioned switching elements T1, T2, and T3. The pixel connection electrode 125 may contact the switching elements T1, T2, and T3 through a contact hole penetrating the first planarization layer 120.

[0162] The second planarization layer 130 may be disposed on the first planarization layer 120 and the pixel connection electrode 125. The second planarization layer 130 may planarize a lower stepped portion, and may include the same material as the first planarization layer 120 described above.

[0163] The light emitting element portion LEP may be disposed on the second planarization layer 130. The light emitting element portion LEP may include pixel electrodes PE1, PE2, and PE3, a connection electrode BOL, a light emitting element LE, and a common electrode CE. For example, the light emitting element portion LEP may further include an organic layer 140.

[0164] The pixel electrodes PE1, PE2, and PE3 may include a first pixel electrode PE1, a second pixel electrode PE2, and a third pixel electrode PE3. The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be connected (e.g., electrically connected) to the light emitting element LE through a connecting electrode BOL. The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may serve as a first electrode of the light emitting element LE, and may be an anode electrode or a cathode electrode. The pixel electrodes PE1, PE2, and PE3 may be disposed in the light emitting areas EA1, EA2, and EA3. At least a portion of the pixel electrodes PE1, PE2, and PE3 may not overlap with the non-light emitting area NEA.

[0165] Each of the pixel electrodes PE1, PE2, and PE3 may be connected (e.g., directly connected) to the pixel connection electrode 125 through a contact hole penetrating the second planarization layer 130, and may be connected (e.g., electrically connected) to each of the switching elements T1, T2, and T3 through the pixel connection electrode 125. The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may include a metal. The metal may include, for example, copper (Cu), titanium (Ti), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a mixture thereof. For example, the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may have a multilayer structure in which two or more metal layers are stacked. For example, the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may have a two-layer structure in which a copper layer is stacked on a titanium layer, but the embodiment is not limited thereto.

[0166] The light emitting element LE may be disposed on each of the first pixel electrode PE1 , the second pixel electrode PE2 , and the third pixel electrode PE3 .

[0167] Reference Fig.16 , the light emitting element LE may be arranged so that the first semiconductor layer SEM1 faces the first pixel electrode PE1. The connecting electrode BOL may be further arranged between the light emitting element LE and the first pixel electrode PE1. The connecting electrode BOL may be used to transmit the light emitting signal from the first pixel electrode PE1 to the light emitting element LE. The connecting electrode BOL may be arranged at the lowermost end of the light emitting element LE, and may be arranged farther from the light emitting layer MQW than the first semiconductor layer SEM1. The connecting electrode BOL may include at least one of gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and titanium (Ti). For example, the connecting electrode BOL may include a 9:1 alloy, an 8:2 alloy, or a 7:3 alloy of gold and tin, or may include an alloy of copper, silver, and tin (e.g., SAC305).

[0168] The connecting electrode BOL may surround the side surface of the light emitting element bar LER. For example, the connecting electrode BOL may surround the first semiconductor layer SEM1 and the light emitting layer MQW. Therefore, light emitted from the light emitting layer MQW may be easily reflected from the connecting electrode BOL and emitted upward. In this way, the connecting electrode BOL surrounding the side surface of the light emitting element bar LER may be used as a reflective layer. The thickness of the connecting electrode BOL surrounding the side of the light emitting element bar LER may be different according to the height. For example, the connecting electrode BOL surrounding the side of the light emitting element bar LER may have the thickest middle portion, but the embodiment is not limited thereto. Fig.18As shown in , the connection electrode BOL surrounding the side of the light emitting element rod LER may be formed to have a constant thickness.

[0169] like Fig.15 and Fig.16 As shown in FIG. 1 , the light emitting element LE may be disposed in each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3. The light emitting element LE may be a reference Figures 3 to 9 The light emitting element LE is described.

[0170] The angle θ between the side surface of the light emitting element LE and the bottom surface of the first semiconductor layer SEM1 may be greater than or equal to 90 degrees. When the side surface of the light emitting element LE is inclined, light emitted from the light emitting layer MQW may be easily reflected from the connection electrode BOL and emitted upward. Therefore, the light emitting efficiency of the light emitting element LE may be further improved.

[0171] The organic layer 140 may be disposed on the pixel electrodes PE1, PE2, and PE3 and the portion of the second planarization layer 130 on which the light emitting element LE is not disposed. The organic layer 140 may flatten the step portion below so that the common electrode CE to be described later may be formed. The organic layer 140 may be disposed at the same height as the light emitting element LE, but the embodiment is not limited thereto. For example, the organic layer 140 may be formed to a specific height so that at least a portion of the light emitting element LE may protrude above the organic layer 140. For example, the height of the organic layer 140 based on the top surface of the first pixel electrode PE1 may be less than the height of the light emitting element LE.

[0172] The organic layer 140 may include an organic material that planarizes the lower stepped portion. For example, the organic layer 140 may include polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB) resin.

[0173] The common electrode CE may be disposed on the organic layer 140 and the light emitting element LE. For example, the common electrode CE may be disposed on the surface of the substrate 110 on which the light emitting element LE is formed, and may be disposed in the entire display area DPA. The common electrode CE may be disposed to overlap each of the light emitting areas EA1, EA2, and EA3 in the display area DPA, and may have a thin thickness so that light may be emitted.

[0174] The common electrode CE may be disposed (eg, directly disposed) on the upper surface of the light emitting element LE. For example, the common electrode CE may contact (eg, directly contact) the second semiconductor layer SEM2 as the upper surface of the light emitting element LE. The common electrode CE may be a common layer disposed to cover the light emitting element LE and commonly connect the light emitting element LE.

[0175] Since the common electrode CE is entirely disposed on the substrate 110 and a common voltage is applied, the common electrode CE may include a material having a low resistance. For example, the common electrode CE may be formed to have a thin thickness so that light is easily transmitted. For example, the common electrode CE may include a low resistance metal material such as aluminum (Al), silver (Ag), or copper (Cu) or a metal oxide (ITO, IZO, or ITZO). The common electrode CE may have a thickness of about 10Å to about 200Å, but the embodiment is not limited thereto.

[0176] The light emitting element LE may receive a pixel voltage or an anode voltage from each of the pixel electrodes PE1, PE2, and PE3, and may receive a common voltage through the common electrode CE. The light emitting element LE may emit light having a specific brightness according to a voltage difference between the pixel voltage and the common voltage. In an embodiment, by providing a light emitting element LE (e.g., an inorganic light emitting diode) on the pixel electrodes PE1, PE2, and PE3, it is possible to eliminate (or prevent) the disadvantages of an organic light emitting diode that is susceptible to external moisture or oxygen, and improve lifespan and reliability.

[0177] like Fig.17 As shown in , the light emitting element LE may be disposed on each of the pixel electrodes PE1, PE2, and PE3. The light emitting elements LE may be regularly arranged according to a specific rule. For example, the light emitting elements LE may be spaced apart from each other at regular intervals. However, the embodiment is not limited thereto, and the light emitting elements LE may be irregularly arranged.

[0178] Each of the light emitting elements LE may be substantially disposed on each of the pixel electrodes PE1, PE2, and PE3. However, the embodiment is not limited thereto, and some of the light emitting elements LE may be disposed between adjacent pixel electrodes PE1, PE2, and PE3, may be partially disposed across any one of the pixel electrodes, or may not be disposed on any pixel electrode.

[0179] For example, the first cover layer CPL1 may be disposed on the substrate 110 on which the common electrode CE is disposed. The first cover layer CPL1 may be disposed (eg, directly disposed) on the common electrode CE. The first cover layer CPL1 may be used to protect components disposed therebelow (eg, the light emitting element LE and the common electrode CE) from moisture or foreign matter by covering them.

[0180] The first cover layer CPL1 may include an inorganic material. For example, the first cover layer CPL1 may include at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxide. For example, although the drawings show that the first cover layer CPL1 is formed of a single layer, the embodiment is not limited thereto. For example, the first cover layer CPL1 may be formed as a plurality of layers of alternating inorganic layers stacked, the alternating inorganic layers including at least one of the materials such as the materials that the first cover layer CPL1 may include. The thickness of the first cover layer CPL1 may be in the range of about 0.05 μm to about 2 μm, but the embodiment is not limited thereto.

[0181] For example, the wavelength control unit 200 may be disposed on the light emitting element part LEP. The wavelength control unit 200 may include a first wavelength conversion layer WCL1, a second wavelength conversion layer WCL2, and a light-transmitting layer TPL. For example, the wavelength control unit 200 may further include a bank layer BNL.

[0182] The bank layer BNL may be disposed on the first cover layer CPL1 and may separate the light emitting areas EA1, EA2, and EA3. The bank layer BNL may be disposed to extend in the first direction DR1 and the second direction DR2 and may be formed in a lattice pattern throughout the display area DPA. For example, the bank layer BNL may not overlap the light emitting areas EA1, EA2, and EA3 and may overlap the non-light emitting area NEA.

[0183] The bank layer BNL may be used to provide a space in which the first wavelength conversion layer WCL1, the second wavelength conversion layer WCL2, and the light-transmitting layer TPL are formed. For example, the bank layer BNL may have a thickness of about 1 μm to about 10 μm. The bank layer BNL may include an organic insulating material to be formed to a large thickness. The organic insulating material may include, for example, an epoxy resin, an acrylic resin, a cardo resin, or an imide resin.

[0184] In an embodiment, the bank layer BNL may further include a light blocking material, and may include a dye or pigment having a light blocking property. For example, the bank layer BNL may be a black matrix. External light incident from outside the display device 10 may cause a problem of color gamut distortion of the wavelength control unit 200. According to an embodiment, the color distortion caused by reflection of external light may be reduced by providing a bank layer BNL including a light blocking material in the wavelength control unit 200. For example, the bank layer BNL including a light blocking material may prevent light from penetrating between adjacent light emitting areas EA1, EA2, and EA3 and thus prevent color mixing, thereby further improving color reproducibility.

[0185] The first wavelength conversion layer WCL1, the second wavelength conversion layer WCL2, and the light-transmitting layer TPL may be disposed in the light-emitting areas EA1, EA2, and EA3. The first wavelength conversion layer WCL1 and the second wavelength conversion layer WCL2 may convert or shift incident light having a peak wavelength into light having another specific peak wavelength and emit the light. The first wavelength conversion layer WCL1 may convert blue light emitted from the light-emitting element LE into red light, and the second wavelength conversion layer WCL2 may convert blue light into green light. The light-transmitting layer TPL may transmit blue light as it is.

[0186] The first wavelength conversion layer WCL1, the second wavelength conversion layer WCL2, and the light-transmitting layer TPL may be disposed in each of the light-emitting areas EA1, EA2, and EA3 partitioned by the bank layer BNL, and may be arranged to be spaced apart from each other. For example, the first wavelength conversion layer WCL1, the second wavelength conversion layer WCL2, and the light-transmitting layer TPL may be formed in a dot-shaped island pattern spaced apart from each other.

[0187] The first wavelength conversion layer WCL1 may be disposed to overlap the first light emitting area EA1. The first wavelength conversion layer WCL1 may convert or shift incident light having a peak wavelength into light having another specific peak wavelength and emit the light. In an embodiment, the first wavelength conversion layer WCL1 may convert blue light emitted from the light emitting element LE of the first light emitting area EA1 into red light having a peak wavelength in the range of about 610 nm to about 650 nm, and may emit red light.

[0188] The first wavelength conversion layer WCL1 may include a first matrix resin BRS1, first wavelength conversion particles WCP1 and scatterers SCP. The first matrix resin BRS1 may include a light-transmitting organic material. For example, the first matrix resin BRS1 may include epoxy resin, acrylic resin, cardo resin or imide resin.

[0189] The first wavelength conversion particle WCP1 may convert blue light incident from the light emitting element LE into red light. For example, the first wavelength conversion particle WCP1 may convert light in a blue band into light in a red band. The first wavelength conversion particle WCP1 may be a quantum dot (QD), a quantum rod, a fluorescent material, or a phosphorescent material. For example, a quantum dot may be a specific material that emits light of a specific color when electrons transition from a conduction band to a valence band.

[0190] Quantum dots can be semiconductor nanocrystal materials. Depending on their composition and size, quantum dots can have a specific band gap to absorb light and emit light with an inherent wavelength. Examples of semiconductor nanocrystals of quantum dots include IV group nanocrystals, II-VI group compound nanocrystals, III-V group compound nanocrystals, IV-VI group compound nanocrystals, or a combination thereof.

[0191] The II-VI compounds may be binary compounds selected from the group consisting of CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS and mixtures thereof; ternary compounds selected from the group consisting of InZnP, AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS , CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and mixtures thereof; and a quaternary compound selected from the group consisting of CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and mixtures thereof.

[0192] The III-V compound may be a binary compound selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb and mixtures thereof; a ternary compound selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InAlP, InNAs, InNSb, InPAs, InPSb and mixtures thereof; and a quaternary compound selected from the group consisting of GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb and mixtures thereof.

[0193] The IV-VI compound may be selected from the group consisting of: a binary compound selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe and mixtures thereof; a ternary compound selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe and mixtures thereof; and a quaternary compound selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe and mixtures thereof. The IV group element may be selected from the group consisting of Si, Ge and mixtures thereof. The IV group compound may be a binary compound selected from the group consisting of SiC, SiGe and mixtures thereof.

[0194] The binary, ternary or quaternary compound may be present in a particle at a uniform concentration, or may be present in the same particle at a partially different concentration distribution. The quantum dot may also have a core / shell structure in which one quantum dot surrounds another quantum dot. The interface of the core and the shell may have a concentration gradient in which the concentration of the element present in the shell decreases toward the center.

[0195] In an embodiment, the quantum dot may have a core / shell structure including a core comprising a nanocrystal as described above and a shell surrounding the core. The shell of the quantum dot may act as a protective layer to prevent chemical denaturation of the core to maintain semiconductor properties, and / or act as a charged layer to impart electrophoretic properties to the quantum dot. The shell may be a single layer or multiple layers. Examples of the shell of the quantum dot include oxides of metals or non-metals, semiconductor compounds, or combinations thereof.

[0196] For example, oxides of metals or nonmetals may include binary compounds such as SiO 2 、Al 2 O 3 、TiO 2 、ZnO、MnO、Mn 2 O 3 , Mn 3 O 4 , CuO, FeO, Fe 2 O 3 , Fe 3 O 4 , CoO, Co 3 O 4 , NiO) or ternary compounds (such as MgAl 2 O 4 、CoFe 2 O 4 、NiFe 2 O 4 、CoMn 2 O 4 ), but the embodiment is not limited thereto.

[0197] For example, the semiconductor compound may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb, etc., but the embodiment is not limited thereto.

[0198] The scatterer SCP may scatter the light of the light emitting element LE in random directions. The scatterer SCP may have a refractive index different from that of the first matrix resin BRS1 and form an optical interface with the first matrix resin BRS1. For example, the scatterer SCP may be light scattering particles. The scatterer SCP is not particularly limited as long as it is any material capable of scattering at least a portion of the transmitted light, and may be, for example, metal oxide particles or organic particles. Examples of metal oxides include titanium oxide (TiO 2 )、ZrO 2 )、Alumina(Al 2 O 3 )、Indium oxide(In 2 O 3 )、ZnO、SnO 2 ), etc. Examples of the organic particle material include acrylic resin or urethane resin. The scatterer SCP can scatter light in random directions without substantially converting the wavelength of the light, regardless of the incident direction of the incident light.

[0199] The second wavelength conversion layer WCL2 may be disposed to overlap with the second light emitting area EA2. The second wavelength conversion layer WCL2 may convert or shift incident light having a peak wavelength into light having another specific peak wavelength and emit the light. In an embodiment, the second wavelength conversion layer WCL2 may convert blue light emitted from the light emitting element LE of the second light emitting area EA2 into green light having a peak wavelength in the range of about 510 nm to about 550 nm and emit green light.

[0200] The second wavelength conversion layer WCL2 may include a second matrix resin BRS2 and second wavelength conversion particles WCP2 and scatterers SCP dispersed in the second matrix resin BRS2.

[0201] The second base resin BRS2 may be made of a material having high light transmittance, and may be made of the same material as the first base resin BRS1, or may include at least one of the materials as a constituent material thereof.

[0202] The second wavelength conversion particles WCP2 may convert or shift incident light having a peak wavelength into light having another specific peak wavelength. In an embodiment, the second wavelength conversion particles WCP2 may convert blue light provided from the light emitting element LE into green light having a peak wavelength in the range of about 510 nm to about 550 nm and emit green light. Examples of the second wavelength conversion particles WCP2 include quantum dots, quantum rods, or phosphors. A more specific description of the second wavelength conversion particles WCP2 is substantially the same or similar to that described above in the description of the first wavelength conversion particles WCP1, and therefore will be omitted for ease of description.

[0203] The light-transmitting layer TPL may be disposed to overlap with the third light-emitting area EA3. The light-transmitting layer TPL may transmit incident light. The light-transmitting layer TPL may transmit blue light emitted from the light-emitting element LE disposed in the third light-emitting area EA3 as it is. The light-transmitting layer TPL may include a third base resin BRS3 and a scatterer SCP dispersed in the third base resin BRS3. Since the third base resin BRS3 is substantially the same as or similar to the above-mentioned first base resin BRS1, its description will be omitted for the sake of convenience of description.

[0204] The light transmitted through the wavelength control unit 200 may realize (or display) full color by passing through a color filter layer CFL which will be described later.

[0205] The wavelength control unit 200 may further include a second cover layer CPL2. The second cover layer CPL2 may cover the first wavelength conversion layer WCL1, the second wavelength conversion layer WCL2, the light-transmitting layer TPL, and the bank layer BNL disposed thereunder to protect them from moisture or foreign matter. The second cover layer CPL2 may include an inorganic material, and may include a material substantially the same as or similar to that of the first cover layer CPL1 described above.

[0206] First, second, and third color filters CF1, CF2, and CF3 may be disposed on the second cover layer CPL2. The first color filter CF1 may be disposed in the first emission area EA1, the second color filter CF2 may be disposed in the second emission area EA2, and the third color filter CF3 may be disposed in the third emission area EA3.

[0207] The first color filter CF1, the second color filter CF2, and the third color filter CF3 may include a colorant (such as a dye or a pigment) that absorbs wavelengths other than the corresponding color wavelengths. The first color filter CF1 may selectively transmit red light and block or absorb blue light and green light. The second color filter CF2 may selectively transmit green light and block or absorb blue light and red light. The third color filter CF3 may selectively transmit blue light and block or absorb red light and green light. For example, the first color filter CF1 may be a red color filter, the second color filter CF2 may be a green color filter, and the third color filter CF3 may be a blue color filter.

[0208] In an embodiment, the light incident on the first color filter CF1 may be light converted into red light by the first wavelength conversion layer WCL1, and the light incident on the second color filter CF2 may be light converted into green light by the second wavelength conversion layer WCL2, and the light incident on the third color filter CF3 may be blue light transmitted through the light-transmitting layer TPL. Therefore, the red light transmitted through the first color filter CF1, the green light transmitted through the second color filter CF2, and the blue light transmitted through the third color filter CF3 may be emitted to the upper portion of the substrate 110 to realize (or display) full color.

[0209] The first color filter CF1, the second color filter CF2, and the third color filter CF3 can absorb some of the light introduced from the outside of the display device 10 to reduce the reflected light caused by the external light. Therefore, the first color filter CF1, the second color filter CF2, and the third color filter CF3 can prevent color distortion caused by external light reflection.

[0210] like Fig.17 As shown in , the plane area of ​​each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be greater than the plane area of ​​each of the light emitting areas EA1, EA2, and EA3. For example, the first color filter CF1 may have a larger plane area than the first light emitting area EA1. The second color filter CF2 may have a larger plane area than the second light emitting area EA2. The third color filter CF3 may have a larger plane area than the third light emitting area EA3. However, the embodiment is not limited thereto, and the plane area of ​​each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be substantially equal to the plane area of ​​each of the light emitting areas EA1, EA2, and EA3.

[0211] For example, the first color filter CF1 may be disposed in the non-emission area NEA, and at least one of the second color filter CF2 and the third color filter CF3 may be further disposed to overlap the first color filter CF1 in the non-emission area NEA. For example, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed in the non-emission area NEA.

[0212] Therefore, light emission from the display device can be blocked in the non-light emitting area NEA, and reflection of external light can be suppressed. Each color filter CF1, CF2, and CF3 can block the emission of light of colors other than the corresponding color of each light emitting area EA1, EA2, and EA3, and thus, red, green, and blue light can all be blocked in the non-light emitting area NEA. However, the embodiment is not limited thereto, and a light absorbing member including a light absorbing material absorbing a visible light band can be provided in the non-light emitting area NEA.

[0213] The protective layer OC may be disposed on the color filter layer CFL. The protective layer OC may be disposed (eg, directly disposed) on the color filter layer CFL. The protective layer OC may be disposed (eg, entirely disposed) in the display area DPA and may have a flat surface. The protective layer OC may flatten a stepped portion formed by the underlying color filter layer CFL. The protective layer OC may include a light-transmitting organic material.

[0214] In another example, the first light emitting element LE1 disposed in the first light emitting area EA1 may emit a blue first light, the second light emitting element LE2 disposed in the second light emitting area EA2 may emit a red second light, and the third light emitting element LE3 disposed in the third light emitting area EA3 may emit a green third light. In the case where the light emitting elements LE disposed in different light emitting areas may emit light of different wavelengths, reference to Fig.15 The wavelength control unit 200 and the color filter layer CFL are described.

[0215] Fig.19 is a graph showing reflectivity of a connection electrode according to an embodiment.

[0216] exist Fig.19 In FIG. 1 , the dotted line indicates the reflectivity according to the wavelength in the case where an aluminum reflective layer is formed on the side surface of a conventional light emitting element, and the solid line indicates the reflectivity according to the wavelength in the case where the connection electrode of the light emitting element according to the embodiment is formed to surround the light emitting layer. Fig.19 As shown in , in the case where the connection electrode of the light emitting element according to the embodiment is formed to surround the light emitting layer, the light emitting element can have a reflectivity of 70% or more at all wavelengths without a separate reflective layer.

[0217] Fig. 20 This is a SEM photograph of the light-emitting element according to the example, taken with a scanning electron microscope.

[0218] Reference Fig. 20 , the connection electrode may be formed to surround the side surface of the light emitting layer MQW of the light emitting element. Therefore, light emitted from the light emitting layer MQW may be reflected by the connection electrode BOL and emitted upward, so that the light emitting efficiency may be increased.

[0219] Hereinafter, a manufacturing process of the display device 10 according to the embodiment will be described with reference to other drawings.

[0220] Fig.21 is a flowchart showing steps of a method of manufacturing a display device according to an embodiment. Figure 22 to Figure 29 It is shown Fig.21 Diagram of the steps. Figure 22 to Figure 29 1 is a schematic cross-sectional view of a structure according to the formation order of each layer of the display device 10 .

[0221] Figure 21 to Figure 29 The manufacturing process of the light emitting element portion LEP is shown, and these manufacturing processes can be Figure 7 Hereinafter, a first light emitting area EA1 and a second light emitting area EA2 of the display device 10 are shown. For example, for ease of description, a single light emitting element LE may be disposed in a single light emitting area EA1 or EA2, but the embodiment is not limited thereto.

[0222] Reference Fig.21 , the method for manufacturing the display device 10 may include: forming a light emitting element bar LER in which a third semiconductor layer USE, a second semiconductor layer SEM2, a light emitting layer MQW, and a first semiconductor layer SEM1 are sequentially stacked on a base substrate BSUB (step S110); forming an insulating layer INS surrounding the light emitting element bar LER (step S120); and forming a connecting electrode BOL by depositing an electrode material layer on the entire substrate on which the light emitting element bar LER is formed (step S130).

[0223] The following will refer to Figure 22 to Figure 29 describe Fig.21 Detailed example of the steps in .

[0224] Reference Figure 22 to Figure 25 , a light emitting element LE may be formed on the base substrate BSUB.

[0225] For example, refer to Fig. 22 , a base substrate BSUB can be prepared. The base substrate BSUB can be a sapphire base Al 2 O 3 Or a silicon wafer including silicon. However, the embodiment is not limited thereto, and in the embodiment, a case where the base substrate BSUB is a sapphire substrate will be described as an example.

[0226] Semiconductor material layers USEL, SEM2L, MQWL, and SEM1L may be formed on the base substrate BSUB. The semiconductor material layer grown by an epitaxial method may be formed by growing a seed crystal. Methods for forming the semiconductor material layer include electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, metal organic chemical vapor deposition (MOCVD), etc. For example, the semiconductor material layer may be formed by metal organic chemical vapor deposition (MOCVD). However, the embodiment is not limited thereto.

[0227] The precursor material used to form the semiconductor material layer is not limited within the range conventionally selected for forming the target material. In an example, the precursor material can be a metal precursor including an alkyl group such as a methyl group or an ethyl group. For example, the precursor material can be a metal precursor such as trimethylgallium (Ga(CH 3 ) 3 ), trimethylaluminum (Al(CH 3 ) 3 ), triethyl phosphate ((C 2 H 5 ) 3 PO 4 ), but the embodiments are not limited thereto.

[0228] For example, a third semiconductor material layer USEL may be formed on the base substrate BSUB. Although the drawings show a further stacked third semiconductor material layer USEL, the embodiment is not limited thereto, and a plurality of layers may be formed. The third semiconductor material layer USEL may be provided to reduce the lattice constant difference between the second semiconductor material layer SEM2L and the base substrate BSUB. For example, the third semiconductor material layer USEL may include an undoped semiconductor (which is an n-type or p-type undoped material). In an embodiment, the third semiconductor material layer USEL may be at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, but the embodiment is not limited thereto.

[0229] The second semiconductor material layer SEM2L, the light emitting material layer MQWL, and the first semiconductor material layer SEM1L may be sequentially formed on the third semiconductor material layer USEL by using the above-described method.

[0230] Then, the light emitting element rods LER may be formed by etching the semiconductor material layers USEL, SEM2L, MQWL, and SEM1L.

[0231] For example, a first mask pattern MP1 may be formed on the first semiconductor material layer SEM1L. The first mask pattern MP1 may be a hard mask including an inorganic material or a photoresist mask including an organic material. The first mask pattern MP1 may prevent the semiconductor material layers USEL, SEM2L, MQWL, and SEM1L under the first mask pattern MP1 from being etched. Then, a portion of the semiconductor material layer may be etched (e.g., first etching) using the first mask pattern MP1 as a mask to form a light emitting element rod LER.

[0232] like Fig.23As shown in FIG, on the base substrate BSUB, the semiconductor material layers USEL, SEM2L, MQWL, and SEM1L not overlapping the first mask pattern MP1 may be etched and removed, and portions not etched and overlapping the first mask pattern MP1 may be formed as light emitting element rods LER.

[0233] The semiconductor material layers USEL, SEM2L, MQWL, and SEM1L may be etched by conventional methods. For example, the process of etching the semiconductor material layers USEL, SEM2L, MQWL, and SEM1L may be a dry etching process, a wet etching process, a reactive ion etching (RIE) process, a deep reactive ion etching (DRIE) process, an inductively coupled plasma reactive ion etching (ICP-RIE) process, etc. In the case of the dry etching method, the anisotropic etching process may be applicable to vertical etching. In the case of using the above etching method, the etchant may be Cl 2 or 2 However, the embodiments are not limited thereto.

[0234] The semiconductor material layers USEL, SEM2L, MQWL, and SEM1L overlapping the first mask pattern MP1 may not be etched but may be formed as light emitting elements LE. Thus, the light emitting element rod LER may be formed to include the third semiconductor layer USE, the second semiconductor layer SEM2, the light emitting layer MQW, and the first semiconductor layer SEM1.

[0235] Reference Fig.24 and Fig.25 , an insulating layer INS may be formed on the base substrate BSUB on which the light emitting element rods LER are formed.

[0236] For example, the insulating material layer INSL may be formed on the outer surface of the light emitting element rod LER. The insulating material layer INSL may be formed on the entire surface of the base substrate BSUB, and the insulating material layer INSL may be formed not only on the light emitting element rod LER but also on the upper surface of the base substrate BSUB exposed by the light emitting element LE.

[0237] Then, a second etching (eg, a 2nd etching) may be performed to partially remove the insulating material layer INSL to form a light emitting element LE including the insulating layer INS.

[0238] For example, the second etching process may be performed to partially remove a portion of the insulating material layer INSL so that the insulating material layer INSL may expose the upper surface of the light emitting element rod LER but surround the side of the light emitting element rod LER. For example, in this process, a portion of the insulating material layer INSL may be removed to expose the upper surface of the first semiconductor layer SEM1 of the light emitting element LE. The process of partially removing the insulating material layer INSL may be performed by a process such as anisotropic dry etching or etching back.

[0239] Next, refer to Fig.26 , the connection electrode BOL covering the side (or end) of the light emitting element rod LER can be formed on the light emitting element LE by using an electron beam evaporation method.

[0240] The electron beam evaporation method may be a vacuum deposition method using a high voltage between ionized evaporated metals, and may be a method using electrons instead of heat. As described above, according to the embodiment, the connection electrode BOL may be formed on the light emitting element LE without a mask. Therefore, the diameter (or size / width) of the connection electrode BOL may be formed to be larger than the diameter (or size / width) of the light emitting element LE. Therefore, by forming the connection electrode BOL having a diameter larger than the diameter of the light emitting element LE, stitching unevenness may be improved. By forming the connection electrode BOL having a diameter larger than the diameter of the light emitting element LE, it is possible to eliminate (or prevent) alignment deviation between the light emitting element LE and the substrate. Therefore, in the case of bonding the light emitting element LE to the substrate, tilting of the light emitting element LE may be prevented. In this way, since the mask process is removed (or omitted), the process cost and time may be reduced. However, in the case of forming the connection electrode BOL on the end of the light emitting element rod LER by using the electron beam evaporation method, the material forming the connection electrode BOL may also be deposited on the first side of the base substrate BSUB on which the light emitting element LE is not disposed. However, as will be described later with reference to Fig.28 As described, in the case where the base substrate BSUB is separated from the light emitting element LE, the material forming the connection electrode BOL deposited on the first side of the base substrate BSUB may be removed together with the material deposited on the base substrate BSUB.

[0241] In another example, in addition to the electron beam evaporation method, any one of sputtering and molecular beam epitaxy (MBE) may be used.

[0242] In another example, as shown in Figures 7 to 9 As described, at least one of the upper surface and the side surface of the deposition surface may be formed to be flat by adding an etching step.

[0243] Next, refer to Fig. 27 and Fig.28, the light emitting element LE having the connection electrode BOL may be attached to the first pixel electrode PE1 and the second pixel electrode PE2.

[0244] For example, the substrate 110 on which the first and second switching elements T1 and T2 and the first and second pixel electrodes PE1 and PE2 are disposed may be prepared.

[0245] The substrate 110 may be an insulating substrate. The substrate 110 may include a transparent material. For example, the substrate 110 may include a transparent insulating material such as glass or quartz. The substrate 110 may be a rigid substrate. However, the substrate 110 is not limited thereto and may include plastic such as polyimide and may have a flexible property to be twisted, bent, folded, or curled.

[0246] In an embodiment, each of the first switching element T1 and the second switching element T2 may be a thin film transistor including amorphous silicon, polycrystalline silicon or an oxide semiconductor. For example, a signal line (e.g., a gate line, a data line, a power line, etc.) for transmitting a signal to the first switching element T1 and the second switching element T2 may be further provided on the substrate 110.

[0247] Each of the first switching element T1 and the second switching element T2 may include a semiconductor layer, a gate electrode, a source electrode, and a drain electrode. For example, the semiconductor layer may form a channel of each of the switching elements T1, T2, and T3. The semiconductor layer may include amorphous silicon, polycrystalline silicon, or an oxide semiconductor. The gate electrode may include a conductive material. The gate electrode may include a metal oxide (such as ITO, IZO, ITZO, or In 2 O 3 ) or a metal such as copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg), or nickel (Ni). The source electrode and the drain electrode may be in contact with the semiconductor layer and may include a metal oxide such as ITO, IZO, ITZO, or In 2 O 3 ) or a metal such as copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg) or nickel (Ni).

[0248] A second planarization layer 130 may be disposed on each of the first switching element T1 and the second switching element T2. The second planarization layer 130 may include an organic material. For example, the second planarization layer 130 may include an acrylic resin, an epoxy resin, an imide resin, an ester resin, or the like. In an embodiment, the second planarization layer 130 may include a positive photosensitive material or a negative photosensitive material.

[0249] Pixel electrodes PE1 and PE2 may be disposed on the second planarization layer 130. The pixel electrodes PE1 and PE2 may be disposed to correspond to each of the first switching element T1 and the second switching element T2, and may be connected (e.g., electrically connected) to each of the first switching element T1 and the second switching element T2. The pixel electrodes PE1 and PE2 may contact the first switching element T1 and the second switching element T2 through contact holes penetrating the second planarization layer 130.

[0250] Next, the base substrate BSUB may be aligned on the substrate 110. At this time, the connection electrode BOL of the light emitting element LE may be aligned on the pixel electrodes PE1 and PE2 formed on the substrate 110 to face the substrate 110.

[0251] Subsequently, the substrate 110 and the base substrate BSUB may be bonded together. For example, the connection electrode BOL of the light emitting element LE formed on the base substrate BSUB may be transferred to contact the pixel electrodes PE1 and PE2 of the substrate 110. At this time, the connection electrode BOL of the light emitting element LE may contact the pixel electrodes PE1 and PE2. For example, the substrate 110 and the base substrate BSUB may be bonded by melting and bonding the connection electrode BOL of the light emitting element LE to the pixel electrodes PE1 and PE2. The light emitting element LE may be bonded to the upper surfaces of the pixel electrodes PE1 and PE2.

[0252] Melt bonding may be performed by irradiating laser onto the pixel electrodes PE1 and PE2 on the base substrate BSUB. The laser-irradiated pixel electrodes PE1 and PE2 may conduct high heat from the laser to bond the interface of the connection electrode BOL of the light emitting element LE with the pixel electrodes PE1 and PE2. For example, the pixel electrodes PE1 and PE2 may include copper (Cu) having excellent thermal conductivity and may have excellent bonding properties with the connection electrode BOL of the light emitting element LE. The laser source for melt bonding may be a YAG laser.

[0253] For example, the light emitting element LE may be separated from the base substrate BSUB by irradiating the laser LASER to the base substrate BSUB. The base substrate BSUB may be separated from each third semiconductor layer USE of the light emitting element LE.

[0254] The process of separating the base substrate BSUB may be performed by a laser lift-off (LLO) process. The laser lift-off process may use a laser, and may use a KrF excimer laser (having a wavelength of about 248 nm) as a source. The energy density of the excimer laser may be about 550 mJ / cm 2 About 950mJ / cm 2 The incident area can be approximately 50×50µm 2About 1×1cm 2 When the laser LASER is irradiated to the base substrate BSUB, the base substrate BSUB may be separated from the light emitting element LE.

[0255] Thereafter, the third semiconductor layer USE may be non-conductive and may be removed for connection of the common electrode CE. The third semiconductor layer USE may be removed by an ashing process. Some of the third semiconductor layer USE may remain.

[0256] Reference Fig.29 , the organic layer 140 and the common electrode CE may be formed.

[0257] For example, the organic layer 140 may be formed on the second planarization layer 130 and the pixel electrodes PE1 and PE2 on which the light emitting element LE is not disposed.

[0258] A common electrode CE may be formed on the light emitting element LE and the organic layer 140. The common electrode CE may be continuously formed throughout the entire display area. The common electrode CE may cover the organic layer 140 and the light emitting element LE, and may contact (e.g., directly contact) the organic layer 140 and the light emitting element LE. The common electrode CE may be formed to directly contact the upper surface of the second semiconductor layer SEM2 of the light emitting element LE.

[0259] Then, if Fig.15 As shown in , the display device 10 according to the embodiment may be manufactured by forming a bank layer, a wavelength control unit, a color filter layer, and the like.

[0260] Although the disclosure describes that the light emitting element LE formed on the base substrate BSUB is bonded to the substrate 110 , the light emitting element LE may be stretched using a stretched substrate.

[0261] The stretchable substrate may include a stretchable material. The stretchable material may include, for example, polyolefin, polyvinyl chloride (PVC), elastic silicone, elastic polyurethane, elastic polyisoprene, etc. By transferring the light emitting elements LE to such a stretchable substrate and then stretching the light emitting elements LE, the space between the light emitting elements LE can be adjusted.

[0262] Fig.30 is an exemplary diagram showing a virtual reality device including a display device according to an embodiment. Fig.30 A virtual reality device 1 in which a display device 10 according to the embodiment is used is shown.

[0263] Reference Fig.30The virtual reality device 1 according to the embodiment may be a device formed as glasses. The virtual reality device 1 according to the embodiment may include a display device 10_1, a left-eye lens 10a, a right-eye lens 10b, a support frame 20, left and right temples 30a and 30b, a reflective member 40, and a display device housing 50.

[0264] Fig.30 The virtual reality device 1 including two temples 30a and 30b is shown. However, the embodiment is not limited thereto. The virtual reality device 1 according to the embodiment may be used for a head mounted display including a head mounted band mounted on the head instead of the temples 30a and 30b. For example, the virtual reality device 1 according to the embodiment may not be limited to Fig.30 The examples shown in and can be applied in various forms and in various electronic devices.

[0265] The display device housing 50 can accommodate the display device 10_1 and the reflective member 40. The image displayed on the display device 10_1 can be reflected from the reflective member 40 and provided to the right eye of the user through the right eye lens 10b. Therefore, the user can view the virtual reality image displayed on the display device 10_1 through the right eye.

[0266] Fig.30 It is shown that the display device housing 50 is disposed at the right end of the supporting frame 20. However, the embodiment is not limited thereto. For example, the display device housing 50 may be disposed at the left end of the supporting frame 20. For example, the image displayed on the display device 10_1 may be reflected from the reflective member 40 and provided to the left eye of the user via the left eye lens 10a. Therefore, the user can view the virtual reality image displayed on the display device 10_1 via the left eye. As another example, the display device housing 50 may be disposed at each of the left end and the right end of the supporting frame 20. For example, the user can view the virtual reality image displayed on the display device 10_1 via both the left eye and the right eye.

[0267] Fig.31 is an exemplary diagram illustrating a smart device including a display device according to an embodiment.

[0268] Reference Fig.31 The display device 10_2 according to the embodiment can be applied to a smart watch 2 which is one of smart devices.

[0269] Fig.32 is an exemplary diagram showing a vehicle including a display device according to an embodiment. Fig.32 A vehicle in which the display device according to the embodiment is used is shown.

[0270] Reference Fig.32The display devices 10_a, 10_b, and 10_c according to the embodiment may be applied to a dashboard of a vehicle, to a central instrument panel of a vehicle, or to a CID (Central Information Display) provided on a dashboard of a vehicle. In addition, each of the display devices 10_d and 10_e according to the embodiment may be applied to each interior mirror display that replaces each of the side mirrors of the vehicle.

[0271] Fig.33 is an exemplary diagram showing a transparent display device including a display device according to an embodiment.

[0272] Reference Fig.33 , the display device according to the embodiment can be applied to a transparent display device. The transparent display device can allow light to be transmitted through it and can display an image IM thereon. Therefore, a user located in front of the transparent display device can not only view the image IM displayed on the display device 10_3, but also view an object RS or a background located behind the transparent display device. In the case where the display device 10 is applied to a transparent display device, Figure 7 The substrate 110 of the display device 10 shown in FIG. 1 may include a light-transmitting portion through which light is transmitted or be made of a material through which light is transmitted.

[0273] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the embodiments without departing substantially from the principles of the disclosure. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A light emitting element array, comprising: base substrate; a plurality of light emitting elements, each of the plurality of light emitting elements comprising: a light emitting element rod including a third semiconductor layer, a second semiconductor layer, a light emitting layer, and a first semiconductor layer sequentially stacked on the base substrate; and an insulating layer surrounding the light emitting element rod; and A connecting electrode is provided on the first semiconductor layer of each of the plurality of light emitting elements, wherein: The length of the connecting electrode in the horizontal direction is greater than the length of the light emitting element in the horizontal direction, and The connection electrode surrounds a side surface of the first semiconductor layer and a side surface of the light emitting layer.

2. The light emitting element array according to claim 1, wherein: The connecting electrode comprises: A first portion is disposed on the first semiconductor layer; and The second portion is provided on the side surface of the light emitting element rod, and The first portion of the connecting electrode protrudes upward.

3. The light emitting element array according to claim 2, wherein: A length of the second portion of the connection electrode in the horizontal direction varies according to a height of the second portion.

4. The light emitting element array according to claim 2, wherein: A length of the second portion of the connection electrode in the horizontal direction is constant according to a height of the second portion.

5. The light emitting element array according to claim 1, wherein: The connecting electrode comprises: A first portion is disposed on the first semiconductor layer; and The second part is provided on the side surface of the light emitting element rod, The first portion of the connecting electrode has a flat upper surface, and A length of the second portion of the connection electrode in the horizontal direction varies according to a height of the second portion.

6. The light emitting element array according to claim 1, wherein: The connecting electrode comprises: A first portion is disposed on the first semiconductor layer; and The second part is provided on the side surface of the light emitting element rod, The first portion of the connecting electrode has a flat upper surface, and A width of the second portion of the connection electrode is constant according to a height of the second portion.

7. The light emitting element array according to claim 1, wherein: Each of the plurality of light emitting elements has at least one of a circular shape, a hexagonal shape, and a rectangular shape in a plan view.

8. A display device, comprising: a substrate including a pixel electrode; A plurality of light emitting elements, each of the plurality of light emitting elements comprising: a light emitting element bar including a first semiconductor layer, a light emitting layer, and a second semiconductor layer sequentially stacked on the pixel electrode of the substrate; and an insulating layer surrounding the light emitting element bar; A connecting electrode, disposed between the pixel electrode and the plurality of light emitting elements; and A common electrode is disposed on the plurality of light emitting elements, wherein: The length of the connecting electrode in the horizontal direction is greater than the length of the light emitting element in the horizontal direction, and The connection electrode surrounds a side surface of the first semiconductor layer and a side surface of the light emitting layer.

9. The display device according to claim 8, wherein: The connecting electrode comprises: A first portion is disposed on the first semiconductor layer; and The second portion is provided on the side surface of the light emitting element rod, and A length of the second portion of the connection electrode in the horizontal direction varies according to a height of the second portion.

10. The display device according to claim 8, wherein: The connecting electrode comprises: A first portion is disposed on the first semiconductor layer; and The second portion is provided on the side surface of the light emitting element rod, and The length of the second portion in the horizontal direction is constant according to the height of the second portion.

11. The display device according to claim 8, wherein: Each of the plurality of light emitting elements has at least one of a circular shape, a hexagonal shape, and a rectangular shape in a plan view.

12. The display device according to claim 8, wherein: The connection electrode includes at least one of gold, copper, tin, silver, aluminum and titanium.

13. A method for manufacturing a light emitting element, the method comprising the following steps: forming a light emitting element bar including a third semiconductor layer, a second semiconductor layer, a light emitting layer, and a first semiconductor layer sequentially stacked on a base substrate; forming an insulating layer surrounding the light emitting element rod; as well as A connection electrode having a length greater than that of the light emitting element in a horizontal direction and surrounding a portion of a side surface of the light emitting element bar on the base substrate on which the light emitting element bar is formed is formed.

14. The method according to claim 13, wherein: The step of forming the connection electrode is performed by at least one of an electron beam evaporation method, a sputtering method, and a molecular beam epitaxy method.

15. The method according to claim 14, wherein: The connection electrode surrounds a side surface of the first semiconductor layer and a side surface of the light emitting layer.

16. The method according to claim 14, further comprising the steps of: aligning the light emitting element having the connection electrode formed thereon on a substrate having a pixel electrode formed thereon; bonding the connection electrode to the pixel electrode; removing the base substrate and the third semiconductor layer; as well as A common electrode is formed on the light emitting element.

17. The method according to claim 15, wherein: The connecting electrode comprises: A first portion is disposed on the first semiconductor layer; and The second portion is provided on the side surface of the light emitting element rod, and The length of the second portion in the horizontal direction varies according to the height of the second portion.

18. The method according to claim 15, wherein: The connecting electrode comprises: A first portion is disposed on the first semiconductor layer; and The second portion is provided on the side surface of the light emitting element rod, and The length of the second portion in the horizontal direction is constant according to the height of the second portion.

19. The method according to claim 15, wherein: The light emitting element has at least one of a circular shape, a hexagonal shape, and a rectangular shape in a plan view.

20. The method according to claim 15, wherein: The connection electrode includes at least one of gold, copper, tin, silver, aluminum and titanium.

Images