Signal processing circuit

Abstract

The present invention is provided with: a capacitor connected to a signal line connected to a sensor and connected in series to the sensor; and a variable resistance circuit connected in parallel to the capacitor, in which the variable resistance circuit and the capacitor constitute a high-pass filter through which a signal having a cutoff frequency or higher passes, the variable resistance circuit being set to a first resistance value when a target signal having a peak component on a time axis passes through the high-pass filter, and the variable resistance circuit being set to a second resistance value when a target signal having a peak component on a time axis passes through the high-pass filter. The cut-off frequency at the first resistance value is 1 / 10 or less of the frequency of the peak component.

Description

Technical Field

[0001] The present invention relates to a signal processing circuit for processing a signal output from a sensor. Background Art

[0002] Patent document 1 describes a pressure sensor having a piezoelectric element, a circuit unit, and a receiving unit. The receiving unit deforms in response to a user's pressing operation. The piezoelectric element is mounted on the receiving unit. The piezoelectric element deforms in response to the deformation of the receiving unit. The piezoelectric element outputs a charge corresponding to the amount of deformation of the piezoelectric element. The circuit unit converts the charge generated by the piezoelectric element into a voltage. When the circuit unit detects a voltage above a preset threshold, it determines that the receiving unit has been pressed.

[0003] The piezoelectric element of Patent Document 1 generates positive charge when deformed by a pressing operation. The piezoelectric element is an elastic body. Therefore, after the positive charge is generated, negative charge of the opposite polarity is generated due to rebound. The circuit unit changes the threshold value to prevent the voltage of the opposite polarity caused by the rebound of the pressing operation from being mistakenly detected as a pressing operation.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: International Publication No. 2019 / 069786 Summary of the invention

[0007] Problem that the invention aims to solve

[0008] The structure shown in Patent Document 1 cannot cope with the case where the rebound becomes larger. In addition, the reason for generating the component of opposite polarity is not only the rebound shown in Patent Document 1. For example, as shown below, when the circuit has a high-pass characteristic, the component of opposite polarity may be generated. Figure 1A It is a diagram showing a waveform in the time domain (voltage waveform) of an input signal after passing through a high-pass filter. Figure 1B 1 is a diagram showing a time-domain waveform (voltage waveform) of an input signal before passing through a high-pass filter.

[0009] When the input signal passes through the high-pass filter, the low-frequency components of the input signal are removed. Therefore, the time domain waveform of the input signal is destroyed by the high-pass filter. For example, Figure 1A As shown, the high-pass filter may output a negative voltage component for a single-wave input signal having a positive peak component on the time axis ( Figure 1A In addition, the high-pass filter may output a positive voltage component for a single-wave input signal with a negative voltage component ( Figure 1AHereinafter, a negative voltage component generated for a positive voltage input signal, or a positive voltage component generated for a negative voltage input signal is referred to as an overshoot.

[0010] An object of the present invention is to provide a signal processing circuit capable of suppressing overshoot.

[0011] Solutions for solving problems

[0012] A signal processing circuit according to one embodiment of the present invention includes:

[0013] a capacitor connected to a signal line connected to the sensor and connected in series with the signal line; and

[0014] a variable resistance circuit connected in parallel with the signal line,

[0015] The variable resistance circuit and the capacitor form a high-pass filter that passes signals above the cutoff frequency.

[0016] When a target signal having a peak component on a time axis is passed through the high-pass filter, the variable resistance circuit is set to a first resistance value,

[0017] The cutoff frequency at the first resistance value is less than or equal to 1 / 10 of the frequency of the peak component.

[0018] Effects of the Invention

[0019] According to the signal processing circuit of the present invention, overshoot can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1A It is a diagram showing a waveform in the time domain (voltage waveform) of an input signal after passing through a high-pass filter. Figure 1B 1 is a diagram showing a time domain waveform (voltage waveform) of an input signal before passing through a high-pass filter.

[0021] Figure 2 It is a diagram showing an example of the circuit configuration of the sensor system SS1.

[0022] Figure 3 is a cross-sectional view of the piezoelectric sensor 1 .

[0023] Figure 4 3 is a diagram showing the relationship between the amount of pressure applied by the user and the voltage output from the charge-voltage conversion circuit 20 .

[0024] Figure 5 2 is a diagram showing a circuit configuration of the high-pass filter 21 .

[0025] Figure 6: is a graph showing the relationship between the ratio of the cut-off frequency fc to the frequency of the signal and the ratio of the overshoot peak voltage OSP to the peak voltage SGP of the signal.

[0026] Figure 7 2 is a diagram showing the variable resistance circuit 211 .

[0027] Figure 8 1 is a diagram showing a reference voltage generating circuit 25 a included in a signal processing circuit 2 a according to Modification 1. FIG.

[0028] Fig. 9 1 is a diagram showing an AD conversion circuit 24 b included in a signal processing circuit 2 b according to Modification 2.

[0029] Fig.10 1 is a diagram showing a high-pass filter 21 c included in a signal processing circuit 2 c according to Modification 3. DETAILED DESCRIPTION

[0030] (First Embodiment)

[0031] Hereinafter, a signal processing circuit 2 according to an embodiment of the present invention will be described with reference to the drawings. Figure 2 It is a diagram showing an example of the circuit configuration of the sensor system SS1. Figure 3 is a cross-sectional view of the piezoelectric sensor 1 . Figure 4 3 is a diagram showing the relationship between the amount of pressure applied by the user and the voltage output from the charge-voltage conversion circuit 20 . Figure 5 2 is a diagram showing a circuit configuration of the high-pass filter 21 .

[0032] like Figure 2 As shown, the sensor system SS1 includes a piezoelectric sensor 1 , a signal processing circuit 2 , and an MPU (MicroProcessing Unit) 3 .

[0033] In the present embodiment, the piezoelectric sensor 1 is a pressure sensor for detecting a pressing operation. The piezoelectric sensor 1 is installed in a touch panel display of an electronic device such as a smartphone, for example. The piezoelectric sensor 1 generates an electric charge corresponding to the amount of change in the user's pressing. Specifically, the user performs a pressing operation on the touch panel display. The touch panel display is deformed in response to the pressing. As a result, the piezoelectric sensor 1 installed in the touch panel display is deformed (stretched and compressed) in response to the pressing, thereby generating an electric charge.

[0034] like Figure 3 As shown, the piezoelectric sensor 1 includes a first electrode 10 , a piezoelectric film 11 and a second electrode 12 .

[0035] The following, such as Figure 3As shown, the vertical direction of the paper is set as the Z-axis direction (the thickness direction of the piezoelectric sensor 1), the left and right direction of the paper is set as the X-axis direction, and the direction orthogonal to the Z-axis direction and the X-axis direction is set as the Y-axis direction for explanation.

[0036] like Figure 3 As shown, the piezoelectric film 11 has a first main surface SF1 and a second main surface SF2 arranged in the Z-axis direction. In the present embodiment, the piezoelectric film 11 is, for example, a film with a chiral polymer as the main material. The chiral polymer is, for example, polylactic acid (PLA), in particular, L-type polylactic acid (PLLA) or D-type polylactic acid (PDLA). Polylactic acid is a chiral polymer with a helical structure in the main chain. Polylactic acid has piezoelectricity by being oriented in a specified axial direction. The piezoelectricity is represented by the piezoelectric tensor d14.

[0037] The piezoelectric film 11 is mounted on the touch panel display in such a manner that the stretching direction forms an angle of about 45° with the X-axis direction and the Y-axis direction. As a result, polarization is generated due to the expansion and contraction of the touch panel display in the X-axis direction or the Y-axis direction, and an output is generated in the piezoelectric sensor 1. That is, the piezoelectric film 11 is deformed in accordance with the deformation (extension and compression) of the touch panel display, thereby generating electric charge.

[0038] In addition, the extending direction does not necessarily need to form an exact 45-degree angle with the X-axis direction and the Y-axis direction. For example, the extending direction may be mounted on a touch panel display in such a manner that the extending direction forms an angle of about 45±10° with the X-axis direction and the Y-axis direction.

[0039] The first electrode 10 is a signal electrode. The first electrode 10 is attached to the first main surface SF1 by an adhesive (not shown) or the like. The first electrode 10 covers the first main surface SF1. The first electrode 10 is, for example, an organic electrode of ITO (indium tin oxide) or ZnO (zinc oxide). Alternatively, the first electrode 10 is a metal film formed by evaporation or plating or a printed electrode film formed by silver paste or the like.

[0040] The second electrode 12 is a reference voltage electrode. The second electrode 12 is connected to a reference voltage source. The second electrode 12 is attached to the second main surface SF2 by an adhesive (not shown) or the like. The second electrode 12 covers the second main surface SF2. The second electrode 12 is, for example, an organic electrode of ITO (indium tin oxide) or ZnO (zinc oxide). Alternatively, the second electrode 12 is a metal film formed by evaporation or plating or a printed electrode film formed by silver paste or the like.

[0041] like Figure 2 As shown in FIG. 1 , the signal processing circuit 2 is disposed between the piezoelectric sensor 1 and the MPU 3. The signal processing circuit 2 converts the charge output from the piezoelectric sensor 1 into a voltage signal and performs various signal processing on the voltage signal obtained by the conversion. Figure 2As shown, the signal processing circuit 2 includes a charge-to-voltage conversion circuit 20 , a high-pass filter 21 , an amplifier circuit 22 , a capacitor 23 , an AD (analog-to-digital) conversion circuit 24 , and a reference voltage generation circuit 25 .

[0042] like Figure 2 As shown, the charge-to-voltage conversion circuit 20 is disposed between the piezoelectric sensor 1 and the high-pass filter 21. The charge-to-voltage conversion circuit 20 converts the charge detected by the piezoelectric sensor 1 into a voltage. The magnitude and polarity of the charge generated in the piezoelectric film 11 are proportional to the differential value of the pressing amount. Figure 4 As shown, when the user presses the touch panel display, the polarity of the voltage output from the charge voltage conversion circuit 20 is positive. On the other hand, when the user releases the pressure on the touch panel display, the polarity of the voltage output from the charge voltage conversion circuit 20 is negative.

[0043] like Figure 2 As shown in FIG. 2 , the high-pass filter 21 is disposed between the charge-to-voltage conversion circuit 20 and the amplifier circuit 22. Figure 5 As shown, the high-pass filter 21 has a capacitor Cd1 and a variable resistor circuit 211. The capacitor Cd1 is connected in series with the signal line. The capacitor Cd1 has a capacitance value Cc1. The variable resistor circuit 211 is connected in parallel with the signal line. The variable resistor circuit 211 has a resistance value Rc. The high-pass filter 21 allows signals above the cut-off frequency fc determined by the resistance value Rc of the variable resistor circuit 211 and the capacitance value Cc1 of the capacitor Cd1 to pass. According to the resistance value Rc and the capacitance value Cc1, the cut-off frequency fc of the high-pass filter 21 is expressed as "fc=1 / (2π×Rc×Cc1)". Therefore, the high-pass filter 21 allows signals with a frequency above "1 / (2π×Rc×Cc1)" to pass.

[0044] A single-wave or burst-wave signal is input to the high-pass filter 21. The single-wave or burst-wave signal sometimes contains more than one frequency component. In this case, in the present embodiment, the frequency of the temporal peak component in the signal is defined as follows. That is, the maximum frequency component among the more than one frequency components contained in the signal processed by the high-pass filter 21.

[0045] In addition, the signal processed by the high-pass filter 21 sometimes contains a DC component. In this case, the frequency of the temporal peak component in the signal is defined as follows. That is, the maximum frequency component among one or more frequency components contained in the signal after the DC component is removed from the signal processed by the high-pass filter 21.

[0046] like Figure 2As shown in FIG. 2 , the amplifier circuit 22 is connected in series with the signal line. The amplifier circuit 22 amplifies the signal that has passed through the high-pass filter 21. The amplifier circuit 22 outputs the amplified signal to the capacitor 23.

[0047] like Figure 2 As shown in FIG. 2 , the capacitor 23 is disposed between the amplifier circuit 22 and the AD conversion circuit 24. The capacitor 23 is a DC shielding capacitor for removing a DC component included in a signal. The capacitor 23 has a capacitance value Cc23.

[0048] like Figure 2 As shown, the AD conversion circuit 24 is arranged between the capacitor 23 and the MPU 3. The AD conversion circuit 24 converts the analog signal output from the capacitor 23 into a digital signal (AD conversion).

[0049] The reference voltage generating circuit 25 generates a reference voltage PV. Figure 2 As shown, the reference voltage generating circuit 25 is electrically connected to the piezoelectric sensor 1 and the high-pass filter 21 .

[0050] The MPU 3 performs various processes, for example, by reading a program stored in a storage device (not shown) into a working memory (not shown). The various processes refer to processes for determining a user's pressing operation on the touch panel display. The MPU 3 is electrically connected to the AD conversion circuit 24. The MPU 3 receives an AD-converted signal from the AD conversion circuit 24. The MPU 3, for example, determines that a user has pressed the touch panel display when a signal value above a predetermined threshold value (stored in a storage device, etc.) is detected. In addition, the MPU 3 may also be, for example, a CPU (Central Processing Unit) or the like.

[0051] The signal processing circuit 2 involved in this embodiment can suppress the overshoot generated in the signal (such as Figure 1A Hereinafter, the detailed description will be given with reference to the accompanying drawings. Figure 6 : is a graph showing the relationship between the ratio of the cut-off frequency fc to the frequency of the signal and the ratio of the overshoot peak voltage OSP to the peak voltage SGP of the signal. Figure 6 In the figure, the horizontal axis is the ratio of the cutoff frequency fc to the frequency of the signal. Figure 6 In FIG. 8 , the vertical axis is the ratio of the overshoot peak voltage OSP to the signal peak voltage SGP.

[0052] In this embodiment, the peak voltage SGP of the signal is defined as "the voltage at which the difference DF1 between the voltage (signal) output from the piezoelectric sensor 1 and the reference voltage PV becomes maximum" (see Figure 1A and Figure 1B). In addition, the peak voltage OSP of the overshoot is defined as "the voltage at which the difference DF2 between the voltage (signal) and the reference voltage PV becomes maximum during the overshoot".

[0053] Figure 1B FIG. 2 shows an example of a signal input to the high-pass filter 21. When such a signal is subjected to signal processing by the high-pass filter 21, the following may occur: Figure 1A In this case, the peak voltage OSP of the overshoot may become above a predetermined threshold value (threshold value used in determining the pressing operation of the MPU 3). As a result, the MPU 3 may erroneously determine that the user has performed a pressing operation when the user has not performed a pressing operation due to the overshoot.

[0054] Therefore, the inventors of the present application have studied the cause of the overshoot. As a result, the inventors of the present application have noticed that "the overshoot varies depending on the relationship between the cutoff frequency fc of the high-pass filter 21 and the frequency of the input signal". The high-pass filter 21 removes the spectral components of the frequencies less than the cutoff frequency fc. Therefore, the waveform of the signal on the time axis is deformed. Here, in the signal having a peak component on the time axis, the spectral component extends to a frequency band lower than the fundamental frequency. When the cutoff frequency fc is increased, the removed low-frequency components increase. Therefore, the waveform of the signal on the time axis is greatly deformed. As a result, the peak voltage OSP of the overshoot becomes larger.

[0055] Therefore, the inventors of the present application believe that it is sufficient to reduce the cutoff frequency fc to a level that can avoid the erroneous judgment of the MPU 3. The inventors of the present application obtained the following results through experiments: if "the ratio of the overshoot peak voltage OSP to the signal peak voltage SGP is less than 0.2", the erroneous judgment of the MPU 3 can be avoided. In addition, the inventors of the present application obtained the following results through experiments (refer to Figure 6 ): When the condition "the ratio of the cut-off frequency fc to the frequency of the peak component of the signal is less than 1 / 10" (hereinafter referred to as condition A) is met, "the peak voltage of the overshoot becomes less than 0.2 of the peak voltage of the signal". In the high-pass filter 21, the cut-off frequency fc is "fc = 1 / (2π×Rc×Cc1)". Therefore, the inventor of the present application thought of a method of reducing the cut-off frequency fc by increasing the resistance value Rc.

[0056] Therefore, the present invention makes the resistance value Rc variable to suppress overshoot and realize a practical operating time as a sensor. Figure 7 2 is a diagram showing the variable resistance circuit 211 .

[0057] In this embodiment, if Figure 7As shown, the variable resistance circuit 211 is a switched capacitor having switches S1, S2 and a capacitor Cd2. Both the switch S1 and the switch S2 are equivalent to the first switch in the present invention. The capacitor Cd2 is connected in parallel with the signal line. The capacitor Cd2 has a capacitance value Cc2. The switch S1 is arranged between the signal line and the capacitor Cd2. The switch S2 is connected in parallel with the capacitor Cd2.

[0058] The resistance value Rc of the variable resistance circuit 211 is the equivalent resistance value of the switch capacitor determined based on the switching frequency fs used in the switching of the switches S1 and S2. Specifically, the equivalent resistance value Rc of the switch capacitor is "Rc = 1 / (fs × Cc2)". Therefore, as the switching frequency fs increases, the equivalent resistance value Rc of the switch capacitor decreases. In addition, the switching of the switches S1 and S2 is performed by a processing device (not shown) such as a CPU (Central Processing Unit), for example.

[0059] When the target signal passes through the high-pass filter 21, the variable resistor circuit 211 increases the resistance value Rc (reduces the switching frequency fs). Specifically, the variable resistor circuit 211 increases the resistance value Rc (first resistance value) so that the cutoff frequency fc of the high-pass filter 21 becomes 1 / 10 or less of the frequency of the peak component on the time axis of the signal (so as to satisfy the condition A). In this case, Figure 6 As shown in FIG. 1 , the ratio of the overshoot peak voltage OSP to the signal peak voltage SGP is 0.2 or less. Therefore, the possibility that the MPU 3 erroneously determines that the user has performed a pressing operation when the user has not performed a pressing operation due to the overshoot is reduced.

[0060] Here, a waiting time of about time constant τ is required from the start of the sensor system SS1 until the high-pass filter 21 can perform the desired action. Specifically, in order for the circuit of the sensor system SS1 to perform the desired action, the capacitor Cd1 needs to be charged to a charge amount determined by the DC voltage biased at both ends of the capacitor Cd1 and the capacitance of the capacitor Cd1. In order to achieve this state, the sensor system SS1 needs a waiting time of about "time constant τ = Rc × Cc" after the sensor system SS1 is started. In other words, by reducing the time constant τ, the waiting time during use can be reduced.

[0061] For example, in the present embodiment, the capacitance value Cc1 of the capacitor Cd1 is 0.1μF, and the capacitance value Cc2 of the capacitor Cd2 is 6.5pF. In addition, the switching frequency fs of the switching capacitor is, for example, 5kHz. In this case, the cutoff frequency fc of the high-pass filter 21 is approximately 0.05Hz. Therefore, the cutoff frequency fc becomes the frequency of the input signal: 1 / 10 or less of 1Hz. Here, the time constant τ of the high-pass filter 21 is represented by "τ=1 / (2π×fc)". Therefore, when the cutoff frequency fc of the high-pass filter 21 is 0.05Hz, the time constant τ is approximately 3sec. In other words, in order to use the sensor system SS1 to perform the desired action, the user needs to wait for at least 3sec. As a result, the user may feel uncomfortable when using the sensor system SS1.

[0062] Therefore, at a time other than when the target signal passes through the high-pass filter 21 (except when the signal is processed), the variable resistor circuit 211 sets the resistance value Rc to a second resistance value lower than the first resistance value (increasing the switching frequency fs). The time other than when the target signal passes through the high-pass filter 21 is, for example, when the user turns on the power of an electronic device such as a smartphone (when the sensor system SS1 is started). As a result, the time constant τ of the high-pass filter 21 becomes shorter than when the target signal passes through the high-pass filter 21.

[0063] For example, if the switching frequency fs of the switched capacitor becomes 500kHz, which is 100 times the above 5kHz, the time constant τ becomes about 30msec, which is 1 / 100. Therefore, the time required for the user to start the sensor system SS1 and use it is about 30msec. 30msec is a time so short that it is almost imperceptible to humans. Therefore, the user is unlikely to feel uncomfortable. That is, the signal processing circuit 2 involved in this embodiment can realize practical operation as the sensor system SS1.

[0064] The variable resistance circuit 211 may have any structure as long as it can change the resistance value Rc. For example, the variable resistance circuit 211 may be a variable resistor.

[0065] In addition, the piezoelectric sensor 1 does not necessarily need to be a pressure sensor.

[0066] In addition, Figure 1A and Figure 1B In the example shown, the signal input to the signal processing circuit 2 is a single-shot waveform. However, a burst waveform signal including two or more continuous waves may be input to the signal processing circuit 2. In this case, the signal processing circuit 2 can suppress overshoot generated in the burst waveform input signal.

[0067] In addition, the high-pass filter 21 sometimes processes a signal having multiple frequencies. In this case, the cutoff frequency fc only needs to be 1 / 10 or less of the lowest frequency among the multiple frequencies included in the signal. The case where the signal has multiple frequencies refers to, for example, the case where the sensor system SS1 has multiple piezoelectric sensors 1, or the case where the speed at which the piezoelectric sensor 1 is deformed changes due to the change in the speed at which the user presses the touch panel display.

[0068] also, Figure 1B The signal input to the high-pass filter 21 shown in FIG. 2 is an example. Therefore, the signal input to the high-pass filter 21 may not necessarily be the same as Figure 1B The signals shown are identical.

[0069] (Variant 1)

[0070] Hereinafter, a signal processing circuit 2 a according to Modification 1 will be described with reference to the drawings. Figure 8 1 is a diagram showing a reference voltage generating circuit 25 a included in a signal processing circuit 2 a according to Modification 1. FIG.

[0071] In this modification, the signal processing circuit 2a includes a reference voltage generating circuit 25a instead of the reference voltage generating circuit 25. Figure 8 As shown, the reference voltage generating circuit 25a includes a reference voltage source Pa, a buffer amplifier Ap1a, and a switch S1a (second switch). The reference voltage source Pa generates a reference voltage. The buffer amplifier Ap1a is arranged between the output of the reference voltage source Pa and the circuit to which the reference voltage is supplied. For example, the buffer amplifier Ap1a is connected in series with the variable resistor circuit 211 and the reference voltage source Pa. The switch S1a is connected in parallel with the buffer amplifier Ap1a. The buffer amplifier Ap1 increases the current supplied from the reference voltage source Pa.

[0072] As the switching frequency fs becomes higher, the speed of charging the capacitor Cd2 becomes faster. At this time, the charging speed of the capacitor Cd2 may exceed the current supply capacity of the reference voltage source Pa. In this case, it may not be possible to charge the capacitor Cd2 with the target charging time (for example, 30msec). In other words, as the sensor system SS1, it may be difficult to achieve practical operation. Therefore, when the resistance value Rc of the variable resistance circuit 211 is set to the second resistance value, the buffer amplifier Ap1 is set to be turned on, and the switch S1a is turned off. As a result, the current supplied from the reference voltage source Pa is increased to reduce the possibility that the charging speed of the capacitor Cd2 exceeds the current supply capacity of the reference voltage source Pa.

[0073] On the other hand, when the resistance value Rc of the variable resistor circuit 211 is set to the first resistance value (when the switching frequency fs is low), the buffer amplifier Ap1a is set to be turned off, and the switch S1a is set to be turned on. That is, when there is no need to increase the current input to the capacitor Cd2, the buffer amplifier Ap1a is set to be turned off. This can prevent unnecessary power consumption in the buffer amplifier Ap1a.

[0074] also, Figure 8 The circuit structure of the reference voltage generating circuit 25a shown in FIG. 1 is an example. Therefore, the circuit structure of the reference voltage generating circuit 25a does not need to be Figure 8 The circuit structure shown.

[0075] (Variant 2)

[0076] Hereinafter, a signal processing circuit 2 b according to Modification 2 will be described with reference to the drawings. Fig. 9 1 is a diagram showing an AD conversion circuit 24 b included in a signal processing circuit 2 b according to Modification 2.

[0077] In this modification, the signal processing circuit 2b includes an AD conversion circuit 24b instead of the AD conversion circuit 24. Fig. 9 As shown, the AD conversion circuit 24b has a sample-and-hold circuit 24b1 and an integration circuit 24b2.

[0078] The sampling and holding circuit 24b1 is configured on the input side of the integration circuit 24b2. In this modification, the sampling and holding circuit 24b1 is a switched capacitor having switches S1b, S2b, S3b, S4b and a capacitor Cd1b (hereinafter referred to as a switched capacitor involved in Modification 2). The switches S1b and S3b are connected in series with the signal line. The switches S2b and S4b are connected in parallel with the signal line. The switches S1b and S2b are configured on the input side of the capacitor Cd1b. The switches S3b and S4b are configured on the output side of the capacitor Cd1b. The capacitor Cd1b is configured between the switch S1b and the switch S3b. The capacitor Cd1b has a capacitance value Ccb.

[0079] The sampling and holding circuit 24b1 performs a sampling and holding process of a signal by switching switches S1b, S2b, S3b, and S4b. Specifically, the sampling and holding circuit 24b1 turns on switches S1b and S4b, and turns off switches S2b and S3b. Thus, the sampling and holding circuit 24b1 charges the capacitor Cd1b and performs sampling and holding. Then, the sampling and holding circuit 24b1 turns off switches S1b and S4b, and turns on switches S2b and S3b. Thus, the sampled and held signal is output to the integration circuit 24b2. The switching of the switches S1b, S2b, S3b, and S4b is performed based on the switching frequency fsb.

[0080] The sample and hold circuit 24b1 shown in the above structure is the same as Figure 2 The signal line on the output side of the capacitor 23 shown is equivalent to the case where the reference voltage is connected in parallel via a resistor. That is, the sampling and holding circuit 24b1 is equivalent to the variable resistor circuit in the present invention, and the sampling and holding circuit 24b1 and the capacitor 23 constitute a high-pass filter (hereinafter referred to as the high-pass filter involved in Modification 2). At this time, the resistance value Rb of the high-pass filter involved in Modification 2 is the equivalent resistance value of the switching capacitor (hereinafter referred to as the switching capacitor involved in Modification 2) determined based on the switching frequency fsb used in the switching of switches S1b, S2b, S3b, and S4b and the capacitance value Ccb of the capacitor Cd1b. Specifically, the resistance value Rb is "Rb = 1 / (fsb×Ccb)".

[0081] The high-pass filter involved in Modification Example 2 allows signals above the cutoff frequency fcb determined by the equivalent resistance value Rb of the switched capacitor involved in Modification Example 2 and the capacitance value Ccb of the capacitor Cd1b to pass. Specifically, the cutoff frequency fcb is expressed as "fcb = 1 / (2π×Rb×Ccb)". In this case, as with the high-pass filter 21, the waveform of the signal on the time axis is greatly deformed according to the high-pass filter involved in Modification Example 2. As a result, the peak voltage OSP of the overshoot becomes larger. Therefore, when the target signal passes through the high-pass filter involved in Modification Example 2, the resistance value Rb is set so that the cutoff frequency fcb is less than 1 / 10 of the frequency of the signal. For example, in this modification, the capacitance value Cc23 of the capacitor 23 is 0.082pF, and the capacitance value Ccb of the capacitor Cd1b is 3.5pF. In addition, the switching frequency fsb of the switched capacitor involved in Modification Example 2 is, for example, about 5kHz. At this time, the cutoff frequency fcb of the high-pass filter involved in the second modification is about 0.034 Hz, which is less than 1 / 10 of the frequency of the input signal: 1 Hz. Therefore, the ratio of the peak voltage OSP of the overshoot to the peak voltage SGP of the signal becomes less than 0.2 (refer to Figure 6). Thus, similarly to the signal processing circuit 2 according to the first embodiment, according to the signal processing circuit 2b, the possibility of the MPU 3 making an erroneous determination can be reduced.

[0082] Here, the time constant τb of the high-pass filter according to Modification 2 is expressed as “τb=1 / (2π×fcb)” and is approximately 4.7 seconds. Therefore, similarly to the signal processing circuit 2 according to the first embodiment, the user may feel uncomfortable when the sensor system SS1 is activated.

[0083] Therefore, the signal processing circuit 2b sets the switching frequency fsb to be higher than the switching frequency when the target signal passes through the high-pass filter, except when the target signal passes through the high-pass filter. For example, the signal processing circuit 2b sets the switching frequency fsb to 500kHz, which is about 100 times. In this case, the time constant τb is 1 / 100 of 4.7sec, that is, about 47msec. 47msec is a time so short that it is almost imperceptible to humans. Therefore, the user is not likely to feel uncomfortable. That is, the signal processing circuit 2b involved in the modification 2 can realize practical operation as the sensor system SS1.

[0084] The integration circuit 24b2 includes an amplifier Ap1b and a capacitor Cd2b. The amplifier Ap1b of the integration circuit 24b2 is disposed between the switch S3b and the MPU 3. The capacitor Cd2b is connected in parallel to the amplifier Ap1b. The amplifier Ap1b and the capacitor Cd2b perform a process of integrating a signal input to the integration circuit 24b2.

[0085] also, Fig. 9 The circuit structure of the AD conversion circuit 24b shown in FIG. 1 is an example. Therefore, the circuit structure of the AD conversion circuit 24b does not necessarily need to be Fig. 9 The circuit structure shown.

[0086] (Variant 3)

[0087] Hereinafter, a signal processing circuit 2c according to Modification 3 will be described with reference to the drawings. Fig.10 1 is a diagram showing a high-pass filter 21 c included in a signal processing circuit 2 c according to Modification 3.

[0088] like Fig.10 As shown, the signal processing circuit 2c includes a high-pass filter 21c instead of the high-pass filter 21. The high-pass filter 21c includes a variable resistance circuit 211c instead of the variable resistance circuit 211.

[0089] The variable resistor circuit 211c includes a switch S1c, a buffer amplifier Ap1c, and a fixed resistor R1c. The fixed resistor R1c is connected in parallel with the signal line. The switch S1c (third switch) and the buffer amplifier Ap1c are connected in parallel with the fixed resistor R1c. The buffer amplifier Ap1c is connected in series with the switch S1c. In addition, the fixed resistor R1c may also be a variable resistor, a switched capacitor, or the like.

[0090] In this modification, when the target signal passes through the high-pass filter 21c, the variable resistor circuit 211c turns off the switch S1c. In this case, the resistance value Rcc of the variable resistor circuit 211c is determined by the resistance value (first resistance value) of the fixed resistor R1c. In this modification, the resistance value of the fixed resistor R1c is a value that satisfies the condition A (the resistance value when the cutoff frequency of the high-pass filter 21c is less than 1 / 10 of the frequency of the signal). Therefore, Figure 6 As shown in FIG. 1 , the ratio of the overshoot peak voltage OSP to the signal peak voltage SGP is 0.2 or less. Therefore, similarly to the signal processing circuit 2 , the possibility of the MPU 3 making an erroneous determination can be reduced.

[0091] On the other hand, the high-pass filter 21c turns on the switch S1c and sets the buffer amplifier Ap1c to be turned on at times other than when the target signal passes through the high-pass filter 21c. As a result, the fixed resistor R1c is bypassed. In this case, the high-pass filter 21c changes the resistance value Rcc from a value (first resistance value) mainly determined by the resistance value of the fixed resistor R1c to a value (second resistance value) determined by the actual resistance value of the entire circuit including the buffer amplifier Ap1c and the wiring. The actual resistance value of the entire circuit including the buffer amplifier Ap1c and the wiring is lower than the resistance value of the fixed resistor R1c. Therefore, compared with the case where the switch S1c is turned off, the time required to charge the capacitor Cd2 becomes shorter. That is, similar to the signal processing circuit 2, according to the signal processing circuit 2c, as the sensor system SS1, practical operation can be achieved.

[0092] The buffer amplifier Ap1c is set to be off when the switch S1c is turned off (when the resistance value Rcc is set to the first resistance value). This can prevent unnecessary power consumption in the buffer amplifier Ap1c.

[0093] In addition, when the current supply amount of the reference voltage source is sufficient to achieve the target time constant (for example, 100 msec), the variable resistance circuit 211 c may not include the buffer amplifier Ap1 c.

[0094] The variable resistance circuit 211c may include a variable resistor or a switched capacitor capable of changing the resistance value instead of the fixed resistor R1c. In this case, the signal processing circuit 2c also achieves the same effect as that of the case of including the fixed resistor R1c.

[0095] Furthermore, the variable resistor circuits 211 and 211c only need to be set to a second resistance value lower than the first resistance value at any time except when the target signal passes through the high-pass filter. Therefore, the variable resistor circuits 211 and 211c can also maintain the first resistance value at any time except when the target signal passes through the high-pass filter.

[0096] Furthermore, the variable resistance circuits 211 and 211 c may be always set to a second resistance value lower than the first resistance value except when the target signal is passed through the high-pass filter.

[0097] Furthermore, the structures of the signal processing circuits 2 and 2a to 2c may be arbitrarily combined.

[0098] The present invention has the following configuration.

[0099] (1) A signal processing circuit comprising:

[0100] a capacitor connected to a signal line connected to the sensor and connected in series with the signal line; and

[0101] a variable resistance circuit connected in parallel with the signal line,

[0102] The variable resistance circuit and the capacitor form a high-pass filter that passes signals above the cutoff frequency.

[0103] When a target signal having a peak component on a time axis is passed through the high-pass filter, the variable resistance circuit is set to a first resistance value,

[0104] The cutoff frequency at the first resistance value is less than or equal to 1 / 10 of the frequency of the peak component.

[0105] (2) The signal processing circuit according to (1), wherein:

[0106] At any time when the target signal does not pass through the high pass filter, the variable resistance circuit is set to a second resistance value lower than the first resistance value.

[0107] (3) The signal processing circuit according to (1), wherein:

[0108] The variable resistance circuit is always set to a second resistance value lower than the first resistance value except when the target signal is passed through the high-pass filter.

[0109] (4) The signal processing circuit according to (2) or (3), wherein:

[0110] The variable resistance circuit includes a switched capacitor having a capacitor and a first switch,

[0111] The variable resistance circuit changes the first resistance value to the second resistance value by increasing a switching frequency of the first switch.

[0112] (5) The signal processing circuit according to (2) or (3), wherein:

[0113] The variable resistance circuit is a variable resistor.

[0114] (6) The signal processing circuit according to (4) or (5), wherein:

[0115] The signal processing circuit comprises:

[0116] a buffer amplifier connected in series with the variable resistance circuit and the reference voltage source; and

[0117] a second switch connected in parallel with the buffer amplifier,

[0118] When the first resistance value is set, the buffer amplifier is set to be disconnected.

[0119] When the second resistance value is set, the buffer amplifier is set to be turned on.

[0120] When the first resistance value is set, the second switch is set to be turned on.

[0121] When the second resistance value is set, the second switch is set to be off.

[0122] (7) The signal processing circuit according to (2) or (3), wherein:

[0123] The variable resistance circuit comprises:

[0124] Resistors; and

[0125] a third switch connected in parallel with the resistor,

[0126] By turning on the third switch, the first resistance value is changed to the second resistance value.

[0127] (8) The signal processing circuit according to (7), wherein:

[0128] The variable resistance circuit further includes a buffer amplifier connected in series with the third switch,

[0129] When the first resistance value is set, the buffer amplifier is set to be disconnected.

[0130] When the second resistance value is set, the buffer amplifier is set to be turned on.

[0131] (9) The signal processing circuit according to any one of (1) to (8), wherein:

[0132] The signal processing circuit further comprises:

[0133] a charge-to-voltage conversion circuit for converting the charge of the sensor into a voltage; and

[0134] an amplifier circuit, which amplifies the signal,

[0135] The capacitor and the variable resistance circuit are arranged between the charge-voltage conversion circuit and the amplifier circuit.

[0136] (10) The signal processing circuit according to any one of (1) to (8), wherein:

[0137] The signal processing circuit further comprises:

[0138] an amplifier circuit for amplifying the signal; and

[0139] The AD conversion circuit has an integration circuit for performing AD conversion on the signal.

[0140] The variable resistance circuit is arranged on the input side of the integration circuit.

[0141] (11) The signal processing circuit according to any one of (1) to (10), wherein:

[0142] The sensor is a press sensor that detects a press operation.

[0143] Description of Reference Numerals

[0144] 1: piezoelectric sensor; 2, 2a, 2b, 2c: signal processing circuit; 20: charge-voltage conversion circuit; 21, 21c: high-pass filter; 22: amplifier circuit; 23: capacitor; 24, 24b: AD conversion circuit; 211, 211c: variable resistance circuit; Cd1, Cd1b, Cd2, Cd2b: capacitor; Rb, Rc, Rcc: resistance value; fc, fcb: cut-off frequency; fs, fsb: switching frequency; τ, τb: time constant.

Claims

1. A signal processing circuit comprising: a capacitor connected to a signal line connected to the sensor and connected in series with the signal line; and a variable resistance circuit connected in parallel with the signal line, in, The variable resistance circuit and the capacitor form a high-pass filter that passes signals above the cutoff frequency. When a target signal having a peak component on a time axis is passed through the high-pass filter, the variable resistance circuit is set to a first resistance value, The cutoff frequency at the first resistance value is less than or equal to 1 / 10 of the frequency of the peak component.

2. The signal processing circuit according to claim 1, wherein: At any time when the target signal does not pass through the high pass filter, the variable resistance circuit is set to a second resistance value lower than the first resistance value.

3. The signal processing circuit according to claim 1, wherein: The variable resistance circuit is always set to a second resistance value lower than the first resistance value except when the target signal is passed through the high-pass filter.

4. The signal processing circuit according to claim 2 or 3, wherein: The variable resistance circuit includes a switched capacitor having a capacitor and a first switch, The variable resistance circuit changes the first resistance value to the second resistance value by increasing a switching frequency of the first switch.

5. The signal processing circuit according to claim 2 or 3, wherein: The variable resistance circuit is a variable resistor.

6. The signal processing circuit according to claim 4, wherein: The signal processing circuit comprises: a buffer amplifier connected in series with the variable resistance circuit and the reference voltage source; and a second switch connected in parallel with the buffer amplifier, When the first resistance value is set, the buffer amplifier is set to be disconnected. When the second resistance value is set, the buffer amplifier is set to be turned on. When the first resistance value is set, the second switch is set to be turned on. When the second resistance value is set, the second switch is set to be off.

7. The signal processing circuit according to claim 5, wherein: The signal processing circuit comprises: a buffer amplifier connected in series with the variable resistance circuit and the reference voltage source; and a second switch connected in parallel with the buffer amplifier, When the first resistance value is set, the buffer amplifier is set to be disconnected. When the second resistance value is set, the buffer amplifier is set to be turned on. When the first resistance value is set, the second switch is set to be turned on. When the second resistance value is set, the second switch is set to be off.

8. The signal processing circuit according to claim 2 or 3, wherein: The variable resistance circuit comprises: Resistors; and a third switch connected in parallel with the resistor, By turning on the third switch, the first resistance value is changed to the second resistance value.

9. The signal processing circuit according to claim 8, wherein: The variable resistance circuit further includes a buffer amplifier connected in series with the third switch, When the first resistance value is set, the buffer amplifier is set to be disconnected. When the second resistance value is set, the buffer amplifier is set to be turned on.

10. The signal processing circuit according to any one of claims 1 to 9, wherein: The signal processing circuit further comprises: a charge-to-voltage conversion circuit for converting the charge of the sensor into a voltage; and an amplifier circuit for amplifying the signal, The capacitor and the variable resistance circuit are arranged between the charge-voltage conversion circuit and the amplifier circuit.

11. The signal processing circuit according to any one of claims 1 to 9, wherein: The signal processing circuit further comprises: an amplifier circuit for amplifying the signal; as well as The analog-to-digital conversion circuit includes an integration circuit for performing analog-to-digital conversion on the signal, wherein the variable resistance circuit is arranged on the input side of the integration circuit.

12. The signal processing circuit according to any one of claims 1 to 11, wherein: The sensor is a press sensor that detects a press operation.

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