Multilayer ceramic capacitor

Abstract

A laminated ceramic capacitor is provided with: a laminated body having a plurality of laminated dielectric layers and a plurality of internal electrodes formed along the interfaces between the dielectric layers; a plurality of external electrodes formed on the outer surface of the laminate and electrically connected to the internal electrodes; the dielectric layer contains, as a main component, a perovskite-type compound containing Ba and Ti (wherein a portion of Ba may be substituted by Ca and a portion of Ti may be substituted by Zr); the total of the resistance values of the main component and other components contained in the dielectric layer as measured by an AC impedance method is 1 M [omega] or more.

Description

Technical Field

[0001] The present disclosure relates to a stacked ceramic capacitor. Background Art

[0002] A conventional multilayer ceramic capacitor is described in Patent Document 1, for example.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent No. 5757319 Summary of the invention

[0006] The laminated ceramic capacitor disclosed herein is characterized in that it comprises: a laminate having a plurality of laminated dielectric layers and a plurality of internal electrodes formed along interfaces between the dielectric layers; a plurality of external electrodes formed on the outer surface of the laminate and electrically connected to the internal electrodes; the dielectric layer comprising a perovskite compound containing Ba and Ti (wherein a portion of Ba may be substituted by Ca, and a portion of Ti may be substituted by Zr) as a main component; and the total resistance value of the main component and other components contained in the dielectric layer measured by an AC impedance method is 1 MΩ or more.

[0007] In addition, the multilayer ceramic capacitor disclosed in the present invention is characterized in that it is divided into four components, namely, a core as the central part of the grain of the main component and other components in the dielectric layer, a shell as the outer periphery of the grain, a grain boundary phase, and an interface between the internal electrode and the dielectric layer, and each component is set as a parallel circuit of a resistor R and a capacitor C, and is represented by an equivalent circuit model in which each component is connected in series; when the resistance value of the core measured by an AC impedance method is set to R1, the resistance value of the shell is set to R2, the resistance value of the grain boundary is set to R3, and the resistance value of the interface is set to R4, the total value of R1, R2, R3, and R4 is greater than 1MΩ. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The objects, features and advantages of the present disclosure will become more apparent from the following detailed description and accompanying drawings.

[0009] Figure 1A 1 is a schematic cross-sectional view showing a multilayer ceramic capacitor of the present disclosure.

[0010] Figure 1B yes Figure 1A Magnified view of area IB.

[0011] Figure 2It is a schematic cross-sectional view showing the internal structure of crystal grains of a perovskite compound containing Ba and Ti in a dielectric layer constituting the multilayer ceramic capacitor of the present disclosure.

[0012] Figure 3 It is an AC impedance measurement device.

[0013] Figure 4 This is a diagram showing a Cole-Cole plot of a conventional multilayer ceramic capacitor.

[0014] Figure 5 This is a diagram showing an equivalent circuit used for analysis.

[0015] Fig. 6A The following is a process diagram showing a method for manufacturing the multilayer ceramic capacitor disclosed in the present invention.

[0016] Figure 6B The following is a process diagram showing a method for manufacturing the multilayer ceramic capacitor disclosed in the present invention.

[0017] Figure 6C The following is a process diagram showing a method for manufacturing the multilayer ceramic capacitor disclosed in the present invention.

[0018] Fig.6D The following is a process diagram showing a method for manufacturing the multilayer ceramic capacitor disclosed in the present invention.

[0019] Figure 7 This is a graph showing the total value of the resistance values ​​of the four components in Table 3 by the AC impedance method.

[0020] Figure 8 This is a graph showing the relationship between the core resistance value R1 and the insulation resistance.

[0021] Fig. 9 It is a graph showing the relationship between the case resistance value R2 and the insulation resistance.

[0022] Fig.10 This is a graph showing the relationship between the grain boundary phase resistance value R3 and the insulation resistance.

[0023] Fig.11 This is a graph showing the relationship between the interface resistance value R4 between the internal electrode and the dielectric layer and the insulation resistance.

[0024] Fig.12 This is a graph showing the relationship between R1, R2, R3, R4 and insulation resistance. DETAILED DESCRIPTION

[0025] In recent years, there has been a demand for further miniaturization and higher capacity of multilayer ceramic capacitors, and the dielectric layer has been thinning. However, when the dielectric layer is thinned, the electric field strength applied to each layer becomes relatively high, so it is necessary to improve the reliability when voltage is applied. As a prior art of this kind, for example, a multilayer ceramic capacitor has been proposed, in which an internal electrode mainly composed of Ni contains Sn at a specific ratio, so that even when a voltage with a high electric field strength is applied, it shows good dielectric properties and excellent reliability (for example, refer to Patent Document 1).

[0026] However, even in the above-mentioned multilayer ceramic capacitor, the insulation is not sufficient, and therefore the reliability when voltage is applied is not sufficient. Therefore, there is a need for a multilayer ceramic capacitor that improves the insulation of the dielectric layer and improves the reliability when voltage is applied.

[0027] Hereinafter, embodiments of the multilayer ceramic capacitor of the present disclosure will be described with reference to the drawings.

[0028] Figure 1A is a schematic cross-sectional view showing a multilayer ceramic capacitor disclosed in the present invention, Figure 1B yes Figure 1A The laminated ceramic capacitor disclosed in the present invention comprises a capacitor body 1 and external electrodes 3 and 4 provided on both end surfaces of the capacitor body 1. The capacitor body 1 is a structure in which dielectric layers 5 and internal electrodes 7 are alternately laminated. The dielectric layer 5 is composed of a plurality of crystal grains 11 of a perovskite compound containing Ba and Ti separated by grain boundaries 9.

[0029] Examples of the material of the external electrodes 3 and 4 include materials containing Ag or Cu as a main component. The internal electrode 7 is electrically connected to the external electrodes 3 and 4 , respectively.

[0030] The main component of the internal electrode 7 is Ni. The internal electrode 7 may contain Sn or may not contain Sn. Preferably, the internal electrode 7 contains Sn. Preferably, the content of Sn is 0.5 to 5 parts by mass relative to 100 parts by mass of Ni. When the content of Sn in the internal electrode 7 is 5 parts by mass or more, there are cases where the electrode melts and the reliability deteriorates, and when it is less than 0.5 parts by mass, the reliability cannot be expected to be improved.

[0031] In this way, when the raw material of the internal electrode 7 contains Sn, Sn diffuses into the dielectric layer 5 (a part of Sn remains in the internal electrode 7) during the firing process of manufacturing the multilayer ceramic capacitor. The diffusion of Sn occurs at the interface 6 between the dielectric layer 5 and the internal electrode 7, and Sn moves from the center to the interface inside the internal electrode 7. In this way, the Sn content of the interface on the dielectric layer 5 side of the internal electrode 7 becomes higher than the Sn content of the center in the thickness direction of the internal electrode 7. As a result, the m value becomes higher in the evaluation of the failure time of the HALT test of the multilayer ceramic capacitor, and the failure time does not vary. In addition, the CR product becomes higher, and the reliability of the multilayer ceramic capacitor is improved.

[0032] As described above, the Sn content at the interface of the internal electrode 7 on the dielectric layer 5 side is higher than the Sn content at the center of the internal electrode 7. This can be adjusted so that the Sn content has a peak not inside the internal electrode 7 but at the interface between the internal electrode 7 and the dielectric layer 5 by, for example, using a heat-resistant material also called a silicon carbide (SiC) placer and performing high-speed sintering.

[0033] The dielectric layer 5 contains a perovskite compound containing Ba and Ti (wherein a part of Ba may be substituted with Ca, and a part of Ti may be substituted with Zr) as a main component.

[0034] The perovskite compound containing Ba and Ti may be barium titanate (hereinafter, sometimes referred to as BT) or a perovskite barium titanate in which a portion of Ba (A position) is replaced by Ca (hereinafter, sometimes referred to as BCT). 1-x Ca x )TiO3. Here, the Ca substitution amount in the A position of the BCT powder is preferably X=0.01 to 0.2, and particularly preferably X=0.03 to 0.1. In addition, it may be a perovskite-type barium titanate in which a part of Ti in the B position is substituted by Zr.

[0035] Among them, barium titanate is preferred. Barium titanate has a high dielectric constant and enables the multilayer ceramic capacitor to exhibit excellent reliability.

[0036] In addition, BT powder and BCT powder (hereinafter, sometimes simply referred to as dielectric powder) are synthesized by mixing compounds containing Ba components, Ca components, and Ti components to a predetermined composition. These dielectric powders can be obtained by a synthesis method selected from a liquid phase method such as a coprecipitation method and an oxalate method, and a hydrothermal synthesis method.

[0037] The product of the lattice constants a, b, and c of the dielectric obtained by the oxalate method is 0.0653 nm 3 Above, in the case of solid phase method, it is 0.0652nm3 As for the measurement method of the lattice constant, for dielectric ceramics, the lattice constants a, b, and c can be obtained by performing X-ray diffraction measurement at a 2θ angle of 10 to 80 degrees and performing Rietveld crystal structure analysis.

[0038] Furthermore, from the viewpoint of making it easy to reduce the thickness of dielectric layer 5 and increasing the relative dielectric constant of dielectric powder, the particle size distribution of BT powder and BCT powder is preferably 0.05 to 0.1 μm.

[0039] Generally, in the case of dielectric powders such as BT powder and BCT powder, additives such as MgO, oxides of rare earth elements, and MnO are coated on the surface of the powder to dissolve the additives.

[0040] Mg has a barrier effect of improving the insulation of dielectric powder when covering the surface of dielectric powder and inhibiting the solid solution of other additives when other additives are added later. In addition, Mn also contributes to high insulation, but Mn has a particularly good effect of improving reduction resistance.

[0041] In addition, rare earth elements also contribute to improving the insulation of barium titanate, and have the effect of increasing the relative dielectric constant and stabilizing the temperature characteristics of the relative dielectric constant. In particular, when using BT powder coated with rare earth elements, the rare earth elements are easily formed in a layer on the surface of the BT powder.

[0042] Preferably, the amount of Mg added is 0.5 to 1 mol% in terms of oxide relative to 100 mol% of dielectric powder such as BCT powder or BT powder, and preferably, the amount of Mn added is 0.2 to 0.5 mol% in terms of oxide relative to 100 mol% of dielectric powder such as BCT powder or BT powder.

[0043] Preferably, the rare earth element added to the dielectric powder is 0.5 to 3 mol% in terms of oxide relative to 100 mol% of the dielectric powder such as BT powder or BCT powder. The rare earth element is preferably at least one of Y, Dy, Yb, Tb, and the like.

[0044] As a sintering aid added to a dielectric powder such as BT powder or BCT powder, a sol-gel glass having a composition of BaO:CaO:SiO2=25-35:45-55:15-25 is preferred.

[0045] In addition, when the raw material of the internal electrode 7 contains Sn, the Sn in the internal electrode 7 diffuses into the dielectric layer 5 during the firing process, so that the dielectric layer 5 contains Sn. In addition, preferably, the dielectric layer 5 contains 0.03 to 3 parts by mass of Sn relative to 100 parts by mass of BT. Thus, a laminated ceramic capacitor with improved insulation of the dielectric layer 5 and improved reliability when a voltage is applied can be provided. SnO is weighed and added to the raw material of the internal electrode so that the amount of Sn contained in the internal electrode after forming the laminated ceramic capacitor and the amount of Sn contained in the dielectric layer 5 after forming the laminated ceramic capacitor become the values ​​of Table 1 described later.

[0046] As described above, among “the main component and other components contained in the dielectric layer 5 ”, examples of other components include MgO, oxides of rare earth elements, MnO, BaO, CaO, SiO 2 , SnO 2 , and the like.

[0047] In the present disclosure, the total resistance value of the main component and other components contained in the dielectric layer 5 measured by the AC impedance method is 1 MΩ or more. This can provide a laminated ceramic capacitor having improved insulation properties of the dielectric layer 5 and improved reliability when voltage is applied.

[0048] In addition, the dielectric layer 5 can be divided into four components, in addition to the core of the central part of the crystal grains of the main component and other components of the perovskite type compound, the shell of the outer periphery of the crystal grain, the grain boundary phase, and the interface between the internal electrode 7 and the dielectric layer 5. Since the dielectric layer 5 sometimes contains holes, etc., sometimes it is impossible to measure all the resistance values ​​in the dielectric layer 5 only by the resistance values ​​of the components of the dielectric layer 5. Therefore, it is preferable to divide into four components as described above and measure the resistance value for each component.

[0049] That is, one embodiment of the present disclosure is divided into four components, namely: the core of the central part of the grain of the main component of the perovskite compound and other components in the dielectric layer 5, the shell of the outer periphery of the grain, the grain boundary phase, and the interface between the internal electrode 7 and the dielectric layer 5; each component is set as a parallel circuit of a resistor R and a capacitor C, and is represented by an equivalent circuit model in which each component is connected in series. When the resistance value of the core measured by the AC impedance method is set to R1, the resistance value of the shell is set to R2, the resistance value of the grain boundary is set to R3, and the resistance value of the interface is set to R4, the total value of R1, R2, R3, and R4 is greater than 1MΩ. It is preferably greater than 3MΩ, and particularly preferably greater than 5MΩ. As a result, a laminated ceramic capacitor with improved insulation of the dielectric layer 5 and improved reliability when voltage is applied can be provided.

[0050] Hereinafter, the perovskite type compound containing Ba and Ti will be described using barium titanate (BT) as a representative.

[0051] Figure 2 1 is a schematic cross-sectional view showing the internal structure of the BT grains in the dielectric layer 5 constituting the multilayer ceramic capacitor of the present disclosure. The BT grains 11 in the dielectric layer 5 of the multilayer ceramic capacitor of the present disclosure have a core-shell structure consisting of a core 11a and a shell 11b formed around it. The shell is the outer peripheral portion of the BT grain after firing, and is a portion where the concentration of rare earth oxides and MgO is higher than that of the core. Moreover, as shown in FIG. 1 , the dielectric layer 5 is composed of a plurality of BT grains 11 separated by grain boundaries 9.

[0052] Preferably, the average particle size of the BT grains 11 in the dielectric layer 5 is 0.001 μm to 0.2 μm. When the average particle size of the BT grains 11 is 0.01 μm or more, the BT grains 11 can obtain a clear core-shell structure, so that the core 11a and the shell 11b are clearly defined, and a dielectric layer with high dielectric constant and high insulation can be obtained.

[0053] On the other hand, when the average grain size of the BT crystal grains 11 is 0.1 μm or less, the thinned dielectric layer 5 becomes a dielectric layer sintered with many grain boundaries 9 interposed therebetween, and thus high insulation is obtained.

[0054] The measurement method of the AC impedance method is as follows.

[0055] Figure 3 It is an AC impedance measurement device. Figure 3 In the figure, 20a is a thermostatic bath in which a multilayer ceramic capacitor as a sample is installed and temperature is controlled, and 20c is an impedance measuring device having an AC power supply.

[0056] Figure 4 : is a graph showing a Cole-Cole diagram of a conventional multilayer ceramic capacitor. In the present embodiment, similarly, a graph (Cole-Cole diagram) showing impedance changes when the measurement frequency is changed for the core (center), shell (periphery), grain boundary phase of the main component of the perovskite compound and other components of the grains in the dielectric layer 5, and the interface between the internal electrode 7 and the dielectric layer 5 is shown. In this evaluation, as Figure 5 As shown in the equivalent circuit of , the dielectric layer 5 is divided into four components: the core (center), the shell (periphery), the grain boundary phase, and the interface between the internal electrode 7 and the dielectric layer 5. The horizontal axis of the graph represents the real part of the impedance signal, and the vertical axis represents the imaginary part.

[0057] Figure 4 The Cole-Cole plot can be obtained by dividing the phase into four components: the core (central portion), the shell (peripheral portion), the grain boundary phase, and the interface between the internal electrode 7 and the dielectric layer 5 using dedicated software.

[0058] Next, a method for manufacturing the multilayer ceramic capacitor according to the present embodiment will be described in detail. Figure 6A to Figure 6D The following is a process diagram showing a method for manufacturing a multilayer ceramic capacitor according to an embodiment of the present disclosure.

[0059] Step (a): First, a dielectric powder as a raw material powder shown below is mixed with an organic resin such as polyvinyl butyral resin, and a solvent such as toluene and ethanol using a ball mill or the like to prepare a ceramic slurry. Next, the ceramic slurry is formed into a ceramic green sheet 31 using a sheet forming method such as a doctor blade method or a die coating method. Preferably, from the viewpoint of thinning for high capacity of the dielectric layer 5 and maintaining high insulation, the thickness of the ceramic green sheet 31 is preferably 1 μm to 3 μm.

[0060] Step (b): Next, a rectangular internal electrode pattern 33 is printed and formed on the main surface of the ceramic green sheet 31 obtained above. The conductor paste that becomes the internal electrode pattern 33 is prepared by mixing Ni or its alloy powder as the main component metal, and adding an organic binder, a solvent and a dispersant.

[0061] For the reasons of miniaturization of the multilayer ceramic capacitor and reduction of the step difference caused by the internal electrode pattern 33 , the thickness of the internal electrode pattern 33 is preferably 1 μm or less.

[0062] In order to eliminate the step difference caused by the internal electrode pattern 33 on the ceramic green sheet 31, it is preferable to form a ceramic pattern 35 around the internal electrode pattern 33 with substantially the same thickness as the internal electrode pattern 33. From the viewpoint of making the firing shrinkage in simultaneous firing the same, it is preferable that the ceramic component constituting the ceramic pattern 35 uses the dielectric powder used in the ceramic green sheet 31.

[0063] Step (c): Next, a desired number of ceramic green sheets 31 having internal electrode patterns 33 are stacked, and a plurality of ceramic green sheets 31 having no internal electrode patterns 33 are stacked above and below the ceramic green sheets 31 so that the same number of sheets are stacked above and below, thereby forming a temporary stack. The internal electrode patterns 33 in the temporary stack are staggered by half a pattern in the longitudinal direction. By this stacking method, the internal electrode patterns 33 can be alternately exposed on the end faces of the stack after cutting.

[0064] As described above, in addition to the method of pre-forming the internal electrode pattern 33 on the main surface of the ceramic green sheet 31 and stacking it, it can also be formed by the following method: after the ceramic green sheet 31 is temporarily pressed against the substrate on the lower side, the internal electrode pattern 33 is printed and dried, and then on the printed and dried internal electrode pattern 33, the ceramic green sheet 31 without the internal electrode pattern 33 printed is stacked and temporarily pressed against it, and the pressing of the ceramic green sheet 31 and the printing of the internal electrode pattern 33 are performed in sequence.

[0065] Step (d): Next, the temporary laminate is pressed under conditions of a higher temperature and pressure than those during the temporary lamination, to form a laminate 39 in which the ceramic green sheets 31 and the internal electrode patterns 33 are firmly and closely attached. Next, the laminate 39 is cut along the cutting line h, which is approximately the center of the ceramic pattern 35 formed in the laminate 39, in a direction perpendicular to the longitudinal direction of the internal electrode pattern 33 and parallel to the longitudinal direction of the internal electrode pattern 33, so that the end of the internal electrode pattern 33 is exposed to form a capacitor body molded body. On the other hand, on the side edge side, the internal electrode pattern 33 is formed in a non-exposed state.

[0066] Next, the capacitor body molded body is fired under a predetermined atmosphere and temperature condition to form a capacitor body. Depending on the situation, the edge line portion of the capacitor body may be chamfered, and barrel polishing may be performed to expose the internal electrode 7 exposed from the opposite end surface of the capacitor body 1. In the manufacturing method of this embodiment, preferably, the degreasing is performed in a temperature range up to 500°C, the heating rate is 5 to 20°C / h, the firing temperature is a maximum temperature range of 1000 to 1250°C, the heating rate from degreasing to the maximum temperature is 200 to 500°C / h, the holding time at the maximum temperature is 0.5 to 4 hours, the cooling rate from the maximum temperature to 1000°C is 200 to 500°C / h, the atmosphere is hydrogen-nitrogen, and the maximum temperature of the heat treatment (reoxidation treatment) after firing is 900 to 1100°C, and the atmosphere is nitrogen.

[0067] Next, external electrode paste is applied to the opposite ends of the capacitor body 1 and fired to form external electrodes 3 and 4. In addition, a plating film is formed on the surface of the external electrodes 3 and 4 to improve mounting performance.

[0068] Example

[0069] The present invention is further described below by way of examples, but is not limited thereto.

[0070] A laminated ceramic capacitor is produced as described below. BT powder (BaTiO3) is used as a dielectric powder. As described in the dielectric layer 5 of Table 1, the ratio of MnO, MgO, and DyO relative to 100 mol% of BT powder is 0.2 mol%, Mg1.5 mol%, and Dy1.5 mol%, and the glass is further set to 0.8 mass parts when MnMgDy is 100 mass parts, and MnO, MgO, DyO and glass are covered and processed on the surface of the BT powder by a liquid phase method at this ratio, and fixed by heating below 500°C.

[0071] Next, the dielectric powder was wet mixed using a zirconia ball with a diameter of 5 mm and a mixed solvent of toluene and ethanol as a solvent. Next, polyvinyl butyral resin and a mixed solvent of toluene and ethanol were added to the wet mixed dielectric powder, and wet mixed using a zirconia ball with a diameter of 5 mm to prepare a ceramic slurry, and a ceramic green sheet with a thickness of 2.5 μm was prepared by a scraper method.

[0072] Next, a plurality of rectangular internal electrode patterns mainly composed of Ni were formed on the upper surface of the ceramic green sheet by printing. The conductor paste used for the internal electrode pattern used Ni powder having an average particle size of 0.3 μm.

[0073] Next, 100 ceramic green sheets with internal electrode patterns printed on them were stacked, and 20 ceramic green sheets without internal electrode patterns printed on them were stacked on the upper and lower surfaces, respectively. 7 The sheets were stacked together at 100 °C for 10 minutes and cut into a predetermined size.

[0074] Next, the laminated body was subjected to a debinding treatment at 300°C / h in the atmosphere at a heating rate of 10°C / h, and then calcined at 1040-1200°C for 2 hours in hydrogen-nitrogen at a heating rate of 300°C / h starting from 500°C, and then cooled to 1000°C at a cooling rate of 300°C / h, and then reoxidized at 1000°C for 4 hours in a nitrogen atmosphere, and then cooled at a cooling rate of 300°C / h to produce a capacitor body. The size of the capacitor body is 1×0.5×0.5mm 3 , the thickness of the dielectric layer 5 is 1.8 μm.

[0075] Next, after the fired capacitor body is barrel-polished, an external electrode paste containing Cu powder and glass is applied to both ends of the capacitor body and sintered at 850°C to form external electrodes 3 and 4. Thereafter, Ni and Sn are plated in sequence on the surfaces of the external electrodes 3 and 4 using an electrolytic barrel machine to produce a laminated ceramic capacitor.

[0076] As shown in Table 1, when making the above-mentioned stacked ceramic capacitors, the composition of the dielectric layer 5 is the same, but the mass of Sn contained in the internal electrode 7 is changed from sample No. 1 to sample No. 6, the particle size of the BT powder in sample No. 7 is changed from 50nm to 70nm, and samples No. 8 and 9 use a solid phase method instead of an oxalate method to make stacked ceramic capacitors.

[0077] Each sample of the embodiment described in Table 1 was prepared by weighing SnO and adding it to the raw material of the internal electrode so that the amount of Sn contained in the internal electrode after forming the multilayer ceramic capacitor and the amount of Sn contained in the dielectric layer 5 after forming the multilayer ceramic capacitor became the values ​​shown in Table 1. The materials of the capacitors of the obtained samples correspond to the table.

[0078] For these multilayer ceramic capacitors, the insulation resistance value (IR), electrostatic capacitance (Cap), the product of insulation resistance and electrostatic capacitance (CR product), dielectric breakdown voltage (BVD), Weibull coefficient (m value), and mean time to failure (MTTF) were measured and shown in Table 2.

[0079] [Table 1]

[0080]

[0081] [Table 2]

[0082]

[0083] Insulation resistance (IR): measured using an insulation resistance meter R8340A manufactured by Advantest Corporation in accordance with the insulation resistance measurement method specified in JIS C 5101-1.

[0084] Electrostatic capacitance (Cap): The capacitance was measured using an LCR meter 4284A manufactured by YHP at 25° C. under the measurement conditions of a frequency of 1.0 kHz and a measurement voltage of 0.5 Vrms.

[0085] CR product: The product of insulation resistance and electrostatic capacitance.

[0086] Dielectric breakdown voltage (BDV): The DC breakdown voltage was measured in silicone oil using a withstand voltage meter manufactured by Kikusui Electronics Co., Ltd.

[0087] Weibull coefficient (m value) and mean time to failure (MTTF):

[0088] A HALT test (Highly Accelerated Limit Test) was conducted. Specifically, 20 multilayer ceramic capacitors were used for each sample number under a 125°C environment and a continuous voltage of 10V was applied. The time point when the insulation resistance became 0Ω was considered as a failure. The mean time to failure (MTTF) and the deviation of the failure time (Weibull coefficient: m value) were calculated based on the Weibull plot. The longer the MTTF, the longer the life.

[0089] Average particle size: The average particle size of BT powder was determined by scanning electron microscope (SEM). The polished surface was etched, 20 crystal grains in the electron microscope photograph were randomly selected, and the maximum diameter of each crystal grain was determined by the intercept method, and the average value was calculated.

[0090] In addition, among Samples No. 1 to 9, for Samples No. 1, 3, 6, and 9, the resistance values ​​of the four components, namely the core (central portion), the shell (peripheral portion), the grain boundary phase, and the interface between the internal electrode 7 and the dielectric layer 5, and their total value were obtained by the AC impedance method. The results are shown in Table 3. Figure 7 This is a diagram that graphs it. Figure 7 This is a graph showing the total value of the resistance values ​​of the four components in Table 3 obtained by the AC impedance method.

[0091] [Table 3]

[0092]

[0093] In addition, based on the results in Table 3, the relationship between the resistance values ​​R1, R2, R3, and R4 of the four components of the core (center), shell (periphery), grain boundary phase, and the interface between the internal electrode 7 and the dielectric layer 5 and the insulation resistance (IR) is shown in the graph.

[0094] Figure 8 This is a graph showing the relationship between the core resistance value R1 and the insulation resistance.

[0095] Fig. 9 It is a graph showing the relationship between the case resistance value R2 and the insulation resistance.

[0096] Fig.10 This is a graph showing the relationship between the grain boundary phase resistance value R3 and the insulation resistance.

[0097] Fig.11 It is a graph showing the relationship between the interface resistance value R4 between the internal electrode 7 and the dielectric layer and the insulation resistance.

[0098] Fig.12This is a graph showing the relationship between R1, R2, R3, R4 and insulation resistance.

[0099] In any graph, it can be seen that there is a proportional relationship between the resistance value and the insulation resistance (IR).

[0100] The total resistance value of the four components of the dielectric layer 5 measured by the AC impedance method for samples No. 1, 3, and 6 exceeded 3 million Ω, which was 1 MΩ or more. Therefore, the insulation resistance (IR) and dielectric breakdown voltage (withstand voltage: BDV) of the laminated ceramic capacitors of samples No. 1, 3, and 6 were high, and the reliability was good.

[0101] In contrast, the total resistance value of the four components of the dielectric layer 5 of sample No. 9 measured by the AC impedance method is less than 1 million Ω, and is not greater than 1 MΩ. The insulation resistance (IR) and dielectric breakdown voltage (withstand voltage: BDV) of the multilayer ceramic capacitor of sample No. 9 are low, and the reliability is poor.

[0102] In Table 3, R2 (resistance value of the outer periphery of the BT crystal grain, i.e., the shell) of Sample No. 1 and 3 is 200,000Ω or more, indicating that the shell thickness is large. Therefore, the insulation resistance (IR) of the multilayer ceramic capacitor becomes higher, and the insulation resistance (IR) can be made 8000MΩ or more, and the reliability is further improved.

[0103] The internal electrode 7 contains Sn, but during the firing process, Sn diffuses into the dielectric layer 5, and the dielectric layer 5 contains 0.5 to 5 parts by mass of Sn (samples No. 2, 3, 4, 5, and 6). As a result, the insulation resistance (IR) of the multilayer ceramic capacitor can be made 6000 MΩ or more, and the reliability is improved. In contrast, although the multilayer ceramic capacitor of sample No. 9 contains 2 parts by mass of the internal electrode 7 like sample No. 4, the total resistance value of the four components of the dielectric layer 5 measured by the AC impedance method is less than 1 MΩ, and the insulation resistance (IR) of the multilayer ceramic capacitor is 2174Ω, which is quite small and has low reliability compared with sample No. 4, in which the total resistance value of the four components of the dielectric layer 5 measured by the AC impedance method is more than 1 MΩ.

[0104] The quantitative analysis of Sn was performed as follows.

[0105] Three internal electrodes 7 were randomly selected from a multilayer ceramic capacitor, and only the internal electrode parts were cut out by FIB processing (focused ion beam method), and three thin-sheet samples were prepared. The average value of 30 places (10 places × 3) at the interface with the dielectric layer and the average value of 30 places (10 places × 3) at the center of the internal electrode were calculated, and the quantitative analysis of Sn was performed by transmission electron microscope (TEM), and the two were compared. The Sn content was calculated from the average value of the total 30 places (10 places × 3).

[0106] Samples No. 2, 3, 4, and 5 contain Sn in the internal electrode 7. Diffusion of Sn occurs from the interface between the internal electrode 7 and the dielectric layer 5, and Sn moves from the center to the interface inside the internal electrode 7. As a result, the Sn content at the interface of the internal electrode 7 on the dielectric layer 5 side becomes higher than the Sn content at the center of the internal electrode 7.

[0107] As a result, in the HALT test of the multilayer ceramic capacitor, the m value and MTTF in the evaluation of the failure time become higher, and the failure time does not vary. In addition, the CR product becomes higher, and the reliability of the multilayer ceramic capacitor is improved.

[0108] If we observe the samples No. 2, 3, 4, and 5, the Sn content of the internal electrode 7 increases from 0.5 parts by mass to 4 parts by mass. However, although the values ​​of m value, MTTF, IR, Cap, CR, and BDV are the largest when the amount of Sn is 1 part by mass, they slightly decrease thereafter, and the various values ​​of the laminated ceramic capacitor do not increase. This indicates that, although Sn diffuses from the internal electrode 7 on the dielectric layer 5 side to the interface of the dielectric layer 5 during the firing process, the Sn content of the internal electrode 7 on the dielectric layer 5 side is large. In other words, it can be said that the Sn content at the interface is larger than the Sn content in the center of the internal electrode 7.

[0109] The quantitative analysis of Sn was performed as follows.

[0110] The Sn content in the internal electrode 7 can be measured in the central portion and the end portion by the following method: three internal electrodes 7 are randomly selected from a multilayer ceramic capacitor, and only the internal electrodes 7 are cut out and sliced ​​using FIB processing (focused ion beam method), and three samples each divided into a central portion and an end portion are prepared, and a quantitative analysis of Sn is performed at 10 randomly selected locations on each sample using a transmission electron microscope (TEM).

[0111] It is confirmed from the above experimental examples that when the resistance value in the dielectric layer 5 of the present invention is 1MΩ or more, the insulation resistance of the stacked ceramic capacitor is high and the reliability is greatly improved. The dielectric layer 5 of the stacked ceramic capacitor disclosed in the present invention contains a perovskite compound containing Ba and Ti (wherein a portion of Ba can be replaced by Ca and a portion of Ti can be replaced by Zr) as the main component. In addition, the total resistance value of the main component and other components contained in the dielectric layer 5 measured by the AC impedance method is more than 1MΩ. This is because, as mentioned above, the dielectric layer is made of barium titanate powder prepared by the oxalate method. The dielectric layer disclosed in the present invention is obtained by sintering the barium titanate powder prepared by the oxalate method containing various additives shown in Table 1.

[0112] When the lattice constants a, b, and c of the barium titanate crystal grains contained in the dielectric layer of the present disclosure are measured by X-ray diffraction, the volume V per unit cell represented by the product of the lattice constants a, b, and c is 0.0653 nm. 3 Above and 0.0657nm 3 Below. The volume V per unit cell represented by the product of the lattice constants a, b, and c of the barium titanate powder prepared by the oxalate method is greater than the volume V per unit cell represented by the product of the lattice constants a, b, and c of the grains made from the barium titanate powder prepared by the solid phase method. The dielectric layer made from the barium titanate powder prepared by the oxalate method has a large lattice constant as described above, so magnesium (Mg), manganese (Mn), and dysprosium (Dy) as additives shown in Table 1 are easily partially dissolved in the barium titanate. Therefore, it is speculated that the IR of the dielectric layer is increased, and the AC impedance of the stacked ceramic capacitor is increased. In addition, in this case, the average particle size of the barium titanate powder prepared by the oxalate method can be less than 50 nm. Even for the barium titanate powder prepared by the oxalate method, when the average particle size exceeds the above range, the IR tends to be lower. For example, since the average particle size of barium titanate powder prepared by the oxalate method in sample No. 7 is 70 nm, the IR of sample No. 7 is lower than the IR of samples Nos. 1 to 6 using barium titanate powder prepared by the oxalate method and having an average particle size of 50 nm.

[0113] In addition, the AC impedance of samples No. 1 to 6 is significantly higher than the AC impedance of the multilayer ceramic capacitors of samples No. 8 and 9 having dielectric layers made of barium titanate powder having the same average particle size of 50 nm and prepared by a solid phase method. As described above, this is considered to be because the product of the lattice constants of barium titanate constituting the dielectric layers of samples No. 1 to 6 is greater than the product of the lattice constants of barium titanate constituting the dielectric layers of samples No. 8 and 9.

[0114] Among them, the AC impedance R3 of the grain boundary of sample No. 3 (adding 0.1 mass part of Sn) is higher than that of sample No. 1 (adding 0 mass part of Sn). Considering that IR is higher in sample No. 3 than in sample No. 1, it is estimated that the increase in R3 due to the addition of a predetermined amount of Sn contributes to the increase in IR.

[0115] In addition, when measuring the AC impedance, the reduction in the AC impedance R4 of the interface of sample No. 6 (adding 3 parts by mass of Sn) is greater than the reduction in the AC impedance R3 of the grain boundary. As a result, the AC impedance R3 of the grain boundary of sample No. 6 is greater than the AC impedance R4 of the interface. It is speculated that the reduction in the AC impedance of the interface of sample No. 6 is related to the reduction in IR. As shown above, when a specified amount of Sn component is included, as seen in No. 3, the AC impedance of the stacked ceramic capacitor increases in the order of core, shell, grain boundary, and interface, and if the AC impedance R3 of the grain boundary is increased compared to the case where Sn is not added, the IR can be further increased in the same way as the AC impedance.

[0116] According to the present disclosure, it is possible to provide a multilayer ceramic capacitor having improved insulation properties of a dielectric layer and improved reliability when a voltage is applied.

[0117] The multilayer ceramic capacitor of the present disclosure can be implemented in the following configurations (1) to (5).

[0118] (1) A laminated ceramic capacitor comprising: a laminate having a plurality of laminated dielectric layers and a plurality of internal electrodes formed along interfaces between the dielectric layers; and a plurality of external electrodes formed on an outer surface of the laminate and electrically connected to the internal electrodes;

[0119] The dielectric layer contains a perovskite compound containing Ba and Ti (wherein a part of Ba may be substituted by Ca, and a part of Ti may be substituted by Zr) as a main component;

[0120] The total resistance value of the main component and other components contained in the dielectric layer measured by an AC impedance method is 1 MΩ or more.

[0121] (2) The multilayer ceramic capacitor according to the above configuration (1) is divided into four components, namely, a core at the center of a grain of the main component and other components in the dielectric layer, a shell at the periphery of the grain, a grain boundary phase, and an interface between the internal electrode and the dielectric layer, and each component is set as a parallel circuit of a resistor R and a capacitor C, and is represented by an equivalent circuit model in which each component is connected in series;

[0122] When the resistance value of the core measured by an AC impedance method is R1, the resistance value of the shell is R2, the resistance value of the grain boundary is R3, and the resistance value of the interface is R4,

[0123] The total value of R1, R2, R3, and R4 is 1 MΩ or more.

[0124] (3) In the multilayer ceramic capacitor according to the above configuration (1) or (2), the dielectric layer contains 0.03 to 3 parts by mass of Sn.

[0125] (4) In the multilayer ceramic capacitor according to the above configuration (2), R2 is 200,000Ω or more.

[0126] (5) In the multilayer ceramic capacitor according to the above configuration (2), the Sn content at the interface is higher than the Sn content at the center of the internal electrode.

[0127] The embodiments of the present disclosure are described in detail above. In addition, the present disclosure is not limited to the above embodiments, and various changes and improvements can be made without departing from the spirit of the present disclosure. It goes without saying that all or part of the above embodiments can be combined within an appropriate and non-contradictory range.

[0128] Explanation of symbols

[0129] 1Capacitor body

[0130] 3.4 External electrodes

[0131] 5 Dielectric layer

[0132] 6. Interface

[0133] 7 Internal Electrode

[0134] 9 Grain Boundary

[0135] 11 Grains of perovskite compounds containing Ba and Ti

[0136] 11a Core

[0137] 11b Shell

[0138] 20a Constant temperature bath

[0139] 20c Impedance Measurement Device

[0140] 31 Ceramic Green Sheet

[0141] 33 Internal electrode pattern

[0142] 35 Ceramic Patterns

[0143] 39 stacked bodies.

Claims

1. A laminated ceramic capacitor comprising: a laminate having a plurality of laminated dielectric layers and a plurality of internal electrodes formed along interfaces between the dielectric layers; and a plurality of external electrodes formed on an outer surface of the laminate and electrically connected to the internal electrodes; The dielectric layer contains a perovskite compound containing Ba and Ti as a main component, wherein A part of Ba can be replaced by Ca, and a part of Ti can be replaced by Zr; The total resistance value of the main component and other components contained in the dielectric layer measured by an AC impedance method is 1 MΩ or more.

2. The multilayer ceramic capacitor according to claim 1, wherein the capacitor is divided into four components, namely, a core at the center of a grain of the main component and other components in the dielectric layer, a shell at the periphery of the grain, a grain boundary phase, and an interface between the internal electrode and the dielectric layer, and each component is set as a parallel circuit of a resistor R and a capacitor C, and is represented by an equivalent circuit model in which each component is connected in series; When the resistance value of the core measured by an AC impedance method is R1, the resistance value of the shell is R2, the resistance value of the grain boundary is R3, and the resistance value of the interface is R4, The total value of R1, R2, R3, and R4 is 1 MΩ or more. 3 . The multilayer ceramic capacitor according to claim 1 , wherein the dielectric layer contains 0.03 to 3 parts by mass of Sn.

4. The multilayer ceramic capacitor according to claim 2, wherein R2 is 200000Ω or more. 5 . The multilayer ceramic capacitor according to claim 2 , wherein the Sn content at the interface is higher than the Sn content at the center of the internal electrode.

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