Microelectronic assembly including stacked dies coupled by through dielectric vias

Abstract

Disclosed herein are microelectronic assemblies, and related devices and methods. In some embodiments, a microelectronic assembly may include a plurality of vertically stacked dies; a trench of dielectric material through the plurality of vertically stacked dies; and a plurality of conductive vias extending through the trenches of the dielectric material, wherein individual conductive vias of the plurality of conductive vias are electrically coupled to individual vertically stacked dies of the plurality of vertically stacked dies.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATION(S)

[0002] This application claims the benefit of U.S. Non-Provisional Application No. 17 / 854,728, filed on June 30, 2022, entitled “MICROELECTRONIC ASSEMBLIES INCLUDING STACKEDDIES COUPLED BY A THROUGH DIELECTRIC VIA,” and the entire contents of the U.S. Non-Provisional Application are hereby incorporated by reference for all purposes. Background Art

[0003] Integrated circuit (IC) packaging often includes stacked dies. Die stacking includes the process of mounting multiple chips one on top of another within a single IC package. Die stacking has recently become a powerful tool for meeting the requirements of the growing demand for processing power and storage capacity. Die stacking is used in many different computer products, and further improvements are always desirable. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, similar reference numerals designate similar structural elements. In the various figures of the accompanying drawings, the embodiments are illustrated by way of example and not by way of limitation.

[0005] Figure 1A is a side cross-sectional view of an exemplary microelectronic assembly according to various embodiments.

[0006] Figure 1B is a top view of an exemplary assembly according to various embodiments.

[0007] Figure 1C is a detailed view of a trench with a through-dielectric via according to various embodiments.

[0008] Figure 1D According to various embodiments Figure 1C A side cross-sectional view of a portion of.

[0009] Figure 1E is a detailed view of a single stacked die according to various embodiments.

[0010] FIG. 2A to FIG. 2J is a side cross-sectional view of an exemplary process for fabricating a microelectronic assembly according to various embodiments.

[0011] FIG. 3A to FIG. 3J is a side cross-sectional view of another exemplary process for fabricating a microelectronic assembly according to various embodiments.

[0012] FIG. 4A to FIG. 4D is a side cross-sectional view of still another exemplary process for fabricating a microelectronic assembly according to various embodiments.

[0013] FIG. 5A to FIG. 5D is a side cross-sectional view of an exemplary microelectronic assembly according to various embodiments.

[0014] Figure 6 is a side cross-sectional view of another exemplary microelectronic assembly according to various embodiments.

[0015] 7A to 7E is a side cross-sectional view of an exemplary process for fabricating a microelectronic assembly according to various embodiments.

[0016] Figure 8 is a side cross-sectional view of another exemplary microelectronic assembly according to various embodiments.

[0017] 9A to 9E is a side cross-sectional view of an exemplary process for fabricating a microelectronic assembly according to various embodiments.

[0018] Fig.10 is a side cross-sectional view of another exemplary microelectronic assembly according to various embodiments.

[0019] FIG. 11A to FIG. 11D is a side cross-sectional view of an exemplary process for fabricating a microelectronic assembly according to various embodiments.

[0020] FIG. 12A to FIG. 12J is a side cross-sectional view of another exemplary process for fabricating a microelectronic assembly according to various embodiments.

[0021] Fig.13 is a side cross-sectional view of another exemplary microelectronic assembly according to various embodiments.

[0022] Fig.14 is a flow chart of an example method of fabricating a microelectronic assembly according to various embodiments.

[0023] Fig.15 is a top view of a wafer and die that may be included in a microelectronic assembly according to any of the embodiments disclosed herein.

[0024] Fig.16 is a cross-sectional side view of an IC device that may be included in a microelectronic assembly according to any of the embodiments disclosed herein.

[0025] Fig.17 is a cross-sectional side view of an IC device assembly that may include a microelectronic assembly according to any of the embodiments disclosed herein.

[0026] Fig.18 is a block diagram of an example electrical device that may include a microelectronic assembly according to any of the embodiments disclosed herein. DETAILED DESCRIPTION

[0027] Microelectronic assemblies, and related devices and methods are disclosed herein. For example, in some embodiments, the microelectronic assembly may include a plurality of vertically stacked dies; a trench through a dielectric material of the plurality of vertically stacked dies; and a plurality of conductive vias extending through the trench of the dielectric material, wherein individual conductive vias of the plurality of conductive vias are electrically coupled to individual vertically stacked dies of the plurality of vertically stacked dies.

[0028] An IC package having multiple vertically stacked chips or dies in a single package (i.e., die stacking) advantageously increases the amount of processing and / or memory that can be located within a given footprint on a substrate or printed circuit board on which the die stack is arranged. Die stacking can enable shorter routing interconnects from chip to chip, thereby increasing signal speeds between chips, reducing noise, and reducing crosstalk. Another benefit of die stacking is that surface mounting to a printed circuit board assembly is simplified because fewer components are required to be placed on the printed circuit board. As processing demands and storage capacity continue to increase while system size continues to decrease, chip stacking is becoming increasingly useful for different memory configurations. An example IC assembly may include a stack of a computing logic die and a memory die coupled to the computing logic die (i.e., the computing logic die and the memory die are arranged according to 3D integration). The memory die may include static random access memory (SRAM) cells, dynamic random access memory (DRAM), resistive switching memory (e.g., magnetoresistive random access memory (MRAM) or resistive random access memory (RRAM)), spin transfer torque random access memory (STTRAM) cells, etc. Although the description of the present disclosure may refer to a computing logic device (e.g., implemented using front-end transistors, referred to herein as a logic transistor) or a memory cell included in a given die of an IC assembly, any die described herein may also include other types of devices. For example, in some embodiments, any of the memory dies described herein may also include a logic transistor, and / or any of the computing logic dies described herein may also include a memory cell. Further, some embodiments of the present disclosure may refer to memory dies, however, embodiments of the present disclosure are equally applicable to other dies, including processing dies, such as a central processing unit (CPU) or a graphics processing unit (GPU). For example, unless otherwise described, the die described herein includes one or more IC structures (or simply "ICs") that implement (i.e., are configured to perform) specific functionality. In one such example, the term "memory die" may be used to describe a die that includes one or more ICs that implement memory circuits (e.g., ICs that implement one or more of a memory device, a memory array, control logic configured to control the memory device and array, etc.). In another such example, the term "compute die" may be used to describe a die that includes one or more ICs that implement logic / compute circuits (e.g., ICs that implement one or more of input / output (I / O) functions, arithmetic operations, data pipelining, etc.). The term "circuit" may be used to describe one or more passive and / or active components that are arranged to cooperate with each other to provide a desired functionality.

[0029] Memory is important for the performance of IC packaging. Typically, a stacked memory assembly includes one or more memory arrays and control circuits for the memory arrays arranged in vertical layers, and the vertical layers have interconnections between the layers to electrically couple the memory levels, which increases the overall thickness of the IC package. In order to provide a more dense memory for computing operations, an architecture involving a memory device (which may be referred to as a three-dimensional (3D) stacked memory or stacked memory) with multiple tightly coupled memory elements has been developed. 3D stacked memory may include a coupling layer or package of a memory element, and the coupling layer or package of the memory element may be referred to as a memory stack. Stacked memory may be utilized to provide a large amount of computer memory in a single device or package, wherein the device or package may also include specific system components, such as a memory controller and a CPU (central processing unit). Current practices for assembling 3D stacks (such as memory stacks) include having through silicon vias (TSVs) in each level of the memory, and electrically coupling each level by solder microbumps or recently by hybrid bonding. Since TSVs and interconnect metallizations are required to be formed at each level, this increases complexity and cost, and is more likely to cause yield reductions as failures at lower levels cause failures at more distant (e.g., higher) levels. Further, the thickness of the interconnects (e.g., z-height) increases the overall thickness of the IC package and limits the number of levels that can be included in the stack. Various of the embodiments disclosed herein can help achieve improved processing and memory performance of IC packages with reduced thickness by stacking dies and forming conductive vias in trenches in dielectric material adjacent to the stacked dies relative to conventional approaches.

[0030] In the following detailed description, reference is made to the accompanying drawings forming a part of the detailed description, wherein similar reference numerals always designate similar parts, and embodiments that can be put into practice are shown by way of illustration in the accompanying drawings. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be understood in a restrictive sense. The accompanying drawings are not necessarily drawn to scale. Although many of the drawings illustrate straight line structures with flat walls and right angle corners, this is only for ease of illustration, and actual devices manufactured using these techniques will exhibit rounded corners, surface roughness, and other features.

[0031] Various operations can be described in turn as multiple discrete actions or operations in a manner that is most helpful for understanding the disclosed subject matter. However, the order of description should not be interpreted as implying that these operations are necessarily order-dependent. In particular, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. In additional embodiments, various additional operations may be performed, and / or the described operations may be omitted.

[0032] For the purposes of this disclosure, the expressions "A and / or B" and "A or B" mean (A), (B), or (A and B). For the purposes of this disclosure, the expressions "A, B, and / or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When the term "between" is used in reference to a measurement range, the term "between" includes both ends of the measurement range. As used herein, the designation "A / B / C" means (A), (B), and / or (C).

[0033] The description uses the expressions "in an embodiment" or "in various embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "including," "comprising," "having," and the like as used with respect to the embodiments of the present disclosure are synonymous. As used herein, "package" and "IC package" are synonymous, as are "die," "IC die," "microelectronic assembly," and "electronic assembly." The terms "top" and "bottom" may be used herein to explain various features of the drawings, but these terms are merely for ease of discussion and do not imply a desired or required orientation.

[0034] The terms "substantially," "close," "approximately," "near," and "approximately" generally refer to within + / - 20% of a target value based on the context of a specific value as described herein or as known in the art. Similarly, terms indicating the orientation of various elements, such as, for example, "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between elements, generally refer to within + / - 5-20% of a target value based on the context of a specific value as described herein or as known in the art.

[0035] As used herein, unless otherwise specified, the term "insulated" means "electrically isolated". Throughout the specification and in the claims, the term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical or magnetic connection between the things being connected, or an indirect connection through one or more passive or active intermediate devices. The meanings of "a", "an", and "the" include plural references. The meaning of "in" includes "in" and "on".

[0036] Unless otherwise specified, the use of the ordinal adjectives "first," "second," and "third," etc., to describe common objects merely indicates that different instances of similar objects are referenced and is not intended to imply that the objects so described must be in a given sequence in time, space, ranking, or in any other manner.

[0037] When used to describe a range of dimensions, the expression "between X and Y" means a range that includes X and Y. For convenience, the expression "FIG. 2" may be used to refer to FIG. 2A to FIG. 2J 3 may be used to refer to the set of drawings of FIG. 3A to FIG. 3J A collection of drawings, etc. Although a particular element may be referred to in the singular herein, such an element may include multiple sub-elements. For example, an "insulating material" may include one or more insulating materials. As used herein, a "conductive contact" may refer to a portion of a conductive material (e.g., a metal) that serves as an electrical interface between different components; a conductive contact may be recessed into a surface of a component, flush with a surface of a component, or extend away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket, or a portion of a conductive wire or through-hole).

[0038] "Interconnection" refers to any element that provides a physical connection between two other elements. For example, an electrical interconnection provides an electrical connection between two electrical components, thereby facilitating the transmission of electrical signals between them; an optical interconnection provides an optical connection between two optical components, thereby facilitating the transmission of optical signals between them. As used herein, the term "interconnection" includes both electrical and optical interconnections. The nature of the interconnection described herein should be understood with reference to the signal medium associated therewith. Therefore, when used with reference to an electronic device (such as an IC that operates using electrical signals), the term "interconnection" describes any element formed by a conductive material for providing an electrical connection to one or more elements associated with the IC and / or between various such elements. In such a case, the term "interconnection" may refer to a conductive trace (sometimes also referred to as a "metal trace", "wire", "metal wire", "wire", "metal wire", "trench" or "metal trench") and a conductive via (sometimes also referred to as a "via" or "metal via"). Sometimes, conductive traces and vias may be referred to as "conductive traces" and "conductive vias", respectively, to highlight the fact that these elements include conductive materials such as metals. Likewise, when used with reference to devices that also operate on optical signals, such as photonic ICs (PICs), "interconnect" may also describe any element formed from optically conductive materials for providing an optical connection to one or more elements associated with the PIC. In such cases, the term "interconnect" may refer to optical waveguides (e.g., structures that guide and constrain light waves), including optical fibers, optical splitters, optical combiners, optical couplers, and optical vias.

[0039] Figure 1A is a side cross-sectional view of a microelectronic assembly 100 according to various embodiments. The microelectronic assembly 100 may include a base die 103 and a multi-level die assembly 104 disposed thereon. In particular, the multi-level die assembly 104 may include a vertically stacked die 114 having a trench 135 and a conductive through dielectric via (TDV) 115 passing through a dielectric material 133 of the vertically stacked die 114. The dielectric material 133 in the trench 135 may include any suitable dielectric material commonly used in semiconductor manufacturing, such as silicon and one or more of oxygen, nitrogen, and carbon (e.g., in the form of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride); a polyimide material; or a low-k or ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, an organic polymer dielectric, a photoimageable dielectric, and / or a benzocyclobutene-based polymer). In particular, Figure 1A yes Figure 1B Side cross-sectional view along line A-A'.

[0040] Figure 1B is a top view of an exemplary microelectronic assembly according to various embodiments. Figure 1B The diagram shows a top view of a multi-level die assembly 104 including one or more trenches 135 of a dielectric material 133 and one or more TDVs 115 in the trenches 135. The trenches 135 may have any suitable shape. Figure 1B As shown in , the grooves 135 can have a rectangular or cubic shape, but can also have other shapes, such as cylindrical or conical. The grooves 135 can have any suitable dimensions, for example, a single groove 135 can have a width 191 (e.g., y dimension) between 0.5 microns and 200 microns and a length 193 (e.g., x dimension) between 0.5 microns and 200 microns. The one or more grooves 135 can have any suitable pattern, arrangement, and configuration. As shown in FIG. Figure 1B As shown in , for example, the grooves 135 can have the same size and shape, can have different sizes and shapes, can be arranged symmetrically, can be arranged asymmetrically, can be within an interior portion of the multi-level tube die assembly 104, or can be along an exterior portion of the multi-level tube die assembly 104 (for example, along a perimeter or edge).

[0041] Figure 1C According to various embodiments Figure 1B An enlarged view of a portion of the , as indicated by the dotted line. Figure 1C 1 and 12. A circuit diagram having four TDVs 115 and conductive paths (eg, Figure 1A A top view of the groove 135 of the conductive path 117. Figure 1C As shown in , the TDV 115 (e.g., the top TDV 115) can be electrically coupled to one side of the die 114 through the conductive path 117, (e.g., the bottom TDV 115) can be electrically coupled to both sides of the die through the conductive path 117, or the first TDV 115 can be electrically coupled to the first side of the die 114 through the first conductive path 117, and the second TDV 115 can be electrically coupled to the second side of the die 114 (e.g., two middle TDVs 115). The trench 135 can further include a conductive path 111 that is not electrically coupled to the TDV 115 (e.g., the top conductive path). The TDV 115 can have any suitable size. In some embodiments, an individual TDV 115 can have a cross-section or diameter 195 between 40 nanometers and 10 microns (e.g., between 40 nanometers and 0.5 microns, between 0.5 microns and 2.5 microns, between 2 microns and 5 microns, or between 5 microns and 10 microns). TDVs 115 can have any suitable cross-sectional shape, such as square, triangular, and oval, among others. TDVs 115 can have any suitable arrangement. For example, in some embodiments, TDVs 115 can be spaced 197 between 40 nanometers and 5 micrometers (e.g., between 40 nanometers and 80 nanometers, between 1 micrometer and 5 micrometers, or between 5 micrometers and 10 micrometers). In some embodiments, conductive path 111 or conductive path 117 can have a length 199 (e.g., x dimension) between 40 nanometers and 5 micrometers.

[0042] Figure 1D According to various embodiments Figure 1C Side cross-sectional view along line BB'. Figure 1D A portion of a multi-level die assembly 104 is shown having three vertically stacked die 114-1, 114-2, 114-3 and a trench 135 through the dielectric material of the stacked die 114 having two TDVs 115. As described above with reference to Figure 1B As shown, trench 135 may have a width 191 (eg, a y-dimension). TDVs 115 may have a diameter 195 and may be spaced 197 apart, as described above with reference to FIG. Figure 1C Although Figure 1D Three vertically stacked dies are illustrated, but the stack may include any suitable number of dies.

[0043] like Figure 1AAs shown in FIG. 1 , TDV 115 may electrically couple individual die 114 and / or base die 103 to each other via conductive paths 118. In some embodiments, base die 103 may be a support structure (e.g., such as a substrate) that does not include circuitry and is not electrically coupled to TDV 115. Figure 6 In some embodiments, as shown Figure 1A As shown in , base die 103 includes logic circuits and can be electrically coupled to components in a microelectronic assembly (eg, electrically coupled to TDV 115 or other conductive paths (not shown)). Figure 1A As shown in , the base die 103 may include a bottom surface (e.g., first surface 172-1) and an opposite top surface (e.g., second surface 172-2). The base die 103 may further include a conductive path 119 on the top surface 172-2. The first level 104-1 of the multi-level die assembly 104 may be attached to the top surface 172-2 of the base die 103. Figure 1E As shown in , the die 114 may have a bottom surface (e.g., a first surface 171-1), an opposite top surface (e.g., a second surface 171-2), and a side surface 171-3, also referred to herein as a lateral surface, which is substantially perpendicular to the top surface 171-2 and the bottom surface 171-1. The lateral surface 171-3 may include an inner lateral surface of the trench 135 adjacent to the dielectric material 133, or may include an edge or outer lateral surface of the die 114. Further, the bottom surface 171-1 may be referred to herein as the "active side", which may include devices and components such as transistors, capacitors, inductors, resistors, etc., as indicated by the diagonal lines. The die 114 may further include a conductive path 117 extending laterally from the active surface 171-1 that is electrically coupled to the TDV 115. In some embodiments, the die 114 may further include a redistribution layer (RDL) 149 at the active surface 171-1. RDL 149 may include insulating material 137 (e.g., a dielectric material formed in multiple layers as known in the art) and one or more conductive paths (e.g., including conductive traces and / or conductive vias) through the dielectric material coupled to conductive path 117. Figure 1AAs shown in , the die 114 can be at least partially surrounded by a dielectric material 137 (e.g., the dielectric material 137 can be on the bottom surface 171-1 and the top surface 171-2 of the die 114). In some embodiments, the dielectric material 137 can include an oxide-based material (e.g., silicon dioxide, silicon oxynitride, or spin-on oxide), or a low-k and ultra-low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymer dielectrics). In some embodiments, the dielectric material 137 around the die 114 and the dielectric material 137 of the RDL 149 can be the same dielectric material. In some embodiments, the dielectric material 137 around the die 114 and the dielectric material 137 of the RDL 149 can be different dielectric materials. In some embodiments, the dielectric material 133 of the trench 135 can be a different dielectric material than the dielectric material 137 around the die 114 and the dielectric material 137 of the RDL 149. In some embodiments, the dielectric materials 133 and 137 can be the same dielectric material. The TDV 115 may be bounded by a gasket material, such as an adhesive gasket and / or a barrier gasket.

[0044] The multi-level die assembly 104 may include multiple levels or layers (e.g., layers 104-1, 104-2, 104-3, and 104-4). Individual layers of the multi-level die assembly 104 may include a die 114 having a trench 135 of dielectric material 133 on a side surface 171-3, and a TDV 115 electrically coupled to a conductive path 117 on the die 114. For example, Figure 1AAs shown in , the multi-level die assembly 104 may include four vertically stacked layers (e.g., layers 104-1, 104-2, 104-3, and 104-4), each layer including a die 114 (e.g., die 114-1, 114-2, 114-3, and 114-4, respectively), each die 114 having a conductive path 117 (e.g., conductive paths 117-1, 117-2, 117-3, and 117-4, respectively) coupled to a separate TDV 115 (e.g., TDV 115-1, 115-2, 115-3, and 115-4, respectively) at a side surface 171-3 of the die 114. By electrically coupling the TDV 115 directly to the die 114, any connection failure may be limited to the level having the affected die and / or the affected connection, without accumulating and affecting connections in other levels. In some embodiments, the conductive paths 119 on the base die 103 may be electrically coupled to the TDVs 115 (e.g., TDV 115-5). In some embodiments, the multi-level die assembly 104 may include conductive paths 118 electrically coupled to the TDVs 115 at the top surface. In some embodiments, the multi-level die assembly 104 may be attached to the base die 103 by fusion bonding. As used herein, the term "fusion bonding" refers to a dielectric-to-dielectric bonding technique (e.g., a technique in which dielectrics of opposing interfaces are brought into contact and then subjected to heat and sometimes pressure).

[0045] TDV 115 may be formed of any suitable conductive material, including metals such as copper, nickel, molybdenum, ruthenium, cobalt, polysilicon, or tungsten, or metal alloys thereof. TDV 115 may have any suitable size and shape, which may depend on the process used to form TDV 115, as described below in Figure 6 12. TDV 115 may span any suitable number of layers. In some embodiments, TDV 115 may span four layers, such as Figure 1A In some embodiments, TDV 115 may span two layers, such as Fig.13 . In some embodiments, a single TDV 115 may span more than four layers. In some embodiments, a single TDV 115 may have an aspect ratio (height: diameter) between 10:1 and 100:1 (e.g., between 25:1 and 75:1). In some embodiments, the pitch of the TDVs is between 80 nanometers and 10 microns. As used herein, the pitch is measured from center to center (e.g., from the center of a TDV to the center of an adjacent TDV).

[0046] The multi-level die assembly 104 may have any suitable dimensions. For example, in some embodiments, the thickness (eg, z dimension or height) of the multi-level die assembly 104 may be between 1 micrometer (um) and 1000 um. Figure 1A A multi-level die assembly 104 having four layers is illustrated in the figure, but the multi-level die assembly 104 may include any suitable number of layers, any suitable number of dies, and any suitable die arrangement. For example, the multi-level die assembly 104 may include between 2 and 128 vertically stacked dies. In some embodiments, the multi-level die assembly 104 may include between 2 and 32 vertically stacked dies. In some embodiments, the multi-level die assembly 104 may include between 2 and 16 vertically stacked dies (e.g., SRAM) and may have a thickness of less than or equal to 4um. In some embodiments, the multi-level die assembly 104 may include between 32 and 128 vertically stacked dies (e.g., DRAM), may have a thickness of less than or equal to 700um, and may have a thickness of less than 50 square millimeters (mm 2 ) to 200mm 2 The area between.

[0047] The tube core 114 and the base tube core 103 disclosed in this article may include an insulating material (e.g., an insulating material formed in multiple layers as known in the art) and multiple conductive paths formed through the insulating material. In some embodiments, the insulating material of the tube core may include a dielectric material commonly used in semiconductor manufacturing, such as silicon and one or more of oxygen, nitrogen and carbon (e.g., in the form of silicon oxide, silicon nitride, silicon oxynitride or silicon carbonitride); a polyimide material; or a low-k or ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, an organic polymer dielectric, a photoimageable dielectric and / or a benzocyclobutene-based polymer). The conductive path in the tube core may include conductive traces and / or conductive vias, and any of the conductive contacts in the tube core may be connected in any suitable manner (e.g., connecting multiple conductive contacts on the same surface or different surfaces of the tube core). Refer to the following. Fig.16 Example structures that may be included in the dies disclosed herein are discussed.Conductive paths in the die may be bounded by liner materials, such as bond pads and / or barrier pads, as applicable.

[0048] In some embodiments, microelectronic assembly 100 may include a redistribution layer (RDL) (not shown) between one or more of the layers of multi-level die assembly 104 and / or between multi-level die assembly 104 and base die 103. The RDL may include an insulating material (e.g., a dielectric material formed in multiple layers as known in the art) and one or more conductive paths (e.g., including conductive traces and / or conductive vias) passing through the dielectric material.

[0049] Although Figure 1A A single multi-level die assembly 104 and a single base die 103 are illustrated in FIG, but this is merely an example, and the microelectronic assembly 100 may include any number of multi-level die assemblies 104 and any number of base die 103. In some embodiments, the multi-level die assembly 104 may not be attached to the base die 103, but may instead be attached to an interposer or substrate. The die 103, 114 may perform any suitable functionality and may include processing devices, memory, communication devices, sensors, or any other computing components or circuits. For example, the base die 103 may include a controller die having logic elements (e.g., logic circuits), and the die 114 may include memory, such as SRAM, DRAM, or MRAM. In another example, the base die 103 may include a central processing unit (CPU), a platform controller hub (PCH), a graphics processing unit (GPU), a field programmable gate array (FPGA), a system on chip (SoC) die, or an input / output (I / O) hub die, and the die 114 may include SRAM, DRAM, or MRAM.

[0050] The microelectronic assembly 100 may further include a packaging substrate 102. The packaging substrate 102 may have a bottom surface (e.g., a first surface 170-1) and an opposite top surface (e.g., a second surface 170-2). The base die 103 may be electrically coupled to the packaging substrate 102 via a first level interconnect 120. The first level interconnect 120 may be surrounded by an underfill material 160 (e.g., the underfill material 160 may be disposed between the base die 103 and the second surface 170-2 of the packaging substrate 102). The packaging substrate 102 may have a first conductive contact 134 on the first surface 170-1 and a second conductive contact 122 on the second surface 170-2. The base die 103 may have a conductive contact 124. The conductive contact 124 on the base die 103 may be coupled to the conductive contact 122 on the second surface 170-2 of the packaging substrate 102 via the first level interconnect 120. In some embodiments, the first level interconnect 120 may include solder bumps in flip chip technology (eg, Figure 1Ain other embodiments, the first level interconnect 120 may include a wire for wire bonding technology, or any other suitable interconnect surrounded by the bottom fill material 160.

[0051] The bottom fill material 160 may be any suitable material. The bottom fill material 160 may be an insulating material, such as an appropriate epoxy resin material. In some embodiments, the bottom fill material 160 may include a capillary bottom fill material, a thermal interface material (TIM), a non-conductive film (NCF), or a molded bottom fill material. The bottom fill material 160 may be selected to have a CTE that can relieve or minimize stress between the base die 103 and the package substrate 102. In some embodiments, the bottom fill material 160 may include an epoxy flux that assists in soldering the base die 103 to the package substrate 102 when forming the first level interconnect 120, and then polymerizes and seals the first level interconnect 120. In some embodiments, the CTE of the bottom fill material 160 may have a value between the CTE of the package substrate 102 (e.g., the CTE of the dielectric material of the package substrate 102) and the CTE of the base die 103. The bottom fill material 160 may be dispensed using any suitable process, such as a capillary bottom fill process or a molded bottom fill process.

[0052] The packaging substrate 102 may include an insulating material (e.g., a dielectric material formed in multiple layers as known in the art) and one or more conductive paths (not shown) to route power, ground, and signals through the dielectric material (e.g., including conductive traces and / or conductive vias, as shown). In some embodiments, the insulating material of the packaging substrate 102 may be a dielectric material, such as an organic dielectric material, a flame retardant grade 4 material (FR-4), a BT resin, a polyimide material, a glass-reinforced epoxy matrix material, an organic dielectric with an inorganic filler, or a low-k and ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). In particular, when the packaging substrate 102 is formed using a standard PCB process, the packaging substrate 102 may include FR-4, and the conductive paths in the packaging substrate 102 may be formed by patterned copper sheets separated by stacked layers of FR-4. The conductive paths in the packaging substrate 102 may be delimited by a liner material, such as an adhesive liner and / or a barrier liner, as applicable. In some embodiments, packaging substrate 102 may be a coreless substrate, a UTC substrate, a wafer-level package, or any other suitable package known in the art that is designed to minimize z-height. Packaging substrate 102 may include conductive paths (not shown) that allow power, ground, and other electrical signals to move between base die 103 and packaging substrate 102. In some embodiments, base die 103 may not be coupled to packaging substrate 102, but may instead be coupled to an interposer, other substrate, or circuit board, such as a PCB.

[0053] In some embodiments, the encapsulation substrate 102 may be formed using a lithographically defined through-hole encapsulation process. In some embodiments, the encapsulation substrate 102 may be manufactured using a standard organic encapsulation manufacturing process, and thus the encapsulation substrate 102 may take the form of an organic encapsulation. In some embodiments, the encapsulation substrate 102 may be a collection of redistribution layers formed on a panel carrier by laminating or spin coating on a dielectric material and creating conductive vias and lines by laser drilling or ablation and plating. In some embodiments, the encapsulation substrate 102 may be formed on a removable carrier using any suitable technology such as redistribution layer technology. Any method known in the art for manufacturing the encapsulation substrate 102 may be used, and for the sake of brevity, such methods will not be discussed in further detail herein.

[0054] In some embodiments, the package substrate 102 can be a low-density medium, and the base die 103 and the die 114 can be a high-density medium or have areas with higher-density medium. As used herein, the terms "lower density" and "higher density" are relative terms, indicating that the conductive paths (e.g., including conductive interconnects, conductive lines, and conductive vias) in the lower-density medium are larger and / or have a larger pitch than the conductive paths in the higher-density medium. In some embodiments, the higher-density medium can be manufactured using a modified semi-additive process or a semi-additive deposition process using advanced lithography (with small vertical interconnect features formed by advanced laser or photolithography processes), while the lower-density medium can be a PCB manufactured using a standard PCB process (e.g., a standard subtractive process that uses etching chemistry to remove areas of unwanted metal such as copper, and has rough vertical interconnect features formed by a standard laser process). In other embodiments, the higher-density medium can be manufactured using semiconductor manufacturing processes, such as a single damascene process or a dual damascene process.

[0055] The microelectronic assembly 100 may further include a circuit board 131. The first conductive contacts 134 on the first surface 170-1 of the package substrate 102 may be coupled to the conductive contacts 132 on the surface of the circuit board 131 via the second level interconnects 130. The second level interconnects 130 may be surrounded by an underfill material 160. In some embodiments, the second level interconnects 130 may include solder balls (e.g., solder balls) for ball grid array (BGA) coupling. Figure 1A ); in other embodiments, the second level interconnect 130 may include solder paste contacts to provide a land grid array (LGA) interconnect or any other suitable interconnect. In some embodiments, the circuit board 131 may include one or more components (not shown) disposed thereon. The circuit board 131 may include conductive paths that allow power, ground, and other electrical signals to move between the circuit board 131 and the package substrate 102 and between the circuit board 131 and the base die 103, as is known in the art.

[0056] Although Figure 1A A single IC package (e.g., package substrate 102 with multi-level die assembly 104 on base die 103) is illustrated as being disposed on circuit board 131, but this is for ease of illustration only, and multiple IC packages with multiple dies may be disposed on circuit board 131. In some embodiments, circuit board 131 may be a PCB (e.g., a motherboard). In some embodiments, circuit board 131 may be another IC package, and microelectronic assembly 100 may be a package-on-package structure. In some embodiments, circuit board 131 may be an interposer, and microelectronic assembly 100 may be a package-on-interposer structure.

[0057] Figure 1A Many elements of the microelectronic assembly 100 are included in other accompanying drawings in the accompanying drawings; when discussing these figures, the discussion of these elements will not be repeated, and any of these elements can take any form disclosed herein. For simplicity, Figure 1A Some of the elements of the microelectronic assembly 100 are not included in other accompanying drawings in the accompanying drawings, but the microelectronic assembly 100 may include these omitted elements. In some embodiments, individual microelectronic assemblies in the microelectronic assembly 100 disclosed herein may be used as a system-in-package (SiP) in which multiple dies 114 with different functionalities are included. In such an embodiment, the microelectronic assembly 100 may be referred to as a SiP.

[0058] Any suitable technique may be used to fabricate the microelectronic assembly 100 disclosed herein. For example, FIG. 2A to FIG. 2J According to various embodiments, Figure 1A 1 is a side cross-sectional view of various stages in the exemplary process of a microelectronic assembly 100. Although the following reference FIG. 2A to FIG. 2J The operations discussed in the present disclosure (and other figures showing the manufacturing process) are illustrated in a particular order, but these operations may be performed in any suitable order. Further, additional operations not illustrated may also be performed without departing from the scope of the present disclosure. In addition, the descriptions herein may be modified according to the present disclosure. FIG. 2A to FIG. 2J Various ones of the operations discussed herein may be used to fabricate other ones of the microelectronic assemblies 100 disclosed herein.

[0059] FIG. 2A to FIG. 2H An example process of creating trenches 135 with dielectric material in a multi-level die assembly 104 of vertically stacked dies 114 is illustrated. Figures 2I to 2J An example process for forming a via opening and depositing a conductive material to create a TDV 115 through the trench 135 is illustrated. FIG. 2A to FIG. 2J The process at the die level is illustrated, but the process can be performed at the wafer level and then undergo a singulation process to form individual dies. FIG. 2A to FIG. 2J The formation of a single trench is illustrated, but the process can be performed to form multiple trenches. FIG. 2A to FIG. 2JAs shown in , in each layer of the multi-level die assembly 104, a trench may be formed through the material of the die 114, the trench and the top surface of the die 114 may be filled with a dielectric material 133, and after all layers are stacked, a via opening may be formed through the dielectric material in the trench and filled with a conductive material to form a TDV 115, which allows a single etching process and a single conductive filling process for electrically coupling the die 114 in each layer of the multi-level die assembly 104. By forming the trench and filling with a dielectric material, a connection area for the TDV 115 through the dielectric material may be created. Because the connection area includes only dielectric material, a high aspect ratio drilling process may be used to form the via opening. The etching process is simplified by eliminating the need for different etching processes; a first process to remove the material of the die 114 and a second process to remove the dielectric material 133. A less complex etching process may enable better and more consistent electrical contact with the conductive metal without the need for a dielectric liner, and may prevent the conductive metal from shorting to the silicon. By creating a connection region, the TDV 115 can be formed as a photolithographically large structure with a relaxed aspect ratio. Further, by enabling a less complex etching process, very small and high-yield vertical connections can be formed, which are impossible to form using other die stacking and bonding techniques. Small and high-yield vertical connections increase bandwidth, reduce latency, and reduce power due to reduced interconnect length, which leads to significantly higher performance, lower cost, and / or higher volume density.

[0060] Figure 2A A die 114-1 including an active surface 171-1 and a conductive path 117 in a dielectric material 133 and a base die 103 including a conductive path 119 in a dielectric material 133 are illustrated. Die 114-1 is positioned with active surface 171-1 facing conductive path 119 on a surface of base die 103. Die 114-1 and base die 103 may include semiconductor dies or supporting substrates. In some embodiments, a carrier may be used instead of base die 103.

[0061] Figure 2B The assembly is illustrated after attaching the active surface 171-1 of die 114-1 to the surface of base die 103. Die 114-1 may be attached to base die 103 using any suitable technique, including fusion bonding. In some embodiments, the surfaces of base die 103 and die 114-1 may undergo additional operations prior to bonding, such as planarization using chemical mechanical polishing (CMP) and / or plasma activation.

[0062] Figure 2CThe assembly is shown after material is removed from the top surface of die 114-1 to thin die 114-1. The material that is the inactive portion of die 114-1 may include silicon, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, another material classified as a III-V group, or an insulating material such as silicon dioxide (glass), ceramic or quartz, among other materials. The material may be removed using any suitable technique, including, for example, grinding, etching, such as chemical etching.

[0063] Figure 2D The assembly is illustrated after openings 165 are formed through the material of die 114-1. Openings 165 may be formed by removing material of die 114-1 and exposing conductive paths 117 and dielectric material 133 on bottom surface 171-1 of die 114-1. The material of die 114-1 may be removed using any suitable technique, including, for example, grinding, etching, such as chemical etching. Openings 165 may have any suitable dimensions for creating connection areas, and may depend on the number and size of TDVs 115 to be formed.

[0064] Figure 2E The assembly is illustrated after dielectric material 133 is deposited in opening 165 to form trench 135 and dielectric material 133 is deposited on and around die 114-1 to form first layer 104-1. Dielectric material 133 may be formed using any suitable process, including chemical vapor deposition (CVD) or a spin-on-glass process. The thickness of dielectric material 133 on die 114-1 may depend on the desired overall thickness of multi-level die assembly 104 and / or on whether RDLs are to be deposited between layers.

[0065] Figure 2F The die 114-2 is shown including an active surface 171-1 and a conductive path 117 in a dielectric material 133, which is connected to the Figure 2E The die 114-2 is positioned with the active surface 171-1 facing the Figure 2E The top surface of the assembly (eg, the first layer 104-1).

[0066] Figure 2G The active surface 171-1 of the die 114-2 is shown by attaching (eg, as Figure 2B ) to Figure 2E The top surface of the assembly and perform as FIG. 2C to FIG. 2EThe assembly after forming the second layer 104-2 by the operations described in (e.g., removing material from the top surface of the tube core 114-2 to thin the tube core 114-2, forming an opening 165 through the material of the tube core 114-2, and depositing the dielectric material 133 in the opening 165 to form the trench 135 and depositing the dielectric material 133 on and around the tube core 114-1).

[0067] Figure 2H The diagram shows that by executing Figure 2G The assembly after forming the third layer 104 - 3 and the fourth layer 104 - 4 of the multi-level die assembly 104 by following the operations described in 1 for forming the layer 104 - 2 .

[0068] Fig.2I The diagram shows Figure 2H The assembly after depositing a mask material 109 on the top surface of the assembly and forming via openings 113 through the dielectric material 133 to the corresponding conductive paths 117-1, 117-2, 117-3, 117-4, 119. The via openings 113 can be formed using any suitable technique, including selective dielectric material etching (e.g., high aspect ratio etching) that stops at the metal material of the conductive paths 117, 119.

[0069] Figure 2J The assembly is illustrated after removing the mask material 109 and depositing a conductive material (such as copper, nickel, molybdenum, ruthenium, cobalt, polysilicon, or tungsten) in the via openings 113 to form conductive TDVs 115 (e.g., TDVs 115-1, 115-2, 115-3, 115-4, 115-5). The conductive material may be deposited using any suitable process, such as electroplating, ALD, sputtering, or electroless plating. In some embodiments, the via openings 113 may undergo a cleaning process prior to depositing the conductive material. If multiple assemblies are manufactured together, the assemblies may be singulated. Figure 2J Further manufacturing operations are performed on the microelectronic assembly 100 to form other microelectronic assemblies 100. For example, Figure 2J The assembly may undergo a finishing process and / or a metallization or RDL process on the top surface of the assembly to electrically couple the TDVs 115 together (eg, to form Figure 1A In another example, Figure 2J The bottom surface of the base die 103 of the assembly can be electrically coupled to the package substrate 102 through the first level interconnect 120, and the package substrate 102 can be electrically coupled to the circuit board 131 through the second level interconnect 130 to form Figure 1A A microelectronic assembly 100 is provided.

[0070] FIG. 3A to FIG. 3Jare side cross-sectional views of various stages in an example process for manufacturing a portion of a microelectronic assembly according to various embodiments. In particular, FIG. 3A to FIG. 3J Another example process for creating trenches with dielectric material in a multi-level die assembly 104 of vertically stacked dies 114 is illustrated.

[0071] Figure 3A Die 114-1 is illustrated including dielectric material 133 on active surface 171-1. Wafer 314-1 may include a semiconductor wafer.

[0072] Figure 3B Die 114-1 is illustrated after removing dielectric material 133 and forming openings 165 by removing material of die 114-1. Dielectric material 133 and material of die 114-1 may be removed using any suitable technique, including, for example, grinding, etching, such as chemical etching. Openings 165 may have any suitable dimensions for creating connection areas, and may depend on the number and size of TDVs 115 to be formed.

[0073] Figure 3C Die 114-1 is illustrated after depositing dielectric material 133 in opening 165 and forming conductive paths 117 at active surface 171-1. Dielectric material may be deposited using any suitable technique, including as described above with reference to Figure 2. Conductive paths 117 may be formed using any suitable technique, including ALD or electroplating.

[0074] Figure 3D The diagram shows the alignment with the base die 103. Figure 3C The present invention relates to a chip 114-1 having a base die 103 including a conductive path 119 in a dielectric material 133. The die 114-1 is positioned with the active surface 171-1 facing the conductive path 119 on the surface of the base die 103. The base die 103 may include a semiconductor die. In some embodiments, a carrier or support structure may be used instead of the base die 103.

[0075] Figure 3E The assembly is illustrated after attaching the active surface 171-1 of the die 114-1 to the surface of the base die 103. The die 114-1 may be attached to the base die 103 using any suitable technique, including as described above with reference to FIG.

[0076] Figure 3FThe assembly is shown after material is removed from the top surface of die 114-1 to expose trench 135. The material that is the inactive portion of die 114-1 can be removed using any suitable technique, including, for example, grinding, etching, such as chemical etching. In some embodiments, a portion of dielectric material 133 can be removed along with the material of die 114-1.

[0077] Figure 3G The assembly is illustrated after depositing dielectric material 133 on die 114-1 and on dielectric material 133 in trenches 165 to form first layer 104-1. Dielectric material 133 may be formed using any suitable process and have any suitable dimensions, including as described above with reference to FIG.

[0078] Figure 3H The die 114-2 is shown including an active surface 171-1 having a conductive path 117 in a dielectric material 133 and having a conductive path 117 in a dielectric material 133. Figure 3G The groove 135 of the assembly is aligned with the opening 165 of the dielectric material 133. Figure 3A-3C Die 114-2 is formed by the operations described with reference to forming die 114-1. Die 114-2 is positioned with active surface 171-1 facing Figure 3G The top surface of the assembly (eg, the first layer 104-1).

[0079] Fig. 3I The diagram shows that by executing Figure 3F-3G The assembly after forming the second layer 104 - 2 by the operations described in (eg, removing material from the top surface of the die 114 - 2 and depositing the dielectric material 133 on the die 114 - 2 and on the dielectric material 133 in the trenches 135 ).

[0080] Figure 3J The diagram shows that by executing Figure 3H-Figure 3I The assembly after forming the third layer 104-3 and the fourth layer 104-4 of the multi-level die assembly 104 is formed by performing the operations described in the for forming layer 104-2. Figure 3J Further operations may be performed on the assembly, including, for example, adding additional layers and / or forming TDV 115, as described above with reference to Figures 2I to 2J described.

[0081] FIG. 4A to FIG. 4D are side cross-sectional views of various stages in an example process for manufacturing a portion of a microelectronic assembly according to various embodiments. In particular, FIG. 4A to FIG. 4D Another example process for creating a die 114 similar to Figure 3CThe die 114 - 1 has a trench 135 with a dielectric material 133 .

[0082] Figure 4A Illustrated is die 114 , which may include a semiconductor die.

[0083] Figure 4B Die 114 is illustrated after opening 165 is formed by removing material of die 114. Any suitable technique may be used to remove material, including as described above with reference to FIG.

[0084] Figure 4C Die 114 is illustrated after deposition of dielectric material 133 in opening 165. The dielectric material may be deposited using any suitable technique, including as described above with reference to FIG.

[0085] Figure 4D The die 114 is shown after forming the active surface 171-1 and the conductive paths 117 in the dielectric material 133 on the active surface 171-1. The active surface 171-1 and the conductive paths 117 may be formed using any suitable technique, including ALD or electroplating. Figure 4D Further operations are performed on the die 114, including, for example, adding additional layers, as described above with reference to Figures 3D to 3J As described above, and forming TDV 115, as described above with reference to Figures 2I to 2J As described.

[0086] Figure 5A 1 is a side cross-sectional view of another example microelectronic assembly 100 according to various embodiments. The microelectronic assembly 100 may include a first base die 103-1 and a multi-level die assembly 104 having vertically stacked die 114 and a TDV 115 passing through a trench 135 of a dielectric material 133 through the die 114, the TDV 115 being electrically coupled to the die 114 and the first base die 103-1 at one end and being electrically coupled to the second base die 103-2 at an opposite end through a direct bonding interconnect 180. For example, as Figure 5AAs shown in , the multi-level die assembly 104 may include four vertically stacked layers including die 114 (e.g., die 114-1, 114-2, 114-3, and 114-4, respectively) on a first base die 103-1, the base die 103-1 having a conductive path 119, and each individual die 114 having a conductive path 117, wherein a TDV 115 is electrically coupled to the die (e.g., die 114 or base die 103) at the bottom end, and directly bonded to a second base die 103-2 at the top end. In some embodiments, the second base die 103-2 may electrically couple the die 114 and the first base die 103-1 together through the TDV 115. As used herein, the term "direct bonding" is used to include metal-to-metal bonding techniques (e.g., copper-to-copper bonding, or other techniques in which the conductive contacts of the opposing interfaces are first contacted and then subjected to heat and / or compression) and hybrid bonding techniques (e.g., techniques in which the dielectric materials of the opposing interfaces are first contacted and then subjected to heat and sometimes compression, or techniques in which the conductive contacts and dielectric materials of the opposing interfaces are contacted substantially simultaneously and then subjected to heat and compression). In such techniques, elevated pressures and / or temperatures may be applied to bond the contacting conductive contacts and / or the contacting dielectric materials.

[0087] Figure 5B is a side cross-sectional view of another example microelectronic assembly 100 according to various embodiments. Figure 5B The microelectronic assembly 100 of FIG. 1 illustrates an assembly having a plurality of vertically stacked dies and a plurality of trenches 135 having TDVs 115. For example, the microelectronic assembly 100 may include a first base die 103-1 and a multi-level die assembly 104 having vertically stacked dies 114 (e.g., dies 114-1, 114-2, 114-3, and 114-4). The microelectronic assembly may include a first TDV 115A in a first trench 135A that is electrically coupled at one end to a conductive path 117A of the die 114 and a conductive path 119A of the base die 103-1, and at an opposite end to a second base die 103-2 through a direct bonding interconnect 180A. The microelectronic assembly may further include a second TDV 115B in the second trench 135B electrically coupled at one end to the conductive path 117B of the die 114 and the conductive path 119B of the first base die 103-1 and at an opposite end to the second base die 103-2 through a direct bonding interconnect 180B.

[0088] Figure 5C is a side cross-sectional view of another example microelectronic assembly 100 according to various embodiments. Figure 5CThe microelectronic assembly 100 of FIG. 1 illustrates an assembly having a plurality of vertically stacked dies having trenches through the dielectric material of the dies and a plurality of first TDVs 115A and second TDVs 115B. For example, the microelectronic assembly 100 may include a first base die 103-1 and a multi-level die assembly 104 having vertically stacked dies 114 (e.g., dies 114-1, 114-2, 114-3, and 114-4). The microelectronic assembly may include a first TDV 115A electrically coupled at one end to a conductive path 117A of the die 114 and a conductive path 119A of the first base die 103-1 on a first side of a trench 135, and electrically coupled at an opposite end to a second base die 103-2 through a direct bonding interconnect 180A. The microelectronic assembly may further include a second TDV 115B electrically coupled at one end to the conductive path 117B of the die 114 and the conductive path 119B of the first base die 103-1 on the second side of the trench 135, and electrically coupled at an opposite end to the second base die 103-2 through a direct bonding interconnect 180B.

[0089] Figure 5D is a side cross-sectional view of another example microelectronic assembly 100 having two TDVs electrically coupled to two separate conductive contacts according to various embodiments. Figure 5DThe microelectronic assembly 100 of FIG. 1 illustrates an assembly having a plurality of vertically stacked dies, wherein the plurality of stacked dies have trenches through a dielectric material of the die, a plurality of TDVs through the trenches 165, wherein more than one TDV is electrically coupled to the die. For example, the microelectronic assembly 100 may include a first base die 103-1 and a multi-level die assembly 104 having vertically stacked dies 114 (e.g., dies 114-1, 114-2, 114-3, and 114-4) and trenches 135 of dielectric material having a plurality of first TDVs 115A and a plurality of second TDVs 115B through the dielectric material. The microelectronic assembly may include two first TDVs 115A, which are electrically coupled to a separate conductive path 117A of the die 114 and a conductive path 119A of the first base die 103-1 on a first side of the trenches 135. The microelectronic assembly may further include two second TDVs 115B electrically coupled to the individual conductive paths 117B of the die 114 and the conductive paths 119B of the first base die 103-1 on the second side of the trench 135. The TDVs 115A, 115B may be electrically coupled to the die 114 and the first base die 103-1 at one end and electrically coupled to the second base die 103-2 at the opposite end through a direct bonding interconnect 180B.

[0090] Figure 6 is a side cross-sectional view of another example microelectronic assembly 100 having a single TDV electrically coupled to a plurality of vertically stacked dies according to various embodiments. Figure 6 The microelectronic assembly 100 of FIG. 1 illustrates an assembly having a plurality of vertically stacked dies including a first trench 135A and a second trench 135B through a dielectric material 133 of a die 114 (e.g., die 114-1, 114-2, 114-3, and 114-4). The first trench 135A has a first TDV 115A, and the second trench 135B has a second TDV 115B electrically coupled to the vertically stacked die 114. For example, the microelectronic assembly 100 may include a base die 103 and a multi-level die assembly 104 having vertically stacked dies 114. The microelectronic assembly may include a first TDV 115A through a first trench 135A of a dielectric material 133 electrically coupled to a conductive path 117A of a die 114. The microelectronic assembly can further include a second TDV 115B that is electrically coupled to the conductive path 117B of the die 114 through the second trench 135B of the dielectric material 133. In some embodiments, the first TDV 115A and the second TDV 115B can be stepped (eg, as shown in FIG. 1 ). Figure 6 ) or may have other shapes (e.g., Figure 8 , Figure 11 and Fig.13 ). The TDVs 115A, 115B may have conductive paths 118A, 118B at the top surface to electrically couple the die 114 to the base die 103 and / or other components (not shown) of the microelectronic assembly 100. Figure 6 A single TDV in a trench is shown, but a trench may have any number of TDVs, including two or more TDVs.

[0091] 7A to 7E Another example process for forming via openings and depositing conductive material to create the TDV 115 is illustrated. Fig. 7A The assembly is illustrated after depositing and patterning mask material 109 on the top surface (eg, patterning mask material 109 having openings 113 for forming vias) and forming via openings 113 through dielectric material 133 in trenches 135 to conductive paths 117-4, 117-8 in layer 104-4. Fig. 7A The assembly can be formed using any suitable technique, including any of the techniques described above in Figures 2-4. Fig. 7A The assembly may include vertically stacked dies 114 having conductive paths 117 (e.g., dies 114-1, 114-2, 114-3, 114-4 having first conductive paths 117-1, 117-2, 117-3, 117-4 and second conductive paths 117-5, 117-6, 117-7, 117-8, respectively). The mask material 109 may include any suitable material, such as a thick metal material, and may be deposited and patterned using any suitable technique. The via opening 113 may be formed using any suitable technique, including selective etching of the dielectric material 133 in the trench 135 (e.g., a high aspect ratio etch), the selective etching stopping at the metal material of the conductive paths 117-4, 117-8.

[0092] Figure 7B The assembly is shown after selectively removing the metal material of the conductive paths 117-4, 117-8. The metal material of the conductive paths 117-4, 117-8 can be removed using any suitable technique, such as a timed metal etch. If a metal mask material 109 is used, the timed metal etch can remove a portion of the metal mask material 109 (e.g., the mask can be "shrinked") and a larger opening 113 can be formed in the metal mask material 109, such as Figure 7B as shown in .

[0093] Figure 7CThe assembly is illustrated after forming a via opening 113 through the dielectric material 133 in the layer 104-3 to the conductive paths 117-3, 117-7 and selectively removing the metal material of the conductive paths 117-3, 117-7. The dielectric material 133 of the layer 104-3 can be removed using any suitable technique, including selective etching of the dielectric material 133, which can remove the dielectric material 133 from the via opening in the previous layer 104-4, so that the via opening 113 in the layer 104-4 has a larger cross-sectional dimension (e.g., x dimension and / or y dimension) than the via opening 113 in the layer 104-3. The larger cross-sectional size of the via opening 113 in layer 104-4 can expose additional metallic material of conductive paths 117-4, 117-8 so that when metallic material of conductive paths 117-3, 117-7 in layer 104-3 is removed, for example using a timed metal etch, the newly exposed metallic material of conductive paths 117-4, 117-8 in layer 104-4 can also be removed.

[0094] Fig.7D The assembly is shown after forming via openings through layers 104-2 and 104-1 and exposing conductive paths 117-1, 117-5 in layer 104-1 by removing dielectric and metal materials, as shown above. Figure 7C As described in .

[0095] Fig. 7E The assembly is illustrated after removing the mask material 109 and depositing a conductive material (such as copper, nickel, molybdenum, ruthenium, cobalt, polysilicon, or tungsten) in the via opening 113 to form a conductive TDV 115. The conductive material may be deposited using any suitable process, such as electroplating, ALD, sputtering, or electroless plating. In some embodiments, the via opening 113 may undergo a cleaning process prior to depositing the conductive material. If multiple assemblies are manufactured together, the assemblies may be singulated. Fig. 7E Further manufacturing operations are performed on the microelectronic assembly 100 to form other microelectronic assemblies 100. For example, Fig. 7E The assembly may undergo a finishing process and / or a metallization or RDL process on the top surface of the assembly to electrically couple the TDVs 115 together (eg, to form Figure 6 In another example, Fig. 7E The bottom surface of the base die 103 of the assembly may be electrically coupled to the package substrate 102 through the first level interconnect 120 , and the package substrate 102 may be electrically coupled to the circuit board 131 through the second level interconnect 130 .

[0096] Figure 8is a side cross-sectional view of another example microelectronic assembly 100 having a single TDV electrically coupled to a plurality of vertically stacked dies according to various embodiments. Figure 8 The microelectronic assembly 100 of FIG. 1 illustrates an assembly including a plurality of vertically stacked dies having a first trench 135A and a second trench 135B through a dielectric material 133 of a die 114 (e.g., die 114-1, 114-2, 114-3, and 114-4). The first trench 135A has a first TDV 115A, and the second trench 135B has a second TDV 115B electrically coupled to the vertically stacked die 114. The microelectronic assembly may include a first TDV 115A electrically coupled to a conductive path 117A of the die 114 through the first trench 135A of the dielectric material 133. The microelectronic assembly may further include a second TDV 115B electrically coupled to a conductive path 117B of the die 114 through the second trench 135B of the dielectric material 133. In some embodiments, the first TDV 115A and the second TDV 115B may be cylindrical or rectangular in shape (e.g., as shown in FIG. Figure 8 TDVs 115A, 115B may have conductive paths 118A, 118B at the top surface to electrically couple die 114 to base die 103 and / or other components (not shown) of microelectronic assembly 100 .

[0097] 9A to 9E Another example process for forming via openings and depositing conductive material to create the TDV 115 is illustrated. Fig.9A The assembly is illustrated after depositing and patterning mask material 109 on the top surface (eg, patterning mask material 109 having openings 113 for forming vias) and forming via openings 113 through dielectric material 133 in trenches 135 to conductive paths 117-4, 117-8 in layer 104-4. Fig.9A The assembly can be formed using any suitable technique, including any of the techniques described above in Figures 2-4. Fig.9AThe assembly may include vertically stacked dies 114 having conductive paths 117 (e.g., dies 114-1, 114-2, 114-3, 114-4 having first conductive paths 117-1, 117-2, 117-3, 117-4 and second conductive paths 117-5, 117-6, 117-7, 117-8, respectively). The mask material 109 may be any suitable material and may be deposited and patterned using any suitable technique, as described above with reference to FIG. 7. The via opening 113 may be formed using any suitable technique, including selective etching (e.g., high aspect ratio etching) of the dielectric material 133 in the trench 135, the selective etching stopping at the metal material of the conductive paths 117-4, 117-8.

[0098] Fig. 9B The assembly is shown after selectively removing the metal material of the conductive paths 117-4, 117-8 in the layer 104-4. The metal material of the conductive paths 117-4, 117-8 can be removed using any suitable technique, such as timed metal etching, but the mask may not be "shrinked" so that the via openings 113 have the same cross-sectional dimensions (e.g., x-dimension and / or y-dimension), as shown in FIG. Fig. 9B as shown in .

[0099] Fig. 9C The assembly is illustrated after forming via openings through layers 104-3, 104-2, and 104-1 by removing dielectric and metallic materials (as described above in FIG. 7) and exposing conductive paths 117-1, 117-5 in layer 104-1.

[0100] Fig.9D The assembly is illustrated after removing the mask material 109 and selectively etching the dielectric material from the via opening 113 to expand the cross-sectional dimensions (e.g., x-dimension and / or y-dimension) of the via opening 113 to expose a larger portion of the conductive path 117 to improve electrical contact between the conductive path 117 and the corresponding TDV 115. The dielectric material may be removed from the via opening 113 using any suitable technique, including, for example, isotropic etching.

[0101] Fig.9E The assembly is shown after depositing a conductive material (such as copper, nickel, molybdenum, ruthenium, cobalt, polysilicon, or tungsten) in the via opening 113 to form the conductive TDV 115. The conductive material can be deposited using any suitable process, such as electroplating, ALD, sputtering, or electroless plating. In some embodiments, the via opening 113 can undergo a cleaning process before depositing the conductive material. If multiple assemblies are manufactured together, the assemblies can be singulated. Fig.9EFurther manufacturing operations are performed on the microelectronic assembly 100 to form other microelectronic assemblies 100. For example, Fig.9E The assembly may undergo a finishing process and / or a metallization or RDL process on the top surface of the assembly to electrically couple the TDVs 115 together (eg, to form Figure 8 In another example, Fig.9E The bottom surface of the base die 103 of the assembly may be electrically coupled to the package substrate 102 through the first level interconnect 120 , and the package substrate 102 may be electrically coupled to the circuit board 131 through the second level interconnect 130 .

[0102] Fig.10 is a side cross-sectional view of another example microelectronic assembly 100 having a single TDV electrically coupled to a plurality of vertically stacked dies according to various embodiments. Fig.10 The microelectronic assembly 100 of FIG. 1 illustrates an assembly including a plurality of vertically stacked dies having a first trench 135A and a second trench 135B through a dielectric material 133 of a die 114 (e.g., die 114-1, 114-2, 114-3, and 114-4). The first trench 135A has a first TDV 115A, and the second trench 135B has a second TDV 115B electrically coupled to the vertically stacked die 114. The microelectronic assembly may include a first TDV 115A electrically coupled to a conductive path 117A of the die 114 through the first trench 135A of the dielectric material 133. The microelectronic assembly may further include a second TDV 115B electrically coupled to a conductive path 117B of the die 114 through the second trench 135B of the dielectric material 133. In some embodiments, the first TDV 115A and the second TDV 115B may be cylindrical or rectangular in shape (e.g., as shown in FIG. Fig.10 ). The TDVs 115A, 115B may have conductive paths 118A, 118B at the top surface to electrically couple the die 114 to the base die 103 and / or other components (not shown) of the microelectronic assembly 100 .

[0103] FIG. 11A to FIG. 11D Another example process for forming via openings and depositing conductive material to create the TDV 115 is illustrated. Fig.11A The assembly is illustrated after depositing and patterning a mask material 109 on the top surface (eg, patterning the mask material 109 having openings for forming vias). Fig.11A The assembly can be formed using any suitable technique, including any of the techniques described above in Figures 2 to 4. Fig.11AThe assembly may include vertically stacked dies 114 having conductive paths 117 (e.g., dies 114-1, 114-2, 114-3, 114-4 having first conductive paths 117-1, 117-2, 117-3, 117-4 and second conductive paths 117-5, 117-6, 117-7, 117-8, respectively). The conductive paths 117 may be patterned to be discontinuous (e.g., having openings filled with dielectric material 133) so that via openings may be formed in a single operation by selectively removing the dielectric material, as described below with reference to Fig. 11B The mask material 109 may be any suitable material and may be deposited and patterned using any suitable technique, as described above with reference to FIG.

[0104] Fig. 11B The assembly is illustrated after forming via openings 113 through dielectric material 133 in layers 104-4, 104-3, 104-2, 104-1. Via openings 113 may be formed using any suitable technique, including selective etching of dielectric material 133 in trenches 135 (eg, high aspect ratio etching).

[0105] Fig. 11C The assembly is illustrated after removing the mask material 109 and selectively etching the dielectric material from the via opening 113 to expand the cross-sectional dimensions (e.g., x-dimension and / or y-dimension) of the via opening 113 to expose a larger portion of the conductive path 117 to improve electrical contact between the conductive path 117 and the corresponding TDV 115. The dielectric material may be removed from the via opening 113 using any suitable technique, including, for example, isotropic etching.

[0106] Fig.11D The assembly is shown after depositing a conductive material (such as copper, nickel, molybdenum, ruthenium, cobalt, polysilicon, or tungsten) in the via opening 113 to form the conductive TDV 115. The conductive material can be deposited using any suitable process, such as electroplating, ALD, sputtering, or electroless plating. In some embodiments, the via opening 113 can undergo a cleaning process before depositing the conductive material. If multiple assemblies are manufactured together, the assemblies can be singulated. Fig.11D Further manufacturing operations are performed on the microelectronic assembly 100 to form other microelectronic assemblies 100. For example, Fig.11D The assembly may undergo a finishing process and / or a metallization or RDL process on the top surface of the assembly to electrically couple the TDVs 115 together (eg, to form Fig.10 In another example, Fig.11DThe bottom surface of the base die 103 of the assembly may be electrically coupled to the package substrate 102 through the first level interconnect 120 , and the package substrate 102 may be electrically coupled to the circuit board 131 through the second level interconnect 130 .

[0107] FIG. 12A to FIG. 12J According to various embodiments, Figure 8 and Fig.10 FIG. 1 is a side cross-sectional view of another example microelectronic assembly 100 at various stages in the process. Fig. 12A Die 114-1 is illustrated including opening 165 and dielectric material 133 in opening 165 and on active surface 171-1 of die 114-1. Die 114-1 may include a semiconductor die.

[0108] Fig. 12B Die 114-1 is illustrated after removing dielectric material 133 on active surface 171-1 of die 114-1 and forming via openings 1213 in openings 165 by selectively removing dielectric material 133 in openings 165. Dielectric material 133 may be removed using any suitable technique, including, for example, as described above with reference to FIG.

[0109] Fig. 12C The diagram shows Fig. 12B Die 114-1 after depositing etchable material 1215 in via opening 1213. Etchable material 1215 may be any suitable material that may be selectively and more easily etched than dielectric material 133 in trench 135. Etchable material 1215 may be deposited using any suitable technique, and may enable very fine pitch vias having very high aspect ratios, such as vias having an aspect ratio (height: diameter) greater than 50:1.

[0110] Fig.12D Die 114-1 is illustrated after forming conductive paths 117 in dielectric material 133 at active surface 171-1. Conductive paths 117 may be formed using any suitable technique, such as described above with reference to FIG.

[0111] Fig.12E The diagram shows the alignment with the base die 103. Fig.12D The base die 103 includes a conductive path 119 in the dielectric material 133. The die 114-1 is positioned with the active surface 171-1 facing the conductive path 119 on the surface of the base wafer 103. The base die 103 may include a semiconductor die. In some embodiments, a carrier may be used instead of the base die 103.

[0112] Fig.12F The assembly is illustrated after attaching the active surface 171-1 of the die 114-1 to the surface of the base die 103. As described above with reference to FIG2, the die 114-1 may be attached to the base die 103 using any suitable technique.

[0113] Figure 12G The assembly is illustrated after removing material from the top surface of the die 114 - 1 to expose the trenches 135 and the dielectric material 133 and the etchable material 1215 in the trenches 135 to form the first layer 104 - 1 . Fig.12F The thin layer of silicon (not shown) on the top surface of the assembly may undergo an oxidation process (e.g., a thermal oxidation process) to create a thin layer of silicon dioxide for bonding to the dielectric material 133 on the active surface of the next die 114-2 (e.g., as shown in FIG. Fig.12H The first layer 104 - 1 may be formed using any suitable process, including the process described above with reference to FIG. 2 .

[0114] Fig.12H The diagram shows that by executing the above Figure 12A-12G The assembly after forming the second layer 104 - 2 , the third layer 104 - 3 , and the fourth layer 104 - 4 of the multi-level die assembly 104 using the operations used to form the layer 104 - 1 .

[0115] Fig.12I The assembly is illustrated after selectively removing the etchable material 1215 and forming via openings 113 through the dielectric material 133 to respective conductive paths 117-1, 117-2, 117-3, 117-4. The etchable material 1215 may be removed using any suitable technique, such as low-cost wet etching.

[0116] Fig.12J The assembly is shown after depositing a conductive material (such as copper, nickel, molybdenum, ruthenium, cobalt, polysilicon, or tungsten) in the via opening 113 to form the conductive TDV 115. The conductive material can be deposited using any suitable process, such as electroplating, ALD, sputtering, or electroless plating. In some embodiments, the via opening 113 can undergo a cleaning process before depositing the conductive material. If multiple assemblies are manufactured together, the assemblies can be singulated. Fig.12J Further manufacturing operations are performed on the microelectronic assembly 100 to form other microelectronic assemblies 100. For example, Fig.12J The assembly may undergo a finishing process and / or a metallization or RDL process on the top surface of the assembly to electrically couple the TDV 115 to the base die 103 or other components (not shown) of the microelectronic assembly 100. In another example, Fig.12JThe bottom surface of the base die 103 of the assembly may be electrically coupled to the package substrate 102 through the first level interconnect 120 , and the package substrate 102 may be electrically coupled to the circuit board 131 through the second level interconnect 130 .

[0117] Fig.13 is a side cross-sectional view of another example microelectronic assembly 100 having vertically stacked TDVs 115 electrically coupled to vertically stacked dies 114 according to various embodiments. Fig.13The microelectronic assembly 100 of FIG. 1 illustrates a base die 103 and a multi-level die assembly 104 including eight vertically stacked dies 114 (e.g., dies 114-1, 114-2, 114-3, 114-4, 114-5, 114-6, 114-7, 114-8) and eight layers (e.g., layers 104-1, 104-2, 104-3, 104-4, 104-5, 104-6, 104-7, 104-8), each individual die having a conductive path 117 and a trench 135 of a dielectric material 133 along a side surface 171-3 of the die 114. The multi-level die assembly 104 may include a first subassembly 104A and a second subassembly 104B. The vertically stacked TDV 115 may include a first TDV 115A and a second TDV 115B, wherein the second TDV 115B is on and electrically coupled to the first TDV 115A. The first TDV 115A may be electrically coupled to the die 114-1, 114-2, 114-3, and 114-4, and the second TDV 115B may be electrically coupled to the die 114-5, 114-6, 114-7, and 114-8. The first subassembly 104A (e.g., including the first TDV 115A and the layers 104-1, 104-2, 104-3, and 104-4) may be formed using any suitable process, including, for example, the processes described above with reference to FIGS. 2 to 4, 7, 9, 11, and 12. The second subassembly 104B (e.g., including the second TDV 115B and layers 104-5, 104-6, 104-7, and 104-8) can be formed using any suitable process, including, for example, the process described above with reference to FIGS. 2 to 4, 7, 9, 11, and 12, wherein the second assembly 104B is formed on the first subassembly 104A (e.g., layer 104-5 is formed on layer 104-4 of the first subassembly, then layer 104-6 is formed on layer 104-5, and so on until layer 104-8 is formed and the second TDV 115B is formed). In some embodiments, the first subassembly 104A and the second subassembly 104B can be formed, and then the second subassembly 104B can be attached and electrically coupled to the top surface of the first subassembly 104A. The TDV 115 can have a conductive path 118 at the top surface to electrically couple the die 114 to the base die 103 and / or other components (not shown) of the microelectronic assembly 100 .

[0118] Fig.141 is a flow chart of an example method of manufacturing a microelectronic assembly according to various embodiments. At 1402, a vertical stack of die 114 (e.g., a multi-level die assembly 104) having a trench 135 through a dielectric material 133 of the die 114 can be formed using any suitable process, such as the process disclosed above with reference to FIGS. 2, 3, 4, 7, 9, 11, and 12. At 1404, a via opening 113 can be formed through the trench 135 through the dielectric material 133 of the die 114. The via opening can be formed using any suitable process, such as the process disclosed above with reference to FIGS. 2, 3, 4, 7, 9, 11, and 12. At 1406, a conductive material such as copper, nickel, molybdenum, ruthenium, cobalt, polysilicon, or tungsten can be deposited in the via opening to form a TDV 115 electrically coupled to the stack of die 114.

[0119] The microelectronic assemblies disclosed herein may be included in any suitable electronic device. Figures 15 to 18 Various examples of devices that may be included in or may include one or more of any of the microelectronic assemblies disclosed herein are illustrated.

[0120] Fig.15 1 is a top view of a wafer 1500 and die 1502 that may be included in any of the microelectronic assemblies disclosed herein. For example, die 1502 may be used as die 114, or may be included in die 114. Wafer 1500 may be composed of semiconductor material and may include one or more die 1502 having IC structures formed on a surface of wafer 1500. Each of die 1502 may be a repeating unit of a semiconductor product including any suitable IC. After fabrication of the semiconductor product is completed, wafer 1500 may undergo a singulation process in which die 1502 are separated from one another to provide discrete “chips” of the semiconductor product. Die 1502 may include one or more transistors (e.g., the ICs discussed below). Fig.16Some of the transistors 1640) and / or supporting circuits for routing electrical signals to the transistors and any other IC components. In some embodiments, the wafer 1500 or die 1502 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND gates, OR gates, NAND gates, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1502. For example, a memory array formed by multiple memory devices may be combined with a processing device (e.g., a processor) configured to store information in the memory devices or to execute instructions stored in the memory array. Fig.18 The processing device 1802) or other logic is formed on the same tube die 1502.

[0121] Fig.16 1 is a side cross-sectional view of an IC device 1600 that can be included in any of the dies 114 disclosed herein. For example, the IC device 1600 (eg, as part of the die 1502, as described above with reference to Fig.15 114, or may be included in die 114. One or more of IC devices 1600 may be included in one or more die 1502 ( Fig.15 ). IC device 1600 may be formed on substrate 1602 (eg, Fig.15 1500) and may be included in a die (e.g., Fig.15 The substrate 1602 may be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of the two). The substrate 1602 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the substrate 1602 may be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Additional materials classified as Group II-VI, Group III-V, or Group IV may also be used to form the substrate 1602. Although several examples of materials that may form the substrate 1602 are described herein, any material that may serve as the basis for the IC device 1600 may be used. The substrate 1602 may be a singulated die (e.g., Fig.15 of a die 1502) or a wafer (e.g., Fig.15 A portion of chip 1500).

[0122] IC device 1600 may include one or more device layers 1604 disposed on substrate 1602. Device layer 1604 may include features of one or more transistors 1640 (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on substrate 1602. Device layer 1604 may include, for example, one or more source and / or drain (S / D) regions 1620, a gate 1622 to control current in transistor 1640 between S / D regions 1620, and one or more S / D contacts 1624 to route electrical signals to / from S / D regions 1620. For clarity, transistor 1640 may include additional features not depicted, such as device isolation regions, gate contacts, and the like. Transistor 1640 is not limited to Fig.16 The types and configurations depicted in the drawings and may include a wide variety of other types and configurations, such as, for example, planar transistors, non-planar transistors, or a combination of the two. Planar transistors may include bipolar junction transistors (BJTs), heterojunction bipolar transistors (HBTs), or high electron mobility transistors (HEMTs). Non-planar transistors may include FinFET transistors, such as dual-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.

[0123] Each transistor 1640 may include a gate 1622 formed by at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include a layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide and / or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium and zinc. Examples of high-k materials that can be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium oxide silicon, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and lead zinc niobate. In some embodiments, when a high-k material is used, an annealing process may be performed on the gate dielectric to improve its quality.

[0124] Depending on whether transistor 1640 is a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor, a gate electrode may be formed on a gate dielectric and may include at least one p-type work function metal or an n-type work function metal. In some embodiments, the gate electrode may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a fill metal layer. For other purposes, additional metal layers, such as barrier layers, may be included. For PMOS transistors, metals that may be used for gate electrodes include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, metals that may be used for gate electrodes include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function adjustment).

[0125] In some embodiments, when viewed as a cross-section of transistor 1640 along the source-channel-drain direction, the gate electrode may be composed of a U-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and does not include a sidewall portion substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on one or more planar non-U-shaped layers.

[0126] In some embodiments, sidewall spacer pairs may be formed on opposite sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, multiple spacer pairs may be used; for example, two, three, or four sidewall spacer pairs may be formed on opposite sides of the gate stack.

[0127] The S / D region 1620 may be formed in the substrate 1602 adjacent to the gate 1622 of each transistor 1640. For example, the S / D region 1620 may be formed using an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the substrate 1602 to form the S / D region 1620. An annealing process to activate the dopants and diffuse them further into the substrate 1602 may be performed after the ion implantation process. In the latter process, the substrate 1602 may first be etched to form a recess at the location of the S / D region 1620. An epitaxial deposition process may then be performed to fill the recess with the material used to fabricate the S / D region 1620. In some embodiments, the S / D region 1620 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with a dopant such as boron, arsenic, or phosphorus. In some embodiments, the S / D region 1620 may be formed using one or more alternative semiconductor materials, such as germanium or a III-V material or alloy. In other embodiments, one or more metal and / or metal alloy layers may be used to form the S / D region 1620 .

[0128] The device layer 1604 may be provided through one or more interconnect layers (in Fig.16 1606-1610) to route electrical signals, such as power and / or input / output (I / O) signals, to and / or from devices (e.g., transistors 1640) of device layer 1604. For example, conductive features (e.g., gates 1622 and S / D contacts 1624) of device layer 1604 can be electrically coupled to interconnect structures 1628 of interconnect layers 1606-1610. One or more interconnect layers 1606-1610 can form a metallization stack (also referred to as an "ILD stack") 1619 of IC device 1600.

[0129] Interconnect structures 1628 may be arranged within interconnect layers 1606-1610 to route electrical signals according to a wide variety of designs (particularly, the arrangements are not limited to Fig.16 ). Fig.16 A particular number of interconnect layers 1606 - 1610 are depicted in FIG. 1 , but embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

[0130] In some embodiments, interconnect structure 1628 may include wires 1628a and / or vias 1628b filled with a conductive material such as metal. Wires 1628a may be arranged to route electrical signals in a planar direction substantially parallel to the surface of substrate 1602 on which device layer 1604 is formed. Fig.16 From the perspective of FIG. 16A , the wires 1628 a can route electrical signals in a direction into and out of the page. The vias 1628 b can be arranged to route electrical signals in a planar direction substantially perpendicular to the surface of the substrate 1602 on which the device layer 1604 is formed. In some embodiments, the vias 1628 b can electrically couple wires 1628 a of different interconnect layers 1606-1610 together.

[0131] The interconnect layers 1606-1610 may include a dielectric material 1626 disposed between interconnect structures 1628, such as Fig.16 In some embodiments, the dielectric material 1626 between the interconnect structures 1628 disposed in different layers of the interconnect layers 1606-1610 may have different compositions; in other embodiments, the composition of the dielectric material 1626 between different interconnect layers 1606-1610 may be the same.

[0132] First interconnect layer 1606 may be formed over device layer 1604. In some embodiments, as shown, first interconnect layer 1606 may include wires 1628a and / or vias 1628b. Wires 1628a of first interconnect layer 1606 may be coupled to contacts of device layer 1604 (e.g., S / D contacts 1624).

[0133] The second interconnect layer 1608 may be formed over the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include a via 1628b to couple a line 1628a of the second interconnect layer 1608 with a line 1628a of the first interconnect layer 1606. Although the lines 1628a and the vias 1628b are structurally depicted using lines within each interconnect layer (e.g., within the second interconnect layer 1608) for clarity, in some embodiments, the lines 1628a and the vias 1628b may be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0134] A third interconnect layer 1610 (and additional interconnect layers, as desired) may be successively formed on the second interconnect layer 1608 according to similar techniques and configurations as described in connection with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, interconnect layers that are "higher" in the metallization stack 1619 in the IC device 1600 (i.e., further away from the device layer 1604) may be thicker.

[0135] IC device 1600 may include solder resist material 1634 (e.g., polyimide or similar material) and one or more conductive contacts 1636 formed on interconnect layers 1606-1610. Fig.16 , the conductive contacts 1636 are illustrated as taking the form of bonding pads. The conductive contacts 1636 can be electrically coupled to the interconnect structure 1628 and configured to route electrical signals of the transistor(s) 1640 to other external devices. For example, solder joints can be formed on one or more conductive contacts 1636 to mechanically and / or electrically couple a chip including the IC device 1600 to another component (e.g., a circuit board). The IC device 1600 can include additional or alternative structures to route electrical signals from the interconnect layers 1606-1610; for example, the conductive contacts 1636 can include other similar features (e.g., pillars) that route electrical signals to external components.

[0136] Fig.17 17 is a side cross-sectional view of an IC device assembly 1700 that may include any of the die 114 and / or microelectronic assemblies 100 disclosed herein. The IC device assembly 1700 includes a plurality of components disposed on a circuit board 1702 (e.g., which may be a motherboard). The IC device assembly 1700 includes components disposed on a first side 1740 of the circuit board 1702 and an opposing second side 1742 of the circuit board 1702; in general, the components may be disposed on one or both of the sides 1740 and 1742. Any of the IC packages discussed below with reference to the IC device assembly 1700 may include any of the embodiments of the microelectronic assembly 100 disclosed herein (e.g., may include a stack of multiple die 114 coupled together).

[0137] In some embodiments, circuit board 1702 may be a printed circuit board including multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 1702 (optionally in combination with other metal layers). In other embodiments, circuit board 1702 may be a non-PCB substrate.

[0138] Fig.17 The IC device assembly 1700 illustrated in FIG. 1 includes a package structure on an interposer 1736 coupled to a first side 1740 of a circuit board 1702 via a coupling component 1716. The coupling component 1716 can electrically and mechanically couple the package structure on the interposer 1736 to the circuit board 1702 and can include solder balls (e.g., Fig.17), male and female portions of a socket, adhesive, bottom fill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0139] The package-on-interposer structure 1736 may include an IC package 1720 coupled to the package interposer 1704 via a coupling component 1718. The coupling component 1718 may take any suitable form for the application, such as those discussed above with reference to the coupling component 1716. Fig.17 1704, but multiple IC packages may be coupled to package interposer 1704; in fact, additional interposers may be coupled to package interposer 1704. Package interposer 1704 may provide an intervening substrate for bridging circuit board 1702 and IC package 1720. IC package 1720 may be or include, for example, a die ( Fig.15 1502), IC devices (e.g. Fig.16 In general, the package interposer 1704 can extend the connection to a wider pitch or reroute the connection to a different connection. For example, the package interposer 1704 can couple the IC package 1720 (e.g., a die) to a BGA conductive contact set of the coupling component 1716 for coupling to the circuit board 1702. Fig.17 , IC package 1720 and circuit board 1702 are attached to opposite sides of package interposer 1704; in other embodiments, IC package 1720 and circuit board 1702 may be attached to the same side of package interposer 1704. In some embodiments, three or more components may be interconnected by way of package interposer 1704.

[0140] In some embodiments, the package interposer 1704 may be formed as a PCB, including multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some embodiments, the package interposer 1704 may be formed of epoxy, glass fiber reinforced epoxy, epoxy with inorganic filler, ceramic material, or polymer material such as polyimide. In some embodiments, the package interposer 1704 may be formed of alternative rigid or flexible materials, which may include the same materials used in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. The package interposer 1704 may include metal lines 1710 and vias 1708, including but not limited to TSV 1706. The package interposer 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices may also be formed on packaging interposer 1704. Package-on-interposer structure 1736 may take the form of any of the package-on-interposer structures known in the art.

[0141] IC device assembly 1700 may include an IC package 1724 coupled to first side 1740 of circuit board 1702 via coupling assembly 1722. Coupling assembly 1722 may take the form of any of the embodiments discussed above with reference to coupling assembly 1716, and IC package 1724 may take the form of any of the embodiments discussed above with reference to IC package 1720.

[0142] Fig.17 1700 includes a package-on-package structure 1734 coupled to a second side 1742 of a circuit board 1702 by a coupling component 1728. The package-on-package structure 1734 may include an IC package 1726 and an IC package 1732 coupled together by a coupling component 1730, such that the IC package 1726 is disposed between the circuit board 1702 and the IC package 1732. The coupling components 1728 and 1730 may take the form of any of the embodiments of the coupling component 1716 discussed above, and the IC packages 1726 and 1732 may take the form of any of the embodiments of the IC package 1720 discussed above. The package-on-package structure 1734 may be configured according to any of the package-on-package structures known in the art.

[0143] Fig.181 is a block diagram of an example electrical device 1800 that may include any of the microelectronic assemblies 100 disclosed herein. For example, any suitable component in the components of the electrical device 1800 may include one or more of the IC device assembly 1700, the IC device 1600, or the die 1502 disclosed herein. Fig.18 1800, but any one or more of these components may be omitted or duplicated as applicable to the application. In some embodiments, some or all of the components included in the electrical device 1800 may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured on a single system-on-chip (SoC) die.

[0144] Additionally, in various embodiments, the electrical device 1800 may not include Fig.18 , but the electrical device 1800 may include interface circuitry for coupling to one or more of the components illustrated in . For example, the electrical device 1800 may not include the display device 1806, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which the display device 1806 may be coupled. In another example set, the electrical device 1800 may not include the audio input device 1824 or the audio output device 1808, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which the audio input device 1824 or the audio output device 1808 may be coupled.

[0145] The electrical device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The electrical device 1800 may include a memory 1804, which itself may include one or more storage devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the memory 1804 may include a memory that shares a die with the processing device 1802. The memory may be used as a cache memory, and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0146] In some embodiments, the electrical device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured to manage wireless communications for transferring data to and from the electrical device 1800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data by using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain any wires.

[0147] The communication chip 1812 can implement any of a plurality of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendments), Long Term Evolution (LTE) projects, and any amendments, updates, and / or revisions (e.g., Advanced LTE projects, Ultra Mobile Broadband (UMB) projects (also known as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are generally referred to as WiMAX networks, which is an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed conformance and interoperability testing of the IEEE 802.16 standard. The communication chip 1812 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1812 can operate according to Enhanced Data GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1812 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and above. In other embodiments, the communication chip 1812 can operate according to other wireless protocols. The electrical device 1800 may include an antenna 1822 to facilitate wireless communications and / or receive other wireless communications (such as AM or FM radio transmissions).

[0148] In some embodiments, the communication chip 1812 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As noted above, the communication chip 1812 can include multiple communication chips. For example, the first communication chip 1812 can be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, and the second communication chip 1812 can be dedicated to long-range wireless communications such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication chip 1812 can be dedicated to wireless communications, and the second communication chip 1812 can be dedicated to wired communications.

[0149] The electrical device 1800 may include a battery / power circuit 1814. The battery / power circuit 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuits for coupling components of the electrical device 1800 to an energy source separate from the electrical device 1800 (e.g., AC line power).

[0150] Electrical device 1800 may include a display device 1806 (or corresponding interface circuitry, as discussed above). Display device 1806 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0151] The electrical device 1800 may include an audio output device 1808 (or corresponding interface circuitry, as discussed above). The audio output device 1808 may include any device that generates an audible indicator, such as a speaker, headphones, or earbuds.

[0152] Electrical device 1800 may include an audio input device 1824 (or corresponding interface circuitry, as discussed above). Audio input device 1824 may include any device that generates a signal representing sound, such as a microphone, microphone array, or digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0153] The electrical device 1800 may include a GPS device 1818 (or corresponding interface circuitry, as discussed above). The GPS device 1818 may communicate with a satellite-based system and may receive the location of the electrical device 1800, as is known in the art.

[0154] Electrical device 1800 may include other output devices 1810 (or corresponding interface circuitry, as discussed above). Examples of other output devices 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0155] The electrical device 1800 may include other input devices 1820 (or corresponding interface circuits, as discussed above). Examples of other input devices 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0156] The electrical device 1800 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cell phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a notebook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop electrical device, a server device or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some embodiments, the electrical device 1800 may be any other electronic device that processes data.

[0157] The following examples pertain to further embodiments. The various features of the different embodiments may be combined in various ways, with some features included and others excluded, to suit a wide variety of different applications.

[0158] Example 1 is a microelectronic assembly comprising a plurality of vertically stacked dies; a trench of a dielectric material extending through the plurality of vertically stacked dies; and a plurality of conductive vias extending through the trench of the dielectric material, wherein individual ones of the plurality of conductive vias are electrically coupled to individual ones of the plurality of vertically stacked dies.

[0159] Example 2 may include the subject matter of Example 1, and may further specify that the trench of dielectric material is within an interior portion of the plurality of vertically stacked dies.

[0160] Example 3 may include the subject matter of Example 1, and may further specify that the trench of dielectric material is along a perimeter of the plurality of vertically stacked dies.

[0161] Example 4 may include the subject matter of any of Examples 1 to 3, and may further specify that the trench of dielectric material is one of a plurality of trenches of dielectric material passing through the plurality of vertically stacked dies.

[0162] Example 5 may include the subject matter of any of Examples 1 to 4, and may further specify that the dielectric material includes silicon dioxide, silicon nitride, oxynitride, a polyimide material, a low-k dielectric, or an ultra-low-k dielectric.

[0163] Example 6 may include the subject matter of any of Examples 1 to 5, and may further specify that the material of the plurality of conductive vias includes one or more of copper, nickel, molybdenum, ruthenium, cobalt, polysilicon, and tungsten.

[0164] Example 7 may include the subject matter of any of Examples 1-6, and may further specify that a cross-sectional dimension of an individual conductive via in the plurality of conductive vias is between 40 nanometers and 5 micrometers.

[0165] Example 8 may include the subject matter of any of Examples 1 to 7, and may further specify that the plurality of vertically stacked dies have a first surface and a second surface opposite the first surface, and the microelectronic assembly further includes a base die at the first surface of the plurality of vertically stacked dies, the base die being electrically coupled to a separate conductive via of the plurality of conductive vias.

[0166] Example 9 may include the subject matter of Example 8, and may further specify that the base die is a controller die having logic elements, and the plurality of vertically stacked dies are memory dies.

[0167] Example 10 may include the subject matter of Example 8, and may further specify that the base die is a first base die, and the microelectronic assembly further includes a second base die at a second surface of the plurality of vertically stacked dies, the second base die being electrically coupled to a separate conductive via of the plurality of conductive vias.

[0168] Example 11 may include the subject matter of Example 8, and may further specify that the base die includes a first surface and an opposing second surface, wherein the plurality of vertically stacked dies are at the second surface of the base die, and the microelectronic assembly further includes a packaging substrate electrically coupled to the first surface of the base die.

[0169] Example 12 may include the subject matter of any of Examples 1-11, and may further specify that the plurality of vertically stacked dies includes between 2 and 32 dies.

[0170] Example 13 may include the subject matter of any of Examples 1 to 11, and may further specify that the plurality of vertically stacked dies includes between 32 and 128 dies.

[0171] Example 14 is a microelectronic assembly comprising a plurality of vertically stacked dies; a first groove in a dielectric material passing through the plurality of vertically stacked dies; a plurality of first conductive vias extending through the first groove in the dielectric material, wherein individual first conductive vias of the plurality of first conductive vias are electrically coupled to individual vertically stacked dies of the plurality of vertically stacked dies; a second groove in the dielectric material passing through the plurality of vertically stacked dies; and a plurality of second conductive vias extending through the second groove in the dielectric material, wherein individual second conductive vias of the plurality of second conductive vias are electrically coupled to individual vertically stacked dies of the plurality of vertically stacked dies.

[0172] Example 15 may include the subject matter of Example 14, and may further specify that the first trench of dielectric material is within an interior portion of the plurality of vertically stacked dies.

[0173] Example 16 may include the subject matter of Example 14, and may further specify that the second trench of dielectric material is along a perimeter of the plurality of vertically stacked dies.

[0174] Example 17 may include the subject matter of any of Examples 14-16, and may further specify that the material of the plurality of first conductive vias and the second conductive vias includes one or more of copper, nickel, molybdenum, ruthenium, cobalt, polysilicon, and tungsten.

[0175] Example 18 is a computing device comprising a circuit board; and an integrated circuit (IC) package electrically coupled to the circuit board, wherein the IC package comprises a packaging substrate; a base die having a first surface and an opposing second surface, the first surface of the base die being electrically coupled to the packaging substrate; a plurality of dies vertically stacked on the second surface of the base die; a groove of a dielectric material extending through the plurality of dies; and a through hole extending through the groove of the dielectric material, wherein the through hole is electrically coupled to the plurality of dies.

[0176] Example 19 may include the subject matter of Example 18, and may further specify that the base die is a controller die having logic elements, and the plurality of vertically stacked dies are memory dies.

[0177] Example 20 may include the subject matter of Example 18 or Example 19, and may further specify that the material of the via includes one or more of copper, nickel, molybdenum, ruthenium, cobalt, polysilicon, and tungsten.

[0178] Example 21 is a method of manufacturing a microelectronic assembly, comprising forming a vertical die stack having a trench through a dielectric material of the vertical die stack; forming a through-hole opening through the trench through the dielectric material; and depositing a conductive material in the through-hole opening to form a through-hole electrically coupled to the vertical die stack.

[0179] Example 22 may include the subject matter of Example 21, and may further specify forming a vertical die stack having a trench of dielectric material on a base wafer.

[0180] Example 23 may include the subject matter of Example 21 or Example 22, and may further specify that forming a vertical chip stack having a groove having a dielectric material includes bonding a first chip to a base chip; forming a first groove through the first chip; depositing a dielectric material in the first groove and on the first chip; bonding a second chip to the dielectric material on the first chip; forming a second groove through the second chip; and depositing a dielectric material in the second groove and on the second chip.

[0181] Example 24 may include the subject matter of Example 23, and may further include singulating the first wafer and the second wafer into dies.

[0182] Example 25 may include the subject matter of Example 21 or Example 22, and may further specify that forming a vertical die stack having a groove having a dielectric material includes forming a first groove through a first wafer; bonding the first wafer to a base wafer; thinning the first wafer to expose the first groove; depositing a dielectric material in the first groove and on the first wafer; forming a second groove through a second wafer; bonding the second wafer to the first wafer; thinning the second wafer to expose the second groove; and depositing a dielectric material in the second groove and on the second wafer.

[0183] Example 26 may include the subject matter of Example 25, and may further include singulating the first wafer and the second wafer into dies.

Claims

1. A microelectronic assembly comprising: multiple vertically stacked dies; a trench through the dielectric material of the plurality of vertically stacked dies; as well as A plurality of conductive vias extend through the trench of the dielectric material, wherein individual ones of the plurality of conductive vias are electrically coupled to individual ones of the plurality of vertically stacked dies.

2. The microelectronic assembly of claim 1, wherein the trenches of dielectric material are within interior portions of the plurality of vertically stacked dies.

3. The microelectronic assembly of claim 1, wherein the trench of dielectric material is along a perimeter of the plurality of vertically stacked die.

4. The microelectronic assembly of claim 1, wherein the trench of dielectric material is one of a plurality of trenches of dielectric material passing through the plurality of vertically stacked dies.

5. The microelectronic assembly of any one of claims 1 to 4, wherein the dielectric material comprises silicon dioxide, silicon nitride, oxynitride, a polyimide material, a low-k dielectric, or an ultra-low-k dielectric.

6. The microelectronic assembly of any one of claims 1 to 4, wherein the material of the plurality of conductive vias comprises one or more of copper, nickel, molybdenum, ruthenium, cobalt, polysilicon, and tungsten.

7. A microelectronic assembly as claimed in any one of claims 1 to 4, wherein individual ones of the plurality of conductive vias have a cross-sectional dimension between 40 nanometers and 5 micrometers.

8. The microelectronic assembly of claims 1 to 4, wherein the plurality of vertically stacked dies have a first surface and a second surface opposite the first surface, and the microelectronic assembly further comprises: A base die at the first surface of the plurality of vertically stacked dies is electrically coupled to a separate conductive via of the plurality of conductive vias.

9. The microelectronic assembly of claim 8, wherein the base die is a controller die having logic elements and the plurality of vertically stacked dies are memory dies.

10. The microelectronic assembly of claim 8, wherein the base die is a first base die, and the microelectronic assembly further comprises: A second base die at the second surface of the plurality of vertically stacked dies, the second base die being electrically coupled to a separate conductive via of the plurality of conductive vias.

11. The microelectronic assembly of claim 8, wherein the base die comprises a first surface and an opposing second surface, wherein the plurality of vertically stacked dies are at the second surface of the base die, and the microelectronic assembly further comprises: A packaging substrate is electrically coupled to the first surface of the base die.

12. The microelectronic assembly of any one of claims 1 to 11, wherein the plurality of vertically stacked dies comprises between 2 and 32 dies.

13. The microelectronic assembly of any one of claims 1 to 11, wherein the plurality of vertically stacked dies comprises between 32 and 128 dies.

14. A microelectronic assembly comprising: multiple vertically stacked dies; a first trench through the dielectric material of the plurality of vertically stacked dies; a plurality of first conductive vias extending through the first trench of the dielectric material, wherein individual first conductive vias of the plurality of first conductive vias are electrically coupled to individual vertically stacked dies of the plurality of vertically stacked dies; a second trench through the dielectric material of the plurality of vertically stacked dies; as well as A plurality of second conductive vias extend through the second trench of the dielectric material, wherein individual second conductive vias of the plurality of second conductive vias are electrically coupled to individual vertically stacked dies of the plurality of vertically stacked dies.

15. The microelectronic assembly of claim 14, wherein the first trench of dielectric material is within an interior portion of the plurality of vertically stacked dies.

16. A microelectronic assembly as claimed in claim 14 or claim 15, wherein the second trench of dielectric material is along a perimeter of the plurality of vertically stacked die.

17. The microelectronic assembly of any one of claims 14 to 16, wherein the material of the plurality of first and second conductive vias comprises one or more of copper, nickel, molybdenum, ruthenium, cobalt, polysilicon, and tungsten.

18. A computing device comprising: Circuit boards; as well as an integrated circuit (IC) package electrically coupled to the circuit board, wherein the IC package comprises: Package substrate; a base die having a first surface and an opposing second surface, the first surface of the base die being electrically coupled to the packaging substrate; a plurality of dies stacked vertically on the second surface of the base die; a trench extending through the dielectric material of the plurality of dies; and A via extends through the trench of the dielectric material, wherein the via is electrically coupled to the plurality of dies.

19. The computing device of claim 18, wherein the base die is a controller die having logic elements and the plurality of vertically stacked dies are memory dies.

20. The computing device of claim 18 or claim 19, wherein the material of the through-hole comprises one or more of copper, nickel, molybdenum, ruthenium, cobalt, polysilicon, and tungsten.

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