Method and apparatus for fast switching of radio frequency switch

Abstract

Methods and apparatus for reducing switching time of a radio frequency (RF) switch including an antenna switch are disclosed. The disclosed teachings include a capacitive element and a resistive element that selectively bypass a circuit during transition of the RF switch from one state to another. Several implementations of the disclosed method and apparatus are also presented.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application No. 17 / 831,761, filed on June 3, 2022, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to radio frequency (RF) switches. The disclosed methods and apparatus may be used to improve switching times of RF switches, including antenna switches. Background Art

[0004] The design of radio frequency front end (RFFE) modules has become more challenging due to increasing complexity and stringent system requirements. As part of the overall performance requirements, the switching time of radio frequency (RF) switches, including antenna switches implemented as part of such modules, is critical. Methods and apparatus for reducing the switching time of such switches are generally desired. Summary of the invention

[0005] The disclosed method and apparatus solve the above-mentioned design challenges by reducing the overall RC time constant that affects the switching time of an RF switch. As described in detail later, this is performed by selectively bypassing specific circuit elements implemented as part of the design of such a switch and when the RF switch transitions from one state to another.

[0006] According to a first aspect of the present disclosure, a radio frequency (RF) switch is provided, comprising: a switch stack, the switch stack comprising a plurality of transistors arranged in a stacked configuration; a plurality of gate resistors, each gate resistor being connected to a gate terminal of a corresponding transistor among the plurality of transistors, the plurality of gate resistors being connected together at a first terminal of the RF switch; a capacitor coupling the first terminal to ground; and a first switch coupled across the capacitor; the first switch being configured to selectively bypass the capacitor during a transition of the switch stack from an on state to an off state or from an off state to an on state.

[0007] According to a second aspect of the present disclosure, a radio frequency (RF) switch is provided, comprising: a switch stack comprising a plurality of transistors arranged in a stacked configuration; a plurality of gate resistors, each gate resistor being connected to a gate terminal of a corresponding transistor among the plurality of transistors, the plurality of gate resistors being connected together at a first terminal of the RF switch; a first capacitor and a second capacitor, each of the first capacitor and the second capacitor being configured to selectively and independently: be turned on to couple the first terminal to ground, or be turned off to decouple the first terminal from the ground; and a series resistor connecting the second terminal of the RF switch to the first terminal, wherein the first capacitor is pre-charged with a positive bias voltage, and the second capacitor is pre-charged with a negative bias voltage.

[0008] According to a third aspect of the present disclosure, a radio frequency (RF) switch is provided, comprising: a switch stack, the switch stack comprising a plurality of transistors arranged in a stacked configuration; a plurality of gate resistors, each gate resistor being connected to a gate terminal of a corresponding transistor among the plurality of transistors, the plurality of gate resistors being connected together at a first terminal of the RF switch; a capacitor having a first capacitor terminal and a second capacitor terminal, the capacitor being a precharged capacitor; and a series resistor connecting the second terminal of the RF switch to the first terminal; wherein: during a transition of the switch stack from an on state to an off state or from an off state to an on state, the capacitor is configured to couple the first terminal to ground, so that selectively: the first capacitor terminal is connected to the first terminal and the second capacitor terminal is connected to ground, or the second capacitor terminal is connected to the first terminal and the first capacitor terminal is connected to ground.

[0009] According to a fourth aspect of the present disclosure, a radio frequency (RF) switch is provided, comprising: a switch stack, the switch stack comprising a plurality of transistors arranged in a stacked configuration; a plurality of gate resistors, each gate resistor being connected to a gate terminal of a corresponding transistor among the plurality of transistors, the plurality of gate resistors being connected together at a first terminal of the RF switch; a capacitor coupling the first terminal to ground; a series resistor connecting a second terminal of the RF switch to the first terminal; and a plurality of gate switches having a ladder configuration, the plurality of gate switches being configured to bypass the plurality of gate resistors during a transition of the switch stack from an on state to an off state or from an off state to an on state, and wherein a drain or source terminal of each gate switch is connected to a gate terminal of a corresponding first transistor among the plurality of transistors, and a source or drain terminal of each gate switch is connected to a gate terminal of a corresponding second transistor among the plurality of transistors, the first transistor and the second transistor being adjacent transistors.

[0010] According to a fifth aspect of the present disclosure, a method for reducing the switching time of a radio frequency (RF) switch is disclosed, the RF switch comprising: a switch stack comprising a plurality of transistors arranged in a stacked configuration; a plurality of gate resistors, each gate resistor being connected to a gate terminal of a corresponding transistor among the plurality of transistors, the plurality of gate resistors being connected together at a first terminal of the RF switch; a capacitor coupling the first terminal to ground; and a series resistor connecting a second terminal of the RF switch to the first terminal, the method comprising: when transitioning from an on state to an off state or from an off state to an on state: in a first step, bypassing the plurality of gate resistors, and in a second step delayed from the first step, bypassing the capacitor.

[0011] Further aspects of the disclosure are provided in the description, drawings and claims of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A radio frequency (RF) switch is shown.

[0013] Figure 2A An exemplary RF switch according to an embodiment of the present disclosure is shown.

[0014] Figure 2B An exemplary timing diagram of various elements in a bypass RF switch according to an embodiment of the present disclosure is shown.

[0015] Figure 3A An exemplary RF switch according to an embodiment of the present disclosure is shown.

[0016] Figure 3B An exemplary timing diagram of various elements in a bypass RF switch according to an embodiment of the present disclosure is shown.

[0017] Figures 4 to 6 An exemplary RF switch according to an embodiment of the present disclosure is shown.

[0018] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0019] Figure 1An RF switch (100) is shown that includes a switch stack (101) including transistors (T1, ..., Tn) having corresponding gate resistors (Rg1, ..., Rgn). The transistor (T1) is referred to as a transistor disposed at the bottom of the switch stack (101), and in the case of a shunt switch, the source terminal of the transistor (T1) can be connected to a reference voltage or to ground. In addition, the transistor (Tn) is referred to as a transistor disposed at the top of the switch stack (101), and the drain terminal of the transistor (Tn) can be coupled to an RF antenna or a terminal for receiving an RF signal.

[0020] continue Figure 1 The RF switch (100) further includes a switch driver (L) that operates with a positive voltage (Vdd) and a negative voltage (Vss) to provide a positive bias voltage and a negative bias voltage (e.g., +Vbias, -Vbias) at a first terminal (N) of the circuit. The voltages (+Vbias, -Vbias) are used by the switch stack (101) to place the switch in an on or off state, or vice versa. A series resistor (R1) connects the second terminal of the RF switch to the first terminal (N). The resistor (R1) and the capacitor (C1) form an RC filter at the output of the switch driver (L) to reduce the voltage swing at the switch driver (L) caused by the RF power and improve linearity. A control signal for controlling the state of the switch stack (101) is applied to the input terminal (IN) of the switch driver (L). As is known in the art, under operating conditions, the combination of the individual gate resistors (Rg1, ..., Rgn), the common gate resistor (R1), the capacitor (C1) and the inherent capacitance of the transistors (T1, ..., Tn) determines the overall RC time constant of the circuit and, therefore, the switching time of the switch stack (101) when transitioning from one state to another (on to off or off to on). As an example, the combination of the gate resistor (Rgi) and the inherent capacitance of the corresponding transistor (Ti) will determine the switching time of the transistor (Ti) during the transition of the RF switch stack (101) from the on state to the off state or from the off state to the on state.

[0021] In the following, a method and apparatus for reducing the overall RC time constant and thus improving the switching time of an RF switch will be disclosed. Figure 1 The present invention is performed with an exemplary RF switch (100) of the present invention, but the described methods and apparatus are also applicable to switches with different topologies.

[0022] Figure 2A An exemplary RF switch (200A) according to an embodiment of the present disclosure is shown. Figure 1Unlike the RF switch (100) of FIG. 2, the RF switch (200A) further includes a gate switch (Mg1, ..., Mgn) arranged / coupled across corresponding gate resistors (Rg1, ..., Rgn) and a switch (M1) coupled across a capacitor (C1), wherein the capacitor (C1) couples a terminal (N) of the switch (220A) to ground. When the switch stack (101) changes from one state to another state (on to off or off to on), the gate switch (Mg1, ..., Mgn) is used to bypass / short-circuit the corresponding resistor (Rg1, ..., Rgn). Therefore, the inherent charge of the switch stack (101) is discharged. Similarly, when such a transition occurs, the switch (M1) is used to selectively short-circuit the capacitor (C1). In other words, by selectively (and in a short time) bypassing / shorting the R element and / or C element of the circuit, the overall RC time constant of the circuit can be reduced to improve the switching time of the switch stack (101). As also shown, switches (Mg1, ..., Mgn) are controlled by control pulses (Ctrl1), and switch (M1) is controlled by control pulses (Ctrl2).

[0023] According to the teachings of this disclosure, Figure 2A The control switches (M1, Mg1, ..., Mgn) for disconnecting / shorting the various resistor elements and capacitor elements of the switch (200A) during the transition can be implemented according to a specific timing. Figure 2B It is shown in Figure 2B An exemplary timing diagram of the present disclosure is shown. Figure 2A In the control signal (210) at the input terminal (Ctrl_IN), the rising edge (which may be a falling edge in different embodiments) occurring at time (T02) indicates that Figure 2A The switch stack (101) is switched from the on state to the off state or from the off state to the on state. FIG. 2A to FIG. 2B According to an embodiment of the present disclosure, briefly following such a rising edge, at time (T12), a control pulse (Ctrl1) is applied to the gate terminal of the switch (Mg1, ..., Mgn) to bypass / short the corresponding gate resistor (Rg1, ..., Rgn). Figure 2B After the delay / interval time (D2) shown, at time (T22), a pulse control (Ctrl2) is applied to the gate terminal of the switch (M1) to bypass the capacitor (C1). Therefore, the gate resistor (Rg1, ..., Rgn) and the capacitor (C1) are bypassed for a duration equal to the pulse width (W2, W2') of the control pulse (Ctrl1, Ctrl2), respectively. In an embodiment, the pulse widths (W2, W2') may be equal.

[0024] The overall improvement in the switching time of the switch stack depends on the pulse width (W2, W2') and the interval time (D2) between the control pulses (Ctrl1, Ctrl2). Design selection and optimization for the control pulse width (W2, W2') and the interval time (D2) can be based on the application and may involve an appropriate trade-off between the required space and the overall performance requirements (e.g., insertion loss, linearity, etc.). In other words, as an example, the size of the transistors (T1, ..., Tn) will affect how to select the control pulse width (W2, W2') and the interval time (D2) to optimize the improvement in the switching time of the switch stack. In an exemplary embodiment, the pulse width (W2, W2') can be 100 nanoseconds. Also as Figure 2B As shown in the exemplary timing diagram of FIG. 3 , at time (T32), the switching of the switch stack is completed and the switch reaches a stable on or off state. Signal (211) represents the timing of the RF output (off switching to on). Such a signal shows how the RF output gradually changes from one level (e.g., corresponding to the off state) to another level (e.g., corresponding to the on state). Figure 2B The exemplary timing shown in corresponds to the case where bypassing occurs during the transition (after T02) and ends before the transition is complete (before T32). In some embodiments, bypassing of some elements may continue until the switch stack transition is complete, i.e., closer to T32 than shown in the figure. Figure 2B As shown, generally, D2+W2'<T32.

[0025] Figure 3A An exemplary RF switch (300A) according to another embodiment of the present disclosure is shown. The operating principle of such a switch is similar to that of the embodiment of the present disclosure, except that the RF switch (300A) also implements a switch (M1) coupled across a capacitor (C1) and a switch (M2) coupled across a common gate resistor (R1). Figure 1 The operating principle of the RF switch (100) described is similar. The function of the switches (M1, M2) is to bypass the capacitor (C1) and the common gate resistor (R1) respectively during the transition of the switch stack (101) from one state to another. This will reduce the overall RC time constant of the circuit during the transition, thereby resulting in an improvement in the switching time of the switch stack (101). Figure 3A As shown, switches (M1, M2) are controlled by control signals (Ctrl2, Ctrl3), respectively.

[0026] Figure 3B An exemplary timing diagram (300B) showing the timing of the control signals (Ctrl2, Ctrl3) is shown. Figure 3AIn the control signal (310) at the input terminal (Ctrl_IN), the rising edge (which may be a falling edge in different embodiments) occurring at time (T03) indicates that Figure 3A The switch stack (101) is switched from the on state to the off state or from the off state to the on state. FIG. 3A to FIG. 3B According to an embodiment of the present disclosure, briefly following such a rising edge, at time (T13), a control pulse (Ctrl2) is applied to the gate terminal of the switch (M1) to bypass / short the capacitor (C1). Figure 3B After the interval time (D3) shown, at time (T23), a pulse control (Ctrl3) is applied to the gate terminal of the switch (M2) to bypass the common gate resistor (R1). Therefore, the common gate resistor (R1) and the capacitor (C1) are bypassed for a duration equal to the pulse width (W3, W3') of the control pulse (Ctrl2, Ctrl3), respectively. In an embodiment, the pulse widths (W3, W3') may be equal. As previously described with respect to Figure 2A As mentioned in the embodiment of , also in this case, the overall improvement of the switching time of the switch stack depends on the pulse width (W3, W3') and the interval time (D3) between the control pulses (Ctrl2, Ctrl3). The design choice for the control pulse width (W3, W3') and the interval time (D3) can be made according to the application and may involve an appropriate trade-off between space and overall performance requirements (e.g., insertion loss, linearity, etc.). Figure 3B As shown in the exemplary timing diagram of FIG. 3 , at time (T33), the switching of the switch stack is completed and the switch reaches a stable on or off state. Signal (311) represents the timing of the RF output (off switching to on). Such a signal shows how the RF output gradually changes from one level (e.g., corresponding to the off state) to another level (e.g., corresponding to the on state). Figure 3B The exemplary timing shown in corresponds to the case where bypassing occurs during the transition (after T03) and ends before the transition is complete (before T32). In some embodiments, bypassing of some elements may continue until the switch stack transition is complete, i.e., closer to T33 than shown in the figure. Figure 3B As shown, generally, D3+W3'<T33.

[0027] Return to reference Figure 1, when the switch stack (101) is in the on state, the terminal (N) is at a positive voltage +Vbias (e.g., 3.5V), and when the switch is in the off state, the terminal (N) is at a negative voltage -Vbias. In other words, as an example, when the switch stack transitions from the on state to the off state, the capacitor (C1) must be discharged from a positive charge and then recharged to a negative charge, so that the bias voltage at the terminal (N) changes from a positive voltage +Vbias to a negative voltage -Vbias. This change in polarity takes time, resulting in a negative impact on the switching time. The disclosed method and apparatus solve this problem by implementing a pre-charged capacitor, as described in more detail below by the next exemplary embodiment.

[0028] Figure 4 An exemplary RF switch (400) according to yet another embodiment of the present disclosure is shown. Figure 1 The RF switch (100) described above, during the operating condition, when the switch stack (101) is in the on state, the terminal (N) is at a positive bias voltage (+Vbias), and when the switch stack (101) is in the off state, the terminal (N) is at a negative bias voltage (-Vbias). In addition to the RF switch (400) further comprising capacitors (C1, C2) that can be selectively connected to / disconnected from the terminal (N) by switches (M3, M4), the RF switch (400) and Figure 1 The RF switch (100) is similar. The capacitors (C1, C2) are pre-charged so that the voltages across the capacitors (C1, C2) are (+Vbias, -Vbias), respectively. When the switch stack (101) is in the on state, the capacitor (C1) is turned on and the capacitor (C2) is turned off, and therefore the terminal (N) is at a positive voltage +Vbias. When transitioning from the on state to the off state, the capacitor (C1) is turned off and the capacitor (C2) is turned on, and therefore the terminal (N) will now be at a negative bias voltage (-Vbias). The connection and disconnection of the capacitors (C1, C2) are performed by switches (M3, M4), respectively. Also as Figure 4 As shown, switches (M3, M4) are controlled by control signals (Ctrl4, Ctrl5). According to the teachings of the present disclosure, during the transition of the switch stack, care must be taken to avoid any overlap when switching capacitors (C1, C2) on and off. In other words, one capacitor should be completely disconnected before switching on other capacitors. In an embodiment, switches (M3, M4) are implemented using field effect transistor (FET) switches.

[0029] Figure 5 An exemplary RF switch (500) according to another embodiment of the present disclosure is shown. In this switch, instead of Figure 4In the embodiment of the present invention, two pre-charged capacitors are implemented, and a single pre-charged capacitor (C3) is implemented. The capacitor (C3) is pre-charged to a charge that causes the voltage across the capacitor (C3) to be Vbias. The RF switch (500) also includes switches (M5, M6, M7, M8). The function of such a switch is to connect the capacitor (C3) across the terminal (N) and the ground so that the terminal (N) receives the appropriate bias voltage (i.e., +Vbias or -Vbias) when the switch stack (101) is in the on or off state. To further illustrate this point, consider the following example: the capacitor (C3) is pre-charged so that there is a positive voltage (+Vbias) from the terminal (N2) of such a capacitor to the terminal (N1). Under operating conditions, when the switch stack (101) is in the on state, the switches (M5, M8) are turned on (closed), while the switches (M6, M7) are turned off (open), and therefore the terminal (N) will be at a positive bias voltage (+Vbias). On the other hand, when the switch stack (101) is in the off state, switches (M5, M8) are off (open), while switches (M6, M7) are on (closed), and therefore the terminal (N) is at a negative bias voltage (-Vbias). Figure 4 Compared to the embodiment of the present invention, the RF switch (500) requires less die space because one capacitor is implemented (rather than two) and the size of the additional switch is smaller than the size of the additional capacitor. Figure 5 As shown, the switches (M5, M6, M7, M8) are controlled by control signals (Ctrl6, Ctrl7, Ctrl8, Ctrl9), respectively. In an embodiment, each of the switches (M5, M6, M7, M8) can be implemented using a FET.

[0030] Figure 6An exemplary RF switch (600) according to an embodiment of the present disclosure is shown. In the RF switch, the gate switches (S1, ..., Sn-1) are implemented in a ladder configuration to bypass the gate resistor and short / connect the gate terminals of the transistors (T1, ..., Tn) during the transition of the control signal of the main switch. Each of the gate switches (S1, ..., Sn-1) has a drain / source terminal connected to the gate terminal of the corresponding transistor (Ti) of the transistor (T1, ..., Tn) and a source / drain terminal connected to the gate terminal of the adjacent transistor (Ti+1 or Ti-1) of the transistor (T1, ..., Tn). This causes the switch stack (101) to discharge from the inherent charge. In order to further improve the switching time of the switch stack (101), the switch (Sg1) can also be optionally implemented across the resistor (Rg1) to bypass such a resistor during the transition of the switch stack (101) from one state to another. In embodiments implementing the switch (Sg1), the bypass resistor (Rg1) may be implemented after shorting the gate terminals of the switch stack together. Figure 6 As shown, switches (S1, ..., Sn-1) are controlled by a control signal (Ctrl11), and switch (Sg1) is controlled by a control signal (Ctrl10).

[0031] Return to reference Figure 2A , each of the switches (Mg1, ..., Mgn) is designed to handle the full voltage swing across the corresponding gate resistor. In other words, in order to better handle the voltage, each of such switches can be implemented as a stack of several transistors, which will however increase the occupied space on the die. Figure 6 The RF switch (600) may be a preferred alternative in applications that impose more stringent die area requirements. For bypass purposes, as opposed to a set of "n" bypass stacked transistors (one for each individual gate resistor), the RF switch (600) implements a first "track" stack of switches (S1, ..., Sn-1) and optionally an additional "ladder" switch stack (Sg1) implemented across a gate resistor (Rg1). Figure 2A This will save some die space compared to the implementation scheme of FIG.

[0032] Continue to refer to Figure 6, according to embodiments of the present disclosure, the switch (Sg1) may be implemented across any of the gate resistors (Rg1, ..., Rgn). In applications where the switch stack (101) is used in a shunt configuration where the bottom of the switch is at a reference voltage (as opposed to a series configuration where both the top and bottom of the switch handle different RF signals), the preferred solution is to implement the switch (Sg1) across the gate resistor (i.e., Rg1) at the bottom of the switch stack. The reason is that when in the shunt configuration, the voltage swing to be handled by the switch (Sg1) coupled across the resistor (Rg1) at the bottom of the stack is smaller. This means that the switch (Sg1) can be implemented as a stack with a smaller number of transistors or transistors of smaller size. This provides the benefit of saving some die area.

[0033] According to the teachings of the present disclosure, the disclosed bypass scheme of each embodiment can be combined with another embodiment using a different bypass scheme and further adopted. This will be further illustrated below by several examples and not by way of limitation:

[0034] ·Reference Figure 2A , the presence of switch (M1) or switches (Mg1, ..., Mgn) is optional. In an embodiment, only switch (M1) may be implemented. Different embodiments may implement only switches (Mg1, ..., Mgn) and omit switch (M1). The choice between these options may be driven by the desired overall circuit performance, cost, and die area.

[0035] · Figure 2A and Figure 3A The embodiments can be combined so that the switch (Mg1, ...,

[0036] Mgn) and switches (M1, M2) are all implemented in the same circuit.

[0037] Similarly, it is also conceivable Figure 3A and Figure 6 A combination of implementation methods.

[0038] · Figure 2A The switches (Mg1, ..., Mgn) can be added to Figure 4 or Figure 5 implementation method to further improve the switching time.

[0039] • The inventors have demonstrated through simulations that, depending on the application, improvements of up to 70% in switching time can be achieved in some embodiments.

[0040] As used in the present disclosure, the term "MOSFET" includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and includes insulated gates having metal or metalloid, insulator and / or semiconductor structures. The terms "metal" or "metalloid" include at least one conductive material (e.g., aluminum, copper or other metal or highly doped polysilicon, graphene or other electrical conductors), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric material), and "semiconductor" includes at least one semiconductor material.

[0041] As used in this disclosure, the term "radio frequency" (RF) refers to an oscillation rate in the range of about 3 kHz to about 300 GHz. The term also includes frequencies used in wireless communication systems. RF frequencies can be the frequency of electromagnetic waves or the frequency of an alternating voltage or current in an electrical circuit.

[0042] With respect to the drawings cited in this disclosure, the dimensions of the various elements are not to scale; some dimensions may be significantly exaggerated vertically and / or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., "top," "bottom," "above," "below," "lateral," "vertical," "horizontal," etc.) are relative to the example drawings and are not necessarily absolute orientations or directions.

[0043] Various embodiments of the present invention can be implemented to meet various specifications. Unless otherwise specified above, selecting appropriate component values ​​is a matter of design choice. Various embodiments of the present invention can be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structure) or in hybrid or discrete circuit form. Integrated circuit implementation can be manufactured using any suitable substrate and process (including but not limited to standard bulk silicon, high resistivity bulk CMOS, silicon on insulator (SOI) and silicon on sapphire (SOS)). Unless otherwise specified above, embodiments of the present invention can be implemented in other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT and MESFET technology. However, embodiments of the present invention are particularly useful when using SOI or SOS-based process manufacturing or when using process manufacturing with similar characteristics. The manufacture of SOI or SOS process in CMOS enables the circuit to have low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity and high frequency operation (i.e., up to and exceeding 300GHz radio frequency). Monolithic IC implementations are particularly useful because, through careful design, parasitic capacitances can generally be kept low (or at least consistent across all units, allowing them to be compensated for).

[0044] Voltage levels may be adjusted and / or voltage and / or logic signal polarity may be inverted depending on the particular specification and / or implementation technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adjusted as needed, for example, by adjusting device size, "stacking" components (particularly FETs) in series to withstand higher voltages, and / or using multiple components in parallel to handle higher currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or to provide additional functionality without significantly changing the functionality of the disclosed circuits.

[0045] Circuits and devices according to the present invention can be used alone or in combination with other components, circuits and devices. Embodiments of the present invention can be manufactured as integrated circuits (ICs), which can be packaged in IC packages and / or modules for ease of processing, manufacturing and / or improved performance. In particular, IC embodiments of the present invention are often used in modules, wherein one or more such ICs are combined with other circuit blocks (e.g., filters, amplifiers, passive components and possible additional ICs) into a package. Then, the IC and / or module are usually combined with other components (usually on a printed circuit board) to form a part of a final product such as a cellular phone, a laptop computer or an electronic tablet, or to form a higher-level module that can be used in various products such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and components, such ICs usually implement certain communication modes, usually wireless communications.

[0046] A number of embodiments of the present invention have been described. It should be understood that various modifications may be made without departing from the spirit and scope of the present invention. For example, some of the steps described above may be order-independent and therefore may be performed in an order different from that described. In addition, some of the steps described above may be optional. The various activities described with respect to the methods identified above may be performed in a repetitive, serial and / or parallel manner.

[0047] It should be understood that the foregoing description is intended to illustrate but not to limit the scope of the invention, which is limited by the scope of the appended claims, and other embodiments are within the scope of the claims. Specifically, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that bracketed markings for claim elements are for ease of reference to such elements and do not themselves indicate a specific required order or enumeration of elements; furthermore, such markings may be reused in dependent claims as references to additional elements without being considered to begin a conflicting marking sequence).

Claims

1. A radio frequency (RF) switch, comprising: a switch stack comprising a plurality of transistors arranged in a stack configuration; a plurality of gate resistors, each gate resistor connected to a gate terminal of a respective transistor of the plurality of transistors, the plurality of gate resistors connected together at a first terminal of the RF switch; a capacitor coupling the first terminal to ground; as well as A first switch is coupled across the capacitor; the first switch is configured to selectively bypass the capacitor during a transition of the switch stack from an on state to an off state or from an off state to an on state.

2. The RF switch of claim 1, further comprising a plurality of gate switches, each gate switch: coupled across corresponding gate resistors of the plurality of gate resistors, and The switch stack is configured to bypass the corresponding gate resistor during a transition of the switch stack from an on state to an off state or from an off state to an on state.

3. The RF switch according to claim 2, wherein: During a transition of the switch stack from an on state to an off state or from an off state to an on state, the RF switch is configured to: In a first step, the plurality of gate switches are closed and the plurality of gate resistors are bypassed, and In a second step delayed by a first delay from the first step, the first switch is closed and the capacitor is bypassed.

4. The RF switch according to claim 1, further comprising: a series resistor connecting the second terminal of the RF switch to the first terminal; and a second switch coupled across the series resistor, the second switch configured to bypass the series resistor during a transition of the switch stack from an on state to an off state or from an off state to an on state.

5. The RF switch according to claim 4, wherein: During a transition of the switch stack from an on state to an off state or from an off state to an on state, the RF switch is configured to: In a first step, the first switch is closed and the capacitor is bypassed, and In a second step delayed by a first delay from the first step, the second switch is closed and the series resistor is bypassed.

6. The RF switch of claim 3, wherein: controlling the plurality of gate switches using a first control pulse applied at gate terminals of the plurality of gate switches; controlling the first switch using a second control pulse applied at a gate terminal of the first switch; and The widths of the first and second control pulses and the first delay are selected based on a switching time of the switch stack.

7. The RF switch of claim 5, wherein: controlling the first switch using a first control pulse applied at a gate terminal of the first switch; controlling the second switch using a second control pulse applied at a gate terminal of the second switch; and The widths of the first and second control pulses and the first delay are selected based on a switching time of the switch stack.

8. A radio frequency (RF) switch comprising: a switch stack comprising a plurality of transistors arranged in a stack configuration; a plurality of gate resistors, each gate resistor connected to a gate terminal of a respective transistor of the plurality of transistors, the plurality of gate resistors connected together at a first terminal of the RF switch; a first capacitor and a second capacitor, each of the first capacitor and the second capacitor being configured to selectively and independently: is turned on to couple the first terminal to ground, or disconnecting to decouple the first terminal from ground; as well as a series resistor connecting the second terminal of the RF switch to the first terminal, Wherein, the first capacitor is pre-charged with a positive bias voltage, and the second capacitor is pre-charged with a negative bias voltage.

9. The RF switch of claim 8, wherein: During the transition of the switch stack from the on state to the off state: the first capacitor is disconnected and the second capacitor is connected, and During a transition of the switch stack from an off state to an on state: the second capacitor is disconnected and the first capacitor is connected.

10. The RF switch of claim 9, further comprising: A first switch, the first switch is arranged in series with the first capacitor, and the first switch is configured to receive a first control pulse to switch on or off the first capacitor; as well as A second switch is provided in series with the second capacitor, and the second switch is configured to receive a second control pulse to switch on or off the second capacitor.

11. A radio frequency (RF) switch, comprising: a switch stack comprising a plurality of transistors arranged in a stack configuration; a plurality of gate resistors, each gate resistor connected to a gate terminal of a respective transistor of the plurality of transistors, the plurality of gate resistors connected together at a first terminal of the RF switch; a capacitor having a first capacitor terminal and a second capacitor terminal, the capacitor being a pre-charged capacitor; as well as a series resistor connecting the second terminal of the RF switch to the first terminal; in: During a transition of the switch stack from an on state to an off state or from an off state to an on state, the capacitor is configured to couple the first terminal to ground so that selectively: the first capacitor terminal is connected to the first terminal and the second capacitor terminal is connected to ground, or The second capacitor terminal is connected to the first terminal and the first capacitor terminal is connected to ground.

12. The RF switch of claim 11, further comprising: a first switch connecting the first terminal to the first capacitor terminal; a second switch connecting the first capacitor terminal to ground; a third switch connecting the first terminal to the second capacitor terminal; A fourth switch connects the second capacitor terminal to ground.

13. The RF switch of claim 12, wherein: During a transition of the switch stack from an on state to an off state, the first switch and the third switch are opened, and the second switch and the fourth switch are closed, and During a transition of the switch stack from an off state to an on state, the first switch and the third switch are closed, and the second switch and the fourth switch are open.

14. A radio frequency (RF) switch comprising: a switch stack comprising a plurality of transistors arranged in a stack configuration; a plurality of gate resistors, each gate resistor connected to a gate terminal of a respective transistor of the plurality of transistors, the plurality of gate resistors connected together at a first terminal of the RF switch; a capacitor coupling the first terminal to ground; a series resistor connecting the second terminal of the RF switch to the first terminal; as well as a plurality of gate switches having a ladder configuration, the plurality of gate switches being configured to bypass the plurality of gate resistors during a transition of the switch stack from an on state to an off state or from an off state to an on state, and Wherein, the drain or source terminal of each gate switch is connected to the gate terminal of a corresponding first transistor among the multiple transistors, and the source or drain terminal of each gate switch is connected to the gate terminal of a corresponding second transistor among the multiple transistors, and the first transistor and the second transistor are adjacent transistors.

15. The RF switch according to claim 14 further includes a resistor switch, which is coupled across the gate resistors of the multiple gate resistors; the resistor switch is configured to selectively bypass the gate resistor during the transition of the switch stack from on to off or from off to on.

16. The RF switch according to claim 15, wherein: During a transition of the switch stack from on to off or from off to on, the RF switch is configured to: In a first step, the plurality of gate switches are closed and the plurality of gate resistors are bypassed, and In a second step, optionally delayed by a first delay from the first step, the resistor switch is closed and the gate resistor coupled across the resistor switch is also bypassed.

17. The RF switch of claim 16, wherein: controlling the plurality of gate switches using a first control pulse applied at gate terminals of the plurality of gate switches; controlling the resistor switch using a second control pulse applied at a gate terminal of the resistor switch; and The widths of the first and second control pulses and the first delay are selected based on a switching time of the switch stack.

18. The RF switch of claim 15, wherein: The gate resistor across the resistor switch is connected to a gate terminal of a transistor disposed at a bottom of the switch stack.

19. The RF switch of claim 1 , further comprising a switch driver connected to the series resistor, the switch driver being configured to: providing a positive bias voltage at the first terminal when the switch stack is in an on-state, and When the switch stack is in an off state, a negative bias voltage is provided at the first terminal.

20. The RF switch of claim 2, wherein: The plurality of gate switches include field effect transistors (FETs).

21. The RF switch of claim 1, wherein: The first switch is a FET switch.

22. A method of reducing a switching time of a radio frequency (RF) switch, the RF switch comprising: a switch stack comprising a plurality of transistors arranged in a stack configuration; a plurality of gate resistors, each gate resistor connected to a gate terminal of a respective transistor of the plurality of transistors, the plurality of gate resistors connected together at a first terminal of the RF switch; a capacitor coupling the first terminal to ground; as well as a series resistor connecting the second terminal of the RF switch to the first terminal, The method comprises: When changing from the on state to the off state or from the off state to the on state: In a first step, the plurality of gate resistors are bypassed, and In a second step delayed from the first step, the capacitor is bypassed.

23. The method according to claim 22, wherein: Bypassing the gate resistor is performed using a plurality of gate switches, and wherein each gate switch is coupled across a gate resistor of the plurality of gate resistors.

24. The method of claim 22, further comprising, in the second step, bypassing the series resistor.

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