CXL control system based on fpga pcie controller and application

Abstract

The invention discloses a CXL control system based on an fpga pcie controller and application, and relates to the technical field of control systems. The PCIe PHY module comprises a PCIe PHY module, a cxl arb mux layer, a cxl io ctrl layer, a cxl mem / cache layer, a DDR controller module, an SRAM (Static Random Access Memory) module and a clkrstngen module. According to the method, the conflict between logic resources and a time sequence is effectively solved, and on the basis of realizing high bandwidth, the CXL access delay is effectively reduced by optimizing the CXL function and the time sequence, so that various CXL application scenes are effectively realized; the programmable characteristic of the FPGA is fully utilized, Flex Bus logic resources are optimized, and the utilization rate of the logic resources is reduced, so that the fpga time sequence requirement is met, DDR expansion and SRAM expansion are achieved, and the speed and function requirements of different application scenes are met.

Description

Technical Field

[0001] The invention belongs to the technical field of control systems, and in particular relates to a CXL control system and application based on an FPGA PCIE controller. Background Art

[0002] CXL technology is a new type of high-speed interconnect technology designed to provide higher data throughput and lower latency to meet the needs of modern computing and storage systems. It was originally jointly launched by Intel, AMD and other companies, and has received a lot of support from companies including Google and Microsoft. The purpose of CXL is to solve the memory gap between CPU and device, and between devices. Since servers have huge memory pools and a large number of PCIe-based computing accelerators, each with a large amount of memory, memory segmentation has caused huge waste, inconvenience and performance degradation, so CXL was born to solve this problem.

[0003] The application scenarios of CXL technology are very wide, including data centers, artificial intelligence, and processor interconnection. In the field of data centers, CXL technology can interconnect different computing and storage resources to improve system performance and efficiency. In the field of artificial intelligence, CXL technology can enable accelerators such as GPUs and FPGAs to better collaborate with the main processor and improve the speed of AI model training and reasoning. In terms of processor interconnection, CXL technology can achieve interconnection between processors from different manufacturers and improve the overall performance and flexibility of the system. CXL is a high-speed serial protocol that allows fast and reliable data transmission between different components within a computer system. CXL was launched in 2020 and was jointly designed by Intel, Dell, and HP to solve bottleneck problems in high-performance computing, including memory capacity, memory bandwidth, and I / O latency. CXL can also achieve memory expansion and memory sharing, and can communicate with peripherals such as computing accelerators (such as GPUs and FPGAs) to provide faster and more flexible data exchange and processing methods. CXL technology not only provides high-speed transmission, but also supports memory sharing and virtualization, making collaboration between devices closer and more efficient. This technology helps meet the needs of modern data centers for large-scale processing and analysis, while also providing better support for emerging applications such as AI, machine learning, and blockchain.

[0004] The CXL protocol contains three sub-protocols: CXL.io, CXL.cache, and CXL.memory. Among them, the CXL.io mode can extend the memory to external devices, making data transmission faster. CXL.io connects the CPU and external devices through the PCIe bus, so that the CPU can share memory with external devices and directly access the I / O resources of external devices. The CXL.cache mode can improve performance by caching memory in external devices. The CXL.cache mode allows the CPU to keep the most frequently used data in the local cache and save the less frequently used data in the external device, which can reduce memory access time and improve overall system performance. The CXL.memory mode can use external devices as main memory to achieve larger memory capacity. The CXL.memory mode allows the CPU to treat external devices as extended memory, so that more data can be stored. This method can improve system reliability because even if a memory failure occurs, the CPU can still continue to run through the external device.

[0005] CXL technology has the following advantages: (1) Open source protocol: data sharing among multiple devices is achieved through memory pooling; (2) Lower latency: CXL technology can directly connect computing devices such as CPU, GPU, FPGA to memory, avoiding the latency caused by traditional I / O bus, thereby achieving lower latency and improving computing efficiency; (3) Higher energy efficiency: CXL technology supports memory sharing among multiple computing devices, reducing memory redundancy and improving energy efficiency; in addition, CXL technology also supports memory virtualization, which can dynamically allocate memory resources according to application load, further improving system energy efficiency; (4) Stronger scalability: CXL technology can support memory expansion, allowing more memory capacity to be added without shutting down, thereby increasing the scalability of the system and preparing for future application needs; (5) Wider application scenarios: CXL technology is not only suitable for high-performance computing fields such as data centers, but can also be applied to multiple fields such as artificial intelligence, blockchain, and the Internet of Things; In summary, CXL technology can support high-bandwidth, low-latency data transmission, has better flexibility and scalability, and can achieve mixed use of different types of hardware devices.

[0006] In addition, both CXL and CCIX are high-speed interconnection standards for connecting different chips, but there are differences in some aspects. The following is the main comparison between CXL and CCIX; CCIX is a data transmission protocol based on the PCIe data link layer, which retains the high bandwidth of PCIe. Due to the large number of protocol layers, the latency is higher than CXL, which is not convenient for memory expansion application scenarios.

[0007] The existing technology has the following disadvantages: (1) Closedness: NVlink has high bandwidth and low latency characteristics, and can only be used for data sharing between NVIDIA GPUs, and cannot share data with CPUs and other accelerators; (2) Memory wall: Data communication between CPUs, GPUs and various accelerators requires multiple data transfers; (3) High latency, unable to provide a low-latency memory expansion solution. Therefore, this technical solution proposes a CXL control system and application based on an fpga pcie controller to solve the problems of high bandwidth and low latency, Gen3 / Gen4 compatibility and FPGA resource optimization. Summary of the invention

[0008] The present invention provides a CXL control system and application based on an FPGA PCIe controller. The control system effectively combines universal IPs such as FPGA PCIe PHY and PCIe controller, proposes an effective CXL solution, reduces development cost and cycle; effectively solves the conflict between logic resources and timing through universal IPs such as FPGA PCIe PHY and PCIe controller; effectively reduces CXL access delay by optimizing CXL function and timing on the basis of achieving high bandwidth through universal IPs such as FPGA PCIe PHY and PCIe controller; effectively realizes various CXL application scenarios through universal IPs such as FPGA PCIe PHY, PCIe controller, DDR controller and DDR PHY; makes full use of the programmable characteristics of FPGA to optimize Flex Bus logic resources; makes full use of the configurable characteristics of the host's Flex Bus lane number to reduce logic resource utilization by generating different FPGA configuration files to meet the FPGA timing requirements; optimizes the functional path to meet the timing requirements of different FPGA devices; makes full use of FPGA mature IP to realize DDR expansion and SRAM expansion, such as DDR controller, DDR PHY and RAM controllers realize DDR expansion and SRAM expansion, which can be applied to different expansion requirements of servers, AI processors or other accelerators. They are compatible with different PCIe controllers and PCIe PHY implementations in FPGA to meet the speed and functional requirements of different application scenarios. By being compatible with Gen3 / Gen4 and other rates, they can effectively reduce development and product costs. In summary, the problems in the background technology are solved.

[0009] To solve the above technical problems, the present invention is achieved through the following technical solutions:

[0010] The CXL control system based on the fpga pcie controller of the present invention comprises a PCIePHY module, a cxl arb mux layer, a cxl io ctrl layer, a cxl mem / cache layer, a DDR controller module, an SRAM module and a clk_rstn_gen module;

[0011] The PCIePHY module is used to complete the protocol functions of the Flex Bus Physical Layer in the CXL controller architecture, and adopts the mature FPGA PHY solution to enhance the compatibility of this solution at different rates;

[0012] The cxl arb mux layer includes a pipe_ctrl module, an ARB MUX module and a vlsm module, which are used to complete the CXL ARB MUX protocol function in the CXL controller architecture; wherein the pipe_ctrl module transmits data and control signals with the PCIe PHY through the PIPE interface; the ARB MUX module divides the pipe_ctrl data into three categories of io, mem / cache and vlsm according to the CXL protocol; the vlsm module is used to implement CXL device enumeration;

[0013] The cxl io ctrl layer includes an lpif_ctrl module and an fpga pcie controller module, which are used to complete the PCIe / CXL.io Link Layer and PCIe / CXL.io Transaction Layer protocol parts in the CXL controller structure; the lpif_ctrl module is used to complete the data format conversion, converting the PIPE data format into the LPIF data format; the fpga pcie controller module completes the PCIe / CXL.io Link Layer and PCIe / CXL.io TransactionLayer protocols;

[0014] The DDR controller module and the SRAM module are used for CXL data caching;

[0015] The clk_rstn_gen module is used to implement the clock and reset functions of the CXL subsystem.

[0016] Furthermore, the rates include Gen5, Gen4 and Gen3.

[0017] Application of CXL control system based on fpga pcie controller, using the above CXL control system based on fpga pcie controller to achieve FPGA resource optimization and solve FPGA compatibility;

[0018] The FPGA resource optimization includes:

[0019] Utilize the programmable features of FPGA to optimize Flex Bus logic resources;

[0020] Make full use of the host's Flex Bus lane number configurable feature to reduce logic resource utilization by generating different FPGA configuration files to meet FPGA timing requirements;

[0021] By optimizing the functional path, the timing requirements of different FPGA devices can be met;

[0022] The solution to FPGA compatibility includes:

[0023] Make full use of mature FPGA IP to achieve DDR expansion and SRAM expansion;

[0024] Compatible with different PCIe controllers and PCIe PHY implementations in FPGA;

[0025] It is compatible with Gen5, Gen4 and Gen3 rates, reducing development and product costs.

[0026] Furthermore, the Flex Bus logic resources include optimizing lane flip modules by utilizing the programmable characteristics of FPGA pins.

[0027] Furthermore, the FPGA mature IP includes DDR controller, DDR PHY and RAM controller, which are directly applied to different expansion requirements of accelerators, including servers and AI processors.

[0028] Furthermore, the implementation of being compatible with different PCIe controllers and PCIe PHY in FPGA specifically includes Flex Bus Gen3 / 4 / 5 and subsequent Gen6.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] (1) By being compatible with Gen3 / Gen4 and other rates, development and product costs can be effectively reduced;

[0031] (2) Effectively resolve conflicts in logic resources and timing through common IP such as FPGA PCIe PHY and PCIe controller;

[0032] (3) Through the use of common IP such as FPGA PCIe PHY and PCIe controller, high bandwidth such as PCIe Gen5 rate is achieved, and CXL access latency is effectively reduced by optimizing CXL functions and timing;

[0033] (4) Effectively implement various CXL application scenarios through common IPs such as FPGA PCIe PHY, PCIe controller, DDR controller, and DDR PHY;

[0034] (5) Make full use of the programmable features of FPGA and optimize the Flex Bus logic resources to achieve FPGA timing requirements;

[0035] (6) Make full use of the host's Flex Bus lane number configurable feature to reduce logic resource utilization by generating different FPGA configuration files to meet FPGA timing requirements;

[0036] (7) Optimize the functional path to meet the timing requirements of different FPGA devices;

[0037] (8) Make full use of mature FPGA IP, such as DDR controller, DDR PHY, and RAM controller to achieve DDR expansion and SRAM expansion, which can be applied to different expansion requirements of servers, AI processors or other accelerators;

[0038] (9) It is compatible with different PCIe controllers and PCIe PHY implementations in FPGA, such as Flex Bus Gen3 / 4 / 5 and subsequent Gen6, to meet the speed and functional requirements of different application scenarios; by being compatible with Gen3 / Gen4 and other rates, it can effectively reduce development and product costs.

[0039] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0041] Figure 1 This is the existing CXL control architecture diagram;

[0042] Figure 2 It is the existing CXL application scenario diagram;

[0043] Figure 3 This is the existing CCIX architecture diagram;

[0044] Figure 4 This is the system diagram of the CXL control system based on the fpga pcie controller of this technical solution;

[0045] Figure 5 This is a diagram of the CXL device identification result in a specific embodiment of the technical solution;

[0046] Figure 6 This is a schematic diagram of the application of CXL in a specific embodiment of the technical solution;

[0047] Figure 7 This is a schematic diagram of a CXL Type 1 application scenario in a specific embodiment;

[0048] Figure 8 This is a schematic diagram of a CXL Type 2 application scenario in a specific embodiment;

[0049] Fig. 9 It is a schematic diagram of a CXL Type 3 application scenario in a specific embodiment. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0051] The following are the full names of the specific professional terms in this technical solution:

[0052] CXL: Compute Express Link

[0053] PCIe: Peripheral Component Interconnect Express

[0054] FPGA: Field Programmable Gate Array

[0055] PIPE:PHY Interface for the PCI Express

[0056] LPIF:Logical PHY Interface

[0057] vlsm: virtual link state machine

[0058] like Figure 1 As shown, the existing CXL control architecture diagram is shown. Figure 2 For the existing CXL application scenario diagram, Figure 3 This is the existing CCIX architecture diagram;

[0059] Both CXL and CCIX are high-speed interconnect standards for connecting different chips, but they differ in some aspects. The following is the main comparison between CXL and CCIX: CCIX is a data transmission protocol based on the PCIe data link layer, which retains the high bandwidth of PCIe. Due to the large number of protocol layers, the latency is higher than CXL, which is not convenient for memory expansion application scenarios.

[0060] Disadvantages of existing technologies: (1) Closedness. NVlink has high bandwidth and low latency characteristics, but can only be used for data sharing between NVIDIA GPUs, and cannot be used for data sharing with CPUs and other accelerators. (2) Memory wall. Data communication between CPUs, GPUs, and various accelerators requires multiple data transfers. (3) High latency. It is impossible to provide a low-latency memory expansion solution.

[0061] To this end, the problems to be solved by this technical solution are: providing a CXL FPGA solution to solve high bandwidth and low latency; providing a CXL controller resource optimization solution for FPGA resource optimization; providing a CXL low-cost solution to achieve Gen3 / Gen4 compatibility.

[0062] like Figure 4 As shown, the CXL control system based on the fpga pcie controller of the present invention includes six parts;

[0063] (1) PCIe PHY: Figure 4 The PCIe PHY module in this design technical solution is completed Figure 1 Flex Bus Physical Layer protocol function in the CXL controller architecture diagram. This solution uses FPGA PCIe PHY to reduce development cycle and risk. The use of FPGA mature PHY solution can enhance the compatibility of this solution at different rates (Gen5 / Gen4 / Gen3, etc.);

[0064] (2)cxl arb mux: Figure 4 In this design technical scheme, pipe_ctrl, ARB MUX and vlsm are three modules to complete Figure 1 CXL ARB MUX protocol functions in the CXL controller architecture diagram; the pipe_ctrl module transmits data and control signals to the PCIe PHY through the PIPE interface; the ARB MUX module divides the pipe_ctrl data into three categories: io, mem / cache, and vlsm according to the CXL protocol; the vlsm module is used to implement CXL device enumeration;

[0065] (3)cxl io ctrl: Figure 4 This design technical solution diagram lpif_ctrl and fpga pcie controller two modules to complete Figure 1 The PCIe / CXL.io Link Layer and PCIe / CXL.io Transaction Layer protocol parts in the CXL controller architecture diagram. lpif_ctrl is used to complete the data format conversion, converting the PIPE data format to the LPIF data format; the fpga pcie controller completes the PCIe / CXL.io Link Layer and PCIe / CXL.io Transaction Layer protocols;

[0066] (4)xl mem / cache: Figure 4 The protocol functions of CXL.cache+CXL.mem Link Layer and CXL.cache+CXL.mem Transaction Layer in this design technical solution diagram;

[0067] (5) DDR controller and SRAM are used for CXL data cache;

[0068] (6) Others: Figure 4 The clk_rstn_gen module in this design technical solution is used to implement the clock and reset functions of the CXL subsystem.

[0069] The technical innovation of CXL controller realized by this solution is reflected in three aspects:

[0070] (1) Provides a solution based on FPGA PCIe controller:

[0071] a. Effectively combine FPGA PCIe PHY and PCIe controller and other common IPs to propose an effective CXL solution to reduce development costs and cycles;

[0072] b. Effectively resolve conflicts in logic resources and timing through common IPs such as FPGA PCIe PHY and PCIe controller;

[0073] c. Through common IPs such as FPGA PCIe PHY and PCIe controller, high bandwidth (at PCIe Gen5 rate) is achieved, and CXL access latency is effectively reduced by optimizing CXL functions and timing;

[0074] d. Effectively implement various CXL application scenarios through common IPs such as FPGA PCIe PHY, PCIe controller, DDR controller and DDR PHY ( Figure 2 CXL application scenarios show the three possible application scenarios defined in the CXL2.0 standard and subsequent CXL standards);

[0075] (2) Provides an FPGA-based resource optimization solution:

[0076] a. Make full use of the FPGA programmable features to optimize the Flex Bus logic resources (such as optimizing the lane flip module through the FPGA pin programmable features, etc.) to achieve the FPGA timing requirements;

[0077] b. Make full use of the host's Flex Bus lane number configurable feature to reduce logic resource utilization by generating different FPGA configuration files to meet FPGA timing requirements;

[0078] c. Optimize the functional path to meet the timing requirements of different FPGA devices;

[0079] (3) Provides a FPGA-based compatibility solution:

[0080] d. This solution makes full use of mature FPGA IP, such as DDR controller, DDR PHY, and RAM controller to achieve DDR expansion and SRAM expansion, and can be applied to different expansion requirements of servers, AI processors or other accelerators;

[0081] e. This solution is compatible with different PCIe controllers and PCIe PHY implementations in FPGA (such as FlexBus Gen3 / 4 / 5 and subsequent Gen6, etc.) to meet the speed and function requirements of different application scenarios;

[0082] f. By being compatible with Gen3 / Gen4 and other rates, development and product costs can be effectively reduced;

[0083] This solution identifies the device as Figure 4 As shown;

[0084] The specific code is:

[0085] ubuntu@ubuntu:~$lspci|grep Xilink

[0086] bc:00.0 CLX:xilix Corporation Device 9038

[0087] ubuntu@ubuntu:~$lspci-vv-s bc:00.0

[0088] bc:00.0 CLX:Xilinx Corporation Device 9038(prog-if 10[CXL MemoryDevice(CXL 2.x)])

[0089] Subsystem:Xilinx Corporation Device 0007

[0090] Physical Slot:8191-1

[0091] Control:I / O-Mem+BusMaster-SpecCycle-MemWINV-VGASnoop-ParErr-Step pig-SERR+FastB2B-DisINTx-

[0092] Status:Cap+66MHz-UDF-FastB2B-ParErr-DEVSEL=fast>TAbort-<TAbort- <mabort->SERR- <PERR-INNTx-

[0093] NUMA node:0

[0094] Region 0:Memory at

[0095] dee00000(64bit,non-prefetchable)[size=64k]

[0096] Capabilities:<access denied>

[0097] Kernnel modules:cxl_pci

[0098] ubuntu@ubuntu:~$[]

[0099] like Figure 6 As shown, it is a schematic diagram of the application of CXL in a specific embodiment of the present technical solution; wherein, in the schematic diagram of the CXL application, the Host Processor is a CPU or various accelerators, and the Accelerator is a schematic diagram of the design of the present solution;

[0100] The application embodiments of the CXL control system based on the fpga pcie controller using the technical solution include the following three embodiments: Specific embodiment 1:

[0102] like Figure 7 As shown, this specific embodiment uses FPGA PCIe Gen3 / 5PHY+PCIe Gen3 / 5 controller+DDR3 / 4 controller+DDR3 / 4PHY to implement Figure 2 Type1;

[0103] This application scenario can be used as a network data cache expansion (NIC data cache expansion). If CXLSwitch is not selected, the Flex Bus is directly connected to the CPU; this solution can match the corresponding Flex Bus rate, storage media (SSD / DDR / SRAM, etc.) and capacity according to different NIC performance and system requirements to achieve a balance between cost, performance and energy consumption. Specific embodiment 2:

[0105] like Figure 8 As shown, this specific embodiment uses FPGA PCIe Gen3 / 5PHY+PCIe Gen3 / 5 controller+DDR3 / 4 controller+DDR3 / 4PHY to implement Figure 2 Type2;

[0106] This application scenario can be used as data cache for acceleration cards such as GPUs. If CXL Switch is not selected, the Flex Bus is directly connected to the CPU. This solution can match the corresponding Flex Bus rate, storage media (SSD / DDR / SRAM, etc.) and capacity according to different GPU acceleration capabilities and system requirements to achieve a balance between cost, performance and energy consumption. Specific embodiment 3:

[0108] like Fig. 9 As shown, this specific embodiment uses FPGA PCIe Gen3 / 5PHY+PCIe Gen3 / 5 controller+DDR3 / 4 controller+DDR3 / 4PHY to implement Figure 2 Type3;

[0109] This application scenario can be used for memory expansion or pooling of processors such as CPU / GPU / DPU. If the system requires shared memory or memory pooling between different processors or accelerators, CXL Switch is required; if the system only needs one processor or accelerator to expand memory, CXL Switch is not required; this solution can match the corresponding Flex Bus rate, storage media (SSD / DDR / SRAM, etc.) and capacity according to the bandwidth and capacity requirements of different CPU / GPU / DPU systems to achieve a balance between cost, performance and energy consumption.

[0110] The preferred embodiments of the present invention disclosed above are only used to help illustrate the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. CXL control system based on fpga pcie controller, characterized in that, Including PCIePHY module, cxl arb mux layer, cxl io ctrl layer, cxl mem / cache layer, DDR controller module, SRAM module and clk_rstn_gen module; The PCIePHY module is used to complete the protocol functions of the Flex Bus Physical Layer in the CXL controller architecture, and adopts the mature FPGA PHY solution to enhance the compatibility of this solution at different rates; The cxl arb mux layer includes a pipe_ctrl module, an ARB MUX module and a vlsm module, which are used to complete the CXL ARB MUX protocol function in the CXL controller architecture; wherein the pipe_ctrl module transmits data and control signals with the PCIe PHY through the PIPE interface; the ARB MUX module divides the pipe_ctrl data into three categories of io, mem / cache and vlsm according to the CXL protocol; the vlsm module is used to implement CXL device enumeration; The cxl io ctrl layer includes an lpif_ctrl module and an fpga pcie controller module, which are used to complete the PCIe / CXL.io Link Layer and PCIe / CXL.io Transaction Layer protocol parts in the CXL controller structure; the lpif_ctrl module is used to complete the data format conversion, converting the PIPE data format into the LPIF data format; the fpgapcie controller module completes the PCIe / CXL.io Link Layer and PCIe / CXL.io Transaction Layer protocols; The DDR controller module and the SRAM module are used for CXL data caching; The clk_rstn_gen module is used to implement the clock and reset functions of the CXL subsystem.

2. The CXL control system based on the fpga pcie controller according to claim 1, characterized in that: The rates include Gen5, Gen4 and Gen3.

3. Application of CXL control system based on fpga pcie controller, characterized in that, Adopting the CXL control system based on the fpga pcie controller as described in any one of claims 1-2 to achieve FPGA resource optimization and solve the compatibility of FPGA; The FPGA resource optimization includes: Utilize the programmable features of FPGA to optimize Flex Bus logic resources; Make full use of the host's Flex Bus lane number configurable feature to reduce logic resource utilization by generating different FPGA configuration files to meet FPGA timing requirements; By optimizing the functional path, the timing requirements of different FPGA devices can be met; The solution to FPGA compatibility includes: Make full use of mature FPGA IP to achieve DDR expansion and SRAM expansion; Compatible with different PCIe controllers and PCIe PHY implementations in FPGA; It is compatible with Gen5, Gen4 and Gen3 rates, reducing development and product costs.

4. The application of the CXL control system based on the fpga pcie controller according to claim 3, characterized in that: The Flex Bus logic resources include optimizing lane flip modules by utilizing the programmable features of FPGA pins.

5. The application of the CXL control system based on the fpga pcie controller according to claim 3, characterized in that: The FPGA mature IP includes DDR controller, DDR PHY and RAM controller, which are directly applied to different expansion requirements of accelerators, including servers and AI processors.

6. The application of the CXL control system based on the fpga pcie controller according to claim 3, characterized in that: The implementation of being compatible with different PCIe controllers and PCIe PHY in FPGA specifically includes Flex Bus Gen3 / 4 / 5 and subsequent Gen6.

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