Floating-point number processing methods and apparatuses, electronic devices and storage media

Abstract

This disclosure provides a floating-point number processing method, a floating-point number processing apparatus, an electronic device, and a storage medium. The floating-point number processing method applied to a coprocessor includes: receiving a floating-point addition instruction, wherein the floating-point addition instruction includes an accumulated value and a memory address, the accumulated value being used for floating-point addition; obtaining a first operand, wherein the first operand is a value stored at the memory address; performing a floating-point addition operation based on the first operand and the accumulated value to obtain a second operand; generating a comparison and exchange request based on the first operand, the second operand, and the memory address, and sending the comparison and exchange request to the main processor; and determining whether the floating-point addition instruction has been completed in response to receiving a processing result of the comparison and exchange request from the main processor. This method not only avoids memory bus occupancy but also prevents the main processor from entering a loop and reduces the execution overhead of the main processor.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a floating-point number processing method, a floating-point number processing apparatus, an electronic device, and a storage medium. Background Technology

[0002] In heterogeneous computing architectures, floating-point operations are typically performed by coprocessors, and the data for these operations is usually stored in the main processor's memory. Before performing a floating-point operation, the coprocessor needs to load the data from the main processor's memory into its corresponding storage space. After completing the operation, the coprocessor needs to store the result back into the main processor's memory. In certain specific floating-point operations, such as floating-point accumulation, it is crucial to ensure that the data in the main processor's memory is not modified by other coprocessors during the period between when the coprocessor retrieves the data from the main processor's memory and when it stores the result back into the main processor's memory.

[0003] For example, when multiple coprocessors collaborate on floating-point addition operations, one coprocessor currently accessing the main processor's memory can issue a lock instruction to the memory bus, preventing other coprocessors from accessing memory. Furthermore, coprocessors can implement comparison and swap atomic operations in software. While one coprocessor executes this atomic operation, other coprocessors cannot operate on the data in memory. A comparison and swap atomic operation typically involves four steps: reading the original value at the destination address, comparing one operand with the original value, writing the other operand to the destination address if the operand equals the original value, and otherwise returning the original value.

[0004] However, locking the memory bus by the coprocessor can occupy memory resources for extended periods, resulting in resource waste. Using atomic comparison and swap operations is time-consuming and carries the risk of prolonged unsuccessful operations, which imposes significant overhead on the main processor. Summary of the Invention

[0005] One or more embodiments of this disclosure provide a floating-point number processing method and apparatus, electronic device and storage medium, which can be used to overcome the defects of the coprocessor occupying the main processor's memory in existing floating-point number accumulation operations.

[0006] At least one embodiment of this disclosure provides a floating-point number processing method applied to a coprocessor, comprising: receiving a floating-point addition instruction, wherein the floating-point addition instruction includes an accumulated value and a memory address, the accumulated value being used for floating-point addition; obtaining a first operand, wherein the first operand is a value stored at the memory address; performing a floating-point addition operation based on the first operand and the accumulated value to obtain a second operand; generating a comparison and exchange request based on the first operand, the second operand, and the memory address, and sending the comparison and exchange request to a main processor; and determining whether the floating-point addition instruction has been executed completely in response to receiving the processing result of the comparison and exchange request from the main processor.

[0007] Optionally, in at least one embodiment of the floating-point number processing method of this disclosure, obtaining the first operand includes: generating a read request based on a memory address; and sending the read request to the main processor so that the main processor can return the first operand.

[0008] Optionally, in at least one embodiment of the floating-point number processing method of this disclosure, the processing result includes the stored value of the memory address. Determining whether the floating-point addition instruction has been completed includes: comparing the stored value with a first operand; determining that the floating-point addition instruction has been completed when the stored value is the same as the first operand; and determining that the floating-point addition instruction has not been completed when the stored value is different from the first operand.

[0009] Optionally, the floating-point number processing method of at least one embodiment of the present disclosure further includes: generating and sending a completion response of the floating-point addition instruction when it is determined that the floating-point addition instruction has been executed.

[0010] Optionally, the floating-point number processing method of at least one embodiment of the present disclosure further includes: when it is determined that the floating-point addition instruction has not been completed, using the stored value as the first operand, regenerating the comparison and exchange request, and sending the regenerated comparison and exchange request to the main processor.

[0011] Optionally, in at least one embodiment of the floating-point number processing method disclosed herein, the coprocessor includes a peripheral component interconnect standard PCIe controller.

[0012] At least one embodiment of this disclosure provides a floating-point data processing method applied to a main processor, comprising: receiving a comparison and exchange request obtained from a coprocessor by a floating-point addition instruction, wherein the comparison and exchange request includes a first operand, a second operand, and a memory address; accessing the memory address to read a stored value at the memory address; comparing the stored value with the first operand to obtain a comparison result; generating a processing result of the comparison and exchange request based on the stored value and the comparison result, and sending the processing result to the coprocessor, wherein the processing result includes the stored value; wherein, when the comparison result indicates that the stored value is the same as the first operand, the second operand is stored in the memory address, and when the comparison result indicates that the stored value is different from the first operand, no storage operation is performed on the memory address.

[0013] Optionally, the floating-point number processing method of at least one embodiment of the present disclosure further includes: receiving a read request obtained by floating-point addition from a coprocessor, and accessing a memory address to read a first operand according to the read request; and feeding back the first operand to the coprocessor.

[0014] At least one embodiment of this disclosure provides a floating-point data processing method applied to a data processing apparatus including a main processor and a coprocessor, comprising: receiving a floating-point addition instruction by the coprocessor, wherein the floating-point addition instruction includes an accumulated value and a memory address, the accumulated value being used for floating-point addition; generating a comparison and exchange request by the coprocessor according to the floating-point addition instruction, and sending the comparison and exchange request to the main processor, wherein the comparison and exchange request includes a first operand, a second operand, and a memory address, the first operand being a value stored at the memory address, and the second operand being obtained by the coprocessor performing floating-point addition based on the first operand and the accumulated value; performing a comparison and exchange operation by the main processor in response to the comparison and exchange request, and obtaining a comparison result; generating and sending a processing result by the main processor according to the comparison result, wherein the processing result includes a value stored at the memory address; and determining, in response to the processing result, whether the floating-point addition instruction has been completed; wherein the main processor stores the second operand at the memory address when the comparison result indicates that the stored value is the same as the first operand, and does not perform a storage operation on the memory address when the comparison result indicates that the stored value is different from the first operand.

[0015] Optionally, the floating-point number processing method of at least one embodiment of the present disclosure further includes: generating a read request by a coprocessor based on a memory address; sending the read request to the main processor by the coprocessor; accessing the memory address to read a first operand based on the read request by the main processor; and feeding back the first operand to the coprocessor by the main processor.

[0016] Optionally, in at least one embodiment of the floating-point number processing method of this disclosure, the processing result includes the stored value of the memory address, and the coprocessor determines whether the floating-point addition instruction has been completed, including: the coprocessor comparing the stored value with the first operand; when the stored value is the same as the first operand, the coprocessor determines that the floating-point addition instruction has been completed; when the stored value is different from the first operand, the coprocessor determines that the floating-point addition instruction has not been completed.

[0017] Optionally, the floating-point number processing method of at least one embodiment of the present disclosure further includes: when the coprocessor determines that the floating-point addition instruction has been executed, the coprocessor generates and sends a completion response for the floating-point addition instruction.

[0018] Optionally, the floating-point number processing method of at least one embodiment of the present disclosure further includes: when the coprocessor determines that the floating-point addition instruction has not been completed, using the stored value as the first operand, regenerating the comparison and exchange request, and sending the regenerated comparison and exchange request to the main processor.

[0019] Optionally, in at least one embodiment of the floating-point number processing method of this disclosure, the comparison and swapping operation performed by the main processor to obtain the comparison result includes: the main processor accessing a memory address to read the stored value of the memory address; and the main processor comparing the stored value with a first operand to obtain the comparison result.

[0020] Optionally, in at least one embodiment of the floating-point number processing method disclosed herein, the coprocessor includes a peripheral component interconnect standard PCIe controller.

[0021] Optionally, in at least one embodiment of the floating-point number processing method of this disclosure, the data processing device includes a plurality of coprocessors, and when each of the plurality of coprocessors determines that the corresponding floating-point addition instruction has been executed, the plurality of coprocessors complete the floating-point accumulation operation.

[0022] At least one embodiment of this disclosure provides a floating-point processing apparatus, comprising: a receiving unit configured to receive a floating-point addition instruction, wherein the floating-point addition instruction includes an accumulated value and a memory address, the accumulated value being used for floating-point addition; an operand acquisition unit configured to acquire a first operand, wherein the first operand is a value stored at the memory address; an arithmetic unit configured to perform a floating-point addition operation based on the first operand and the accumulated value to obtain a second operand; a request generation unit configured to generate a comparison and exchange request based on the first operand, the second operand, and the memory address, and send the comparison and exchange request to a main processor; and a determining unit configured to determine whether the floating-point addition instruction has been executed completely in response to the processing result of receiving the comparison and exchange request from the main processor.

[0023] Optionally, according to at least one embodiment of the present disclosure, the floating-point processing device is implemented as a peripheral component interconnect standard PCIe controller.

[0024] At least one embodiment of this disclosure provides a floating-point processing apparatus, comprising: a receiving unit configured to receive a comparison and exchange request obtained from a coprocessor by a floating-point addition instruction, wherein the comparison and exchange request includes a first operand, a second operand, and a memory address; a memory access unit configured to access the memory address to read a stored value at the memory address; a comparison unit configured to compare the stored value and the first operand to obtain a comparison result; a result generation unit configured to generate a processing result of the comparison and exchange request based on the stored value and the comparison result, and send the processing result to the coprocessor, wherein the processing result includes the stored value; and a processing unit configured to store the second operand at the memory address when the comparison result indicates that the stored value is the same as the first operand, and not to perform a storage operation on the memory address when the comparison result indicates that the stored value is different from the first operand.

[0025] At least one embodiment of this disclosure provides a floating-point number processing apparatus, including: at least one processing device and a memory; wherein, the memory stores a computer program, and when the computer program is executed by at least one processing device, it implements the floating-point number processing method of any of the above embodiments.

[0026] At least one embodiment of this disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein when the instructions are executed by a processor, they implement the floating-point number processing method of any of the above embodiments.

[0027] At least one embodiment of this disclosure provides an electronic device, including a floating-point processing apparatus according to any embodiment of this disclosure. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of a floating-point number processing method provided by an embodiment of this disclosure;

[0030] Figure 2 This is a schematic diagram of another floating-point number processing method provided by an embodiment of this disclosure;

[0031] Figure 3This is a schematic diagram of yet another floating-point number processing method provided by an embodiment of this disclosure;

[0032] Figure 4 This is a schematic diagram of a data processing apparatus provided in an embodiment of the present disclosure;

[0033] Figure 5 This is a schematic diagram of a floating-point processing device provided in an embodiment of this disclosure;

[0034] Figure 6 This is a schematic diagram of a floating-point processing device provided in an embodiment of this disclosure;

[0035] Figure 7 This is a schematic diagram of a floating-point processing device provided in an embodiment of the present disclosure. Detailed Implementation

[0036] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0037] Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of this disclosure shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in a common dictionary shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and shall not be interpreted in an idealized or highly formalized sense, unless expressly defined in the embodiments of this disclosure.

[0038] The terms "first," "second," and similar words used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "an," "one," or "the" do not indicate a quantity limitation, but rather indicate the presence of at least one. Likewise, the terms "including" or "comprising" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. The terms "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Flowcharts are used in this disclosure to illustrate the steps of the method according to embodiments of this disclosure. It should be understood that the preceding or following steps are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes, or one or more steps can be removed from these processes.

[0039] Heterogeneous systems typically consist of a main processor and one or more coprocessors. For operations such as floating-point addition, the operand in memory corresponding to the addition operation is a shared variable among multiple coprocessors. Therefore, all coprocessors access memory to obtain the operand. For example, consider four coprocessors, all needing to perform an addition operation on the operand 1 in memory. These four coprocessors are designated as coprocessor 1, coprocessor 2, coprocessor 3, and coprocessor 4. The main processor sends floating-point addition instructions to coprocessors 1 through 4. Coprocessors 1 through 4 do not have a fixed order for executing the addition operation, nor is the execution order indicated in the instructions. After receiving the instruction, coprocessors 1 through 4 access the main processor's memory to obtain the operand. Due to transmission latency and other factors, coprocessors 1 through 4 may not receive the instruction from the main processor simultaneously, or they may not execute the instruction immediately after receiving it. This can lead to conflicts in the memory access times of coprocessors 1 through 4.

[0040] For example, if coprocessors 1-4 use a memory bus-locked access method, then when coprocessor 1 is performing an accumulation operation, coprocessors 2-4 cannot access memory. While there are no conflicts in memory access by coprocessors 1-4 under the memory bus-locked access method, the memory bus lock causes all memory resources to be occupied, resulting in resource waste.

[0041] For example, when coprocessors 1-4 use software-implemented comparison and swap atomic operations to execute the above instructions, while coprocessor 1 has obtained operand 1 but has not yet stored the processing result in memory, coprocessor 4 can access memory and obtain operand 1. Coprocessor 1 then normally stores the processing result in memory, and the operand in memory becomes operand 2. However, when coprocessor 4 obtains the processing result, the operand in memory has already changed from operand 1 to operand 2. This causes coprocessor 4 to be unable to store the processing result in memory, and the comparison and swap atomic operations executed by coprocessor 4 will continuously fail, resulting in significant execution overhead.

[0042] To address the issues of excessive overhead caused by memory bus locking access methods and software-implemented atomic operations, embodiments of this disclosure provide floating-point processing methods and apparatus, electronic devices, and storage media.

[0043] At least one embodiment of this disclosure provides a floating-point number processing method applied to a coprocessor, comprising: receiving a floating-point addition instruction, wherein the floating-point addition instruction includes an accumulated value and a memory address, the accumulated value being used for floating-point addition; obtaining a first operand, wherein the first operand is a value stored at the memory address; performing a floating-point addition operation based on the first operand and the accumulated value to obtain a second operand; generating a comparison and exchange request based on the first operand, the second operand, and the memory address, and sending the comparison and exchange request to a main processor; and determining whether the floating-point addition instruction has been executed completely in response to receiving the processing result of the comparison and exchange request from the main processor.

[0044] At least one embodiment of this disclosure provides a floating-point data processing method applied to a main processor, comprising: receiving a comparison and exchange request obtained from a coprocessor by a floating-point addition instruction, wherein the comparison and exchange request includes a first operand, a second operand, and a memory address; accessing the memory address to read a stored value at the memory address; comparing the stored value with the first operand to obtain a comparison result; generating a processing result of the comparison and exchange request based on the stored value and the comparison result, and sending the processing result to the coprocessor, wherein the processing result includes the stored value; wherein, when the comparison result indicates that the stored value is the same as the first operand, the second operand is stored in the memory address, and when the comparison result indicates that the stored value is different from the first operand, no storage operation is performed on the memory address.

[0045] At least one embodiment of this disclosure provides a floating-point data processing method applied to a data processing apparatus including a main processor and a coprocessor, comprising: receiving a floating-point addition instruction by the coprocessor, wherein the floating-point addition instruction includes an accumulated value and a memory address, the accumulated value being used for floating-point addition; generating a comparison and exchange request by the coprocessor according to the floating-point addition instruction, and sending the comparison and exchange request to the main processor, wherein the comparison and exchange request includes a first operand, a second operand, and a memory address, the first operand being a value stored at the memory address, and the second operand being obtained by the coprocessor performing floating-point addition based on the first operand and the accumulated value; performing a comparison and exchange operation by the main processor in response to the comparison and exchange request, and obtaining a comparison result; generating and sending a processing result by the main processor according to the comparison result, wherein the processing result includes a value stored at the memory address; and determining, in response to the processing result, whether the floating-point addition instruction has been completed; wherein the main processor stores the second operand at the memory address when the comparison result indicates that the stored value is the same as the first operand, and does not perform a storage operation on the memory address when the comparison result indicates that the stored value is different from the first operand.

[0046] According to the floating-point data processing method provided in the embodiments of this disclosure, the coprocessor obtains a first operand and performs a floating-point addition operation based on the first operand and the accumulated value to obtain a second operand; a comparison and swap request is generated based on the first operand, the second operand, and the memory address, and sent to the main processor. The main processor executes the comparison and swap request, and if the comparison result indicates that the stored value is different from the first operand, no storage operation is performed on the memory address. The method provided in the embodiments of this disclosure not only avoids memory bus occupancy but also prevents the main processor from getting stuck in a loop and reduces the execution overhead of the main processor.

[0047] In the embodiments of this disclosure, the main processor may be a central processing unit (CPU), and the coprocessors may include a graphics processing unit (GPU), a tensor processing unit (TPU), or a neural network processing unit (NPU), etc.

[0048] Both the main processor and the coprocessor can have their own memory; for example, the CPU has its own memory, and the GPU also has its own memory. To avoid confusion, the memory in this disclosure refers to the memory of the main processor, while the memory of the coprocessor is referred to as storage space or memory.

[0049] Figure 1 A flowchart of a floating-point number processing method according to an embodiment of the present disclosure is shown. Figure 1 As shown, the floating-point number processing method 100 includes the following steps:

[0050] Step S101: Receive a floating-point addition instruction, wherein the floating-point addition instruction includes an accumulated value and a memory address, and the accumulated value is used for floating-point addition.

[0051] Step S102: Obtain the first operand, where the first operand is the value stored at a memory address; perform floating-point addition based on the first operand and the accumulated value to obtain the second operand.

[0052] Step S103: Generate a comparison and swap request based on the first operand, the second operand, and the memory address, and send the comparison and swap request to the main processor.

[0053] Step S104: In response to the processing result of receiving the comparison and exchange request from the main processor, determine whether the floating-point addition instruction has been executed.

[0054] In this embodiment, the floating-point processing method 100 is executed by a coprocessor. Optionally, the floating-point processing method 100 is executed by a Peripheral Component Interconnect Express (PCIe) controller included in the coprocessor. In yet another optional implementation, the floating-point processing method 100 may be executed by dedicated circuitry. Optionally, the coprocessor in this embodiment includes a PCIe controller. For example, the floating-point processing method 100 is executed by the PCIe controller.

[0055] During step S101, a floating-point addition instruction is received. For example, the control module inside the coprocessor generates and sends a floating-point addition instruction to the PCIe controller in response to a floating-point accumulation instruction from the main processor. For example, the floating-point addition instruction indicates a PCIe atomic operation, such as the FetchAdd operation.

[0056] Floating-point addition instructions include an accumulated value and a memory address; the accumulated value is used for floating-point addition operations. For example, a floating-point addition instruction from the main processor carries an accumulated value and a memory address. The floating-point addition instruction is generated based on the accumulated value and memory address carried by the main processor's floating-point addition instruction. The floating-point addition instructions in this embodiment differ from PCIe atomic operation instructions. For instance, after receiving a PCIe atomic operation instruction, the execution of the atomic operation is uninterrupted; the floating-point addition instructions in this embodiment do not directly instruct the coprocessor to perform the atomic operation.

[0057] During step S102, in response to a floating-point addition instruction, a first operand is retrieved from memory. Based on the memory address in the floating-point addition instruction, memory is accessed; the data stored at that memory address is the first operand. For example, the PCIe controller accesses the memory address via the memory bus to read the first operand. After obtaining the first operand, a single floating-point addition operation is performed based on the first operand and the accumulated value to obtain the second operand.

[0058] Optionally, obtaining the first operand includes: generating a read request based on the memory address; and sending the read request to the main processor so that the main processor can respond with the first operand.

[0059] For example, upon receiving a floating-point addition instruction, a read request is generated based on the memory address and sent to the main processor. The main processor then reads the first operand from memory and sends it to the coprocessor.

[0060] During step S103, a comparison and swap request is generated based on the first operand, the second operand, and the memory address, and then sent to the main processor. In this embodiment, the comparison and swap request can be an atomic operation, wherein the first operand is data read from the memory address, and the second operand is the result of a floating-point addition operation.

[0061] When executing step S104, in response to the processing result of receiving the comparison and exchange request from the main processor, it is determined whether the floating-point addition instruction has been completed.

[0062] Optionally, the processing result includes the stored value at the memory address; determining whether the floating-point addition instruction has been completed includes: comparing the stored value with the first operand; if the stored value is the same as the first operand, determining that the floating-point addition instruction has been completed; if the stored value is different from the first operand, determining that the floating-point addition instruction has not been completed. The stored value at the memory address is the value read from the memory address after the main processor receives the comparison and swap request and before performing the swap operation. The value of this stored value may be equal to the first operand carried in the comparison and swap request or other values. If the floating-point addition instruction has been completed, the stored value should be equal to the first operand. The stored value can be compared with the first operand to determine whether the floating-point addition instruction has been completed.

[0063] Optionally, upon determining that the floating-point addition instruction has been executed, a completion response for the floating-point addition instruction is generated and sent. For example, when the PCIe controller determines that the floating-point addition instruction has been executed, it will send a completion response to the control module to indicate that the floating-point addition operation handled by the PCIe controller has been completed.

[0064] Optionally, if it is determined that the floating-point addition instruction has not been completed, the stored value is used as the first operand, a new comparison and exchange request is generated, and the new comparison and exchange request is sent to the main processor.

[0065] For example, if a floating-point addition instruction is not completed, it means that another coprocessor is simultaneously performing a floating-point addition operation on data at a memory address, and that the other coprocessor has finished processing first. Therefore, the current coprocessor needs to perform the floating-point addition operation again, that is, to regenerate the stored value as the first operand and send a comparison and exchange request to the main processor.

[0066] Figure 2 A flowchart of a floating-point number processing method according to an embodiment of the present disclosure is shown. Figure 2 As shown, the floating-point number processing method 200 includes the following steps:

[0067] Step S201: Receive a comparison and swap request from the coprocessor obtained by a floating-point addition instruction, wherein the comparison and swap request includes a first operand, a second operand, and a memory address.

[0068] Step S202: Access the memory address to read the stored value at the memory address; compare the stored value with the first operand to obtain the comparison result.

[0069] Step S203: Based on the stored value and the comparison result, generate the processing result of the comparison and exchange request, and send the processing result to the coprocessor, wherein the processing result includes the stored value.

[0070] The floating-point number processing method 200 is executed by the main processor. For example, the floating-point number processing method 200 is executed between the above steps S103 and S104.

[0071] Before executing step S201, the main processor receives a read request obtained by floating-point addition from the coprocessor, accesses the memory address according to the read request to read the first operand, and feeds back the first operand to the coprocessor.

[0072] During step S202, the main processor executes the received comparison and swap request. The main processor accesses memory based on the memory address and reads the stored value at that address. Then, the main processor compares the stored value with the first operand to obtain the comparison result. If the comparison result indicates that the stored value is the same as the first operand, the second operand is stored at the memory address. If the comparison result indicates that the stored value is different from the first operand, no storage operation is performed at the memory address.

[0073] When executing step S203, the main processor can generate a processing result based on the stored value and the comparison result, so the coprocessor can directly know the comparison result. Alternatively, the main processor can generate a processing result based solely on the stored value. In this case, the coprocessor needs to compare the stored value with the first operand to determine the comparison result.

[0074] In this embodiment, after comparing the stored value with the first operand, the main processor will not get stuck in a loop because the comparison result is not equal, thereby reducing the execution overhead of the main processor.

[0075] Figure 3 A flowchart of a floating-point number processing method according to an embodiment of the present disclosure is shown. Figure 3 As shown, the floating-point number processing method 300 includes the following steps:

[0076] Step S301: The coprocessor receives a floating-point addition instruction, wherein the floating-point addition instruction includes an accumulated value and a memory address, and the accumulated value is used for floating-point addition.

[0077] In step S302, the coprocessor generates a comparison and swap request based on floating-point addition instructions and sends the comparison and swap request to the main processor. The comparison and swap request includes a first operand, a second operand, and a memory address. The first operand is the value stored at the memory address, and the second operand is obtained by the coprocessor performing floating-point addition on the first operand and the accumulated value.

[0078] In step S303, in response to the comparison and swap request, the main processor performs a comparison and swap operation to obtain a comparison result. If the comparison result indicates that the stored value is the same as the first operand, the second operand is stored in the memory address; if the comparison result indicates that the stored value is different from the first operand, no storage operation is performed on the memory address.

[0079] In step S304, the main processor generates and sends a processing result to the coprocessor based on the comparison result. This processing result includes the stored value at a memory address. For example, if the comparison result indicates that the stored value is the same as the first operand, the stored value at the memory address included in the processing result is the second operand. Conversely, if the comparison result indicates that the stored value is different from the first operand, the stored value at the memory address included in the processing result is not the second operand.

[0080] In step S305, in response to the processing result, the coprocessor determines whether the floating-point addition instruction has been completed. Optionally, when the coprocessor determines that the floating-point addition instruction has been completed, the coprocessor returns a completion response for the floating-point addition instruction. For example, the coprocessor includes a PCIe controller, which receives the floating-point addition instruction from a control module. Therefore, when the PCIe controller receives the processing result from the main processor and determines that the floating-point addition instruction has been completed based on the processing result, it returns a completion response for the floating-point addition instruction to the control module.

[0081] In this embodiment, the floating-point number processing method 300 is applied to a data processing device, which includes a main processor and a coprocessor. The floating-point number processing method 300 can be implemented by having the main processor execute the floating-point number processing method 200 and the coprocessor execute the floating-point number processing method 100.

[0082] Optionally, the coprocessor generates a read request based on the memory address; the coprocessor sends the read request to the main processor; the main processor accesses the memory address to read the first operand based on the read request; and the main processor feeds back the first operand to the coprocessor.

[0083] Optionally, the processing result includes the stored value at the memory address. The coprocessor determines whether the floating-point addition instruction has been completed, including: the coprocessor comparing the stored value with the first operand; if the stored value is the same as the first operand, the coprocessor determines that the floating-point addition instruction has been completed; if the stored value is different from the first operand, the coprocessor determines that the floating-point addition instruction has not been completed.

[0084] Optionally, in at least one embodiment, the method further includes: when the coprocessor determines that the floating-point addition instruction has been executed, the coprocessor generates and sends a completion response for the floating-point addition instruction.

[0085] Optionally, in at least one embodiment, the method further includes: when the coprocessor determines that the floating-point addition instruction has not been completed, using the stored value as the first operand, regenerating the comparison and exchange request, and sending the regenerated comparison and exchange request to the main processor.

[0086] Optionally, the main processor performs the comparison and swap operations to obtain the comparison result, including: the main processor accesses the memory address to read the stored value at the memory address; the main processor compares the stored value with the first operand to obtain the comparison result.

[0087] Optionally, the coprocessor in the data processing device includes a PCIe controller.

[0088] Optionally, the data processing device includes multiple coprocessors. When each of the multiple coprocessors determines that a corresponding floating-point addition instruction has been executed, the multiple coprocessors complete the floating-point accumulation operation. For example, if each of the multiple coprocessors includes a PCIe controller, then each PCIe controller processes the corresponding floating-point addition instruction.

[0089] For example, the number of coprocessors is greater than or equal to 1. For example, when the number of coprocessors is 4, all 4 coprocessors will execute the steps in floating-point processing method 300, which can be considered as all 4 coprocessors executing floating-point processing method 100.

[0090] Figure 4 A schematic diagram of a data processing apparatus 400 provided according to an embodiment of the present disclosure is shown.

[0091] The data processing device 400 includes a main processor 401, coprocessors 402-405, and memory 406. The main processor 401 is connected to the coprocessors 402-405, and the main processor 401 is also connected to the memory 406. For example, the main processor 401 and the coprocessors 402-405 are connected via a PCIe bus.

[0092] Taking the data processing device 400 as an example, the execution method of the above floating-point number processing method 300 will be illustrated.

[0093] Coprocessors 402-405 receive floating-point addition instructions respectively. The floating-point addition instructions received by coprocessors 402-405 carry the same memory address and the same accumulated value, which is denoted as value A.

[0094] Coprocessors 402-405 generate read requests based on the floating-point addition instruction, each read request carrying the memory address. Coprocessors 402-405 then send the read requests to the main processor 401.

[0095] Suppose that coprocessor 402 first sends a read request to main processor 401. Main processor 401 accesses memory 406 based on the memory address, reads the first operand value B, and then sends the first operand value B back to coprocessor 402. Coprocessor 402 performs a floating-point addition operation on the first operand value B and the accumulated value value A to obtain the second operand value C. Coprocessor 402 generates a comparison and swap request based on the first operand value B, the second operand value C, and the memory address, and sends the comparison and swap request to main processor 401. In response to the comparison and swap operation, main processor 401 accesses memory 406 based on the memory address, obtains the current stored value at that memory address, which is value B. Main processor 401 compares the stored value with the first operand. If the comparison result is the same, it stores the second operand value C at the memory address and sends the processing result containing the stored value value B to coprocessor 402. After receiving the processing result, the coprocessor 402 determines that the stored value B is equal to the first operand B, confirms that the floating-point addition operation is complete, and sends a completion response for the floating-point addition instruction.

[0096] While coprocessor 402 is performing a floating-point addition operation, coprocessor 403 sends a read request to main processor 401. At this time, main processor 401 has not yet received the compare and swap request from coprocessor 402, so the first operand that main processor 401 sends back to coprocessor 403 is value B. After receiving the first operand value B, coprocessor 403 performs a floating-point addition operation on the first operand value B and the accumulated value value A to obtain the second operand value C. Coprocessor 403 generates a compare and swap request based on the first operand value B, the second operand value C, and the memory address, and sends the compare and swap request to main processor 401. After processing the compare and swap request from coprocessor 402, main processor 401 receives the compare and swap request from coprocessor 403. At this time, main processor 401 accesses memory 406 according to the memory address and obtains the current stored value at that memory address, which is value C. The main processor 401 compares the stored value with the first operand. If the comparison result is different, no operation is performed on the memory address, and the processing result containing the stored value `value C` is sent to the coprocessor 403. After receiving the processing result, the coprocessor 403 determines that the stored value `value C` is not equal to the first operand `value B`, and that the floating-point addition operation is incomplete. It then uses the stored value `value C` as the new first operand and performs a floating-point addition operation based on the new first operand `value C` and the accumulated value `value A` to obtain the new second operand `value D`. The coprocessor 403 generates a comparison and swap request based on the first operand `value C`, the second operand `value D`, and the memory address, and sends the comparison and swap request to the main processor 401. The main processor 401 accesses memory 406 according to the memory address and obtains the current stored value at that memory address, which is `value C`. The main processor 401 compares the stored value `value C` with the first operand `value C`. If the comparison result is the same, the main processor 401 stores the second operand `value D` at the memory address and sends the processing result containing the stored value `value C` to the coprocessor 402. After receiving the processing result, the coprocessor 403 determines that the stored value C is equal to the first operand C, confirms that the floating-point addition operation is complete, and sends a completion response for the floating-point addition instruction.

[0097] Coprocessors 404 and 405 handle floating-point addition instructions in a similar manner to coprocessor 403; please refer to the description of coprocessor 403. After receiving the processing result, if coprocessors 402-405 determine that the floating-point addition operation is incomplete based on the processing result, they will re-perform the floating-point addition operation using the stored value in the processing result as the new first operand, and regenerate the comparison and swap requests, until the processing result indicates that the floating-point addition operation is complete.

[0098] The data processing apparatus provided by the embodiments of this disclosure does not require pre-determining the processing order of floating-point addition operations among coprocessors, nor does it cause the main processor to get stuck in an execution loop, thereby effectively reducing execution overhead.

[0099] At least one embodiment of this disclosure provides a floating-point number processing apparatus, including: at least one processing device and a memory; wherein, the memory stores a computer program, and when the computer program is executed by at least one processing device, it implements a method, such as any one of the floating-point number processing method 100 or floating-point number processing method 200 in the above embodiments.

[0100] Figure 5 A schematic diagram of a floating-point processing apparatus provided according to at least one embodiment of the present disclosure is shown.

[0101] like Figure 5 As shown, the floating-point processing device 500 includes a receiving unit 501, an operand acquisition unit 502, an arithmetic unit 503, a request generation unit 504, and a determining unit 505. The receiving unit 501 is connected to the operand acquisition unit 502, the operand acquisition unit 502 is connected to the arithmetic unit 503, the request generation unit 504 is connected to the receiving unit 501, the operand acquisition unit 502, and the arithmetic unit 503, and the determining unit 505 is connected to the arithmetic unit 503 and the request generation unit 504.

[0102] The receiving unit 501 receives a floating-point addition instruction, which includes an accumulated value and a memory address, the accumulated value being used for the floating-point addition operation. The operand acquisition unit 502 acquires a first operand, which is the value stored at the memory address. The arithmetic unit 503 performs a floating-point addition operation based on the first operand and the accumulated value to obtain a second operand. The request generation unit 504 generates a comparison and exchange request based on the first operand, the second operand, and the memory address, and sends the comparison and exchange request to the main processor. The determining unit 505, in response to the processing result of receiving the comparison and exchange request from the main processor, determines whether the floating-point addition instruction has been executed successfully.

[0103] Optionally, the floating-point processing device 500 can be implemented as a peripheral component interconnect standard PCIe controller. The PCIe controller may include modules that are the same as or similar to the receiving unit 501, operand acquisition unit 502, arithmetic unit 503, request generation unit 504, and determination unit 505 to achieve the same functions.

[0104] In this embodiment, the operand acquisition unit 502 obtains a memory address from the receiving unit 501 and retrieves a first operand from memory based on the memory address. Optionally, the operand acquisition unit 502 generates a read request based on the memory address and sends the read request to the main processor so that the main processor can return the first operand.

[0105] Optionally, the determining unit 505 is further configured to compare the stored value with the first operand; if the stored value is the same as the first operand, determine that the floating-point addition instruction has been completed; if the stored value is different from the first operand, determine that the floating-point addition instruction has not been completed.

[0106] Optionally, the floating-point processing apparatus of at least one embodiment of the present disclosure further includes: a response unit configured to generate and send a completion response of the floating-point addition instruction when it is determined that the floating-point addition instruction has been executed.

[0107] Optionally, the determining unit 505 is further configured to, when determining that the floating-point addition instruction has not been completed, use the stored value as the first operand, regenerate the comparison and swap request, and send the regenerated comparison and swap request to the main processor. For example, when determining that the floating-point addition instruction has not been completed, the determining unit 505 sends the stored value to the arithmetic unit 503 and the request generation unit 504, so that the arithmetic unit 503 recalculates the second operand based on the stored value, and the request generation unit 504 regenerates the comparison and swap request based on the updated first operand, the second operand, and the original memory address, and sends the comparison and swap request to the main processor again.

[0108] Figure 6 A schematic diagram of another floating-point processing apparatus provided according to at least one embodiment of the present disclosure is shown.

[0109] like Figure 6 As shown, at least one embodiment of this disclosure provides a floating-point number processing device 600, including: a receiving unit 601, a memory access unit 602, a comparison unit 603, a result generation unit 604, and a processing unit 605.

[0110] The receiving unit 601 is configured to receive a comparison and exchange request obtained from a floating-point addition instruction from the coprocessor, wherein the comparison and exchange request includes a first operand, a second operand, and a memory address. The memory access unit 602 is configured to access the memory address to read the stored value at that memory address. The comparison unit 603 is configured to compare the stored value with the first operand to obtain a comparison result. The result generation unit 604 is configured to generate a processing result for the comparison and exchange request based on the stored value and the comparison result, and send the processing result to the coprocessor, wherein the processing result includes the stored value. The processing unit 605 is configured to store the second operand at the memory address when the comparison result indicates that the stored value is the same as the first operand, and not to perform a storage operation on the memory address when the comparison result indicates that the stored value is different from the first operand.

[0111] Optionally, the memory access unit in the floating-point processing apparatus of at least one embodiment of the present disclosure is further configured to receive a read request from the coprocessor for a floating-point addition operation, and access a memory address according to the read request to read a first operand; and feed back the first operand to the coprocessor.

[0112] Figure 7 A schematic diagram of the structure of another electronic device provided according to an embodiment of the present disclosure is shown.

[0113] For example, such as Figure 7 As shown, in some examples, electronic device 700 includes a processing device (e.g., central processing unit, graphics processing unit, etc.) 701. This processing device may include the floating-point processing device of any of the above embodiments, such as a main processor and a coprocessor. The main processor and coprocessor include the corresponding floating-point processing device described above, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 702 or a program loaded from storage device 708 into random access memory (RAM) 703. The RAM 703 also stores various programs and data required for the operation of the computer system. The processor 701, ROM 702, and RAM 703 are connected via bus 704. Input / output (I / O) interface 705 is also connected to bus 704.

[0114] For example, the following components can be connected to I / O interface 705: input devices 706 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 707 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 708 including, for example, magnetic tapes, hard disks, etc.; and communication devices 709, such as network interface cards like LAN cards and modems, etc. Communication device 709 allows electronic device 700 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. Drive 710 is also connected to I / O interface 705 as needed. Removable media 711, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on drive 710 as needed so that computer programs read from them can be installed into storage device 708 as needed. Although Figure 7 An electronic device 700 including various devices is shown; however, it should be understood that implementation or inclusion of all shown devices is not required. More or fewer devices may be implemented or included alternatively.

[0115] For example, the electronic device 700 may further include a peripheral interface (not shown in the figure). This peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 709 can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0116] The electronic devices in this disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 7The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0117] For example, the electronic device 700 can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, server, etc., or any combination of data processing device and hardware. The embodiments disclosed herein do not limit this.

[0118] At least one embodiment of this disclosure provides a computer-readable storage medium having computer-executable instructions stored thereon, wherein the instructions, when executed by a processor, are, for example, the method of any one of the floating-point processing methods 100 or any one of the floating-point processing methods 200 described in the above embodiments.

[0119] This disclosure provides at least one embodiment of an electronic device, including any one of the floating-point processing apparatuses described above.

[0120] It should be noted that the computer-readable medium described above in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In embodiments of this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In embodiments of this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0121] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0122] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0123] It is important to note that the flowcharts and method descriptions in this application are merely illustrative examples and are not intended to require or imply that the steps of the various embodiments must be performed in the given order. Some steps may be performed in parallel, independently of each other, or in another suitable order. Furthermore, words such as "secondly," "then," "next," etc., are not intended to limit the order of steps; these words are merely used to guide the reader through the description of these methods.

[0124] The block diagrams of devices, apparatuses, devices, and systems involved in this application are merely illustrative examples and are not intended to require or imply that connections, arrangements, or configurations must be made in the manner shown in the block diagrams. It should also be noted that in the apparatuses and methods of this application, components or steps can be disassembled and / or recombined. Such disassembly and / or recombination should be considered equivalent solutions to those in this application.

[0125] In addition to the above non-restrictive disclosure, the following points need to be explained in this disclosure:

[0126] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0127] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0128] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure shall be determined by the scope of the claims.

Claims

1. A floating-point number processing method, applied to a coprocessor, comprising: Receive a floating-point addition instruction, wherein the floating-point addition instruction includes an accumulated value and a memory address, and the accumulated value is used for floating-point addition; Obtain the first operand, wherein the first operand is the value stored at the memory address; A floating-point addition operation is performed based on the first operand and the accumulated value to obtain the second operand; Based on the first operand, the second operand, and the memory address, a comparison and swap request is generated and sent to the main processor; In response to the processing result of receiving the comparison and exchange request from the main processor, it is determined whether the floating-point addition instruction has been completed. The processing result includes the stored value of the memory address, and determining whether the floating-point addition instruction has been completed includes: Compare the stored value with the first operand; When the stored value is the same as the first operand, it is determined that the floating-point addition instruction has been completed. If the stored value is different from the first operand, it is determined that the floating-point addition instruction has not been completed.

2. The method according to claim 1, wherein, The process of obtaining the first operand includes: A read request is generated based on the memory address; The read request is sent to the main processor so that the main processor can respond with the first operand.

3. The method according to claim 1, further comprising: Upon determining that the floating-point addition instruction has been executed, a completion response for the floating-point addition instruction is generated and sent.

4. The method according to claim 1, further comprising: When it is determined that the floating-point addition instruction has not been completed, the stored value is used as the first operand, the comparison and exchange request is regenerated, and the regenerated comparison and exchange request is sent to the main processor.

5. The method according to any one of claims 1-4, wherein, The coprocessor includes a peripheral component interconnect standard PCIe controller.

6. A floating-point data processing method, applied to a main processor, comprising: Receive a comparison and swap request from a floating-point addition instruction from the coprocessor, wherein the comparison and swap request includes a first operand, a second operand, and a memory address; Access the memory address to read the stored value at the memory address; The stored value is compared with the first operand to obtain a comparison result; Based on the stored value and the comparison result, a processing result for the comparison and exchange request is generated and sent to the coprocessor, wherein the processing result includes the stored value; Specifically, when the comparison result indicates that the stored value is the same as the first operand, the second operand is stored in the memory address; and when the comparison result indicates that the stored value is different from the first operand, no storage operation is performed on the memory address.

7. The method according to claim 6, wherein, The method further includes: The coprocessor receives a read request obtained by floating-point addition, and accesses a memory address according to the read request to read the first operand; The first operand is fed back to the coprocessor.

8. A floating-point data processing method, applied to a data processing apparatus including a main processor and a coprocessor, comprising: The coprocessor receives a floating-point addition instruction, wherein the floating-point addition instruction includes an accumulated value and a memory address, and the accumulated value is used for floating-point addition. The coprocessor generates a comparison and swap request according to the floating-point addition instruction and sends the comparison and swap request to the main processor. The comparison and swap request includes a first operand, a second operand, and the memory address. The first operand is the value stored at the memory address, and the second operand is obtained by the coprocessor performing floating-point addition on the first operand and the accumulated value. In response to the comparison and exchange request, the main processor performs the comparison and exchange operation to obtain the comparison result; The main processor generates and sends a processing result to the coprocessor based on the comparison result, wherein the processing result includes the stored value of the memory address; In response to the processing result, the coprocessor determines whether the floating-point addition instruction has been completed. Specifically, when the comparison result indicates that the stored value is the same as the first operand, the main processor stores the second operand into the memory address; and when the comparison result indicates that the stored value is different from the first operand, it does not perform a storage operation on the memory address.

9. The method according to claim 8, wherein, The method further includes: The coprocessor generates a read request based on the memory address; The coprocessor sends the read request to the main processor. The main processor accesses the memory address to read the first operand based on the read request; The main processor feeds back the first operand to the coprocessor.

10. The method according to claim 8, wherein, The processing result includes the stored value of the memory address, and the step of the coprocessor determining whether the floating-point addition instruction has been completed includes: The coprocessor compares the stored value with the first operand; When the stored value is the same as the first operand, the coprocessor determines that the floating-point addition instruction has been completed. When the stored value is different from the first operand, the coprocessor determines that the floating-point addition instruction has not been completed.

11. The method of claim 10, further comprising: When the coprocessor determines that the floating-point addition instruction has been executed, the coprocessor generates and sends a completion response for the floating-point addition instruction.

12. The method of claim 10, further comprising: When the coprocessor determines that the floating-point addition instruction has not been completed, it uses the stored value as the first operand, regenerates the comparison and exchange request, and sends the regenerated comparison and exchange request to the main processor.

13. The method according to claim 8, wherein, The comparison and swap operations performed by the main processor to obtain the comparison result include: The main processor accesses the memory address to read the stored value at the memory address; The main processor compares the stored value with the first operand to obtain the comparison result.

14. The method according to any one of claims 8-13, wherein, The coprocessor includes a peripheral component interconnect standard PCIe controller.

15. The method according to any one of claims 8-13, wherein, The data processing device includes multiple coprocessors. When each of the multiple coprocessors determines that the corresponding floating-point addition instruction has been executed, the multiple coprocessors complete the floating-point accumulation operation.

16. A floating-point processing device, comprising: The receiving unit is configured to receive a floating-point addition instruction, wherein the floating-point addition instruction includes an accumulated value and a memory address, and the accumulated value is used for floating-point addition. An operand acquisition unit is configured to acquire a first operand, wherein the first operand is a value stored at the memory address; The arithmetic unit is configured to perform a floating-point addition operation based on the first operand and the accumulated value to obtain a second operand; The request generation unit is configured to generate a comparison and swap request based on the first operand, the second operand, and the memory address, and send the comparison and swap request to the main processor; and The determining unit is configured to, in response to receiving the processing result of the comparison and exchange request from the main processor, determine whether the floating-point addition instruction has been completed. The processing result includes the stored value of the memory address, and determining whether the floating-point addition instruction has been completed includes: Compare the stored value with the first operand; When the stored value is the same as the first operand, it is determined that the floating-point addition instruction has been completed. If the stored value is different from the first operand, it is determined that the floating-point addition instruction has not been completed.

17. The floating-point processing apparatus according to claim 16, wherein, The floating-point processing device is implemented as a peripheral component interconnect standard PCIe controller.

18. A floating-point processing device, comprising: The receiving unit is configured to receive a comparison and exchange request obtained from a floating-point addition instruction from the coprocessor, wherein the comparison and exchange request includes a first operand, a second operand, and a memory address; A memory access unit is configured to access the memory address to read the stored value at the memory address; The comparison unit is configured to compare the stored value with the first operand to obtain a comparison result; The result generation unit is configured to generate a processing result for the comparison and exchange request based on the stored value and the comparison result, and send the processing result to the coprocessor, wherein the processing result includes the stored value; and The processing unit is configured to store the second operand into the memory address when the comparison result indicates that the stored value is the same as the first operand, and not to perform a storage operation on the memory address when the comparison result indicates that the stored value is different from the first operand.

19. A floating-point processing device, comprising: At least one processing device and a memory; The memory stores a computer program, which, when executed by the at least one processing device, implements the method of any one of claims 1 to 5, or the method of claim 6 or 7.

20. A computer-readable storage medium having stored thereon computer-executable instructions, wherein, When the instructions are executed by the processor, they implement the method of any one of claims 1 to 5, or the method of claim 6 or 7.

21. An electronic device comprising a floating-point processing apparatus according to any one of claims 16-19.

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