Flash Memory Error Correction Method, Device, Medium and SSD Device

Abstract

The present invention relates to the technical field of data storage, and provides a flash memory error correction method, device, medium, and SSD device. The method includes: performing error correction on a first target die based on RAID5 error correction technology to obtain first error correction data; acquiring a first target read voltage of the first target die and first target data read using the first target read voltage; performing an exclusive OR operation on target data read at read voltages at preset positions on both sides of the first target read voltage of the first target die to obtain expected error position data of the first target die; performing an exclusive OR operation on the first error correction data and the first target data to obtain first error position data; determining a true error position of the first target die according to the expected error position data and the first error position data, and performing error correction processing on the first target data according to the true error position of the first target die to obtain correct data of the first target die. The present invention enhances the adaptability and reliability of the flash memory.

Description

Technical Field

[0001] The present invention relates to the technical field of data storage, and in particular, to a flash memory error correction method, apparatus, medium, and SSD device. Background Art

[0002] Due to its advantages such as large storage capacity, low power consumption, compatibility with silicon processes, good multi-state characteristics, and non-volatility, NAND Flash has been widely used in the storage field. However, as the number of read and write operations of NAND Flash increases, when a large number of errors occur in the stored information, these errors cannot be corrected by the preset error correction technology, and finally a situation where errors cannot be corrected occurs. This situation is also called UNC (the English name is uncorrectable).

[0003] Currently, the RAID5 error correction technology has been widely used in SSD development. The RAID5 technology only requires one information redundant NAND Flash die to achieve high-speed and high-concurrency read and write operations on data and ensure data correctness. Usually, the configuration of RAID5 in an SSD is N + 1 dies. The RAID5 technology can ensure that any one of these N + 1 dies can ensure the correctness of the data in this die through the correct information on other dies on the basis that its own error correction ability (such as BCH and LDPC error correction) cannot correct errors. However, when two dies cannot correct errors by themselves simultaneously, the RAID5 error correction technology cannot correct the information of any one or both of these two dies through the correct information on other dies, and the result is that the stored information has errors. Summary of the Invention

[0004] In order to solve the above technical problems or at least partially solve the above technical problems, the present invention provides a flash memory error correction method, apparatus, medium, and SSD device.

[0005] In one aspect of the present invention, a flash memory error correction method is provided for correcting UNC errors that occur simultaneously on a first target die and a second target die in a flash memory. The method includes:

[0006] Performing error correction on the first target die based on the RAID5 error correction technology to obtain first error correction data of the first target die;

[0007] Obtaining a first target read voltage of the first target die and first target data read using the first target read voltage;

[0008] Performing an exclusive OR operation on target data read at read voltages at preset positions on both sides of the first target read voltage of the first target die to obtain expected error position data of the first target die;

[0009] Perform an exclusive OR operation on the first error correction data and the first target data to obtain first error location data, where the first error location data includes the error location of the first target die at the first target read voltage and the error location of the second target die at the second target read voltage;

[0010] Judge the true error location of the first target die according to the expected error location data and the first error location data, and perform error correction processing on the first target data according to the true error location of the first target die to obtain the correct data of the first target die.

[0011] Further, the first target read voltage of the first target die is the optimal read voltage of the first target die, and obtaining the first target read voltage of the first target die includes:

[0012] Obtain the quasi-optimal read voltage of the first target die;

[0013] Perform a read voltage scan around the quasi-optimal read voltage of the first target die according to the specified read voltage scan range to obtain first target scan data read at different read voltages;

[0014] Perform an exclusive OR operation on each first target scan data read at different read voltages and the first error correction data respectively to obtain first error location scan data corresponding to each read voltage, and obtain the number of error locations in each first error location scan data;

[0015] Select the read voltage corresponding to the first error location scan data with the least number of error locations as the optimal read voltage of the first target die.

[0016] Further, the obtaining the first error correction data of the first target die by performing error correction on the first target die based on the RAID5 error correction technology includes:

[0017] Obtain the second target read voltage of the second target die and the second target data read at the second target read voltage;

[0018] Perform error correction on the first target die based on the second target data of the second target die and the RAID5 error correction technology.

[0019] Further, the judging the true error location of the first target die according to the expected error location data and the first error location data includes:

[0020] Compare the first error location marked in the first error location data with the expected error location marked in the expected error location data;

[0021] Flip the part of the first error position data where the first error position does not coincide with the expected error position to eliminate the error position of the second target die and obtain the true error position of the first target die.

[0022] Further, the error correction processing of the first target data according to the true error position of the first target die includes:

[0023] S51. Select some error positions from the true error positions of the first target die as target positions to be flipped;

[0024] S52. Perform a flip operation on the data in the target positions to be flipped in the first target data to obtain the first original data of the first target die;

[0025] S53. Decode the first original data of the first target die and determine whether the decoding is successful. If the decoding is successful, execute step S541; if the decoding fails, execute step S542;

[0026] S541. Use the data obtained by successful decoding as the correct data of the first target die;

[0027] S542. Select some error positions from the unselected true error positions of the first target die as new target positions to be flipped, and repeat the operations in steps S52 - S53 until the decoding is successful.

[0028] Further, after obtaining the correct data of the first target die, the method further includes:

[0029] Perform error correction on the second target die based on the correct data of the first target die and the RAID5 error correction technology to obtain the correct data of the second target die.

[0030] On the other hand, the present invention also provides a flash memory error correction device for correcting UNC errors that occur simultaneously on the first target die and the second target die in the flash memory. The device includes:

[0031] A first error correction module for performing error correction on the first target die based on the RAID5 error correction technology to obtain the first error correction data of the first target die;

[0032] A first acquisition module for acquiring the first target read voltage of the first target die and the first target data read using the first target read voltage;

[0033] A first position acquisition module for performing an exclusive OR operation on the target data read at preset positions on both sides of the first target read voltage of the first target die to obtain the expected error position data of the first target die;

[0034] A second position acquisition module, configured to perform an exclusive OR operation on the first error correction data and the first target data to obtain first error position data, where the first error position data includes the error position of a first target die at a first target read voltage and the error position of a second target die at the first target read voltage;

[0035] A second error correction module, configured to determine the true error position of the first target die according to the expected error position data and the first error position data, and perform error correction processing on the first target data according to the true error position of the first target die to obtain the correct data of the first target die.

[0036] Further, the first target read voltage of the first target die is the optimal read voltage of the first target die, and the first acquisition module includes:

[0037] A first acquisition sub-module, configured to acquire the quasi-optimal read voltage of the first target die;

[0038] A scanning module, configured to perform a read voltage scan within a specified read voltage scan range around the quasi-optimal read voltage of the first target die to obtain first target scan data read at different read voltages,

[0039] A position acquisition sub-module, configured to perform an exclusive OR operation on each piece of first target scan data read at different read voltages and the first error correction data to obtain first error position scan data corresponding to each read voltage, and acquire the number of error positions in each piece of first error position scan data;

[0040] An optimal read voltage selection sub-module, configured to select the read voltage corresponding to the first error position scan data with the least number of error positions as the optimal read voltage of the first target die.

[0041] On the other hand, the present invention further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method described in any one of the above are implemented.

[0042] On the other hand, the present invention further provides an SSD device, which includes a storage controller, and the storage controller includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the steps of the above method are implemented.

[0043] The flash memory error correction method, device, medium and SSD device provided by the present invention correct the first target die based on the RAID5 error correction technology to obtain the first error correction data of the first target die. By performing an exclusive OR operation on the target data read at the read voltages at preset positions on both sides of the first target read voltage of the first target die, the expected error position data of the first target die is obtained; by performing an exclusive OR operation on the first error correction data and the first target data, the first error position data is obtained. Since the first error correction data contains the error information of the second target die and the first target data contains the error information of the first target die, the first error position data will simultaneously contain the error position of the first target die at the first target read voltage and the error position of the second target die at the second target read voltage after the exclusive OR operation; since the expected error position data contains the possible error positions of the first target die, the error position introduced by the second target die can be flipped according to the expected error position data and the first error position data, and then the true error position of the first target die can be obtained. Based on the true error position, error correction processing is performed on the first target data, and the correct data of the first target die can be obtained. Based on RAID5, the present invention can achieve error correction of the first target die by means of software operations without changing the existing hardware design and encoding / decoding algorithms, enhancing the adaptability and reliability of the flash memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of illustrating the preferred embodiments and are not considered to be a limitation of the present invention. Moreover, throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0045] Figure 1 It is a probability distribution diagram of the same error bit number in different dies in the embodiment of the present invention;

[0046] Figure 2 It is a schematic flowchart of the flash memory error correction method in the embodiment of the present invention;

[0047] Figure 3 It is a schematic diagram of the error data distribution of the flash memory error correction method in the embodiment of the present invention;

[0048] Figure 4 It is a schematic diagram of the optimal read voltage in the embodiment of the present invention;

[0049] Figure 5 It is a schematic structural diagram of the flash memory error correction device in the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0050] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are only a part rather than all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0051] Before introducing the flash memory error correction method of the embodiments of the present invention, a brief introduction to the background technology in the present invention will be given first:

[0052] Optimal read voltage: The information stored in NAND Flash is represented and encoded by the threshold voltage of the storage unit in a specific range. By setting a reasonable read voltage, these voltage ranges can be distinguished to reduce read errors. Usually, the read voltage can be adjusted within a certain range, and the read bias voltage that minimizes the error of the read information is called the optimal read voltage.

[0053] Threshold voltage distribution: The English name is threshold voltage distribution. NAND Flash represents and encodes information through the threshold voltage of the storage unit in a specific range. The threshold voltages of many storage units in a specific range will form a statistical distribution, and this statistical distribution is the threshold voltage distribution.

[0054] RAID error correction technology: Also known as disk array technology, it ensures storage speed and data reliability through parallel transmission and redundant information bits. Currently, this technology is divided into multiple levels, and each level has its own application scenarios without distinction of superiority or inferiority. Among them, RAID5 and RAID6 technologies have been widely used in SSD storage. RAID5 technology distributes data and parity check across all N + 1 dies, ensuring data security in the case where one die cannot be error-corrected. RAID6 technology can ensure data security in the case where two dies cannot be error-corrected. The present invention mainly makes improvements and explanations for RAID5 technology.

[0055] UNC: The English name is uncorrectable. Usually, due to a large number of errors in the stored information, these errors cannot be corrected by the preset error correction technology, and finally, the situation of uncorrectable errors occurs.

[0056] Among them, the RAID5 technology can be expressed as N + 1, that is, one die is specifically used to store parity information bits. The data of this die is obtained by performing an exclusive OR operation on the data at the same position in N dies. If there is a data error in one of these N + 1 dies, the correct data can be obtained by performing an exclusive OR operation on the data at the same position in each of the other dies with correct data. At the same time, each die has its own data protection measures. However, if the data in two dies both have UNC, then obviously the RAID5 technology cannot achieve the error correction effect in this working mode. The present invention makes corresponding improvements to the existing RAID5 technology that cannot achieve the data error correction ability of two dies.

[0057] In addition, before introducing the flash memory error correction method provided by the embodiments of the present invention in detail, the present invention first proves that the probability that the bits with errors in the same page of two dies in NAND Flash are in the same position is extremely low. The size of an error correction unit frame is M (such as 1024B * 8 = 8096b). Assuming that the number of frame errors in both dies is L, then the probability calculation formula for the occurrence of errors in the same position is as shown in the following formula.

[0058]

[0059] Figure 1 is the probability distribution of the number of bits with errors in the same position when taking different L values. It can be seen from the figure that when the number of common errors is greater than 6, the probability is less than 1% (L = 60 - 140). Therefore, it can be concluded that the probability that the bits with errors in the same page of two dies in NAND Flash are in the same position is extremely low.

[0060] Based on the above factual basis, the flash memory error correction method proposed by the embodiments of the present invention is as Figure 2 shown. Among them, the present invention is mainly used to correct the UNC errors that occur simultaneously on the first target die and the second target die in the flash memory. The method includes the following steps:

[0061] S1. Correct the first target die based on the RAID5 error correction technology to obtain the first error correction data of the first target die;

[0062] In the embodiments of the present invention, correcting the first target die based on the RAID5 error correction technology specifically means performing an exclusive OR operation on the data of all dies other than the first target die to obtain the first error correction data of the first target die. At this time, since the data on the second target die also has errors, the error of the second target die is obviously introduced into the first error correction data.

[0063] It should be noted that the present invention can correct the data of the first target die based on the data of the second target die, or correct the first target die with the second target data under the optimal read voltage of the second target die after the optimal read voltage of the second target die. At this time, the least number of error positions of the second target die is introduced into the first error correction data, thereby further reducing the probability of coincidence of the error positions of the first die and the second die.

[0064] S2. Obtain the first target read voltage of the first target die and the first target data read by using the first target read voltage;

[0065] In the embodiment of the present invention, the first target read voltage of the first target die can be the current read voltage of the first target die or the quasi-optimal read voltage calculated based on the scanning algorithm. As a preferred embodiment of the present invention, the first target read voltage of the first target die can also be the optimal read voltage of the first target die. Since the information read by the first target die under the optimal read voltage has the least error, the probability of coincidence of its error position with that of the second target die will be further reduced.

[0066] S3. Perform an exclusive OR operation on the target data read at the read voltages at the preset positions on both sides of the first target read voltage of the first target die to obtain the expected error position data of the first target die;

[0067] In the embodiment of the present invention, if the two values for the exclusive OR operation are the same, 0 is output; if they are different, 1 is output. Performing an exclusive OR operation on the target data at the preset positions on both sides of the first target read voltage can identify the positions where errors may occur in the first target die. At this time, the positions where errors may occur are 1, and the positions where no errors occur are 0. By observing the positions of 1, the positions where read errors may occur in the first target die, that is, the expected error positions, can be obtained.

[0068] S4. Perform an exclusive OR operation on the first error correction data and the first target data to obtain first error position data, where the first error position data includes the error positions of the first target die under the first target read voltage and the error positions of the second target die under the second target read voltage;

[0069] In the embodiment of the present invention, since the first error correction data includes the errors caused by the second target die, and the first target data includes the errors caused by the first target die, and since the coincidence rate of the error positions of the two is very low, after performing the exclusive OR operation, if the two values at the same position are the same, 0 is output, and if they are different, 1 is output. At this time, the positions where errors occur all output 1. Therefore, the error position of the data can be judged by the position of 1. However, the first error position data at this time cannot distinguish whether the error is caused by the first target die or the second target die.

[0070] S5. Determine the true error position of the first target die according to the expected error position data and the first error position data, and perform error correction processing on the first target data according to the true error position of the first target die to obtain the correct data of the first target die.

[0071] In the embodiment of the present invention, the first error position data includes the error positions caused by the first target die and the second target die, and the expected error position data includes the positions where the first target die may have errors. Based on this, the error positions caused by the second target die can be judged, and then the true error position of the first target die can be judged. Then, based on the true error position of the first target die, error correction is performed on the first target data to obtain the original data of the first target die. After obtaining the original data of the first target die, the original data of the first target die is input into the currently used decoder for decoding, and the correct data of the first target die is obtained. Through the RAID5 technology, based on the correct data of the first target die, the correct data of the second target can be further obtained.

[0072] Based on RAID5, the present invention realizes the error correction ability of two target dies by means of software operation without changing the existing hardware design and encoding / decoding algorithm, enhancing the adaptability and reliability of the flash memory.

[0073] Further, in the embodiment of the present invention, when the first target read voltage of the first target die is the optimal read voltage of the first target die, the obtaining of the first target read voltage in step S2 specifically further includes the following steps:

[0074] S21. Obtain the quasi-optimal read voltage of the first target die;

[0075] The present invention finds the lowest point between two adjacent states by adopting a preset modeling method or algorithm, and takes the read voltage corresponding to the lowest point as the quasi-optimal read voltage of the storage unit. The preset modeling method or algorithm is prior art, and the present invention will not introduce it in detail.

[0076] S22. Perform a read voltage scan around the quasi-optimal read voltage of the first target die within a specified read voltage scan range to obtain first target scan data read at different read voltages;

[0077] In the embodiments of the present invention, a first target scan data can be obtained at each different read voltage. When the scanned read voltage is the optimal read voltage, the number of error data in the first target scan data is the least. In the embodiments of the present invention, the scan range of the read voltage should be less than the distance between the two peak voltages of the threshold voltage distribution state.

[0078] S23. Perform an exclusive OR operation on each of the first target scan data read at different read voltages and the first error correction data respectively to obtain first error position scan data corresponding to each read voltage, and obtain the number of error positions in each of the first error position scan data;

[0079] In the embodiments of the present invention, the error positions of the second target die included in the first error correction data will not change. The change in the number of error positions after each exclusive OR operation is caused by the first target die. Therefore, when the total number of error positions is the least, the scanned read voltage of the first target die is the optimal read voltage.

[0080] S24. Select the read voltage corresponding to the first error position scan data with the least number of error positions as the optimal read voltage of the first target die.

[0081] In the embodiments of the present invention, the optimal read voltage is unknown when error correction fails. The obtained optimal read voltage usually has an error. Moreover, the greater the error of the found optimal read voltage, the more error data there will be in the first target die read out, and the probability of coincidence with the error information in the second target die will increase, affecting the final error correction result.

[0082] Although in the foregoing embodiments, it has been verified that the probability of the occurrence of errors at the same position in the two storage media is very low, in order to further ensure the accuracy of error correction of the present invention, the optimal read voltage of the first target die is obtained by scanning, thereby further reducing the probability of error coincidence between the first target die and the second target die.

[0083] Further, by searching for the quasi-optimal read voltage of the second target die in step S1, data with the fewest error positions of the second target die can be obtained. Therefore, in a preferred embodiment of the present invention, the error correction of the first target die based on the RAID5 error correction technology includes: obtaining the second target read voltage of the second target die and the second target data read using the second target read voltage; performing error correction on the first target die based on the second target data of the second target die and the RAID5 error correction technology. At this time, the obtained first error correction data can include the error positions of the second target die at the second target read voltage.

[0084] Further, the second target read voltage of the second target die can be the quasi-optimal read voltage or the optimal read voltage of the second target die, and most preferably the quasi-optimal read voltage of the second target die, that is, calculating the quasi-optimal read voltage of the second target die based on the scanning algorithm.

[0085] In the embodiment of the present invention, by finding the second target read voltage of the second target die to reduce the original errors of the second target die, the first error position data obtained in step S4 further includes the error positions of the first target die at the first target read voltage and the error positions of the second target die at the second target read voltage of the second target die, further reducing the probability of coincidence of the error positions of the first target die and the second target die, and thus improving the accuracy of error correction.

[0086] Further, when performing an exclusive OR operation on the target data read at the read voltages at the preset positions on both sides of the first target read voltage of the first target die in step S3, the read voltages at the preset positions on both sides of the first target read voltage should be between the peak voltages of the left and right threshold voltage distributions of the optimal read voltage of the first target die, that is, the read voltage at the preset position on the left side of the first target read voltage of the first target die is the read voltage between the optimal read voltage of the first target die and the peak voltage of the left threshold voltage distribution of the first target die, and the read voltage at the preset position on the right side of the first target read voltage of the first target die is the read voltage between the optimal read voltage of the first target die and the peak voltage of the right threshold voltage distribution of the first target die.

[0087] It should be noted that for a bistable (SLC, Single-Level Cell) storage cell, the flash cell has two stable threshold voltage states. When performing step S3, an exclusive OR operation is performed on the target data read at the read voltages at the preset positions on both sides of the first target read voltage among the two stable threshold voltages. For multi-stable (MLC / TLC / QLC, etc.) storage cells, it is achieved by increasing the number of stable states of the threshold voltage. At this time, when performing step S3, an exclusive OR operation is simultaneously performed on the target data read at the read voltages at the preset positions on the left side of multiple target voltages and the target data read at the read voltages at the preset positions on the right side of multiple target voltages.

[0088] As Figure 3 shown, the boundaries of the threshold voltage distribution states are the ends of the two threshold voltage distribution states at the dotted line positions. The preset positions on both the left and right sides should not exceed the peak positions of the threshold voltage distribution states, so as to ensure that in the two data reads, one time the correct data related to the optimal read voltage in the first target die is read, and one time the incorrect data related to the optimal read voltage in the first target die is read. After the exclusive OR operation, the possible error positions of the first target die can be obtained.

[0089] Further, in step S5, the specific process of determining the true error position of the first target die according to the expected error position data and the first error position data includes: comparing the first error position marked in the first error position data with the expected error position marked in the expected error position data; performing a flip operation on the part of the first error position data where the first error position does not coincide with the expected error position to eliminate the error position of the second target die and obtain the true error position of the first target die.

[0090] Further, the steps for correcting the first target data according to the true error position of the first target die in the embodiments of the present invention further include the following steps:

[0091] S51. Select some of the error positions from the true error positions of the first target die as the target bits to be flipped;

[0092] In the embodiments of the present invention, some error positions can be randomly selected from the true error positions of the first target die as the target bits to be flipped, and the specific number of selections can be set according to the actual situation.

[0093] S52. Perform a flip operation on the data of the first target data at the target bits to be flipped to obtain the first original data of the first target die;

[0094] S53. Decode the first original data of the first target die and determine whether the decoding is successful. If the decoding is successful, execute step S541; if the decoding fails, execute step S542;

[0095] It should be noted that there may still be error information in the original data after the flipping operation is performed in step S52. At this time, the decoder needs to decode the first original data. If the number of error data in the first original data is within the error correction ability of the decoder, the decoding is successful and the correct data of the first target die is obtained. If the decoding is not successful and the number of errors in the first original data exceeds the error correction ability of the decoder, at this time, it is necessary to increase the number of target bits to be flipped of the first target data and re-decode until the correct data of the first target die is obtained successfully.

[0096] S541. Use the data obtained successfully by decoding as the correct data of the first target die;

[0097] S542. Select some error positions from the unselected true error positions of the first target die as the newly added target bits to be flipped, and repeat the operations of steps S52 - S53 until the decoding is successful.

[0098] In the embodiment of the present invention, when repeating the flipping operation, the data at the target bits to be flipped in the original first target data can be flipped, or based on the first original data obtained in the previous iteration, only the data at the newly added target bits to be flipped is flipped to obtain the first original data in the current iteration process.

[0099] In the embodiment of the present invention, after step S5, error correction is performed on the second target die based on the correct data of the first target die and the RAID5 error correction technology to obtain the true data of the second target die, thereby completing the error correction of the two target dice simultaneously.

[0100] The following Figure 4 The flash memory error correction method of the present invention will be further described in detail with specific embodiments in the attached

[0101] Figure 4 (a) is the error correction data of die7 obtained by performing an exclusive - OR operation through other dice except die7. The gray circles are the errors of the error correction data caused by the error data in die2. It should be noted that this figure is a simplified demonstration and the actual positions of the gray circles are unknown.

[0102] Figure 4(b) is the data of die7 read, where the blue circles are the error data in die7, and the actual positions of the blue circles are also unknown at this time.

[0103] Figure 4 (c) is Figure 4 (a) and Figure 4 (b) is the result of performing an exclusive OR operation on the two sets of data. It can be understood that since Figure 4 (a) and Figure 4 (b) both show the data in die7, and the data at the other positions are the same except for the error positions. After performing the exclusive OR operation, the data is zero. Figure 4 (a) and Figure 4 (b) have different error positions, that is, the positions where they are different from the actual data in die7 are different. After performing the exclusive OR operation, the data at these positions is 1. At this time, Figure 4 (c) can show all the error positions in die2 and die7, as shown by the positions of the gray circles and blue circles in the figure. Among them, the yellow circles are the common error positions of die2 and die7. Obviously, according to the previous assumptions and arguments, the probability of common errors is very low. Therefore, the probability of the appearance of yellow circles is very low.

[0104] Figure 4 (d) is a schematic diagram of the result of performing an exclusive OR operation on the data of die7 at different read voltages and the data in Figure 4 (a) during the read voltage scan of die7. It can be seen from Figure 3 that during the read voltage scan, the error positions caused by the gray circles do not change, and the number and positions of the blue circles will change with the change of the read voltage. It should be noted that in actual applications, the appearance of yellow dots, that is, the positions of common errors in die2 and die7, is very rare. Therefore, the optimal read voltage of die7 can be determined by judging the number of 1s after the exclusive OR operation.

[0105] Figure 4 (e) is the result of reading the data of die7 once at each of the preset positions on both sides of the optimal read voltage of die7 and performing an exclusive OR operation. The positions shown in the figure are the expected error positions of die7.

[0106] Figure 4 (f) is the true error position of die7 obtained after flipping the data of the first error position with the fewest error positions selected in Figure 4 (d) based on the expected error position of die7. Specifically, the data within the range of the solid circles in Figure 4 (f) in the data of the first error position is retained, and the data outside the range of the solid circles in Figure 4 (f) in the data of the first error position is flipped.

[0107] After obtaining the true error position of die7, the data of die7 can be corrected according to the true error position of die7, that is, the data at the true error position is flipped to obtain the correct original data of die7, and the correct data of die7 can be obtained through decoding. After obtaining the true original data of die7, the correct original data of die2 obtained by performing an exclusive OR operation through other dies except die2 can be decoded to obtain the correct data of die2. Thus, the error correction of two dies is completed simultaneously.

[0108] For the method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the embodiments of the present invention are not limited by the described action sequence, because according to the embodiments of the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0109] Figure 5 The structural schematic diagram of a flash memory error correction device according to an embodiment of the present invention is schematically shown. The device is used to correct UNC errors that occur simultaneously on the first target die and the second target die in the flash memory. Refer to Figure 5 , the flash memory error correction device of the embodiment of the present invention specifically includes a first error correction module 501, a first acquisition module 502, a first position acquisition module 503, a second position acquisition module 504, and a second error correction 504, where:

[0110] The first error correction module 501 is configured to correct the first target die based on the RAID5 error correction technology to obtain the first error correction data of the first target die;

[0111] The first acquisition module 502 is configured to acquire the first target read voltage of the first target die and the first target data read by using the first target read voltage;

[0112] The first position acquisition module 503 is configured to perform an exclusive OR operation on the target data read at preset positions on both sides of the first target read voltage of the first target die to obtain the expected error position data of the first target die;

[0113] The second position acquisition module 504 is configured to perform an exclusive OR operation on the first error correction data and the first target data to obtain first error position data, where the first error position data includes the error position of the first target die at the first target read voltage and the error position of the second target die;

[0114] The second error correction module 505 is configured to determine the true error position of the first target die according to the expected error position data and the first error position data, and perform error correction processing on the first target data according to the true error position of the first target die to obtain the correct data of the first target die.

[0115] Further, the first target read voltage of the first target die is the optimal read voltage of the first target die, and the first acquisition module includes:

[0116] The first acquisition sub-module is configured to acquire the quasi-optimal read voltage of the first target die;

[0117] The scanning module is configured to perform a read voltage scan around the quasi-optimal read voltage of the first target die according to a specified read voltage scan range to obtain first target scan data read under different read voltages.

[0118] The position acquisition sub-module is configured to perform an exclusive OR operation on each first target scan data read under different read voltages and the first error correction data respectively to obtain first error position scan data corresponding to each read voltage, and acquire the number of error positions in each first error position scan data.

[0119] The optimal read voltage selection sub-module is configured to select the read voltage corresponding to the first error position scan data with the least number of error positions as the optimal read voltage of the first target die.

[0120] Further, the flash memory error correction device according to an embodiment of the present invention further includes:

[0121] The second acquisition module is configured to acquire the second target read voltage of the second target die and the second target data read using the second target read voltage.

[0122] The first error correction module 501 is specifically configured to perform error correction on the first target die based on the second target data of the second target die and the RAID5 error correction technology, so that the obtained first error correction data includes the error positions at the optimal read voltage of the second target die.

[0123] Further, the second error correction module specifically includes:

[0124] The comparison sub-module is configured to compare the first error positions marked in the first error position data and the expected error positions marked in the expected error position data.

[0125] The true error position acquisition sub-module is configured to perform a flipping operation on the part of the first error positions in the first error position data that do not coincide with the expected error positions to eliminate the error positions of the second target die and obtain the true error position of the first target die.

[0126] A selection sub-module, configured to select some of the true error positions of the first target die as target bits to be flipped;

[0127] A correction and flip sub-module, configured to perform a flip operation on the data at the target bits to be flipped in the first target data to obtain the first original data of the first target die;

[0128] A decoding module, configured to decode the first original data of the first target die;

[0129] A judgment sub-module, configured to judge whether the decoding is successful. If the decoding is successful, it proceeds to the data output sub-module. If the decoding fails, it proceeds to the second selection sub-module;

[0130] A data output sub-module, configured to use the data obtained by successful decoding as the correct data of the first target die;

[0131] A second selection sub-module, which selects some of the unselected true error positions of the first target die as newly added target bits to be flipped, and returns to the correction and flip sub-module until the decoding is successful.

[0132] Furthermore, the first error correction module 501 of the embodiment of the present invention is further configured to, after obtaining the correct data of the first target die, perform error correction on the second target die based on the correct data of the first target die and the RAID5 error correction technology to obtain the correct data of the second target die.

[0133] For the apparatus embodiment, since it is basically similar to the method embodiment, the description is relatively simple. For the relevant parts, refer to the partial description of the method embodiment.

[0134] In addition, the embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, the steps of the above-mentioned method are implemented.

[0135] In this embodiment, if the modules / units integrated in the SSD device are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, to implement all or part of the processes in the above-described embodiment methods of the present invention, it can also be completed by a computer program instructing relevant hardware. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps of the above-described method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file, or some intermediate form, etc. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disc, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc. It should be noted that the content included in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electrical carrier signals and telecommunication signals.

[0136] In addition, an embodiment of the present invention further provides an SSD device, which includes a storage controller. The storage controller includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the steps of the method described above are implemented. For example Figure 2 the steps S1 to S5 shown. Alternatively, when the processor executes the computer program, the functions of each module / unit in the above-described embodiment of the flash memory error correction device are implemented. For example Figure 5 the first error correction module 501, the first acquisition module 502, the first position acquisition module 503, the second position acquisition module 504, and the second error correction module 505 shown.

[0137] The flash memory error correction method, device, medium and SSD device provided in this embodiment correct the first target die based on the RAID5 error correction technology to obtain the first error correction data of the first target die. By performing an exclusive OR operation on the target data read at the read voltages at preset positions on both sides of the first target read voltage of the first target die, the expected error position data of the first target die is obtained; by performing an exclusive OR operation on the first error correction data and the first target data, the first error position data is obtained. Since the first error correction data contains the error information of the second target die and the first target data contains the error information of the first target die, after performing the exclusive OR operation, the first error position data will simultaneously contain the error position of the first target die at the first target read voltage and the error position of the second target die at the second target read voltage; since the expected error position data contains the possible error positions of the first target die, the error position introduced by the second target die can be flipped according to the expected error position data and the first error position data, and then the true error position of the first target die can be obtained. Based on the true error position, error correction processing is performed on the first target data, and the correct data of the first target die can be obtained. According to the correct data of the first target die, the correct data of the second target die can be obtained through the RAID5 technology. Based on RAID5, the present invention can achieve the error correction ability of two target dies through software operations without changing the existing hardware design and coding / decoding algorithms, enhancing the adaptability and reliability of the flash memory.

[0138] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative effort.

[0139] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence, or the part that contributes to the prior art can be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0140] In addition, those skilled in the art will understand that although some embodiments herein include certain features included in other embodiments but not others, the combination of features of different embodiments means that it is within the scope of the present invention and forms different embodiments. For example, any one of the claimed embodiments can be used in any combination.

[0141] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A flash memory error correction method, characterized in that, For error correction when UNC errors occur simultaneously on the first target die and the second target die in the flash memory, the method includes: Performing error correction on the first target die based on the RAID5 error correction technology to obtain the first error correction data of the first target die; Obtaining the first target read voltage of the first target die and the first target data read using the first target read voltage; Performing an exclusive OR operation on the target data read at the read voltages at preset positions on both sides of the first target read voltage of the first target die to obtain the expected error position data of the first target die; Performing an exclusive OR operation on the first error correction data and the first target data to obtain the first error position data, where the first error position data includes the error position of the first target die at the first target read voltage and the error position of the second target die at the second target read voltage; Judging the true error position of the first target die according to the expected error position data and the first error position data, and performing error correction processing on the first target data according to the true error position of the first target die to obtain the correct data of the first target die; Wherein, The judging the true error position of the first target die according to the expected error position data and the first error position data includes: comparing the first error position marked in the first error position data with the expected error position marked in the expected error position data; flipping the part of the first error position data where the first error position does not coincide with the expected error position to eliminate the error position of the second target die and obtain the true error position of the first target die; The performing error correction processing on the first target data according to the true error position of the first target die includes: S51. Selecting some of the error positions from the true error positions of the first target die as the target bits to be flipped; S52. Performing a flip operation on the data at the target bits to be flipped in the first target data to obtain the first original data of the first target die; S53. Decoding the first original data of the first target die and judging whether the decoding is successful. If the decoding is successful, execute step S541; if the decoding fails, execute step S542; S541. Taking the data obtained by successful decoding as the correct data of the first target die; S542. Selecting some of the true error positions that have not been selected from the first target die as the new target bits to be flipped, and repeating the operations of steps S52 - S53 until the decoding is successful.

2. The method according to claim 1, wherein The first target read voltage of the first target die is the optimal read voltage of the first target die, and the obtaining the first target read voltage of the first target die includes: Obtaining the quasi-optimal read voltage of the first target die; Performing a read voltage scan around the quasi-optimal read voltage of the first target die within the specified read voltage scan range to obtain the first target scan data read under different read voltages; Perform an exclusive OR operation on each of the first target scan data read at different read voltages and the first error correction data to obtain first error position scan data corresponding to each read voltage, and obtain the number of error positions in each of the first error position scan data; Select the read voltage corresponding to the first error position scan data with the least number of error positions as the optimal read voltage of the first target die.

3. The method according to claim 2, wherein The error correction of the first target die based on the RAID5 error correction technology includes: Obtain the second target read voltage of the second target die and the second target data read using the second target read voltage; Perform error correction on the first target die based on the second target data of the second target die and the RAID5 error correction technology.

4. A flash memory error correction device for implementing the flash memory error correction method as described in claim 1, characterized in that, For error correction when UNC errors occur simultaneously on the first target die and the second target die in the flash memory, the device includes: A first error correction module for performing error correction on the first target die based on the RAID5 error correction technology to obtain the first error correction data of the first target die; A first acquisition module for acquiring the first target read voltage of the first target die and the first target data read using the first target read voltage; A first position acquisition module for performing an exclusive OR operation on the target data read at the read voltages at preset positions on both sides of the first target read voltage of the first target die to obtain the expected error position data of the first target die; A second position acquisition module for performing an exclusive OR operation on the first error correction data and the first target data to obtain first error position data, where the first error position data includes the error positions of the first target die at the first target read voltage and the error positions of the second target die at the second target read voltage; A second error correction module for judging the true error positions of the first target die according to the expected error position data and the first error position data, and performing error correction processing on the first target data according to the true error positions of the first target die to obtain the correct data of the first target die.

5. The device according to claim 4, characterized in that, The first target read voltage of the first target die is the optimal read voltage of the first target die, and the first acquisition module includes: A first acquisition sub-module for acquiring the quasi-optimal read voltage of the first target die; A scanning module for performing a read voltage scan within a specified read voltage scan range around the quasi-optimal read voltage of the first target die to obtain first target scan data read at different read voltages, A position acquisition sub-module for performing an exclusive OR operation on each of the first target scan data read at different read voltages and the first error correction data to obtain first error position scan data corresponding to each read voltage, and obtaining the number of error positions in each of the first error position scan data; An optimal read voltage selection sub-module for selecting the read voltage corresponding to the first error position scan data with the least number of error positions as the optimal read voltage of the first target die.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-3.

7. An SSD device, characterized in that, The SSD device includes a storage controller, and the storage controller includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, it implements the steps of the method according to any one of claims 1-3.

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