Driver chip, display panel, and driving method of display panel

Abstract

This application discloses a driver chip, a display panel, and a driving method for the display panel. The driver chip includes a fast discharge circuit, which comprises an input port for receiving a fast discharge signal, a judgment sub-circuit, a buffer sub-circuit, and an electronic shutdown circuit. The judgment sub-circuit, responding to the falling edge of the fast discharge signal, generates a judgment signal based on a target signal within a preset time. The buffer sub-circuit, responding to the judgment signal, generates a control signal and sends it to the electronic shutdown circuit. The electronic shutdown circuit, responding to the control signal, controls the driver chip to perform or not perform a power-off operation. By setting a preset time as a buffer phase, and adding judgment conditions during the buffer phase, it is further determined whether the fast discharge signal is valid, thereby determining whether to perform a power-off operation.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a driver chip, a display panel, and a driving method for the display panel. Background Technology

[0002] In-Plane Switching Panels (IPS Panels) have relatively stable total capacitance, resulting in good stability during driving, and are therefore widely used in the current display panel industry. However, IPS Panels discharge slowly when the driver IC is powered off, which can cause flickering or screen noise. By setting a fast discharge pin (XON pin) on the driver IC, the timing controller outputs a fast discharge signal (XON signal) to the driver IC. This allows all the output signals of the driving circuits to be short-circuited to the common voltage signal at the moment the driver IC is powered off, thus achieving rapid discharge of the panel. However, the presence of other interference on the XON pin can easily lead to malfunctions. Summary of the Invention

[0003] The embodiments of this application provide a driver chip, a display panel, and a driving method for the display panel, so as to at least solve the problem that malfunctions are likely to occur when there are other interferences on the XON pin.

[0004] In a first aspect, embodiments of this application provide a driver chip, including a fast discharge circuit. The fast discharge circuit includes: an access port configured to receive a fast discharge signal, wherein the fast discharge signal is used to indicate that the driver chip is powered off; a sensing sub-circuit connected to the access port and a power supply voltage, the sensing sub-circuit configured to sense the falling edge of the fast discharge signal; a buffer sub-circuit connected to the sensing sub-circuit, a judgment sub-circuit, and a power-off circuit, the buffer sub-circuit configured to, after the sensing sub-circuit senses the falling edge of the fast discharge signal, generate a control signal and send it to the power-off circuit within a preset time in response to a judgment signal output by the judgment sub-circuit; the judgment sub-circuit connected to the buffer sub-circuit configured to generate the judgment signal based on the state of a target signal within the preset time and send it to the buffer sub-circuit; and the power-off circuit connected to the buffer sub-circuit configured to control the driver chip to perform or not perform a power-off operation in response to the control signal.

[0005] In one embodiment, the judgment sub-circuit is further configured to: acquire a shared forward channel control input signal from a timing controller within the preset time period; wherein the shared forward channel control input signal is used to indicate the start of transmission of a frame image signal; generate a judgment signal based on the state of the shared forward channel control input signal, and send it to the buffer sub-circuit.

[0006] In one embodiment, the judgment sub-circuit is further configured to: generate a first judgment signal and send it to the buffer sub-circuit in response to the rising edge of the shared forward channel control input signal within the preset time period; the buffer sub-circuit is further configured to: generate a first control signal and send it to the power-off circuit in response to the first judgment signal within the preset time period; the power-off circuit is further configured to: control the driver chip not to perform a power-off operation in response to the first control signal.

[0007] In one embodiment, the judgment sub-circuit is further configured to: generate a second judgment signal and send it to the buffer sub-circuit in response to the continuous low level state of the shared forward channel control input signal within the preset time; the buffer sub-circuit is further configured to: generate a second control signal and send it to the power-off circuit in response to the second judgment signal within the preset time; the power-off circuit is further configured to: control the driver chip to perform a power-off operation in response to the second control signal.

[0008] In one embodiment, the driver chip includes: an output sub-circuit configured to output a rear-end free signal in response to the falling edge of the shared forward channel control input signal; wherein the rear-end free signal is used to indicate relevant information of the display rear-end free interval after a data transmission is completed.

[0009] In one embodiment, the fast discharge circuit further includes an electrostatic discharge (ESD) protection sub-circuit connected to the access port and the sensing sub-circuit, wherein the ESD protection sub-circuit is configured to perform electrostatic discharge on the driver chip.

[0010] In one embodiment, the power-off circuit includes: a latching unit configured to generate a latching signal in response to the control signal and send it to the power-off unit; and the power-off unit configured to perform or not perform a power-off operation in response to the latching signal.

[0011] In one embodiment, the driver chip is adapted to the USIT transmission protocol.

[0012] Secondly, embodiments of this application also provide a display panel, including the driver chip described in any of the above embodiments.

[0013] Thirdly, embodiments of this application also provide a driving method for a display panel, applied to a driver chip. The driver chip includes a fast discharge circuit, which includes an input port for receiving a fast discharge signal, a judgment sub-circuit, a buffer sub-circuit, and an electronics-disconnection circuit. The method includes: the judgment sub-circuit responding to the falling edge of the fast discharge signal to generate a judgment signal based on a target signal within a preset time; wherein the fast discharge signal is used to instruct the driver chip to power off; the buffer sub-circuit responding to the judgment signal to generate a control signal and send it to the electronics-disconnection circuit; and the electronics-disconnection circuit responding to the control signal to control the driver chip to perform or not perform a power-off operation.

[0014] In one embodiment, the judgment subcircuit responds to the falling edge of the fast discharge signal and generates a judgment signal based on the target signal within a preset time period, including: within the preset time period, the judgment subcircuit acquires a shared forward channel control input signal from the timing controller; wherein the shared forward channel control input signal is used to indicate the start of transmission of a frame image signal; and generates a judgment signal based on the state of the shared forward channel control input signal and sends it to the buffer subcircuit.

[0015] In one embodiment, generating a judgment signal based on the state of the shared forward channel control input signal and sending it to the buffer sub-circuit includes: generating a first judgment signal and sending it to the buffer sub-circuit in response to the rising edge of the shared forward channel control input signal within the preset time period.

[0016] In one embodiment, after generating a first judgment signal and sending it to the buffer sub-circuit, the method further includes: within the preset time period, the buffer sub-circuit generates a first control signal in response to the first judgment signal and sends it to the power-off circuit; the power-off circuit controls the driver chip not to perform a power-off operation in response to the first control signal.

[0017] In one embodiment, generating a judgment signal based on the state of the shared forward channel control input signal and sending it to the buffer sub-circuit includes: within the preset time period, the judgment sub-circuit responds to the continuous low-level state of the shared forward channel control input signal, generates a second judgment signal, and sends it to the buffer sub-circuit.

[0018] In one embodiment, after generating the second judgment signal and sending it to the buffer sub-circuit, the method further includes: within the preset time period, the buffer sub-circuit generates a second control signal in response to the second judgment signal and sends it to the power-off circuit; the power-off circuit controls the driver chip to perform a power-off operation in response to the second control signal.

[0019] The beneficial effects provided by the embodiments of this application include at least the following:

[0020] This application provides a driver chip, a display panel, and a driving method for the display panel. The driver chip includes a fast discharge circuit, which comprises an input port for receiving a fast discharge signal, a judgment sub-circuit, a buffer sub-circuit, and an electronic shutdown circuit. The judgment sub-circuit, responding to the falling edge of the fast discharge signal, generates a judgment signal based on a target signal within a preset time. The buffer sub-circuit, responding to the judgment signal, generates a control signal and sends it to the electronic shutdown circuit. The electronic shutdown circuit, responding to the control signal, controls the driver chip to perform or not perform a power-off operation. By setting a preset time as a buffer phase and adding a judgment condition during the buffer phase to further determine whether the fast discharge signal is valid, and thus determining whether to perform a power-off operation, this approach at least solves the problem of erroneous operation when there is interference on the XON pin, effectively improving the accuracy of fast power-off based on the XON signal.

[0021] Other beneficial effects of the embodiments of this application will be further explained in the following specific embodiments. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of a display panel provided in an optional embodiment of this application;

[0023] Figure 2 This is a signal timing diagram provided in an optional embodiment of this application;

[0024] Figure 3 This is a schematic diagram of the structure of a fast discharge circuit provided in an optional embodiment of this application;

[0025] Figure 4 This is an optional embodiment of the SFC signal timing diagram provided in this application;

[0026] Figure 5 This is yet another SFC signal timing diagram provided in an optional embodiment of this application;

[0027] Figure 6 This is a schematic flowchart of the display panel driving method provided in an optional embodiment of this application. Detailed Implementation

[0028] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. The described technical solutions are for illustrative purposes only and should not be construed as limiting the scope of protection of this application.

[0029] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0030] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0031] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0032] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the embodiments of this application.

[0033] The various embodiments provided in this application are similar, and features in different embodiments can be combined with each other.

[0034] The use of “configured to” in this application embodiment implies an open and inclusive language, which does not exclude the applicability to or configuration of devices to perform additional tasks or steps.

[0035] The order in which the following embodiments are described is not intended to limit the preferred order of the embodiments.

[0036] Reference Figure 1 As shown, this application embodiment provides a display panel 1000, which can be integrated into a display device, such as a television, smartphone, tablet computer, laptop computer, desktop computer, smart speaker, smartwatch, etc., but is not limited thereto. A display panel refers to a component used to display images, which may include many pixel units, each of which can emit light, display color, or reflect light to generate an image. The type of display panel can be set according to actual conditions; for example, the display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED) panel, a mini-LED display panel, or a micro-LED display panel. This application embodiment does not limit this. The pixel units included in the display panel can exist in a row and / or column form.

[0037] The display panel 1000 includes an effective display area AA and a peripheral area NA surrounding the effective display area AA. A circuit board 1100 is disposed in the peripheral area of ​​the display panel 1000 to provide clock signals to the circuitry inside the display panel 1000. The effective display area AA includes a plurality of sub-pixels 1500. For ease of explanation, the plurality of sub-pixels 1500 are described in this application as arranged in a matrix. In this case, sub-pixels arranged in a row along the first direction (X direction) are called a row of sub-pixels, and sub-pixels arranged in a row along the second direction (Y direction) are called a column of sub-pixels. A row of sub-pixels can be connected to a gate signal line GL and a light emission control signal line EM, and a column of sub-pixels can be connected to a data line DL. The X direction and the Y direction intersect perpendicularly.

[0038] Each subpixel 1500 may include a pixel driving circuit 1510 and a light-emitting device 1520. The light-emitting device 1520 may emit at least three primary colors, such as red (R), green (G), and blue (B) light.

[0039] The display panel 1000 also includes a gate driving circuit 1200, a data driving circuit 1300, and a light-emitting control circuit 1400 disposed in the NA area. The gate driving circuit 1200 includes multiple cascaded gate driving sub-circuits 1210, and the light-emitting control circuit 1400 includes multiple cascaded light-emitting control sub-circuits 1410. Each column of sub-pixels is connected to the data driving circuit 1300 via at least one DL (vertical line), each row of sub-pixels is connected to at least one gate driving sub-circuit 1210 via at least one GL (vertical line), and each row of sub-pixels is connected to at least one light-emitting control sub-circuit 1410 via at least one EM (electrical line). It should be noted that, depending on the specific circuit application, a row of sub-pixels can be connected to two or three or more gate driving sub-circuits via two or three or more GLs, and a row of sub-pixels can be connected to two or three or more light-emitting control sub-circuits via two or three or more EMs. Figure 1 The example described uses only one signal line and is not intended to limit the scope of this application.

[0040] In some embodiments, the light-emitting device 1520 can be an organic light-emitting diode (OLED), whose luminous efficiency is positively correlated with the magnitude (or current density) of the current flowing through it. That is, when the current flowing through the light-emitting device 1520 is small, its luminous efficiency is low; when the current flowing through it is large, its luminous efficiency is high. To improve the luminous efficiency of the light-emitting device 1520 when displaying low grayscale, the emission time of the light-emitting device 1520 can be modulated (i.e., pulse width modulation, or PWM) using the emission control signal EM to change the emission duty cycle of the light-emitting device 1520 within a frame, thereby shortening its emission time. By shortening the emission time of the light-emitting device 1520 and increasing the current flowing through it during emission, the luminous efficiency of the light-emitting device 1520 can be improved.

[0041] The pixel driving circuit 1510, gate driving circuit 1200, and data driving circuit 1300 in this embodiment can be implemented using any circuit in the art capable of performing the corresponding functions, and will not be described in detail here. It should be noted that the gate driving circuit 1200 and data driving circuit 1300 can both be integrated on the driver chip.

[0042] Because IPS panels discharge slowly when powered off, resulting in visible flickering or screen noise, a fast discharge input pin (XON pin) is added to the driver chip to receive the XON signal. (See reference...) Figure 2As shown, during the period without data signal input, all data output signals Y1 to Yn are connected to the common voltage signal Vcom. Under normal operating conditions, XON is at a high potential, and the Yn signal changes periodically. When power is cut off and data input is not received, a falling edge appears on the XON signal, and all data output signals are shorted to Vcom and connected to a preset low potential (usually VSS or GND). In general or experimental situations, when noise or interference occurs on the XON pin, the XON pin will perceive it as a falling edge, thus causing malfunction. For example, the phenomenon of the driver chip suddenly losing power during electrostatic discharge (ESD) evaluation, or during other evaluation tests. This malfunction is caused by the XON pin perceiving the driver chip's GND jitter or external signal noise as a falling edge.

[0043] To address the aforementioned problems, one embodiment of this application provides a driver chip, including a fast discharge circuit 100. (See also...) Figure 3 As shown, the fast discharge circuit 100 includes an access port 110, a sensing sub-circuit 120, a buffer sub-circuit 130, a judgment sub-circuit 140, and an electronic disconnection circuit 150.

[0044] The system includes: an access port 110 configured to receive a fast discharge signal (XON signal); a sensing sub-circuit 120 connected to the access port 110 and the power supply voltage VDD, configured to sense the falling edge of the fast discharge signal; a buffer sub-circuit 130 connected to the sensing sub-circuit 120, the judgment sub-circuit 140, and the power-off circuit 150, configured to generate a control signal and send it to the power-off circuit 150 within a preset time T in response to the judgment signal output by the judgment sub-circuit 140 after the sensing sub-circuit 120 senses the falling edge of the fast discharge signal; a judgment sub-circuit 140 connected to the buffer sub-circuit 130 configured to generate a judgment signal based on the state of the target signal within a preset time and send it to the buffer sub-circuit 130; and a power-off circuit 150 connected to the buffer sub-circuit 130 configured to control the driver chip to perform or not perform a power-off operation in response to the control signal.

[0045] By determining the response of the sub-circuit to the falling edge of the fast discharge signal, a judgment signal is generated based on the target signal within a preset time. The buffer sub-circuit, responding to the judgment signal, generates a control signal and sends it to the power-off circuit. The power-off circuit, in response to the control signal, controls the driver chip to perform or not perform a power-off operation. By setting a preset time as a buffer phase, and adding judgment conditions during the buffer phase to further determine whether it is a valid fast discharge signal, and thus determining whether to perform a power-off operation, this approach at least solves the problem of erroneous operation when there is other interference on the XON pin, effectively improving the accuracy of performing fast power-off based on the XON signal.

[0046] The preset time can be the transmission time of N frames of data, for example, 2 to 3 frames, or 2 to 5 frames. This application embodiment does not limit this.

[0047] In one embodiment, the judgment sub-circuit 140 is further configured to: acquire a shared forward channel control input (SFC) signal from the timing controller within a preset time period; generate a judgment signal based on the state of the shared forward channel control input signal and send it to the buffer sub-circuit; wherein the shared forward channel control input signal is used to indicate the start of transmission of a frame of image signal.

[0048] In one embodiment, the target signal can be an SFC signal, used to indicate the start of transmission of a frame of image signal. The SFC signal is generally used in the USIT protocol to mark the start of each frame of signal transmission.

[0049] USIT (Unified Standard Interface for TV) is a point-to-point (P2P) interface protocol primarily used for communication between timing controller chips and driver chips in televisions, or between system-on-a-chip (SoC) and driver chips. The driver chip in this embodiment can be adapted to the USIT protocol. The USIT protocol uses an embedded clock and 10B / 9B encoding, which helps improve transmission rates; currently, the USIT protocol can achieve transmission rates of 1.8-3.0 Gbps.

[0050] In terms of hardware connectivity, the timing controller chip or system-on-a-chip (SoC) communicates with the driver chip via differential signal lines. The USIT protocol specifies that a data packet consists of 10 bits. Before each line of display data is input, the line configuration is entered. Before the start of each frame's display signal input, the frame configuration and digital gamma setting are entered using the time of two lines of data. These configurations are the setting values ​​for certain functions of the driver chip by the timing controller chip or SoC, thereby controlling the driver chip to perform specific functions.

[0051] On the one hand, the USIT protocol enables a programmable panel charging compensation shift function (PPCC), which can control the output time of each channel of the driver chip to be delayed to a certain extent. On the other hand, because the USIT protocol has a high signal transmission rate, it requires fewer differential signal lines, allowing for better routing on the Xboard.

[0052] In one embodiment, the driver chip further includes an output sub-circuit configured to output a Vertical Back porch (VBP) signal in response to a falling edge of the shared forward channel control input signal; wherein the VBP signal is used to indicate relevant information about the display back porch interval after a data transmission is completed. (See also...) Figure 4 As shown, when the SFC signal is low, the driver chip will output the VBP signal. This period is the time used for electron gun retrace after the vertical synchronization cycle.

[0053] Reference Figure 5 As shown, a buffering function is added when the XON pin input falls. This buffering can be for a preset time, where the preset time T can be greater than one frame, for example, 1 frame, 2 frames, 3 frames, or 1.5 frames, 2.5 frames. This embodiment does not limit this. The buffering prevents immediate power-off upon the falling edge of the XON input, i.e., immediately shorting all data output signals to Vcom. Within the preset buffering time, it is determined whether a rising edge appears on the SFC signal, i.e., whether a new frame signal is input. If a rising edge appears, the buffer sub-circuit resets the XON signal, restoring it to a high potential, and does not short-circuit all data output signals to Vcom, thus preventing the power-off operation from being performed by the electronic circuit. For example... Figure 5 As shown, within the preset time T, the rising edge of SFC appeared, so no power-off operation was performed, and the driver chip continued to work normally.

[0054] If no rising edge of SFC occurs within the preset time T, the power-off operation will continue, meaning the XON signal will perform the power-off function normally.

[0055] In one embodiment, the judgment sub-circuit 140 is further configured to: generate a first judgment signal and send it to the buffer sub-circuit in response to the rising edge of the shared forward channel control input signal within a preset time; the buffer sub-circuit 130 is further configured to: generate a first control signal and send it to the power-off circuit 150 in response to the first judgment signal within a preset time; the power-off circuit 150 is further configured to: control the driver chip not to perform a power-off operation in response to the first control signal. (Continuing to refer to...) Figure 5 As shown, due to the ESD electrostatic effect, XON has a falling edge. Within the preset time T of the delay, SFC signal has a rising edge. Judgment sub-circuit 140 generates a first judgment signal and sends it to buffer sub-circuit 130. Buffer sub-circuit 130 sends a first control signal to the power-off circuit 150. Then, in response to the first control signal, the power-off circuit 150 controls the driver chip not to perform a power-off operation, and the driver chip still works normally.

[0056] In one embodiment, the judgment sub-circuit 140 is further configured to: generate a second judgment signal and send it to the buffer sub-circuit 130 in response to a continuous low-level state of the shared forward channel control input signal within a preset time; the buffer sub-circuit 130 is further configured to: generate a second control signal and send it to the power-off circuit 150 in response to the second judgment signal within a preset time; the power-off circuit 150 is further configured to: control the driver chip to perform a power-off operation in response to the second control signal.

[0057] When XON has a falling edge, SFC signal also has a falling edge after a period of time, and no rising edge of SFC appears within the preset time T. At this time, it can be determined that the XON signal is not a false alarm, and the buffer sub-circuit 130 will control the power-off circuit 150 to perform a power-off operation.

[0058] In one embodiment, the fast discharge circuit further includes an electrostatic discharge (ESD) protection sub-circuit 160 connected to the access port 110 and the sensing sub-circuit 120, wherein the ESD protection sub-circuit 160 is configured to perform ESD discharge on the driver chip.

[0059] In one embodiment, the electrostatic discharge protection sub-circuit 160 includes: a diode, including a positive terminal connected to a preset low potential and a negative terminal connected to the access port 110 and the sensing sub-circuit 120; and a transistor, including a control terminal connected to a preset low potential, a first terminal connected to a preset low potential, and a second terminal connected to the access port 110 and the sensing sub-circuit 120.

[0060] It should be noted that the transistors used in all embodiments of this application may be thin film transistors (TFTs), metal oscillating transistors (MOSs), or other devices with the same characteristics. This application does not limit the types of transistors used.

[0061] For example, the transistor can be a TFT. TFTs can be fabricated using a-Si technology, oxide semiconductor technology, low-temperature polysilicon (LTPS) technology, or high-temperature polysilicon (HTPS) technology. The embodiments of this application do not limit this.

[0062] The embodiments of this application do not limit the type of transistor. The transistor can be an N-type transistor, a P-type transistor, an enhancement-mode transistor, or a depletion-mode transistor. In the embodiments of this application, all transistors are assumed to be P-type transistors for illustrative purposes. A P-type transistor is turned on under a low-level voltage signal and turned off under a high-level voltage signal; that is, the operating voltage of a P-type transistor is a low-level voltage, and the turn-off voltage is a high-level voltage.

[0063] In the embodiments of this application, the gate of the transistor is the control electrode. To distinguish the two electrodes of the transistor other than the gate, one electrode is directly described as the first electrode, and the other as the second electrode. In this case, the first electrode of the transistor can be either the source or the drain, and the second electrode can be either the source or the drain. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable.

[0064] In one embodiment, the power-off circuit 150 includes: a latch unit 151 configured to generate a latch signal in response to a control signal and send it to a power-off unit 152; and a power-off unit 152 configured to perform or not perform a power-off operation in response to the latch signal.

[0065] This application also provides a display panel, including the driver chip described in any of the above embodiments, and the contents already stated will not be repeated here.

[0066] This application also provides a driving method for a display panel, applied to a driver chip. The driver chip includes a fast discharge circuit, which comprises an input port for receiving a fast discharge signal, a judgment sub-circuit, a buffer sub-circuit, and an electron-disconnecting circuit. This driving method can be applied to the driver chip described in any of the foregoing embodiments; details already described will not be repeated here. (Refer to...) Figure 6 As shown, the method includes:

[0067] Step S501: The sub-circuit responds to the falling edge of the fast discharge signal and generates a judgment signal based on the target signal within a preset time.

[0068] In step S502, the buffer sub-circuit responds to the judgment signal and generates a control signal to be sent to the disconnection circuit; and;

[0069] In step S503, the electronic circuit responds to the control signal to control the driver chip to perform or not perform a power-off operation.

[0070] In one embodiment, the judgment sub-circuit responds to the falling edge of the fast discharge signal and generates a judgment signal based on the target signal within a preset time period, including: within the preset time period, the judgment sub-circuit acquires a shared forward channel control input signal from the timing controller; wherein the shared forward channel control input signal is used to indicate the start of transmission of a frame image signal; and generates a judgment signal based on the state of the shared forward channel control input signal and sends it to the buffer sub-circuit.

[0071] In one embodiment, generating a judgment signal based on the state of the shared forward channel control input signal and sending it to the buffer sub-circuit includes: generating a first judgment signal and sending it to the buffer sub-circuit in response to the rising edge of the shared forward channel control input signal within a preset time.

[0072] In one embodiment, after generating a first judgment signal and sending it to the buffer sub-circuit, the method further includes: within a preset time period, the buffer sub-circuit generates a first control signal in response to the first judgment signal and sends it to the power-off circuit; the power-off circuit controls the driver chip not to perform a power-off operation in response to the first control signal.

[0073] In one embodiment, generating a judgment signal based on the state of the shared forward channel control input signal and sending it to the buffer sub-circuit includes: within a preset time, the judgment sub-circuit responds to the continuous low level state of the shared forward channel control input signal, generates a second judgment signal and sends it to the buffer sub-circuit.

[0074] In one embodiment, after generating a second judgment signal and sending it to the buffer sub-circuit, the method further includes: within a preset time period, the buffer sub-circuit generates a second control signal in response to the second judgment signal and sends it to the power-off circuit; the power-off circuit controls the driver chip to perform a power-off operation in response to the second control signal.

[0075] Due to the ESD electrostatic effect, XON experiences a falling edge. Within the preset delay time T, the SFC signal experiences a rising edge. The judgment sub-circuit generates a first judgment signal and sends it to the buffer sub-circuit. The buffer sub-circuit sends a first control signal to the power-off circuit. Then, the power-off circuit responds to the first control signal to control the driver chip not to perform a power-off operation, and the driver chip continues to work normally.

[0076] When XON shows a falling edge, the SFC signal also shows a falling edge after a period of time, and no rising edge of SFC appears within the preset time T. At this time, it can be determined that the XON signal is not a false alarm, and the buffer sub-circuit will control the power-off circuit to perform a power-off operation.

[0077] By determining the response of the sub-circuit to the falling edge of the fast discharge signal, a judgment signal is generated based on the target signal within a preset time. The buffer sub-circuit, responding to the judgment signal, generates a control signal and sends it to the power-off circuit. The power-off circuit, in response to the control signal, controls the driver chip to perform or not perform a power-off operation. By setting a preset time as a buffer phase, and adding judgment conditions during the buffer phase to further determine whether it is a valid fast discharge signal, and thus determining whether to perform a power-off operation, this approach at least solves the problem of erroneous operation when there is other interference on the XON pin, effectively improving the accuracy of performing fast power-off based on the XON signal.

[0078] This application also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the above-described display panel driving method. This non-transitory computer-readable storage medium possesses all the beneficial effects of the above-described display panel driving method, which will not be elaborated upon further herein.

[0079] According to a fourth aspect of this application, embodiments of this application also provide an electronic device, including: a memory and a processor, wherein a computer program is stored in the memory; the processor is configured to execute the computer program in the memory to implement the steps of the above-described display panel driving method. This electronic device possesses all the beneficial effects of the above-described display panel driving method, which will not be elaborated upon further herein.

[0080] Computer-readable storage media can be, for example, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof, without particular limitation herein. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0081] In some embodiments of this application, a computer-readable storage medium may be any tangible medium that contains or stores a program that may be used or combined with an instruction execution system, apparatus, or device.

[0082] The aforementioned computer-readable storage medium may be included in the aforementioned electronic device or may exist independently without being assembled into the electronic device.

[0083] Computer program code for performing operations of some embodiments of this application can be written in one or more programming languages ​​or a combination thereof. These programming languages ​​include object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0084] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function.

[0085] It should also be noted that in some alternative implementations, the functions marked in the box may occur in a different order than those marked in the attached figures.

[0086] This application uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

[0087] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A driver chip, characterized in that, The driver chip includes a fast discharge circuit, which includes: The access port is configured to receive a fast discharge signal; wherein the fast discharge signal is used to indicate that the driver chip is powered off. A sensing sub-circuit is connected to the access port and the power supply voltage, and the sensing sub-circuit is configured to sense the falling edge of the fast discharge signal; A buffer sub-circuit is connected to the sensing sub-circuit, the judgment sub-circuit, and the electron disconnection circuit. The buffer sub-circuit is configured to generate a control signal and send it to the electron disconnection circuit within a preset time after the sensing sub-circuit senses the falling edge of the fast discharge signal and responds to the judgment signal output by the judgment sub-circuit. The judgment sub-circuit, connected to the buffer sub-circuit, is configured to generate the judgment signal based on the state of the shared forward channel control input signal from the timing controller within a preset time period, and send it to the buffer sub-circuit; and The power-off circuit is connected to the buffer sub-circuit and is configured to control the driver chip to perform or not perform a power-off operation in response to the control signal. The shared forward channel control input signal is used to indicate the start of transmission of a frame of image signal.

2. The driver chip according to claim 1, characterized in that, The judgment sub-circuit is further configured as follows: Within the preset time period, in response to the rising edge of the shared forward channel control input signal, a first judgment signal is generated and sent to the buffer sub-circuit; The buffer sub-circuit is further configured to: Within the preset time period, a first control signal is generated in response to the first judgment signal and sent to the electronic circuit. The electronic circuit is also configured as follows: In response to the first control signal, the driver chip is controlled not to perform a power-off operation.

3. The driver chip according to claim 1, characterized in that, The judgment sub-circuit is further configured as follows: Within the preset time period, in response to the continuous low level state of the shared forward channel control input signal, a second judgment signal is generated and sent to the buffer sub-circuit; The buffer sub-circuit is further configured to: Within the preset time period, a second control signal is generated in response to the second judgment signal and sent to the electronic circuit. The electronic circuit is also configured as follows: In response to the second control signal, the driver chip is controlled to perform a power-off operation.

4. The driver chip according to claim 3, characterized in that, The driver chip includes: The output sub-circuit is configured to output a rear-end free signal in response to the falling edge of the shared forward channel control input signal; wherein the rear-end free signal is used to indicate relevant information of the display rear-end free interval after a frame of data transmission is completed.

5. The driver chip according to claim 1, characterized in that, The fast discharge circuit also includes: An electrostatic discharge (ESD) protection subcircuit is connected to the access port and the sensing subcircuit, and the ESD protection subcircuit is configured to perform electrostatic discharge on the driver chip.

6. The driver chip according to claim 1, characterized in that, The electronic circuit includes: A latching unit is configured to generate a latching signal in response to the control signal and send it to a power-off unit; and The power-off unit is configured to perform or not perform a power-off operation in response to the latch signal.

7. The driver chip according to any one of claims 1 to 6, characterized in that, The driver chip is compatible with the USIT transmission protocol.

8. A display panel, characterized in that, Includes the driver chip as described in any one of claims 1 to 7.

9. A driving method for a display panel, characterized in that, Applied to a driver chip, the driver chip includes a fast discharge circuit, the fast discharge circuit includes an input port for receiving a fast discharge signal, a judgment sub-circuit, a buffer sub-circuit, and an electron-disconnecting circuit, the method includes: The judgment sub-circuit responds to the falling edge of the fast discharge signal and generates a judgment signal within a preset time according to the shared forward channel control input signal from the timing controller; wherein, the fast discharge signal is used to indicate that the driver chip is powered off; The buffer sub-circuit responds to the judgment signal, generates a control signal, and sends it to the electronic disconnection circuit; and The power-off circuit responds to the control signal to control the driver chip to perform or not perform a power-off operation; The shared forward channel control input signal is used to indicate the start of transmission of a frame of image signal.

10. The driving method for a display panel according to claim 9, characterized in that, The step of generating a judgment signal based on the shared forward channel control input signal within a preset time period includes: Within the preset time period, in response to the rising edge of the shared forward channel control input signal, a first judgment signal is generated and sent to the buffer sub-circuit.

11. The driving method for a display panel according to claim 10, characterized in that, After generating the first judgment signal and sending it to the buffer sub-circuit, the method further includes: Within the preset time period, the buffer sub-circuit generates a first control signal in response to the first judgment signal and sends it to the electronic disconnection circuit; The power-off circuit responds to the first control signal by controlling the driver chip not to perform a power-off operation.

12. The driving method for a display panel according to claim 9, characterized in that, The step of generating a judgment signal based on the shared forward channel control input signal within a preset time period includes: Within the preset time period, the judgment sub-circuit responds to the continuous low level state of the shared forward channel control input signal, generates a second judgment signal, and sends it to the buffer sub-circuit.

13. The driving method for a display panel according to claim 12, characterized in that, After generating the second judgment signal and sending it to the buffer sub-circuit, the method further includes: Within the preset time period, the buffer sub-circuit generates a second control signal in response to the second judgment signal and sends it to the electronic disconnection circuit; The power-off circuit responds to the second control signal by controlling the driver chip to perform a power-off operation.

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