Implementation method of Lag fast switching controller

Abstract

The invention discloses an implementation method of a Lag fast switching controller, and belongs to the technical field of communication. The method comprises the following steps: initializing a local switching node, and configuring group member information of a local switching node Lag group by a software protocol stack; the method comprises the following steps of: initializing a system, generating a data structure object, and initializing a memberRrCheck; reading member information of the Lag group; mapping a link state of a member group port; each clock period can only be judged by one of the eight clock periods; updating member information of the Lag group, and selecting exits from the updated effective members of the Lag group; triggering interruption to inform the CPU, and adding the port into the Lag group again by the software; and real-time rapid switching of the controller is realized. According to the method, a port link state Lag intra-group mapping mechanism is utilized, the configured LAG group member information is updated, a content switching mechanism is updated, rapid and successful switching can be achieved when Lag is subjected to link switching, the number of lost frames caused by switching is reduced, and meanwhile the method is easy to implement, simple in logic and applicable to multi-scene application.

Description

Technical Field

[0001] The invention belongs to the field of communication technology, and in particular relates to a method for implementing a Lag fast switching controller. Background Art

[0002] In Ethernet switching communication technology, link aggregation technology is used to aggregate multiple physical links into a large-bandwidth logical link to transmit service traffic. One feature of this technology is link protection switching. Specifically, when a port in a group is linkdown, it must be removed from the group immediately to prevent service traffic from flowing into the invalid port and causing packet loss.

[0003] Traditional Lag switching technology is implemented by upper-layer protocol software. Two switching devices connected by an aggregated link exchange LAG protocol messages to determine whether to update. Since it is processed by software, the effectiveness is not high. In the era of networks that are not very sensitive to packet loss, this packet loss can be tolerated.

[0004] With the advent of 5G applications and TSN technology, networks are becoming increasingly sensitive to packet loss; in an era of networks that are very sensitive to packet loss, this type of packet loss is intolerable.

[0005] Therefore, how to achieve fast reversal within a clock cycle and achieve ultra-low frame loss during switching when the interface is an optical module is a technical problem that the present invention aims to solve. Summary of the invention

[0006] The object of the present invention is to provide a method for implementing a Lag fast switching controller to solve the problems raised in the above background technology.

[0007] The object of the present invention is achieved by: a method for implementing a Lag fast switching controller, characterized in that the method comprises the following steps:

[0008] Step S1: Initialize the local switching node, and configure the group member information of the local switching node Lag group with the software protocol stack;

[0009] Step S2: After the system is powered on, it is initialized, a data structure object is generated, and memberRrCheck is initialized;

[0010] Step S3: Read Lag group member information;

[0011] Step S4: Map the link status of the member group port, a high level indicates linkup, and a low level indicates linkdown;

[0012] Step S5: determine the update condition, each clock cycle can only make one of the eight to make a determination;

[0013] Step S6: Update the Lag group member information, and select an exit from the updated Lag group valid members;

[0014] Step S7: When the linkdown port is linked up again, an interrupt is triggered to inform the CPU, and the software adds the port to the Lag group again;

[0015] Step S8: Repeat steps S1 to S7 to achieve real-time rapid switching of the controller.

[0016] Preferably, configuring the group member information of the local switching node Lag group in step S1 is to design a Lag group member status information table in the local switching node, and the table is a register array, not SRAM;

[0017] The lag group member status information table is used to view all lag group status information within one clock cycle. The data structure of each lag group status information is {memNum, memIndex0,…, memIndex7}; memNum is the number of valid members in the lag, and memIndexN represents the ID number of the Nth member, which corresponds to the physical port number in the specific design.

[0018] Preferably, in step S2, a data structure object is generated to initialize memberRrCheck, specifically:

[0019] Design a group of status registers portStatus, each bit of which corresponds to the link status of the real physical port; design the Lag member status link status register memberLinkStatus; use the Lag group member Index to realize the conversion from portStatus to memberLinkStatus;

[0020] Design an intra-group shift register MemberRrCheck for the Lag group, which is a circular shift register.

[0021] Preferably, in step S3, the Lag group member information is read in, and the Lag group member information includes the number of valid members of each Lag group and the ID of each valid member of the Lag group.

[0022] Preferably, the mapping of the member group port link status in step S4 is specifically:

[0023] During system operation, the port link status is latched by the status register and output to the fast switching control circuit; at the entrance of the fast switching circuit, the port status is mapped to each lag group through the mapping circuit between the port and the lag group member;

[0024] For a single lag group, monitor the connection status of the member ports in the group;

[0025] After the system power-on reset is released, the shift register in the lag group begins to operate; according to the shift indication of this circuit, the connection status of a member in the group is observed each time.

[0026] Preferably, in step S5, the update condition is determined, and only one of the eight conditions can be determined in each clock cycle, specifically:

[0027] When a port in the group is observed to be linkdown at a certain moment, the switching operation of the lag group is triggered: the number of lag group members is reduced by 1, and the member with linkdown is deleted from the group;

[0028] Specifically, all members after this member are moved forward one position in sequence.

[0029] Preferably, the controller is a reusable unit, which, after determining the number of Lag groups, repeatedly instantiates multiple divisions to achieve a switching time of no more than 8 clock cycles, regardless of the number of ports.

[0030] Compared with the prior art, the present invention has the following improvements and advantages:

[0031] By utilizing the port link status Lag group mapping mechanism, the configured LAG group member information is updated, and the content switching mechanism is updated, so that when Lag link switching occurs, it can be quickly switched successfully, reducing the number of frame losses caused by switching. At the same time, the method of the present invention is easy to implement and has simple logic; it can be applied in multiple scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 The figure is an overall flow chart of the method of the present invention.

[0033] Figure 2 Infographic of Lag group members.

[0034] Figure 3 Port mapping of members in the Lag group

[0035] Figure 4 Figure 8 is a diagram of an 8-bit shift register. DETAILED DESCRIPTION

[0036] The present invention is further summarized below with reference to the accompanying drawings.

[0037] like Figure 1 As shown, a method for implementing a Lag fast switching controller includes the following steps:

[0038] Step S1: Initialize the local switching node, and configure the group member information of the local switching node Lag group with the software protocol stack;

[0039] Configure the group member information of the local switching node Lag group, specifically:

[0040] like Figure 2 As shown, the local switching node designs a set of Lag group member status information tables, which are register arrays rather than SRAMs. The advantage of this design is that all Lag group status information can be viewed within one clock cycle of the design. The data structure of each Lag group status information is {memNum, memIndex0, …, memIndex7}. memNum is the number of valid members in the Lag, and memIndexN represents the ID number of the Nth member, which corresponds to the physical port number in the specific design.

[0041] The designed data structure is as follows:

[0042] typedefstruct{uint32_tmemberNum;

[0043] uint32_tmember0Idx;

[0044] uint32_tmember1Idx;

[0045] uint32_tmember2Idx;

[0046] uint32_tmember3Idx;

[0047] uint32_tmember4Idx;

[0048] uint32_tmember5Idx;

[0049] uint32_tmember6Idx;

[0050] uint32_tmember7Idx;

[0051] uint8_tmember0UpEn,

[0052] uint8_tmember1UpEn,

[0053] uint8_tmember2UpEn,

[0054] uint8_tmember3UpEn,

[0055] uint8_tmember4UpEn,

[0056] uint8_tmember5UpEn,

[0057] uint8_tmember6UpEn,

[0058] uint8_tmember7UpEn,

[0059] uint8_tmemberLinkStatus[8];}MemberInfo;

[0060] Among them, MemberInfo is the control and status variable of the fast switching device, memberNum is the number of valid Lag members in the current Lag group; member0Idx~member7Idx are the port numbers corresponding to the members, member0UpEn~member7UpEn indicate that the member status change leads to the update of Lag enable; memberLinkStatus[8] indicates the status of each member port, 1 is linkup, 0 is linkdown;

[0061] Design a group of status registers portStatus, each bit of which corresponds to the link status of the real physical port; design the Lag member status link status register memberLinkStatus; use the Lag group member Index to realize the conversion from portStatus to memberLinkStatus;

[0062] typedefstruct{

[0063] MemberInfo;

[0064] uint32_tdsMemLagGrpRdData;

[0065] uint32_t linkStatus;}input

[0066] In this data structure, dsMemLagGrpRdData is the Lag group member information, and the data structure is:

[0067] {memNum,memIndex0,…,memIndex7};

[0068] linkStatus is portStatus[N-1:0] mentioned in S2;

[0069] typedefstruct{uint8_tupDataGrp[7];

[0070] uint8_tupEn;}output

[0071] In this data structure, upDataGrp is the update content, that is, {memNum, memIndex0,…, memIndex7}; upEn indicates that the current Lag needs to be updated.

[0072] Step S2: the system is initialized after powering on, wherein the initialization includes releasing reset, issuing design configuration; generating a data structure object, and initializing memberRrCheck;

[0073] like Figure 3 As shown, a data structure object is generated and memberRrCheck is initialized, specifically:

[0074] like Figure 4 As shown, the internal shift register MemberRrCheck of the Lag group is designed, which is a circular shift register. The initial value of the register is 8'b00000001. The high-level bit indicates that the link status of the index corresponding to the member needs to be checked. After the system is initialized, the register is circularly shifted left.

[0075] MemberInfomem;

[0076] inputin;

[0077] outputout;

[0078] uint_8memberRrCheck;

[0079] memberRrCheck=8'b0000_0001.

[0080] Step S3: Read Lag group member information;

[0081] Lag group member information includes the number of valid members in each Lag group and the ID of each valid member in the Lag group;

[0082] The specific design is:

[0083] mem.memberNum=in.dsMemLagGrpRdData[`NUM_RANGE];

[0084] mem.member0Idx=in.dsMemLagGrpRdData[`MEM0_IDX_RANGE];

[0085] mem.member1Idx=in.dsMemLagGrpRdData[`MEM1_IDX_RANGE];

[0086] mem.member2Idx=in.dsMemLagGrpRdData[`MEM2_IDX_RANGE];

[0087] mem.member3Idx=in.dsMemLagGrpRdData[`MEM3_IDX_RANGE];

[0088] mem.member4Idx=in.dsMemLagGrpRdData[`MEM4_IDX_RANGE];

[0089] mem.member5Idx=in.dsMemLagGrpRdData[`MEM5_IDX_RANGE];

[0090] mem.member6Idx=in.dsMemLagGrpRdData[`MEM6_IDX_RANGE];

[0091] mem.member7Idx=in.dsMemLagGrpRdData[`MEM7_IDX_RANGE];

[0092] The information in square brackets is the macro definition of the location of this information in this entry;

[0093] Step S4: Map the link status of the member group port, a high level indicates linkup, and a low level indicates linkdown;

[0094] mem.memberLInkStatus[0]=in.linkStatus[mem.member0Idx];

[0095] mem.memberLInkStatus[1]=in.linkStatus[mem.member1Idx];

[0096] mem.memberLInkStatus[2]=in.linkStatus[mem.member2Idx];

[0097] mem.memberLInkStatus[3]=in.linkStatus[mem.member3Idx];

[0098] mem.memberLInkStatus[4]=in.linkStatus[mem.member4Idx];

[0099] mem.memberLInkStatus[5]=in.linkStatus[mem.member5Idx];

[0100] mem.memberLInkStatus[6]=in.linkStatus[mem.member6Idx];

[0101] mem.memberLInkStatus[7]=in.linkStatus[mem.member7Idx];

[0102] Maps the member group port link status, specifically:

[0103] During system operation, the port link status is latched by the status register and output to the fast switching control circuit; at the entrance of the fast switching circuit, the port status is mapped to each lag group through the mapping circuit between the port and the lag group member;

[0104] For a single lag group, monitor the connection status of the member ports in the group;

[0105] After the system power-on reset is released, the shift register in the lag group begins to operate; according to the shift indication of this circuit, the connection status of a member in the group is observed each time.

[0106] Step S5: determine the update condition, each clock cycle can only make one of the eight to make a determination;

[0107] mem.member0UpEn=~mem.memberLinkStatus[0]&(0 <mem.memberNum)&memberRrCheck[0];

[0108] mem.member1UpEn=~mem.memberLinkStatus[1]&(1 <mem.memberNum)&memberRrCheck[1];

[0109] mem.member2UpEn=~mem.memberLinkStatus[2]&(2 <mem.memberNum)&memberRrCheck[2];

[0110] mem.member3UpEn=~mem.memberLinkStatus[3]&(3 <mem.memberNum)&memberRrCheck[3];

[0111] mem.member4UpEn=~mem.memberLinkStatus[4]&(4 <mem.memberNum)&memberRrCheck[4];

[0112] mem.member5UpEn=~mem.memberLinkStatus[5]&(5 <mem.memberNum)&memberRrCheck[5];

[0113] mem.member6UpEn=~mem.memberLinkStatus[6]&(6 <mem.memberNum)&memberRrCheck[6];

[0114] mem.member7UpEn=~mem.memberLinkStatus[7]&(7 <mem.memberNum)&memberRrCheck[7];

[0115] When a port in a group is observed to be linkdown at a certain moment, the switching operation of this lag is triggered: the number of lag members is reduced by 1, and the linkdown member is deleted from the group;

[0116] Exhaustively list the updated contents brought by member changes, a total of 8 cases; put the linkdown members at the end of info;

[0117] The data structure is:

[0118] mem.member0UpData={mem.memberNum-1,mem.member1Idx,…,mem.member7Idx,mem.member0Idx};

[0119] mem.member1UpData={mem.memberNum-1,mem.member0Idx,mem.member2Idx,…,mem.member7Idx,mem.member1Idx};

[0120] mem.member2UpData={mem.memberNum-1,mem.member0Idx,mem.membe r1Idx,mem.member3Idx,…,mem.member7Idx,mem.member2Idx};

[0121] mem.member3UpData={mem.memberNum-1,mem.member0Idx,…,mem.member2Idx,mem.member4Idx,…,mem.member7Idx,mem.member3Idx};

[0122] mem.member4UpData={mem.memberNum-1,mem.member0Idx,…,mem.member3Idx,mem.member5Idx,…,mem.member7Idx,mem.member4Idx};

[0123] mem.member5UpData={mem.memberNum-1,mem.member0Idx,…,mem.member4Idx,mem.member6Idx,…,mem.member7Idx,mem.member5Idx};

[0124] mem.member6UpData={mem.memberNum-1,mem.member0Idx,…,mem.member5Idx,mem.member7Idx,mem.member6Idx};

[0125] mem.member7UpData={mem.memberNum-1,mem.member0Idx,…,mem.member6Idx,mem.member7Idx};

[0126] The specific operation is to move all members after this member forward one position in sequence.

[0127] Step S6: Update the Lag group member information, and select an exit from the updated Lag group valid members;

[0128] Step S7: When the linkdown port is linked up again, an interrupt is triggered to inform the CPU, and the software adds the port to the Lag group again;

[0129] Step S8: Repeat steps S1 to S7 to achieve real-time rapid switching of the controller.

[0130] The data structure is: memberRrCheck={memberRrCheck[6:0], memberRrCheck[7]}.

[0131] The controller is a reusable unit. After determining the number of lag groups, it can repeatedly instantiate multiple divisions to achieve a switching time of no more than 8 clock cycles, regardless of the number of ports.

[0132] The above description is only an embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A method for implementing a Lag fast switching controller, characterized in that: The method comprises the following steps: Step S1: Initialize the local switching node, and configure the group member information of the local switching node Lag group with the software protocol stack; Step S2: After the system is powered on, it is initialized, a data structure object is generated, and memberRrCheck is initialized; Step S3: Read Lag group member information; Step S4: Map the link status of the member group port, a high level indicates link up, and a low level indicates link down; Step S5: determine the update condition, each clock cycle can only make one of the eight to make a determination; Step S6: Update the Lag group member information, and select an exit from the updated Lag group valid members; Step S7: When the port that was linked down is linked up again, an interrupt is triggered to inform the CPU, and the software adds the port to the Lag group again; Step S8: Repeat steps S1 to S7 to achieve real-time rapid switching of the controller.

2. The method for implementing a Lag fast switching controller according to claim 1, characterized in that: The configuration of the group member information of the local switching node Lag group in step S1 is to design a Lag group member status information table in the local switching node, the table being a register array, not SRAM; The lag group member status information table is used to view all lag group status information within one clock cycle. The data structure of each lag group status information is {memNum, memIndex0,…, memIndex7}; memNum is the number of valid members in the lag, and memIndexN represents the ID number of the Nth member, which corresponds to the physical port number in the specific design.

3. The method for implementing a Lag fast switching controller according to claim 1, characterized in that: In step S2, a data structure object is generated to initialize memberRrCheck, specifically: Design a group of status registers portStatus, each bit of which corresponds to the link status of the real physical port; design the Lag member status link status register memberLinkStatus; use the Lag group member Index to realize the conversion from portStatus to memberLinkStatus; Design an intra-group shift register MemberRrCheck for the Lag group, which is a circular shift register.

4. The method for implementing a Lag fast switching controller according to claim 1, characterized in that: In step S3, the Lag group member information is read in, and the Lag group member information includes the number of valid members of each Lag group and the ID of each valid member of the Lag group.

5. The method for implementing a Lag fast switching controller according to claim 1, characterized in that: The mapping of the member group port link status in step S4 is specifically as follows: During system operation, the port link status is latched by the status register and output to the fast switching control circuit; at the entrance of the fast switching circuit, the port status is mapped to each lag group through the mapping circuit between the port and the lag group member; For a single lag group, monitor the connection status of the member ports in the group; After the system power-on reset is released, the shift register in the lag group begins to operate; according to the shift indication of this circuit, the connection status of a member in the group is observed each time.

6. The method for implementing a Lag fast switching controller according to claim 1, characterized in that: In step S5, the update condition is determined, and each clock cycle can only make one of the eight conditions to be determined, specifically: When a port in the group is observed to be down at a certain moment, the switching operation of the lag group is triggered: the number of lag group members is reduced by 1, and the member with link down is deleted from the group; Specifically, all members after this member are moved forward one position in sequence.

7. The method for implementing a Lag fast switching controller according to claim 1, characterized in that: The controller is a reusable unit. After determining the number of Lag groups, it repeatedly instantiates multiple divisions to achieve a switching time of no more than 8 clock cycles, which is not limited to the number of ports.

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