Vertical gallium oxide heterogeneous super junction Schottky diode and preparation method thereof

Abstract

The invention discloses a vertical gallium oxide heterogeneous super junction Schottky diode and a preparation method thereof, and belongs to the field of semiconductors, the diode comprises an N + type gallium oxide substrate, an N type gallium oxide drift region, a regulation and control layer, an ohmic contact layer, a field oxide layer, a Schottky contact layer, a positive electrode, a negative electrode and a passivation protection layer; wherein a plurality of grooves are etched in the N-type gallium oxide drift region; the plurality of grooves are distributed in a device source region and a terminal region; each groove is filled with a dielectric layer; the regulation and control layer comprises a P-type charge balance regulation and control layer and a P +-type surface electric field regulation and control layer; the P-type charge balance regulation and control layer covers the side wall of each groove; the P + type surface electric field regulation and control layer comprises two parts, one part is arranged on the top layer of the side wall of the device source region groove, and the other part is arranged on the surface layer of the N type gallium oxide drift region of the device terminal region. According to the design, the gallium oxide-based vertical super junction device is realized by utilizing etching and heterogeneous backfill technologies.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a gallium oxide heterojunction superjunction Schottky diode and a preparation method thereof. Background Art

[0002] Gallium oxide (Ga2O3) is a very promising wide bandgap semiconductor material for high voltage and high power applications due to its wide bandgap (about 4.9 Ev), high breakdown electric field strength and excellent thermal stability. Compared with silicon-based and silicon carbide-based devices, gallium oxide devices have higher breakdown voltage and lower on-resistance.

[0003] Gallium oxide superjunction diode is a new type of power electronic device that utilizes the excellent material properties of gallium oxide and heterogeneous superjunction structure design to improve device performance. It is expected to occupy an important position in the field of power electronics in the future, especially in application scenarios that require high voltage, high frequency, and high-efficiency energy conversion, such as electric vehicle charging and solar inverters.

[0004] At present, most existing gallium oxide superjunction diodes use a lateral heterojunction structure to form a superjunction structure. However, lateral devices cannot make good use of the drift layer, which reduces the voltage resistance of the device; at the same time, the lateral structure cannot be effectively designed for the terminal structure, which is not conducive to the full potential of the superjunction structure. In addition, superjunction devices require a deep P junction to balance the electric field, and gallium oxide cannot be effectively implanted with P-type ions, making it difficult to form an effective PN junction structure. And the device terminal area usually also requires P-type ion implantation to achieve this, which also makes it impossible for gallium oxide devices to perform effective terminal design.

[0005] In summary, existing gallium oxide superjunction devices have problems with P-type doping and terminal design, and cannot form effective vertical devices. Summary of the invention

[0006] In order to solve the above problems existing in the prior art, the present invention provides a vertical gallium oxide heterojunction superjunction Schottky diode and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions: In a first aspect, the present invention provides a vertical gallium oxide heterojunction Schottky diode, comprising: N+ type gallium oxide substrate; An N-type gallium oxide drift region is located on the upper surface of an N+ type gallium oxide substrate; a plurality of grooves are etched in the N-type gallium oxide drift region; the plurality of grooves are distributed in the source region and the terminal region of the device; and each groove is filled with a dielectric layer; The control layer includes a P-type charge balance control layer and a P+ type surface electric field control layer; the P-type charge balance control layer covers the sidewall of each groove; the P+ type surface electric field control layer includes two parts, one part is arranged on the top layer of the sidewall of the groove in the device source area, and the other part is arranged on the surface layer of the N-type gallium oxide drift region in the device terminal area; An ohmic contact layer is arranged on the lower surface of the N+ type gallium oxide substrate; A field oxide layer is arranged in a right region of the upper surface of the N-type gallium oxide drift region corresponding to the device terminal region; A Schottky contact layer is provided on the upper surface of the N-type gallium oxide drift region and in the left region corresponding to the device source region, and partially covers the field oxide layer; An anode electrode is arranged on the upper surface of the Schottky contact layer; A cathode electrode is arranged on the lower surface of the ohmic contact layer; The passivation protection layer is arranged on the upper surface of the field oxide layer and partially covers the upper surface of the anode electrode.

[0007] In a second aspect, the present invention provides a method for preparing a vertical gallium oxide heterojunction superjunction Schottky diode, comprising: epitaxially growing an N-type gallium oxide drift region on an N+ type gallium oxide substrate; Dry etching the N-type gallium oxide drift region to form a plurality of trenches in the source region and the terminal region of the device; A P-type charge balance control layer is formed on each trench sidewall, and a P+-type surface electric field control layer is formed on the top layer of the trench sidewall in the device source region and on the surface layer of the N-type gallium oxide drift region in the device terminal region; Filling a dielectric layer in each trench; Depositing metal on the lower surface of the N+ type gallium oxide substrate and forming an ohmic contact layer by laser annealing; A field oxide layer is formed in the right region of the upper surface of the N-type gallium oxide drift region corresponding to the device terminal region; A Schottky contact layer is formed on the upper surface of the N-type gallium oxide drift region and in the left region corresponding to the device source region; Depositing metal on the Schottky contact layer to form an anode electrode; and depositing metal on the ohmic contact layer to form a cathode electrode; A passivation protection layer is formed on the field oxide layer and a portion of the anode electrode.

[0008] Beneficial effects of the present invention: A vertical gallium oxide heterogeneous super junction Schottky diode provided by the present invention includes an N+ type gallium oxide substrate, an N-type gallium oxide drift region and a control layer; wherein a plurality of grooves are etched in the N-type gallium oxide drift region; the plurality of grooves are distributed in the device source region and the terminal region; and each groove is filled with a dielectric layer; the control layer includes a P-type charge balance control layer and a P+ type surface electric field control layer; the P-type charge balance control layer covers the sidewall of each groove to form a deep P junction; the P+ type surface electric field control layer includes two parts, one part is arranged on the top layer of the sidewall of the groove in the device source region, and the other part is arranged on the surface layer of the N-type gallium oxide drift region in the device terminal region. This design realizes a gallium oxide-based vertical super junction device by etching and heterogeneous backfilling technology, avoiding the problem of drift region pressure bearing caused by the lateral structure and the problem of difficult terminal design; at the same time, it solves the problem of being unable to form an effective PN junction structure, terminal design and difficulty in gallium oxide P-type doping due to the limitation of the material itself.

[0009] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic structural diagram of a vertical gallium oxide heterojunction Schottky diode provided by an embodiment of the present invention; Figure 2 It is a schematic flow chart of a method for preparing a vertical gallium oxide heterojunction superjunction Schottky diode provided by an embodiment of the present invention; Figure 3a-3j It is a schematic diagram of a process for preparing a vertical gallium oxide heterojunction super junction Schottky diode provided in an embodiment of the present invention.

[0011] Description of reference numerals: 1-N+ type gallium oxide substrate, 2-N type gallium oxide drift region, 3-groove, 4-dielectric layer, 5-regulating layer, 51-P type charge balance regulating layer, 52-P+ type surface electric field regulating layer, 6-ohmic contact layer, 7-field oxide layer, 8-Schottky contact layer, 9-anode electrode, 10-cathode electrode, 11-passivation protection layer. DETAILED DESCRIPTION

[0012] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0013] The first aspect of the present invention provides a vertical gallium oxide heterojunction Schottky diode. Figure 1 , Figure 1 1 is a schematic diagram of a vertical gallium oxide heterojunction Schottky diode provided by an embodiment of the present invention. The device includes: N+ type gallium oxide substrate 1; An N-type gallium oxide drift region 2 is located on the upper surface of an N+ type gallium oxide substrate 1; a plurality of grooves 3 are etched in the N-type gallium oxide drift region 2; the plurality of grooves 3 are distributed in the source region and the terminal region of the device; and each groove 3 is filled with a dielectric layer 4; The control layer 5 includes a P-type charge balance control layer 51 and a P+ type surface electric field control layer 52; the P-type charge balance control layer 51 covers the sidewall of each trench 3; the P+ type surface electric field control layer 52 includes two parts, one part is arranged on the top layer of the sidewall of the trench in the device source region, and the other part is arranged on the surface layer of the N-type gallium oxide drift region 2 in the device terminal region; The ohmic contact layer 6 is arranged on the lower surface of the N+ type gallium oxide substrate 1; A field oxide layer 7 is provided on the upper surface of the N-type gallium oxide drift region 2 and in the right region corresponding to the device terminal region; The Schottky contact layer 8 is arranged on the left side of the upper surface of the N-type gallium oxide drift region 2 corresponding to the device source region and partially covers the field oxide layer 7; Anode electrode 9, arranged on the upper surface of Schottky contact layer 8; The cathode electrode 10 is arranged on the lower surface of the ohmic contact layer 6; The passivation protection layer 11 is disposed on the upper surface of the field oxide layer 7 and partially covers the upper surface of the anode electrode 9 .

[0014] Optionally, in this embodiment, the material of the N+ type gallium oxide substrate 1 is a heavily doped N type β -Ga2O3, doping concentration 5E18cm -3 -1E19cm -3 , with a thickness of 100μm-200μm. The material of the N-type gallium oxide drift region 2 is N-type β -Ga2O3, doping concentration 6E16cm -3 -1E17cm -3 The doping element is one of Sn, Si, and Ge, and the thickness is 6μm-20μm.

[0015] It is understood that the thickness of the N-type gallium oxide drift region 2 is determined by the withstand voltage level of the device. Generally, the thickness of the N-type drift region of a 1200V-class device may be 10 μm, and the doping concentration may be 6E15 cm -3 .

[0016] Furthermore, in this embodiment, the shape of the grooves 3 may be rectangular or inverted trapezoidal; and the dielectric layers 4 filled in the grooves 3 may be silicon oxide or PI (Polyimide) photoresist.

[0017] Preferably, Figure 1 As shown, in this embodiment, the groove 3 adopts an inverted trapezoidal structure, so that the sidewall of the groove is inclined, which is convenient for the subsequent attachment of the P-type charge balance control layer 51. The dielectric layer 4 filled in the groove 3 is preferably PI photoresist.

[0018] It should be noted that, since the depletion region of the device will extend during operation, a number of trenches 3 extend downward from the upper surface of the N-type gallium oxide drift region 2 to the inside of the N-type gallium oxide drift region 2, and have a certain distance from the upper surface of the N+ type gallium oxide substrate 1, reserved for the extension of the depletion region. Generally speaking, a space of 2μm-4μm is reserved between the bottom of the trench 3 and the upper surface of the N+ type gallium oxide substrate 1. It is understandable that as the reverse blocking voltage specification of the device increases, the reserved space should be increased accordingly.

[0019] In addition, the number and spacing of the grooves 3 can be adjusted according to the specifications and performance of the device during specific implementation, and the present invention does not specifically limit this. For example, the groove spacing of the device source region is generally 1 μm-2 μm, and the grooves of the device terminal region can be equally spaced or have variable spacing, and the spacing is generally 1 μm-2 μm.

[0020] Furthermore, in this embodiment, the material of the P-type charge balance control layer 51 can be P-type NiO with a thickness of 200 nm and a doping concentration of 1E17 cm -3 -5E17cm -3 , the doping element is Mg; the material of the P+ type surface electric field control layer 52 is heavily doped P-type NiO, the depth is 500nm, and the doping concentration is 1E18cm -3 -1E19cm -3 , the doping element is Mg.

[0021] In this embodiment, a vertical gallium oxide heterogeneous super junction is formed by setting a groove in the N-type gallium oxide drift region, covering the sidewall of the groove with P-type NiO as a charge balance control layer, and filling the groove with PI photoresist as a heterogeneous dielectric layer. Among them, the P-type NiO covered on the sidewall of the groove can control the electric field so that the electric field presents a rectangular distribution and delays the breakdown. Accordingly, a highly doped NiO is set at the top of the sidewall of the groove, which together with Ga2O3 can bring a lower resistance in the drift region of the device, thereby reducing the specific on-resistance of the device.

[0022] Regarding the design of the ohmic contact layer 6 and the Schottky contact layer 8, in this embodiment, the material of the ohmic contact layer 6 can be a Ti / Au metal combination with a thickness of 50nm / 100nm respectively; the material of the Schottky contact layer 8 can be one or more combinations of Pt, Ni, and Ti with a thickness of 200nm.

[0023] The field oxide layer 7 is generally disposed on the right terminal region of the device. In this embodiment, silicon oxide material may be selected with a thickness of 1 μm.

[0024] In addition, as an implementation, the material of the anode electrode 9 may be Al, with a thickness of 4 μm; the material of the cathode electrode 10 may be a metal combination of Ti / Ni / Ag, with thicknesses of 200 nm / 4000 nm / 10000 nm, respectively.

[0025] The passivation protection layer 11 is generally a SiNx / SiO2 composite layer with a thickness of 200nm / 200nm respectively.

[0026] The present invention provides a vertical gallium oxide heterogeneous superjunction Schottky diode N+ type gallium oxide substrate, N type gallium oxide drift region and regulation layer; wherein, a plurality of grooves are etched in the N type gallium oxide drift region; the plurality of grooves are distributed in the device source region and the terminal region; and each groove is filled with a dielectric layer; the regulation layer includes a P type charge balance regulation layer and a P+ type surface electric field regulation layer; the P type charge balance regulation layer covers the sidewall of each groove to form a deep P junction; the P+ type surface electric field regulation layer includes two parts, one part is arranged on the top layer of the sidewall of the groove in the device source region, and the other part is arranged on the surface layer of the N type gallium oxide drift region in the device terminal region. The device realizes a gallium oxide-based vertical superjunction device by etching and heterogeneous backfilling technology, avoiding the problem of drift region pressure bearing caused by the lateral structure and the problem of terminal design difficulty; at the same time, it solves the problem of being unable to form an effective PN junction structure, terminal design and difficulty in gallium oxide P-type doping due to the limitation of its own materials.

[0027] Based on the same inventive concept, the second aspect of the present invention provides a method for preparing a vertical gallium oxide heterojunction Schottky diode. The preparation method provided by the present invention is described in detail below in conjunction with the accompanying drawings.

[0028] Please see the joint Figure 2 and Figure 3a-3j , Figure 2 It is a schematic flow chart of a method for preparing a vertical gallium oxide heterojunction superjunction Schottky diode provided by an embodiment of the present invention; Figure 3a-3j 1 is a schematic diagram of a process for preparing a vertical gallium oxide heterojunction Schottky diode provided by an embodiment of the present invention. The method specifically comprises the following steps: Step 1: epitaxially grow an N-type gallium oxide drift region 2 on an N+ type gallium oxide substrate 1.

[0029] Specifically, select heavily doped N-type β -Ga2O3 is used as the N+ type gallium oxide substrate 1, and high-quality N-type β -Ga2O3, forming an N-type gallium oxide drift region 2, such as Figure 3a shown.

[0030] Step 2: dry-etching the N-type gallium oxide drift region 2 to form a plurality of trenches 3 in the source region and the terminal region of the device.

[0031] Optionally, as an implementation, Figure 3b As shown, the plurality of grooves 3 may be inverted trapezoidal structures, wherein the source region on the left side of the device includes three evenly distributed grooves 3, and the active region on the right side of the device also includes three evenly distributed grooves 3. In addition, a wider groove is provided at the junction of the source region and the terminal region.

[0032] Step 3: forming a P-type charge balance control layer 51 on the sidewall of each trench 3, and forming a P+ type surface electric field control layer 52 on the top layer of the trench sidewall in the device source region and the surface layer of the N-type gallium oxide drift region 2 in the device terminal region.

[0033] First, a concentration of 1E17 cm -3 -5E17cm -3 The P-type NiO is formed, and the top is etched to form a P-type charge balance regulating layer 51 on the side wall of the trench 3; Figure 3c shown.

[0034] Then, using photolithography, etching, and ion implantation processes, P-type ions are implanted into the top portion of the P-type charge balance control layer 51 to form a P+ type surface electric field control layer 52. Figure 3d shown.

[0035] Step 4: Fill each trench 3 with a dielectric layer 4 .

[0036] Specifically, the trench 3 is filled with a photolithography process and a PI photoresist to form a dielectric layer 4; Figure 3e shown.

[0037] Step 5: depositing metal on the lower surface of the N+ type gallium oxide substrate 1 and forming an ohmic contact layer 6 by laser annealing.

[0038] Specifically, Ti / Au metal is deposited by electron beam evaporation or magnetron sputtering and laser annealing is used to form the ohmic contact layer 6, such as Figure 3f shown.

[0039] Step 6: Form a field oxide layer 7 on the right side of the upper surface of the N-type gallium oxide drift region 2 corresponding to the device terminal region.

[0040] Specifically, a PECVD (Plasma Enhanced Chemical Vapor Deposition) process is used to deposit silicon oxide on the upper surface of the N-type gallium oxide drift region 2, and then a photolithography process is used to etch away the silicon oxide in the left device source region to form a field oxide layer 7 on the right terminal region surface, as shown in FIG. Figure 3g shown.

[0041] Step 7: forming a Schottky contact layer 8 on the upper surface of the N-type gallium oxide drift region 2 in the left region corresponding to the device source region.

[0042] Specifically, electron beam evaporation or magnetron sputtering is used to deposit the front Schottky contact metal, and then photolithography and wet etching processes are used to form the Schottky contact layer 8, such as Figure 3h shown.

[0043] Step 8: depositing metal on the Schottky contact layer 8 to form an anode electrode 9; and depositing metal on the ohmic contact layer 6 to form a cathode electrode 10.

[0044] First, electron beam evaporation or magnetron sputtering is used to deposit a thick front metal electrode Al, and then photolithography and wet etching are used to form a front metal electrode as the anode electrode 9 of the device. Figure 3i shown.

[0045] Then, a back metal electrode is formed by using photolithography and wet etching process as the cathode electrode 10 of the device. Figure 3j shown.

[0046] Step 9: forming a passivation protection layer 11 on the field oxide layer 7 and a portion of the anode electrode 9 .

[0047] Specifically, a SiN / SiO 2 composite layer is formed by using PECVD and photolithography and etching processes as the passivation protection layer 11 .

[0048] At this point, the preparation of the vertical gallium oxide heterojunction Schottky diode has been completed, and finally formed as follows Figure 1 The device shown.

[0049] It should be noted that the PECVD process, photolithography process, wet etching process, electron beam evaporation or magnetron sputtering process used in the process of preparing the vertical gallium oxide heterojunction Schottky diode in this embodiment are all existing mature processes, and the corresponding parameter settings can be implemented by referring to the existing related technologies.

[0050] The preparation method provided in the second aspect of the present invention can be used to prepare the vertical gallium oxide heterogeneous super junction Schottky diode device provided in the first aspect, and therefore has similar beneficial effects as the device embodiment of the first aspect. The method uses etching and heterogeneous backfilling technology to realize a gallium oxide-based vertical super junction device, avoiding the problem of drift region pressure caused by the lateral structure and the problem of difficult terminal design; at the same time, it solves the problem of being unable to form an effective PN junction structure, terminal design, and difficulty in gallium oxide P-type doping due to material limitations. For technical details not disclosed in the embodiment of the preparation method of the present invention, please refer to the description of the device embodiment for understanding.

[0051] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0052] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0053] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0054] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0055] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A vertical gallium oxide heterojunction Schottky diode, characterized in that: include: N+ type gallium oxide substrate (1); An N-type gallium oxide drift region (2) is located on the upper surface of the N+ type gallium oxide substrate (1); a plurality of grooves (3) are etched in the N-type gallium oxide drift region (2); the plurality of grooves (3) are distributed in the device source region and the terminal region; and each groove (3) is filled with a dielectric layer (4); The control layer (5) comprises a P-type charge balance control layer (51) and a P+ type surface electric field control layer (52); the P-type charge balance control layer (51) covers the side wall of each groove (3); the P+ type surface electric field control layer (52) comprises two parts, one part is arranged on the top layer of the side wall of the groove (3) in the device source region, and the other part is arranged on the surface layer of the N-type gallium oxide drift region (2) in the device terminal region; An ohmic contact layer (6) is arranged on the lower surface of the N+ type gallium oxide substrate (1); A field oxide layer (7) is arranged in a right region of the upper surface of the N-type gallium oxide drift region (2) corresponding to the device terminal region; A Schottky contact layer (8) is arranged on the left side of the upper surface of the N-type gallium oxide drift region (2) corresponding to the device source region and partially covers the field oxide layer (7); an anode electrode (9) disposed on the upper surface of the Schottky contact layer (8); A cathode electrode (10) is arranged on the lower surface of the ohmic contact layer (6); A passivation protection layer (11) is arranged on the upper surface of the field oxide layer (7) and partially covers the upper surface of the anode electrode (9).

2. A vertical gallium oxide heterojunction Schottky diode according to claim 1, characterized in that: The material of the N+ type gallium oxide substrate (1) is a heavily doped N-type β -Ga2O3, doping concentration 5E18cm -3 -1E19cm -3 , thickness is 100μm-200μm.

3. The vertical gallium oxide heterojunction Schottky diode according to claim 1, characterized in that: The material of the N-type gallium oxide drift region (2) is N-type β -Ga2O3, doping concentration 6E16cm -3 -1E17cm -3 The doping element is one of Sn, Si, and Ge, and the thickness is 6μm-20μm.

4. The vertical gallium oxide heterojunction Schottky diode according to claim 1, characterized in that: The shape of the groove (3) is a rectangle or an inverted trapezoid; and the dielectric layer (4) filled in the groove (3) is silicon oxide or PI photoresist.

5. The vertical gallium oxide heterojunction Schottky diode according to claim 1, characterized in that: The material of the P-type charge balance regulating layer (51) is P-type NiO, with a thickness of 200 nm and a doping concentration of 1E17 cm -3 -5E17cm -3 , the doping element is Mg; The material of the P+ type surface electric field regulating layer (52) is heavily doped P type NiO, with a depth of 500nm and a doping concentration of 1E18cm -3 -1E19cm -3 , the doping element is Mg.

6. The vertical gallium oxide heterojunction Schottky diode according to claim 1, characterized in that: The material of the ohmic contact layer (6) is a combination of Ti / Au metals, with thicknesses of 50nm / 100nm respectively; the material of the Schottky contact layer (8) is a combination of one or more of Pt, Ni, and Ti, with a thickness of 200nm.

7. The vertical gallium oxide heterojunction Schottky diode according to claim 1, characterized in that: The field oxide layer (7) is made of silicon oxide and has a thickness of 1 μm.

8. The vertical gallium oxide heterojunction Schottky diode according to claim 1, characterized in that: The material of the anode electrode (9) is Al, and the thickness is 4 μm; The material of the cathode electrode (10) is a metal combination of Ti / Ni / Ag, and the thicknesses are 200nm / 4000nm / 10000nm respectively.

9. The vertical gallium oxide heterojunction Schottky diode according to claim 1, characterized in that: The passivation protection layer (11) is a SiNx / SiO2 composite layer with thicknesses of 200nm / 200nm respectively.

10. A method for preparing a vertical gallium oxide heterojunction superjunction Schottky diode, characterized in that: include: epitaxially growing an N-type gallium oxide drift region on an N+ type gallium oxide substrate; Dry etching the N-type gallium oxide drift region to form a plurality of grooves in the device source region and the terminal region; Forming a P-type charge balance control layer on each trench sidewall, and forming a P+ type surface electric field control layer on the top layer of the trench sidewall in the device source region and the surface layer of the N-type gallium oxide drift region in the device terminal region; filling a dielectric layer in each trench; Depositing metal on the lower surface of the N+ type gallium oxide substrate and forming an ohmic contact layer by laser annealing; Forming a field oxide layer in the right region of the upper surface of the N-type gallium oxide drift region corresponding to the device terminal region; Forming a Schottky contact layer on the upper surface of the N-type gallium oxide drift region and in the left region corresponding to the device source region; Depositing metal on the Schottky contact layer to form an anode electrode; and depositing metal on the ohmic contact layer to form a cathode electrode; A passivation protection layer is formed on the field oxide layer and a portion of the anode electrode.

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