Semiconductor structure and preparation method thereof, memory and electronic equipment

Abstract

The invention relates to a semiconductor structure and a preparation method thereof, a memory and electronic equipment. The preparation method of the semiconductor structure comprises the steps of providing a substrate; forming a first semiconductor layer, a second semiconductor layer and a third semiconductor layer which are sequentially stacked along a first direction on the substrate, wherein the first semiconductor layer covers the top surface of the substrate; the second semiconductor layer comprises a first element and a second element; wherein the second semiconductor layer comprises a first interface layer, a middle layer and a second interface layer adjacent to the third semiconductor layer which are sequentially arranged in the first direction, and the content of a second element in the first interface layer is gradually reduced in the direction away from the top surface of the substrate; the content of the second element in the second interface layer is gradually increased in the direction away from the top surface of the middle layer; and etching the second semiconductor layer by adopting an isotropic etching process to obtain a rectangular groove. The arc effect of the lateral etching process can be inhibited, and a steeper morphology is formed, so that the squareness of an etching section is improved, and the performance and the reliability of a device are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a preparation method thereof, a memory and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] As a common semiconductor process, lateral etching has important applications in the manufacturing of gate all around transistors (GAA transistor), three-dimensional dynamic random access memory (3D DRAM), and three-dimensional flash memory (3D NAND Flash Memory).

[0004] However, in the traditional lateral etching process, since the cross-sectional morphology is difficult to control, the etched material will form an arc effect, which makes it difficult for the traditional lateral etching process to form a steep morphology, thereby reducing device reliability and product yield. Summary of the invention

[0005] Based on this, the present disclosure provides a semiconductor structure and a preparation method thereof, a memory and an electronic device, which can at least suppress the arc effect of the lateral etching process and form a steeper morphology to improve the squareness of the etched cross section, thereby improving device performance and reliability.

[0006] In order to solve the above-mentioned technical problems and other problems, according to some embodiments, one aspect of the present disclosure provides a method for preparing a semiconductor structure, the method comprising: providing a substrate; forming a multilayer stacked structure on the substrate; the stacked structure comprises a first semiconductor layer and a second semiconductor layer stacked in sequence along a first direction, the first semiconductor layer covering the top surface of the substrate; the second semiconductor layer is a semiconductor layer including a first element; wherein the second semiconductor layer comprises a first interface layer and an intermediate layer arranged in sequence along the first direction, and the content of the second element in the first interface layer decreases or increases in a direction away from the top surface of the substrate; and the second semiconductor layer is etched using an isotropic etching process to obtain a rectangular groove.

[0007] In the method for preparing the semiconductor structure of the above embodiment, since in the isotropic etching process, the etching rate of the second semiconductor layer increases with the increase of the content of the first element, or the etching rate of the second semiconductor layer increases with the decrease of the content of the first element, the content of the first element in the first interface layer decreases or increases in the direction away from the top surface of the substrate, so that when the second semiconductor layer is etched using the isotropic etching process, the etching rate of the first interface layer gradually decreases in the direction away from the top surface of the substrate; that is, since the closer the second semiconductor layer is to the contact interface of the first semiconductor layer, the higher or lower the content of the first element therein, the etching rate of the second semiconductor layer from the middle layer through the first interface layer to the contact interface with the first semiconductor layer gradually increases, so that the etching amount of the part of the second semiconductor layer closer to the contact interface is larger, so as to form a steeper morphology, thereby achieving the effect of suppressing the arc effect and improving the squareness of the etched cross section, thereby improving the device performance and reliability. In some embodiments, the stacked structure also includes a third semiconductor layer, which is located on the top surface of the second semiconductor layer; the second semiconductor layer also includes a second interface layer adjacent to the third semiconductor layer; the content of the first element in the second interface layer increases or decreases in the direction away from the top surface of the intermediate layer.

[0008] In some embodiments, forming a multilayer stacked structure on the top surface of a substrate includes: after forming a first semiconductor layer on the top surface of the substrate, within a preset time T1, in the process of depositing a second semiconductor layer on the top surface of the first semiconductor layer, by controlling the flow rate of a first element precursor, so that the content of the first element in the first interface layer decreases or increases in a direction away from the top surface of the substrate, and the content of the first element in the second interface layer increases or decreases in a direction away from the top surface of the intermediate layer. In some embodiments, the content of the first element in the intermediate layer is within a preset range.

[0009] In some embodiments, the content of the first element in the first interface layer decreases or increases linearly or gradiently in a direction away from the top surface of the substrate; and / or the content of the first element in the second interface layer increases or decreases linearly or gradiently in a direction away from the top surface of the intermediate layer.

[0010] In some embodiments, depositing a second semiconductor layer on the top surface of the first semiconductor layer within a preset time T1 includes: within the preset time Td1, controlling the flow rate of the first element precursor to gradually increase or decrease, so that the content of the first element in the first interface layer decreases or increases in the direction away from the top surface of the substrate; within the preset time Td2, controlling the flow rate of the first element precursor to gradually decrease or increase, so that the content of the first element in the second interface layer increases or decreases in the direction away from the top surface of the intermediate layer.

[0011] In some embodiments, forming a first semiconductor layer and a third semiconductor layer includes: within a preset time T2, using a preset deposition process to form a first sub-semiconductor layer and a first sub-interface layer stacked in sequence along a first direction on the top surface of the substrate, the first sub-semiconductor layer covers the substrate, and the second semiconductor layer covers the first sub-interface layer; the doping concentration of the first sub-interface layer increases or decreases toward the direction of the second semiconductor layer; the first sub-semiconductor layer and the first sub-interface layer constitute the first semiconductor layer; and / or within a preset time T3, using a preset deposition process to form a third sub-semiconductor layer and a third sub-interface layer stacked in sequence along the first direction on the top surface of the second semiconductor layer, the third sub-interface layer covers the second semiconductor layer; the doping concentration of the third sub-interface layer increases or decreases toward the direction of the second semiconductor layer, and the third sub-semiconductor layer and the third sub-interface layer constitute the third semiconductor layer.

[0012] In the method for preparing the semiconductor structure of the above embodiment, in the isotropic etching process, due to the insufficient etching selectivity between adjacent layers, when etching the second semiconductor layer, the first semiconductor layer and / or the third semiconductor layer in contact with the second semiconductor layer will also be etched to form a notch phenomenon, resulting in reduced device performance and reliability. Therefore, by increasing or decreasing the doping concentration of the first sub-interface layer toward the second semiconductor layer, the etching rate changes with the increasing or decreasing doping concentration, and under different doping types, the etching rate of the first sub-interface layer and / or the third sub-interface layer decreases toward the second semiconductor layer, that is, in the first semiconductor layer and / or the third semiconductor layer, the closer the part is to the contact interface with the second semiconductor layer, the smaller the etching amount is, so as to improve the etching selectivity between adjacent layers, achieve the effect of suppressing the notch phenomenon, and further improve the squareness of the etched cross section.

[0013] In some embodiments, the doping concentration of the first semiconductor sub-layer and / or the third semiconductor sub-layer is within a preset range.

[0014] In some embodiments, forming the first semiconductor layer and the third semiconductor layer also includes: during the process of depositing the first sub-interface layer on the top surface of the first sub-semiconductor layer and / or depositing the third sub-interface layer on the top surface of the second semiconductor layer, by controlling the flow rate of the doping precursor, the doping concentration of the first sub-interface layer and / or the third sub-interface layer increases or decreases toward the second semiconductor layer.

[0015] In some embodiments, the doping concentration of the first sub-interface layer and / or the third sub-interface layer increases or decreases linearly toward the second semiconductor layer; or the doping concentration of the first sub-interface layer and / or the third sub-interface layer increases or decreases gradiently toward the second semiconductor layer.

[0016] In some embodiments, the doping type of the first semiconductor layer and the third semiconductor layer is P-type; the doping concentration of the first sub-interface layer and / or the third sub-interface layer increases toward the second semiconductor layer; or the doping type of the first semiconductor layer and the third semiconductor layer is N-type; the doping concentration of the first sub-interface layer and / or the third sub-interface layer decreases toward the second semiconductor layer.

[0017] In some embodiments, the precursor of the preset deposition process includes a P-type doping precursor; in the process of depositing the first sub-interface layer on the top surface of the first sub-semiconductor layer, within the preset time Td3, the flow rate of the P-type doping precursor is controlled to gradually increase, so that the doping concentration of the first sub-interface layer increases toward the direction of the second semiconductor layer; and / or in the process of depositing the third sub-interface layer on the top surface of the second semiconductor layer, within the preset time Td4, the flow rate of the P-type doping precursor is controlled to gradually decrease, so that the doping concentration of the third sub-interface layer increases toward the direction of the second semiconductor layer.

[0018] In the method for preparing the semiconductor structure of the above embodiment, the doping concentration of the first sub-interface layer increases toward the second semiconductor layer by controlling the flow rate of the P-type doping precursor to gradually increase, and the doping concentration of the third sub-interface layer increases toward the second semiconductor layer by controlling the flow rate of the P-type doping precursor to gradually decrease. Since the etching rate of the P-type doping material decreases with increasing doping concentration, the etching rate of the first sub-interface layer and / or the third sub-interface layer decreases toward the second semiconductor layer, that is, in the first semiconductor layer and / or the third semiconductor layer, the closer the part is to the contact interface with the second semiconductor layer, the smaller the etching amount is, so as to improve the etching selectivity between adjacent layers and achieve the effect of suppressing the notch phenomenon, thereby further improving the squareness of the etched section.

[0019] In some embodiments, the precursor of the preset deposition process includes an N-type doping precursor; in the process of depositing the first sub-interface layer on the top surface of the first sub-semiconductor layer, within the preset time Td3, the flow rate of the N-type doping precursor is controlled to gradually decrease, so that the doping concentration of the first sub-interface layer decreases toward the direction of the second semiconductor layer; and / or in the process of depositing the third sub-interface layer on the top surface of the second semiconductor layer, within the preset time Td4, the flow rate of the N-type doping precursor is controlled to gradually increase, so that the doping concentration of the first sub-interface layer decreases toward the direction of the second semiconductor layer.

[0020] In the method for preparing the semiconductor structure of the above embodiment, the flow rate of the N-type doping precursor is controlled to gradually decrease, so that the doping concentration of the first sub-interface layer decreases toward the second semiconductor layer; and the flow rate of the N-type doping precursor is controlled to gradually increase, so that the doping concentration of the first sub-interface layer decreases toward the second semiconductor layer. Since the etching rate of the N-type doping material decreases with the decrease of the doping concentration, the etching rate of the first sub-interface layer and / or the third sub-interface layer decreases toward the second semiconductor layer, that is, in the first semiconductor layer and / or the third semiconductor layer, the closer the part is to the contact interface with the second semiconductor layer, the smaller the etching amount is, so as to improve the etching selectivity between adjacent layers, achieve the effect of suppressing the notch phenomenon, and further improve the squareness of the etched cross-section.

[0021] In some embodiments, the isotropic etching process includes an atomic layer etching process and / or a wet-based quasi-atomic layer etching process.

[0022] In some embodiments, the first element includes germanium.

[0023] In some embodiments, 0.5T1>Td1.

[0024] In some embodiments, 0.5T1>Td2.

[0025] In some embodiments, 0.5T2>Td3.

[0026] In some embodiments, 0.5T3>Td4.

[0027] In some embodiments, T1>Td1+Td2.

[0028] According to some embodiments, another aspect of the present disclosure provides a semiconductor structure, which includes a substrate and a multilayer stacked structure located on the substrate; the stacked structure includes a first semiconductor layer and a second semiconductor layer stacked in sequence along a first direction, the first semiconductor layer covering the top surface of the substrate; the second semiconductor layer has a rectangular groove; wherein the second semiconductor layer is a semiconductor layer including a first element; the second semiconductor layer includes a first interface layer and an intermediate layer arranged in sequence along the first direction, and the content of the first element in the first interface layer decreases or increases in a direction away from the top surface of the substrate.

[0029] In some embodiments, the stacked structure also includes a third semiconductor layer, which is located on the top surface of the second semiconductor layer; the second semiconductor layer also includes a second interface layer adjacent to the third semiconductor layer; the content of the first element in the second interface layer increases or decreases in the direction away from the top surface of the intermediate layer.

[0030] In some embodiments, the semiconductor structure also includes a channel layer and a gate structure, the channel layer is formed based on a rectangular groove; the gate structure is located on at least one side of the channel layer; the first semiconductor layer is a drain structure, and the third semiconductor layer is a source structure, and the drain structure and the source structure are respectively located on opposite sides of the channel layer along the first direction.

[0031] In some embodiments, the gate structure surrounds the channel layer.

[0032] According to some embodiments, another aspect of the present disclosure provides a memory including the above-mentioned semiconductor structure.

[0033] According to some embodiments, another aspect of the present disclosure provides an electronic device including the above-mentioned memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, drawings of other embodiments can be obtained based on these drawings without creative work.

[0035] Figure 1 A schematic diagram of a structure obtained by implementing a method for preparing a semiconductor structure provided in the related art;

[0036] Figure 2 A schematic diagram of a flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0037] Figure 3 A schematic diagram of a curve showing a change in etching rate with element content provided in an embodiment of the present disclosure;

[0038] Figure 4 A schematic diagram of a method for preparing a semiconductor structure and a resulting structure provided in an embodiment of the present disclosure;

[0039] Figure 5 A schematic diagram of a curve showing the variation of etching rate with element content provided in another embodiment of the present disclosure;

[0040] Figure 6 A schematic diagram of a method for preparing a semiconductor structure and a resulting structure provided in another embodiment of the present disclosure;

[0041] Figure 7 A schematic diagram of a structure obtained by implementing a method for preparing a semiconductor structure provided in the related art;

[0042] Figure 8A schematic diagram of a method for preparing a semiconductor structure and a resulting structure provided in an embodiment of the present disclosure;

[0043] Fig. 9 A schematic diagram of a method for preparing a semiconductor structure and a resulting structure provided in another embodiment of the present disclosure;

[0044] Fig.10 A schematic diagram of a semiconductor structure provided in one embodiment of the present disclosure.

[0045] Description of reference numerals:

[0046] 1. substrate; 2. first semiconductor layer; 21. first sub-semiconductor layer; 22. first sub-interface layer; 3. second semiconductor layer; 31. first interface layer; 32. intermediate layer; 33. second interface layer; 4. third semiconductor layer; 41. third sub-semiconductor layer; 42. third sub-interface layer; 5. rectangular groove. DETAILED DESCRIPTION

[0047] In order to facilitate the understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are given in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present disclosure more thorough and comprehensive.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0049] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.

[0050] When used herein, the singular forms "a", "an" and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, the presence of the features, integers, steps, operations, elements and / or components may be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups is not excluded.

[0051] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0052] Please refer to Figure 1 The lateral etching process uses isotropic etching technology, that is, equal etching is performed in all directions, that is, the direction of the substrate does not affect the technology of removing materials by the etchant. It has important applications in the manufacturing fields of GAA transistors, 3D DRAM, and 3D NAND. For example, in the manufacturing process of vertical GAA devices based on epitaxy, it is necessary to use the lateral etching process to form a lateral groove structure for growing channel materials, so as to form a self-aligned gate based on the lateral groove structure. However, in the traditional lateral etching process, the cross-sectional morphology is difficult to control, and the etched body material will form a Figure 1 The arc effect shown in the middle area C makes it difficult for the traditional lateral etching process to form a steep morphology, thereby reducing device reliability and product yield.

[0053] The present disclosure aims to provide a semiconductor structure and a method for preparing the same, a memory and an electronic device, which can at least suppress the arc effect of the lateral etching process and form a steeper morphology to improve the squareness of the etched cross section, thereby improving device performance and reliability.

[0054] Please refer to Figures 2 to 6 According to some embodiments, one aspect of the present disclosure provides a method for preparing a semiconductor structure, comprising:

[0055] S10: providing a substrate 1;

[0056] S20: forming a multilayer stacked structure on the substrate 1; the stacked structure comprises a first semiconductor layer 2 and a second semiconductor layer 3 sequentially stacked along a first direction, the first semiconductor layer 2 covers the top surface of the substrate 1; the second semiconductor layer 3 is a semiconductor layer comprising a first element; wherein the second semiconductor layer 3 comprises a first interface layer 31 and an intermediate layer 32 sequentially arranged along the first direction, and the content of the first element in the first interface layer 31 decreases or increases in a direction away from the top surface of the substrate 1;

[0057] S30: etching the second semiconductor layer 3 using an isotropic etching process to obtain a rectangular groove 5.

[0058] Please continue to refer to Figures 2 to 6In step S10, the substrate 1 may be made of semiconductor material, insulating material, conductor material or any combination of their material types. The substrate 1 may be a single-layer structure or a multi-layer structure. For example, the substrate 1 may be a silicon (Si) substrate 1, a silicon germanium (SiGe) substrate 1, a silicon germanium carbon (SiGeC) substrate 1, a silicon carbide (SiC) substrate 1, a gallium arsenide (GaAs) substrate 1, an indium arsenide (InAs) substrate 1, an indium phosphide (InP) substrate 1 or other III / V semiconductor substrates 1 or II / VI semiconductor substrates 1. Alternatively, for example, the substrate 1 may be a layered substrate 1 including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on insulator, etc.

[0059] Please continue to refer to Figures 2 to 6 In step S20, the first direction can be the thickness direction of the substrate 1, that is, the OX direction. Since the etching rate of the second semiconductor layer 3 increases with the increase of the content of the first element, or the etching rate of the second semiconductor layer increases with the decrease of the content of the first element, the content of the first element in the first interface layer 31 decreases or increases in the direction away from the top surface of the substrate 1, so that the etching rate of the first interface layer 31 gradually decreases in the direction away from the top surface of the substrate 1.

[0060] Please continue to refer to Figures 2 to 6 In step S30, the second semiconductor layer 3 can be etched along the second direction to obtain a rectangular groove 5, where the second direction is the OY direction and the second direction is perpendicular to the first direction; or, the second semiconductor layer 3 can be etched around the first direction to obtain a circumferentially surrounding rectangular groove 5.

[0061] Please continue to refer to Figures 2 to 6 In the method for preparing the semiconductor structure of the above embodiment, when the second semiconductor layer 3 is etched by an isotropic etching process, the closer the second semiconductor layer 3 is to the contact interface of the first semiconductor layer 2, the higher or lower the content of the first element therein, and the etching rate of the second semiconductor layer 3 from the middle layer 32 through the interface layers on both sides to the contact interface with the adjacent semiconductor layer gradually increases, so that the etching amount of the second semiconductor layer 3 closer to the contact interface is greater, so as to form a steeper morphology, thereby achieving the effect of suppressing the arc effect and improving the squareness of the etched cross section, thereby improving the device performance and reliability.

[0062] Although Figure 2 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, the execution of these steps is not strictly limited to the order, and these steps can be executed in other orders. Moreover, although Figure 3At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution of these sub-steps or stages is not necessarily carried out sequentially, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0063] Please refer to Figures 2 to 6 In some embodiments, the stacked structure further includes a third semiconductor layer 4, which is located on the top surface of the second semiconductor layer 3; the second semiconductor layer 3 further includes a second interface layer 33 adjacent to the third semiconductor layer 4; the content of the first element in the second interface layer 33 increases or decreases in the direction away from the top surface of the intermediate layer 32.

[0064] Please continue to refer to Figures 2 to 6 In the method for preparing the semiconductor structure of the above embodiment, since the content of the first element in the second interface layer 33 increases or decreases in the direction away from the top surface of the intermediate layer 32, when the second semiconductor layer 3 is etched by an isotropic etching process, the etching rate of the second interface layer 33 gradually increases in the direction away from the top surface of the intermediate layer 32. That is, the etching rate of the second semiconductor layer 3 from the intermediate layer 32 through the interface layers on both sides to the contact interface with the adjacent semiconductor layer gradually increases, so that the etching amount of the second semiconductor layer 3 closer to the contact interface is greater, so as to form a steeper morphology, so as to suppress the arc effect and improve the squareness of the etched cross section, thereby improving the device performance and reliability.

[0065] Please refer to Figure 3 and Figure 4 In some embodiments, for example, when the first element is germanium, in the isotropic etching process, the etching rate of the second semiconductor layer increases with the increase of the content of the first element. Since the content of the first element in the second interface layer 33 increases in the direction away from the top surface of the intermediate layer 32, the etching rate of the second interface layer 33 gradually increases in the direction away from the top surface of the intermediate layer 32. That is, the etching rate of the second semiconductor layer 3 gradually increases from the intermediate layer 32 through the interface layers on both sides to the contact interface with the adjacent semiconductor layer, so that the etching amount of the second semiconductor layer 3 closer to the contact interface is greater.

[0066] Please refer to Figure 5 and Figure 6In some embodiments, in the isotropic etching process, the etching rate of the second semiconductor layer increases as the content of the first element decreases. Since the content of the first element in the second interface layer 33 decreases in the direction away from the top surface of the intermediate layer 32, the etching rate of the second interface layer 33 gradually increases in the direction away from the top surface of the intermediate layer 32. That is, the etching rate of the second semiconductor layer 3 gradually increases from the intermediate layer 32 through the interface layers on both sides to the contact interface with the adjacent semiconductor layer, so that the etching amount of the second semiconductor layer 3 closer to the contact interface is greater.

[0067] Please refer to Figures 2 to 6 In some embodiments, when a stacked first semiconductor layer 2, a second semiconductor layer 3, and a third semiconductor layer 4 are formed on the top surface of the substrate 1, a preset cleaning process can be performed after each semiconductor layer is formed. The preset cleaning process can include a wet cleaning process and a dry cleaning process. The wet cleaning process uses specific chemical liquids and deionized water to clean the wafer surface without damage. The wet cleaning mainly includes RCA cleaning method, dilution chemical method, IMEC cleaning method or single wafer cleaning method. For example, the single wafer cleaning method not only has a better cleaning effect, but also can reduce the consumption of chemicals and improve the cost-effectiveness of the wafer by recycling chemical liquids and deionized water during the cleaning process.

[0068] Please refer to Figures 3 to 6 In some embodiments, a multilayer stacked structure is formed on the top surface of the substrate 1, including: after forming the first semiconductor layer 2 on the top surface of the substrate 1, within a preset time T1, during the process of depositing the second semiconductor layer 3 on the top surface of the first semiconductor layer 2, by controlling the flow rate of the first element precursor, the content of the first element in the first interface layer 31 decreases or increases in a direction away from the top surface of the substrate 1, and the content of the first element in the second interface layer 33 increases or decreases in a direction away from the top surface of the intermediate layer 32.

[0069] Please continue to refer to Figures 3 to 6In the method for preparing the semiconductor structure of the above embodiment, during the process of depositing the second semiconductor layer 3 on the top surface of the first semiconductor layer 2, the greater the flow rate of the first element precursor, the higher the content of the first element in the deposited portion of the second semiconductor layer 3, so that the content of the first element in the first interface layer 31 gradually decreases in the direction away from the top surface of the substrate 1, and the content of the first element in the second interface layer 33 gradually increases in the direction away from the top surface of the intermediate layer 32, and the etching rate of the second semiconductor layer 3 increases with the increase of the content of the first element; or, the smaller the flow rate of the first element precursor, the lower the content of the first element in the deposited portion of the second semiconductor layer 3, so that the content of the first element in the first interface layer 31 gradually decreases in the direction away from the top surface of the substrate 1, the content of the first element in the second interface layer 33 gradually decreases in the direction away from the top surface of the intermediate layer 32, and the etching rate of the second semiconductor layer 3 increases with the decrease of the content of the first element. Therefore, when the second semiconductor layer 3 is etched by an isotropic etching process, the etching rate of the second semiconductor layer 3 from the middle layer 32 through the interface layers on both sides to the contact interface with the adjacent semiconductor layer gradually increases, so that the etching amount of the second semiconductor layer 3 closer to the contact interface is greater, so as to form a steeper morphology, thereby achieving the effect of suppressing the arc effect and improving the squareness of the etched cross section, thereby improving the performance and reliability of the device. Please refer to Figure 4 and Figure 6 In some embodiments, the content W1 of the first element in the intermediate layer 32 is within a preset range.

[0070] Please refer to Figure 4 In some embodiments, the content of the first element in the first interface layer 31 decreases linearly or gradiently in a direction away from the top surface of the substrate 1; and / or the content of the first element in the second interface layer 33 increases linearly or gradiently in a direction away from the top surface of the intermediate layer 32.

[0071] Please refer to Figure 6 In some embodiments, the content of the first element in the first interface layer 31 increases linearly or gradiently in a direction away from the top surface of the substrate 1; and / or the content of the first element in the second interface layer 33 decreases linearly or gradiently in a direction away from the top surface of the intermediate layer 32.

[0072] Please refer to Figure 4 and Figure 6In some embodiments, the second semiconductor layer 3 is deposited on the top surface of the first semiconductor layer 2 within a preset time T1, including: within the preset time Td1, controlling the flow ratio of the first element precursor to the first element precursor to gradually increase or gradually decrease, so that the content of the first element in the first interface layer 31 decreases or increases in the direction away from the top surface of the substrate 1; within the preset time Td2, controlling the flow ratio of the first element precursor to the first element precursor to gradually decrease or gradually increase, so that the content of the first element in the second interface layer 33 increases or decreases in the direction away from the top surface of the intermediate layer 32.

[0073] Please continue to refer to Figure 4 and Figure 6 In some embodiments, 0.5T1>Td1, that is, the thickness of the first interface layer 31 is less than half of the thickness of the second semiconductor layer 3 .

[0074] Please continue to refer to Figure 4 and Figure 6 In some embodiments, 0.5T1>Td2, that is, the thickness of the second interface layer 33 is less than half of the thickness of the second semiconductor layer 3 .

[0075] Please continue to refer to Figure 4 and Figure 6 , in some embodiments, T1>Td1+Td2.

[0076] Please refer to Figure 7 In the isotropic etching process, due to the insufficient etching selectivity between adjacent layers, when etching the second semiconductor layer 3, the first semiconductor layer 2 and / or the third semiconductor layer 4 in contact with the second semiconductor layer 3 will also be etched to form the following: Figure 7 The notch phenomenon shown in the middle area N leads to reduced device performance and reliability.

[0077] Please refer to Figure 8 and Fig. 9In some embodiments, the first semiconductor layer 2 and the third semiconductor layer 4 are formed, including: within a preset time T2, a preset deposition process is used to form a first sub-semiconductor layer 21 and a first sub-interface layer 22 stacked in sequence along a first direction on the top surface of the substrate 1, the first sub-semiconductor layer 21 covers the substrate 1, and the second semiconductor layer 3 covers the first sub-interface layer 22; the doping concentration of the first sub-interface layer 22 increases or decreases toward the direction of the second semiconductor layer 3; the first sub-semiconductor layer 21 and the first sub-interface layer 22 constitute the first semiconductor layer 2; and / or within a preset time T3, a preset deposition process is used to form a third sub-semiconductor layer 41 and a third sub-interface layer 42 stacked in sequence along the first direction on the top surface of the second semiconductor layer 3, the third sub-interface layer 42 covers the second semiconductor layer 3; the doping concentration of the third sub-interface layer 42 increases or decreases toward the direction of the second semiconductor layer 3, and the third sub-semiconductor layer 41 and the third sub-interface layer 42 constitute the third semiconductor layer 4.

[0078] Please refer to Figure 8 and Fig. 9 In some embodiments, the predetermined deposition process may include chemical vapor deposition or physical vapor deposition (PVD), and the chemical vapor deposition process may include one or more of atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD).

[0079] Please continue to refer to Figure 8 and Fig. 9 In some embodiments, the doping concentration D of the first sub-semiconductor layer 21 and / or the third sub-semiconductor layer 41 is within a preset range.

[0080] Please continue to refer to Figure 8 and Fig. 9 In the method for preparing the semiconductor structure of the above embodiment, the doping concentration of the first sub-interface layer 22 increases or decreases toward the second semiconductor layer 3, and the etching rate changes with the increasing or decreasing doping concentration. Under different doping types, the etching rate of the first sub-interface layer 22 and / or the third sub-interface layer 42 decreases toward the second semiconductor layer 3, that is, in the first semiconductor layer 2 and / or the third semiconductor layer 4, the closer the part is to the contact interface with the second semiconductor layer 3, the smaller the etching amount is, so as to improve the etching selectivity between adjacent layers, achieve the effect of suppressing the notch phenomenon, and further improve the squareness of the etched cross-section.

[0081] Please continue to refer to Figure 8 and Fig. 9 In some embodiments, the formation of the first semiconductor layer 2 and the third semiconductor layer 4 also includes: in the process of depositing the first sub-interface layer 22 on the top surface of the first sub-semiconductor layer 21, and / or depositing the third sub-interface layer 42 on the top surface of the second semiconductor layer 3, by controlling the flow rate of the doping precursor, the doping concentration of the first sub-interface layer 22 and / or the third sub-interface layer 42 increases or decreases toward the second semiconductor layer 3.

[0082] Please continue to refer to Figure 8 and Fig. 9 In some embodiments, the doping concentration of the first sub-interface layer 22 and / or the third sub-interface layer 42 increases or decreases linearly toward the second semiconductor layer 3; or the doping concentration of the first sub-interface layer 22 and / or the third sub-interface layer 42 increases or decreases gradiently toward the second semiconductor layer 3.

[0083] Please continue to refer to Figure 8 and Fig. 9 In some embodiments, the doping type of the first semiconductor layer 2 and the third semiconductor layer 4 is P-type; the doping concentration of the first sub-interface layer 22 and / or the third sub-interface layer 42 increases toward the second semiconductor layer 3; or the doping type of the first semiconductor layer 2 and the third semiconductor layer 4 is N-type; the doping concentration of the first sub-interface layer 22 and / or the third sub-interface layer 42 decreases toward the second semiconductor layer 3.

[0084] Please continue to refer to Figure 8 and Fig. 9 In some embodiments, the precursor of the preset deposition process includes a P-type doping precursor; in the process of depositing the first sub-interface layer 22 on the top surface of the first sub-semiconductor layer 21, within the preset time Td3, the flow rate of the P-type doping precursor is controlled to gradually increase, so that the doping concentration of the first sub-interface layer 22 increases toward the direction of the second semiconductor layer 3; and / or in the process of depositing the third sub-interface layer 42 on the top surface of the second semiconductor layer 3, within the preset time Td4, the flow rate of the P-type doping precursor is controlled to gradually decrease, so that the doping concentration of the third sub-interface layer 42 increases toward the direction of the second semiconductor layer 3.

[0085] Please continue to refer to Figure 8 and Fig. 9In the method for preparing the semiconductor structure of the above embodiment, the doping concentration of the first sub-interface layer 22 increases toward the second semiconductor layer 3 by controlling the flow rate of the P-type doping precursor to gradually increase, and the doping concentration of the third sub-interface layer 42 increases toward the second semiconductor layer 3 by controlling the flow rate of the P-type doping precursor to gradually decrease. Since the etching rate of the P-type doping material decreases with increasing doping concentration, the etching rate of the first sub-interface layer 22 and / or the third sub-interface layer 42 decreases toward the second semiconductor layer 3, that is, the closer the etching amount of the first semiconductor layer 2 and / or the third semiconductor layer 4 is to the contact interface with the second semiconductor layer 3, the smaller the etching amount is, so as to improve the etching selectivity between adjacent layers and achieve the effect of suppressing the notch phenomenon, thereby further improving the squareness of the etched cross-section.

[0086] Please continue to refer to Figure 8 and Fig. 9 In some embodiments, the precursor of the preset deposition process includes an N-type doping precursor; in the process of depositing the first sub-interface layer 22 on the top surface of the first sub-semiconductor layer 21, within the preset time Td3, the flow rate of the N-type doping precursor is controlled to gradually decrease, so that the doping concentration of the first sub-interface layer 22 decreases toward the direction of the second semiconductor layer 3; and / or in the process of depositing the third sub-interface layer 42 on the top surface of the second semiconductor layer 3, within the preset time Td4, the flow rate of the N-type doping precursor is controlled to gradually increase, so that the doping concentration of the first sub-interface layer 22 decreases toward the direction of the second semiconductor layer 3.

[0087] Please continue to refer to Figure 8 and Fig. 9 In the method for preparing the semiconductor structure of the above embodiment, the flow rate of the N-type doping precursor is controlled to gradually decrease, so that the doping concentration of the first sub-interface layer 22 decreases toward the direction of the second semiconductor layer 3; and the flow rate of the N-type doping precursor is controlled to gradually increase, so that the doping concentration of the first sub-interface layer 22 decreases toward the direction of the second semiconductor layer 3. Since the etching rate of the N-type doping material decreases with the decrease of the doping concentration, the etching rate of the first sub-interface layer 22 and / or the third sub-interface layer 42 decreases toward the direction of the second semiconductor layer 3, that is, in the first semiconductor layer 2 and / or the third semiconductor layer 4, the closer the part is to the contact interface with the second semiconductor layer 3, the smaller the etching amount is, so as to improve the etching selectivity between adjacent layers, achieve the effect of suppressing the notch phenomenon, and further improve the squareness of the etched cross-section.

[0088] Please continue to refer to Figure 8 and Fig. 9 In some embodiments, 0.5T2>Td3, that is, the thickness of the first sub-interface layer 22 is less than half of the thickness of the first semiconductor layer 2 .

[0089] Please continue to refer to Figure 8 and Fig. 9 In some embodiments, 0.5T3>Td4, that is, the thickness of the third sub-interface layer 42 is less than half of the thickness of the third semiconductor layer 4 .

[0090] Please continue to refer to Figure 8 and Fig. 9 In some embodiments, the isotropic etching process includes an atomic layer etching process and / or a wet-based quasi-atomic layer etching process.

[0091] Please continue to refer to Figure 8 and Fig. 9 , in some embodiments, the first element includes germanium.

[0092] Please continue to refer to Figure 8 and Fig. 9 In some embodiments, when the first semiconductor layer 2 and the third semiconductor layer 4 are both silicon layers, and the second semiconductor layer 3 is a silicon germanium layer, since in the isotropic etching process, the etching rate of the silicon germanium layer increases with the increase of the germanium content, the germanium content in the second interface layer 33 increases in the direction away from the top surface of the middle layer 32, so that the etching rate of the second interface layer 33 gradually increases in the direction away from the top surface of the middle layer 32. That is, the etching rate of the silicon germanium layer gradually increases from the middle layer 32 through the two side interface layers to the contact interface with the adjacent silicon layer, so that the etching amount of the silicon germanium layer closer to the contact interface is greater, so as to form a steeper morphology, so as to achieve the effect of suppressing the arc effect and improving the squareness of the etched cross section.

[0093] And, if Figure 8 As shown in FIG. 1 , when the silicon layer is doped with P-type, since the etching rate of the P-type doped material decreases with increasing doping concentration, the etching rate of the first sub-interface layer 22 and / or the third sub-interface layer 42 decreases toward the silicon germanium layer, that is, the etching amount of the silicon layer on both sides closer to the silicon germanium layer is smaller; accordingly, as shown in FIG. Fig. 9 As shown, when the silicon layer is N-type doped, since the etching rate of the N-type doped material decreases with the decreasing doping concentration, the etching rate of the first sub-interface layer 22 and / or the third sub-interface layer 42 decreases toward the silicon germanium layer, that is, the etching amount of the silicon layer on both sides closer to the silicon germanium layer is smaller, so as to improve the etching selectivity between adjacent layers, achieve the effect of suppressing the notch phenomenon, and further improve the squareness of the etched cross-section.

[0094] Please continue to refer to Figure 8 and Fig. 9In some embodiments, when the material of the first semiconductor layer 2 and the third semiconductor layer 4 is polysilicon, the preset deposition process may be low-pressure chemical vapor deposition. At this time, the low-pressure chemical vapor deposition reactant may be dichlorosilane (SiH2CL2, Dichlorosilane, DCS). Since the silicon content of dichlorosilane is higher than that of trichlorosilane or silicon tetrachloride, using dichlorosilane as the reactant for low-pressure chemical vapor deposition can improve the deposition efficiency of silicon, and the deposition temperature of using dichlorosilane as the reactant for low-pressure chemical vapor deposition is lower than the deposition temperature when other chlorosilanes are used; at the same time, the time required for using dichlorosilane to deposit a thicker semiconductor layer at a reduced temperature is much lower than the time required for using silane; in addition, since the deposition rate of dichlorosilane is less sensitive to temperature than the deposition rate of other chlorosilanes, the deposition rate can be controlled by adjusting the concentration of dichlorosilane in the hydrogen gas flow, which can avoid mechanical inaccuracies caused by bubbling and improve the product quality of the deposition process.

[0095] Please refer to Fig.10 According to some embodiments, a semiconductor structure is provided, the semiconductor structure comprising a substrate 1, and a multilayer stacked structure located on the substrate 1; the stacked structure comprises a first semiconductor layer 2 and a second semiconductor layer 3 stacked in sequence along a first direction, the first semiconductor layer 2 covers the top surface of the substrate 1; the second semiconductor layer 3 has a rectangular groove 5; wherein the second semiconductor layer 3 is a semiconductor layer including a first element; the second semiconductor layer 3 comprises a first interface layer 31 and an intermediate layer 32 arranged in sequence along the first direction, and the content of the first element in the first interface layer 31 decreases or increases in a direction away from the top surface of the substrate 1.

[0096] Please continue to refer to Fig.10 In some embodiments, the stacked structure further includes a third semiconductor layer, which is located on the top surface of the second semiconductor layer; the second semiconductor layer further includes a second interface layer adjacent to the third semiconductor layer; the content of the first element in the second interface layer increases or decreases in a direction away from the top surface of the intermediate layer.

[0097] Please continue to refer to Fig.10 In the semiconductor structure of the above embodiment, since the content of the first element in the second interface layer 33 increases or decreases in the direction away from the top surface of the intermediate layer 32, when the second semiconductor layer 3 is etched by an isotropic etching process, the etching rate of the second interface layer 33 gradually increases in the direction away from the top surface of the intermediate layer 32. That is, the etching rate of the second semiconductor layer 3 from the intermediate layer 32 through the interface layers on both sides to the contact interface with the adjacent semiconductor layer gradually increases, so that the etching amount of the second semiconductor layer 3 closer to the contact interface is greater, so as to form a steeper morphology, so as to achieve the effect of suppressing the arc effect and improving the squareness of the etched cross section, thereby improving the device performance and reliability.

[0098] Please continue to refer to Fig.10 In some embodiments, the semiconductor structure further includes a channel layer and a gate structure, the channel layer is formed based on the rectangular groove 5; the gate structure is located at least on one side of the channel layer; the first semiconductor layer 2 is a drain structure, the third semiconductor layer 4 is a source structure, and the drain structure and the source structure are respectively located on opposite sides of the channel layer along the first direction. Thus, a vertical channel transistor is formed. Since the drain structure of the vertical channel transistor is located at the bottom of the transistor, it does not need to be directly led out from the surface of the transistor, making it easier to form isolation between transistors in the array, thereby reducing the power consumption of the semiconductor device, and being able to reduce the volume of the semiconductor structure while ensuring the storage capacity of the semiconductor device, thereby improving the response speed and storage density of the semiconductor device.

[0099] Please continue to refer to Figure 8 In some embodiments, the gate structure surrounds the channel layer, thereby forming a vertical gate all around transistor (VGAA transistor), thereby further reducing the size of the semiconductor structure.

[0100] Please continue to refer to Figure 8 In some embodiments, the gate structure includes a protective layer, a sidewall, and a gate dielectric layer, a gate conductive layer, and a cap layer stacked in sequence; the protective layer covers the exposed surface of the cap layer, the sidewalls of the gate dielectric layer, and the sidewalls of the gate conductive layer; the sidewalls are located on the sidewalls of the protective layer. As the key dimensions of the device are shrinking with the development of integrated circuit technology, the width of the depletion region extends into the channel, resulting in a narrowing of the effective channel length and an increase in the equivalent electric field on the channel; as the drain voltage increases, the width of the depletion region increases, but the width of the depletion region is not enough to offset the potential difference, resulting in an increase in channel carrier collisions to generate new electron-hole pairs, which in turn leads to a hot carrier injection effect. Under the action of a strong electric field, the carriers form high-energy carriers, become hot carriers, enter the gate or substrate to form current, thereby inducing a latch effect and causing the device to fail. By forming a sidewall on the sidewall of the protective layer, it is possible to prevent a large dose of source and drain injection from being too close to the channel, thereby causing the channel to be too short or even the source and drain to be connected, thereby avoiding the hot carrier injection effect and improving product reliability and yield.

[0101] Please continue to refer to Figure 8 In some embodiments, the material of the gate conductive layer may include doped polysilicon, titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium nitride silicon or any combination thereof; the material of the gate dielectric layer 23 may include silicon oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide or any combination thereof.

[0102] In some embodiments, a memory is provided, comprising the above semiconductor structure. Since a semiconductor structure with better performance and reliability is adopted, the memory of this embodiment has more beneficial performance and higher reliability.

[0103] In some embodiments, an electronic device is provided, comprising the above-mentioned memory. Since a memory with better performance and reliability is used, the electronic device of this embodiment has more beneficial performance and higher reliability.

[0104] To implement all or part of the processes in the above-mentioned embodiments, the relevant hardware can be instructed by a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present disclosure can include non-volatile and / or volatile memory.

[0105] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

[0106] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0107] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0108] The above-mentioned embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the disclosed patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the disclosed patent shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The method comprises: providing a substrate; A multilayer stacked structure is formed on the substrate; the stacked structure comprises a first semiconductor layer and a second semiconductor layer stacked in sequence along a first direction, the first semiconductor layer covers the top surface of the substrate; the second semiconductor layer is a semiconductor layer comprising a first element; wherein the second semiconductor layer comprises a first interface layer and an intermediate layer arranged in sequence along the first direction, and the content of the first element in the first interface layer decreases or increases in a direction away from the top surface of the substrate; The second semiconductor layer is etched using an isotropic etching process to obtain a rectangular groove.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The stacked structure further includes a third semiconductor layer, and the third semiconductor layer is located on the top surface of the second semiconductor layer; The second semiconductor layer further includes a second interface layer adjacent to the third semiconductor layer; the content of the first element in the second interface layer increases or decreases along a direction away from the top surface of the intermediate layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: A multi-layer stacked structure is formed on the top surface of the substrate, comprising: After the first semiconductor layer is formed on the top surface of the substrate, within a preset time T1, during the process of depositing the second semiconductor layer on the top surface of the first semiconductor layer, by controlling the flow rate of the first element precursor, the content of the first element in the first interface layer decreases or increases in a direction away from the top surface of the substrate, and the content of the first element in the second interface layer increases or decreases in a direction away from the top surface of the intermediate layer.

4. The method for preparing a semiconductor structure according to claim 2, characterized in that: The content of the first element in the intermediate layer is within a preset range.

5. The method for preparing a semiconductor structure according to any one of claims 2 to 4, characterized in that: The content of the first element in the first interface layer decreases or increases linearly or gradually in a direction away from the top surface of the substrate; and / or The content of the first element in the second interface layer increases or decreases linearly or gradually in a direction away from the top surface of the intermediate layer.

6. The method for preparing a semiconductor structure according to claim 3, characterized in that: Depositing a second semiconductor layer on the top surface of the first semiconductor layer within a preset time T1, comprising: Within a preset time Td1, controlling the flow rate of the first element precursor to gradually increase or decrease, so that the content of the first element in the first interface layer decreases or increases in a direction away from the top surface of the substrate; and Within the preset time Td2, the flow rate of the first element precursor is controlled to gradually decrease or increase, so that the content of the first element in the second interface layer increases or decreases in a direction away from the top surface of the intermediate layer.

7. The method for preparing a semiconductor structure according to claim 3, characterized in that: Forming the first semiconductor layer and the third semiconductor layer includes: Within a preset time T2, a first sub-semiconductor layer and a first sub-interface layer are sequentially stacked along the first direction on the top surface of the substrate using a preset deposition process, wherein the first sub-semiconductor layer covers the substrate, and the second semiconductor layer covers the first sub-interface layer; the doping concentration of the first sub-interface layer increases or decreases toward the direction of the second semiconductor layer; the first sub-semiconductor layer and the first sub-interface layer constitute the first semiconductor layer; and / or Within the preset time T3, a preset deposition process is used to form a third sub-semiconductor layer and a third sub-interface layer stacked in sequence along the first direction on the top surface of the second semiconductor layer, and the third sub-interface layer covers the second semiconductor layer; the doping concentration of the third sub-interface layer increases or decreases toward the direction of the second semiconductor layer, and the third sub-semiconductor layer and the third sub-interface layer constitute the third semiconductor layer.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: The doping concentration of the first semiconductor sub-layer and / or the third semiconductor sub-layer is within a preset range.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The first semiconductor layer and the third semiconductor layer are formed, further comprising: During the process of depositing the first sub-interface layer on the top surface of the first sub-semiconductor layer and / or depositing the third sub-interface layer on the top surface of the second semiconductor layer, the doping concentration of the first sub-interface layer and / or the third sub-interface layer increases or decreases toward the second semiconductor layer by controlling the flow rate of the doping precursor.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that: The doping concentration of the first sub-interface layer and / or the third sub-interface layer increases or decreases linearly toward the second semiconductor layer; or The doping concentration of the first sub-interface layer and / or the third sub-interface layer increases or decreases gradually toward the second semiconductor layer.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that: The doping type of the first semiconductor layer and the third semiconductor layer is P type; the doping concentration of the first sub-interface layer and / or the third sub-interface layer increases toward the second semiconductor layer; or The doping type of the first semiconductor layer and the third semiconductor layer is N-type; the doping concentration of the first sub-interface layer and / or the third sub-interface layer decreases toward the second semiconductor layer.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that: The precursor of the preset deposition process includes a P-type doping precursor; During the process of depositing the first sub-interface layer on the top surface of the first sub-semiconductor layer, within a preset time Td3, the flow rate of the P-type doping precursor is controlled to gradually increase so that the doping concentration of the first sub-interface layer increases gradually toward the second semiconductor layer; and / or During the deposition of the third sub-interface layer on the top surface of the second semiconductor layer, within the preset time Td4, the flow rate of the P-type doping precursor is controlled to gradually decrease so that the doping concentration of the third sub-interface layer increases toward the second semiconductor layer.

13. The method for preparing a semiconductor structure according to claim 11, characterized in that: The precursor of the preset deposition process includes an N-type doping precursor; During the process of depositing the first sub-interface layer on the top surface of the first sub-semiconductor layer, within a preset time Td3, the flow rate of the N-type doping precursor is controlled to gradually decrease so that the doping concentration of the first sub-interface layer decreases toward the second semiconductor layer; and / or During the deposition of the third sub-interface layer on the top surface of the second semiconductor layer, within the preset time Td4, the flow rate of the N-type doping precursor is controlled to gradually increase so that the doping concentration of the first sub-interface layer decreases toward the second semiconductor layer.

14. The method for preparing a semiconductor structure according to any one of claims 6 to 13, characterized in that: The isotropic etching process includes an atomic layer etching process and / or a quasi-atomic layer etching process based on a wet method.

15. The method for preparing a semiconductor structure according to any one of claims 6 to 13, characterized in that: The first element includes germanium.

16. The method for preparing a semiconductor structure according to any one of claims 6 to 13, characterized in that: Includes at least one of the following features: 0.5T1>Td1; 0.5T1>Td2; 0.5T2>Td3; 0.5T3>Td4; T1>Td1+Td2.

17. A semiconductor structure, characterized in that: It comprises a substrate and a multi-layer stacked structure located on the substrate; the stacked structure comprises a first semiconductor layer and a second semiconductor layer stacked in sequence along a first direction, and the first semiconductor layer covers the top surface of the substrate; The second semiconductor layer has a rectangular groove; Among them, the second semiconductor layer is a semiconductor layer including a first element; the second semiconductor layer includes a first interface layer and an intermediate layer arranged in sequence along the first direction, and the content of the first element in the first interface layer decreases or increases along the direction away from the top surface of the substrate.

18. The semiconductor structure according to claim 17, characterized in that: The stacked structure further includes a third semiconductor layer, and the third semiconductor layer is located on the top surface of the second semiconductor layer; The second semiconductor layer further includes a second interface layer adjacent to the third semiconductor layer; the content of the first element in the second interface layer increases or decreases along a direction away from the top surface of the intermediate layer.

19. The semiconductor structure according to claim 18, characterized in that The semiconductor structure further includes a channel layer and a gate structure, wherein the channel layer is formed based on the rectangular groove; and the gate structure is located at least on one side of the channel layer; The first semiconductor layer is a drain structure, the third semiconductor layer is a source structure, and the drain structure and the source structure are respectively located on two opposite sides of the channel layer along the first direction.

20. The semiconductor structure according to claim 19, characterized in that The gate structure surrounds the channel layer.

21. A memory, characterized in that: include: The semiconductor structure according to any one of claims 17 to 20.

22. An electronic device, characterized in that: include: The memory of claim 21.

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