Transistor and method of manufacturing the same

Abstract

The disclosure provides a transistor and a preparation method thereof, and belongs to the field of power electronics. The transistor comprises an epitaxial wafer, a source electrode, a drain electrode and a gate electrode. The epitaxial wafer comprises a channel layer and a barrier layer, and has an active region and an inactive region. The drain electrode is located on the surface of the barrier layer away from the channel layer, and is located in the active region. The drain electrode is electrically connected to the channel layer through a first through hole. The source electrode and the gate electrode are both located on the surface of the barrier layer away from the channel layer. A first part of the source electrode is electrically connected to the channel layer through a second through hole, and a second part of the source electrode extends to one side of the channel layer away from the barrier layer through a first via. A first part of the gate electrode is connected to the barrier layer, and a second part of the gate electrode extends to one side of the channel layer away from the barrier layer through a second via. The embodiments of the disclosure improve the applicability of the transistor.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of power electronics, and in particular to a transistor and a preparation method thereof. BACKGROUND

[0002] A high electron mobility transistor (HEMT) is a kind of heterojunction field effect transistor, which is widely used in various electrical appliances.

[0003] In the related art, the transistor includes, in sequence, a channel layer and a barrier layer stacked on a substrate, a source and a drain penetrating the barrier layer and connected with the channel layer, and a gate arranged between the source and the drain in the barrier layer. The channel layer and the barrier layer are GaN layer and AlGaN layer respectively. A high-concentration two-dimensional electron gas channel can be formed at the AlGaN / GaN heterojunction interface. The high-concentration and high-electron-mobility two-dimensional electron gas channel is the biggest advantage of gallium nitride high electron mobility transistor compared with traditional field effect transistor.

[0004] In order to utilize the advantages of the two-dimensional electron gas channel, the transistor is usually designed as a planar structure, and the planar structure of the transistor distributes the source, the drain and the gate on the same side of the barrier layer. However, the planar structure of the transistor has poor compatibility with traditional electronic devices, resulting in poor applicability of the transistor. SUMMARY

[0005] The embodiments of the present disclosure provide a transistor and a preparation method thereof, which can utilize the advantages of the two-dimensional electron gas channel and design the transistor as a vertical structure to meet the applicability of the transistor. The technical solutions are as follows:

[0006] In one aspect, the present disclosure provides a transistor, comprising: an epitaxial wafer, a source electrode, a drain electrode, and a gate electrode; the epitaxial wafer comprises a channel layer and a barrier layer stacked in sequence, the epitaxial wafer has an active region and an inactive region, the active region and the inactive region are insulated, the inactive region has a first via and a second via penetrating the epitaxial wafer; the drain electrode is located on a surface of the barrier layer away from the channel layer, and the drain electrode is located in the active region, the barrier layer has a first via exposing the channel layer, and the drain electrode is electrically connected to the channel layer through the first via; the source electrode and the gate electrode are both located on a surface of the barrier layer away from the channel layer, a first part of the source electrode is located in the active region, a second part of the source electrode is located in the inactive region, the barrier layer further has a second via exposing the channel layer, the first part of the source electrode is electrically connected to the channel layer through the second via, and the second part of the source electrode extends to a side of the channel layer away from the barrier layer through the first via; a first part of the gate electrode is located in the active region, a second part of the gate electrode is located in the inactive region, the first part of the gate electrode is connected to the barrier layer, and the second part of the gate electrode extends to a side of the channel layer away from the barrier layer through the second via.

[0007] Optionally, the epitaxial wafer further has an isolation channel region, the isolation channel region surrounds the active region, and the isolation channel region is located between the active region and the inactive region.

[0008] Optionally, the isolation channel region is implanted with N+ ions.

[0009] Optionally, the transistor further comprises a dielectric layer and a drain pad, the dielectric layer is located on a surface of the barrier layer away from the channel layer, and the dielectric layer covers the drain electrode, the source electrode, and the gate electrode, a surface of the dielectric layer away from the barrier layer has a via exposing the drain electrode, and the drain pad is electrically connected to the drain electrode through the via.

[0010] Optionally, the transistor further comprises a bonding metal layer and a conductive substrate, the bonding metal layer is located on a surface of the dielectric layer away from the barrier layer and is electrically connected to the drain electrode through the via, the conductive substrate is located on a surface of the bonding metal layer away from the dielectric layer, and the drain pad is located on a surface of the conductive substrate away from the dielectric layer.

[0011] Optionally, the transistor further comprises a substrate, a source pad and a gate pad, the substrate is located on a surface of the channel layer away from the barrier layer, the surface of the substrate has a third via hole and a fourth via hole exposing the ineffective area; the source pad and the gate pad are both located on a surface of the substrate away from the channel layer, the source pad is connected with the source electrode through the third via hole and the first via hole in sequence, and the gate pad is connected with the gate electrode through the fourth via hole and the second via hole in sequence.

[0012] Optionally, the epitaxial wafer further comprises a p-type layer, the p-type layer is located on a surface of the barrier layer away from the channel layer, the source electrode and the drain electrode are both arranged spaced apart from the p-type layer, and the gate electrode is located on a surface of the p-type layer away from the barrier layer; in the active area, the orthogonal projection of the gate electrode on the surface of the barrier layer is located within the orthogonal projection of the p-type layer on the surface of the barrier layer.

[0013] Optionally, a first part of the source electrode is in a strip shape, a second part of the source electrode is in a block shape, and one end of the first part of the source electrode is connected with the second part of the source electrode; the second via hole is in a strip shape, and the orthogonal projection of the second via hole on the surface of the barrier layer is located within the orthogonal projection of the first part of the source electrode on the surface of the barrier layer; a first part of the gate electrode is in a strip shape, a second part of the gate electrode is in a block shape, and one end of the first part of the gate electrode is connected with the second part of the gate electrode.

[0014] Optionally, the drain electrode is in a strip shape, and the first via hole is in a strip shape, and the orthogonal projection of the first via hole on the surface of the barrier layer is located within the orthogonal projection of the first part of the drain electrode on the surface of the barrier layer.

[0015] In another aspect, the disclosure provides a preparation method of a transistor, the preparation method comprising: forming an epitaxial wafer on a substrate, the epitaxial wafer comprising a channel layer and a barrier layer stacked in sequence on the substrate, the barrier layer having a first via hole and a second via hole exposing the channel layer, the epitaxial wafer having an active area and an ineffective area, the active area and the ineffective area being insulated, and the ineffective area having a first via hole and a second via hole penetrating through the epitaxial wafer; forming a drain electrode, a source electrode and a gate electrode on a surface of the barrier layer away from the channel layer, the drain electrode being located in the active area, the drain electrode being electrically connected with the channel layer through the first via hole, a first part of the source electrode being located in the active area, a second part of the source electrode being located in the ineffective area, the source electrode of the first part being electrically connected with the channel layer through the second via hole, and the source electrode of the second part extending to a side of the channel layer away from the barrier layer through the first via hole.

[0016] The technical scheme provided by the embodiments of the present disclosure has at least the following beneficial effects:

[0017] The embodiments of the present disclosure provide a transistor, in which the drain electrode, the source electrode and the gate electrode are all arranged on the surface of the barrier layer away from the channel layer. The source electrode and the gate electrode both cross the active region and the invalid region of the epitaxial wafer. The source electrode in the first part of the active region is electrically connected to the channel layer through the second through hole, and the source electrode in the second part of the invalid region extends to the side of the channel layer away from the barrier layer through the first via. In this way, the drain electrode and the source electrode are distributed on opposite sides of the epitaxial wafer. Meanwhile, the gate electrode in the first part of the active region is connected to the barrier layer, and the gate electrode in the second part of the invalid region extends to the side of the channel layer away from the barrier layer through the second via. In this way, the drain electrode and the gate electrode are distributed on opposite sides of the epitaxial wafer. That is, the source electrode and the gate electrode are arranged on the side of the channel layer away from the barrier layer, and the drain electrode is arranged on the surface of the barrier layer away from the channel layer, so as to form a vertical structure transistor.

[0018] Meanwhile, when the external power supply is powered on to the source electrode and the gate electrode, the current will cross the channel layer from the invalid region of the active layer. In this way, the current injected from the source electrode or the gate electrode will not enter the channel layer from the side of the channel layer away from the barrier layer, but will cross from the invalid region to the active region, and then enter the channel layer from the side of the channel layer close to the barrier layer through the source electrode or the gate electrode. The drain electrode is located on the surface of the barrier layer away from the channel layer, and the drain electrode can be electrically connected to the channel layer through the first through hole, so that the current injected by the drain electrode can also enter the channel layer from the side of the channel layer close to the barrier layer. Since the source electrode and the drain electrode are both injected from the same surface of the channel layer, rather than from opposite sides of the channel layer, a high-concentration two-dimensional electron gas channel can be formed at the heterojunction interface of the channel layer and the barrier layer, so that the transistor can take advantage of the two-dimensional electron gas channel. In this way, the transistor not only takes advantage of the two-dimensional electron gas channel, but also forms a vertical structure transistor to reduce the difficulty of application of the transistor. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings needed to be used in the embodiments description. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art without any creative effort based on these drawings.

[0020] Figure 1 is a top view of a transistor provided by the embodiments of the present disclosure;

[0021] Figure 2 is a structural schematic diagram of a transistor provided by the embodiments of the present disclosure;

[0022] Figure 3 is a structure schematic diagram of a transistor provided by an embodiment of the present disclosure.

[0023] Figure 4 is a flowchart of a preparation method of a transistor provided by an embodiment of the present disclosure.

[0024] The following marks in the drawings are explained as follows:

[0025] 10, substrate; 11, third via hole; 12, fourth via hole;

[0026] 20, epitaxial wafer; 210, active region; 220, isolation channel region; 230, invalid region;

[0027] 201, first via hole; 202, second via hole;

[0028] 21, channel layer; 22, barrier layer; 221, first through hole; 222, second through hole; 23, p-type layer;

[0029] 31, source electrode; 32, drain electrode; 33, gate electrode;

[0030] 40, dielectric layer;

[0031] 51, source pad; 52, drain pad; 53, gate pad;

[0032] 61, bonding metal layer; 62, conductive substrate. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the following will combine the drawings to further describe the embodiments of the present disclosure in detail.

[0034] Unless otherwise defined, technical terms or scientific terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first", "second", "third", and the like, as used in the description and the claims of this disclosure do not have any quantitatively meaning, unless otherwise defined, but are used only to identify different components. Also, the terms "one", "another", "an" or the like, as used in the description and the claims of this disclosure do not have any quantitatively meaning, unless otherwise defined, but are used only to identify at least one. The terms "including", "containing" or the like, as used in the description and the claims of this disclosure, mean that elements or objects preceding the word "including" or "containing" encompasses the elements or objects listed after the word "including" or "containing" and equivalents thereof, and does not exclude other elements or objects. The terms "connected", "coupled" or the like, as used in the description and the claims of this disclosure, are not limited to physical or mechanical connections or couplings, but can include electrical connections or couplings, whether direct or indirect. The terms "upper", "lower", "left", "right", "top", "bottom", or the like, as used in the description and the claims of this disclosure, are only used to represent relative positions, and can change when the absolute positions of the described objects change.

[0035] Figure 1 is a top view of a transistor provided by an embodiment of the disclosure. Figure 2 is a structural schematic diagram of a transistor provided by an embodiment of the disclosure. Figure 3 is a structural schematic diagram of a transistor provided by an embodiment of the disclosure. Figure 2 is a cross-sectional view along the AA section line in Figure 1 . Figure 3 is a cross-sectional view along the BB section line in Figure 1 .

[0036] As shown in Figure 1 , 2 , the transistor comprises an epitaxial wafer 20, a source electrode 31, a drain electrode 32, and a gate electrode 33; the epitaxial wafer 20 comprises a channel layer 21 and a barrier layer 22 which are stacked in sequence, and the epitaxial wafer 20 has an active region 210 and an inactive region 230, the active region 210 and the inactive region 230 are insulated, and the inactive region 230 has a first via hole 201 and a second via hole 202 which penetrate through the epitaxial wafer 20.

[0037] As shown in Figure 2 , the drain electrode 32 is located on a surface of the barrier layer 22 away from the channel layer 21, and the drain electrode 32 is located in the active region 210, the barrier layer 22 has a first through hole 221 exposing the channel layer 21, and the drain electrode 32 is electrically connected with the channel layer 21 through the first through hole 221.

[0038] As shown in Figures 1 to 3As shown, the source electrode 31 and the gate electrode 33 are both located on the surface of the barrier layer 22 away from the channel layer 21. The first part of the source electrode 31 is located in the active region 210, and the second part of the source electrode 31 is located in the inactive region 230. The barrier layer 22 also has a second via 222 that exposes the channel layer 21. The first part of the source electrode 31 is electrically connected to the channel layer 21 through the second via 222, and the second part of the source electrode 31 extends to the side of the channel layer 21 away from the barrier layer 22 through the first via 201.

[0039] like Figures 1 to 3 As shown, the first part of the gate electrode 33 is located in the active region 210, and the second part of the gate electrode 33 is located in the inactive region 230. The first part of the gate electrode 33 is connected to the barrier layer 22, and the second part of the gate electrode 33 extends to the side of the channel layer 21 away from the barrier layer 22 through the second via 202.

[0040] In the transistor provided in this embodiment, the drain electrode 32, source electrode 31, and gate electrode 33 are all disposed on the surface of the barrier layer 22 away from the channel layer 21. The source electrode 31 and the gate electrode 33 both span the active region 210 and the inactive region 230 of the epitaxial wafer 20. The source electrode 31 is electrically connected to the channel layer 21 through a second via 222 in the first part of the active region 210, and extends to the side of the channel layer 21 away from the barrier layer 22 through a first via 201 in the second part of the inactive region 230. This allows the drain electrode 32 and the source electrode 31 to be distributed on opposite sides of the epitaxial wafer 20. Simultaneously, the gate electrode 33 is connected to the barrier layer 22 in the first part of the active region 210, and extends to the side of the channel layer 21 away from the barrier layer 22 through a second via 202 in the second part of the inactive region 230. This also allows the drain electrode 32 and the gate electrode 33 to be distributed on opposite sides of the epitaxial wafer 20. That is, the source electrode 31 and the gate electrode 33 are disposed on the side of the channel layer 21 away from the barrier layer 22, while the drain electrode 32 is disposed on the side of the barrier layer 22 away from the channel layer 21, so as to form a transistor with a vertical structure.

[0041] Simultaneously, when an external power source supplies power to the source electrode 31 and the gate electrode 33, the current will cross the channel layer 21 from the inactive region 230 of the active layer. This prevents the current injected from the source electrode 31 or the gate electrode 33 from entering the channel layer 21 on the side of the channel layer 21 away from the barrier layer 22. Instead, it crosses from the inactive region 230 to the active region 210 and then enters the channel layer 21 through the source electrode 31 or the gate electrode 33 on the side of the channel layer 21 closest to the barrier layer 22. The drain electrode 32 is located on the surface of the barrier layer 22 away from the channel layer 21, and the drain electrode 32 can be electrically connected to the channel layer 21 through the first via 221, so that the current injected by the drain electrode 32 can also enter the channel layer 21 from the side of the channel layer 21 closest to the barrier layer 22. Because both the source electrode 31 and the drain electrode 32 are injected from the same surface of the channel layer 21, rather than from opposite sides of the channel layer 21, a high-concentration two-dimensional electron gas channel can be formed at the heterojunction interface between the channel layer 21 and the barrier layer 22. This allows the transistor to utilize the advantages of the two-dimensional electron gas channel. This not only allows the transistor to utilize the advantages of the two-dimensional electron gas channel but also creates a vertically structured transistor, reducing the difficulty of transistor application.

[0042] For example, the channel layer 21 is a GaN layer and the barrier layer 22 is an AlGaN layer.

[0043] Optionally, such as Figure 1 As shown, the epitaxial wafer 20 also has an isolation channel region 220, which surrounds the active region 210 and is located between the active region 210 and the inactive region 230.

[0044] In this embodiment, the active region 210 is the functional region of the transistor, and the inactive region 230 is a redundant region. The active region 210 and the inactive region 230 are isolated by setting an isolation channel region 220. In this way, the redundant inactive region 230 is used to allow the source electrode 31 to extend to the side of the channel layer 21 away from the barrier layer 22, so that the drain electrode 32 and the source electrode 31 are distributed on opposite sides of the epitaxial wafer 20, and the source electrode 31 is prevented from being electrically connected to the channel layer 21 when it penetrates the epitaxial wafer 20. Similarly, the drain electrode 32 and the gate electrode 33 can also be distributed on opposite sides of the epitaxial wafer 20, and the source electrode 31 is prevented from being electrically connected to the channel layer 21 when it penetrates the epitaxial wafer 20, thus forming a vertical transistor structure.

[0045] Optionally, N+ ions are injected into the isolation channel region 220. By injecting N+ ions into the isolation channel region 220, the active region 210 and the ineffective region 230 can be isolated, thereby forming a five-effect region that is insulated from the active region 210.

[0046] For example, the concentration of N+ ions injected into the isolation channel region 220 can be greater than or equal to 5 × 10⁻⁶. 14cm -3 .

[0047] Optionally, as shown in Figure 2 , the transistor further comprises a dielectric layer 40 and a drain pad 52, the dielectric layer 40 is located on the surface of the barrier layer 22 away from the channel layer 21, and the dielectric layer 40 covers the drain electrode 32, the source electrode 31 and the gate electrode 33, the surface of the dielectric layer 40 away from the barrier layer 22 has a through hole exposing the drain electrode 32, and the drain pad 52 is electrically connected with the drain electrode 32 through the through hole.

[0048] Illustratively, the dielectric layer 40 is a silicon oxide layer. The silicon oxide layer covers the drain electrode 32, the source electrode 31 and the gate electrode 33 to protect the drain electrode 32, the source electrode 31 and the gate electrode 33, and the silicon oxide layer also has an insulating effect to prevent short circuit between the drain electrode 32, the source electrode 31 and the gate electrode 33.

[0049] In the above implementation, the drain pad 52 is arranged above the dielectric layer 40 to prevent the drain pad 52 from short circuiting with the gate electrode 33 or the source electrode 31, thereby improving the reliability of the transistor.

[0050] Illustratively, the drain pad 52 comprises at least one of a Ti layer, an Al layer, a Pt layer, a Ni layer and an Au layer.

[0051] The above metal material has good heat dissipation performance, therefore, the drain pad 52 prepared by using the above material also has good heat dissipation performance, which can improve the heat dissipation effect of the transistor.

[0052] Optionally, the drain pad 52 comprises a first Ti layer, an Al layer, a second Ti layer, a Pt layer, a Ni layer and an Au layer which are stacked in sequence.

[0053] Optionally, as shown in Figure 2 , the transistor further comprises a bonding metal layer 61 and a conductive substrate 62, the bonding metal layer 61 is located on the surface of the dielectric layer 40 away from the barrier layer 22 and is electrically connected with the drain electrode 32 through the through hole, and the conductive substrate 62 is located on the surface of the bonding metal layer 61 away from the dielectric layer 40, and the drain pad 52 is located on the surface of the conductive substrate 62 away from the dielectric layer 40.

[0054] Illustratively, the conductive substrate 62 can be a silicon substrate 10.

[0055] Wherein, the silicon substrate 10 is a conductive substrate 10, the bonding metal is used to connect the silicon substrate 10 and the drain electrode 32, and the drain pad 52 is arranged on the surface of the silicon substrate 10, so that the drain pad 52 is electrically connected with the drain electrode 32 through the silicon substrate 10.

[0056] The conductive substrate 62 can be directly electrically connected with the drain electrode 32 through the bonding metal. When the drain electrode pad 52 is prepared, the drain electrode pad 52 and the drain electrode 32 can be electrically connected by being laid on the conductive substrate 62, so that the difficulty of preparing the drain electrode pad 52 is reduced.

[0057] Optionally, as shown in Figure 3 The transistor further includes a substrate 10, a source electrode pad 51 and a gate electrode pad 53. The substrate 10 is located on a surface of the channel layer 21 away from the barrier layer 22. The surface of the substrate 10 has a third via hole 11 and a fourth via hole 12 exposing the inactive region 230.

[0058] As shown in Figure 3 The source electrode pad 51 and the gate electrode pad 53 are both located on a surface of the substrate 10 away from the channel layer 21. The source electrode pad 51 is connected with the source electrode 31 through the third via hole 11 and the first via hole 201 in sequence. The gate electrode pad 53 is connected with the gate electrode 33 through the fourth via hole 12 and the second via hole 202 in sequence.

[0059] Exemplarily, the substrate 10 can be a sapphire substrate 10 or other substrate 10 having an insulating effect.

[0060] The substrate 10 is arranged on the surface of the channel layer 21 away from the barrier layer 22 to insulate the channel layer 21 from the source electrode pad 51 and the gate electrode pad 53. The source electrode pad 51 and the gate electrode pad 53 are prevented from being directly electrically connected with the channel layer 21 on the surface of the channel layer 21 away from the barrier layer 22.

[0061] Meanwhile, the substrate 10 arranged on the surface of the channel layer 21 can also prevent dangling bonds generated after the GaN channel layer 21 is broken.

[0062] In the above implementation, the third via hole 11 and the fourth via hole 12 can be arranged on the surface of the substrate 10 to pass through the substrate 10, so that the source electrode pad 51 and the gate electrode pad 53 arranged on the substrate 10 can be connected with corresponding electrodes through the via holes.

[0063] Optionally, as shown in Figure 2 The epitaxial wafer 20 further includes a p-type layer 23. The p-type layer 23 is located on a surface of the barrier layer 22 away from the channel layer 21. The source electrode 31 and the drain electrode 32 are arranged away from the p-type layer 23. The gate electrode 33 is located on a surface of the p-type layer 23 away from the barrier layer 22.

[0064] The p-type layer 23 is arranged between the gate electrode 33 and the barrier layer 22, so that the gate electrode 33 forms a Schottky contact with the p-type layer 23.

[0065] Exemplarily, the p-type layer 23 is a p-type GaN layer.

[0066] As shown in Figure 1 , 2 , in the active region 210, the orthogonal projection of the gate electrode 33 on the surface of the barrier layer 22 is located within the orthogonal projection of the p-type layer 23 on the surface of the barrier layer 22.

[0067] Let the gate electrode 33 in the active region 210 be completely within the p-type layer 23, which can avoid the gate electrode 33 across the peripheral edge of the p-type layer 23 and contact the barrier layer 22, preventing the gate electrode 33 from being directly electrically connected with the barrier layer 22 or the channel layer 21.

[0068] Exemplarily, as shown in Figure 3 , the p-type layer 23 is in a strip shape, and the p-type layer 23 extends from the active region 210 to the inactive region 230, which can ensure that in the inactive region 230, the gate electrode 33 is always covered above the p-type layer 23.

[0069] Optionally, as shown in Figure 1 , the first part of the source electrode 31 is in a strip shape, the second part of the source electrode 31 is in a block shape, and one end of the first part of the source electrode 31 is connected with the second part of the source electrode 31. The second through hole 222 is in a strip shape, and the orthogonal projection of the second through hole 222 on the surface of the barrier layer 22 is located within the orthogonal projection of the first part of the source electrode 31 on the surface of the barrier layer 22.

[0070] The source electrode 31 in a strip shape is arranged in the active region 210, so that the current passes through the source electrode 31 in a strip shape across the epitaxial wafer 20, making the current transmission more uniform. The source electrode 31 in a block shape is arranged in the inactive region 230, which can increase the area of the source electrode 31 receiving the current, facilitating the current injection.

[0071] Optionally, as shown in Figure 1 , the first part of the gate electrode 33 is in a strip shape, the second part of the gate electrode 33 is in a block shape, and one end of the first part of the gate electrode 33 is connected with the second part of the gate electrode 33.

[0072] The gate electrode 33 in a strip shape is arranged in the active region 210, so that the current passes through the gate electrode 33 in a strip shape across the epitaxial wafer 20, making the current transmission more uniform. The gate electrode 33 in a block shape is arranged in the inactive region 230, which can increase the area of the gate electrode 33 receiving the current, facilitating the current injection.

[0073] Optionally, as shown in Figure 1 , the drain electrode 32 is in a strip shape, and the first through hole 221 is in a strip shape, and the orthogonal projection of the first through hole 221 on the surface of the barrier layer 22 is located within the orthogonal projection of the first part of the drain electrode 32 on the surface of the barrier layer 22.

[0074] The drain electrode 32 in a strip shape is arranged in the active region 210, so that the current is allowed to pass through the drain electrode 32 in the strip shape across the epitaxial wafer 20, and the current transmission is more uniform.

[0075] Figure 4 is a flowchart of a preparation method of a transistor provided by an embodiment of the present disclosure. As shown in the figure, the preparation method comprises the following steps. Figure 4

[0076] S11: forming an epitaxial wafer on a substrate.

[0077] Exemplarily, the substrate is a sapphire substrate. The sapphire substrate has a relatively high light transmittance, i.e., the substrate is a transparent substrate. Moreover, the sapphire material is relatively hard and has a stable chemical property, so that the transistor has good stability.

[0078] In the step S11, the epitaxial wafer comprises a channel layer and a barrier layer which are sequentially stacked on the substrate, the barrier layer has a first through hole and a second through hole which expose the channel layer, and the epitaxial wafer has an active region and an inactive region which are insulated, and the inactive region has a first via hole and a second via hole which pass through the epitaxial wafer.

[0079] S12: forming a drain electrode, a source electrode and a gate electrode on a surface of the barrier layer away from the channel layer.

[0080] In the step S12, the drain electrode is located in the active region, the drain electrode is electrically connected to the channel layer through the first through hole, a first part of the source electrode is located in the active region, a second part of the source electrode is located in the inactive region, the first part of the source electrode is electrically connected to the channel layer through the second through hole, and the second part of the source electrode extends to a side of the channel layer away from the barrier layer through the first via hole.

[0081] In the preparation method, the drain electrode, the source electrode and the gate electrode are all arranged on the surface of the barrier layer away from the channel layer. The source electrode and the gate electrode both span the active region and the inactive region of the epitaxial wafer, the first part of the source electrode located in the active region is electrically connected to the channel layer through the second through hole, the second part of the source electrode located in the inactive region extends to the side of the channel layer away from the barrier layer through the first via hole, so that the drain electrode and the source electrode are distributed on opposite sides of the epitaxial wafer; meanwhile, the first part of the gate electrode located in the active region is connected to the barrier layer, and the second part of the gate electrode located in the inactive region extends to the side of the channel layer away from the barrier layer through the second via hole, so that the drain electrode and the gate electrode are distributed on opposite sides of the epitaxial wafer. That is, the source electrode and the gate electrode are arranged on the side of the channel layer away from the barrier layer, and the drain electrode is arranged on the side of the barrier layer away from the channel layer, so as to form a transistor with a vertical structure.

[0082] ​Meanwhile, when the external power supply is connected to the source electrode and the gate electrode, the current will cross the channel layer from the inactive region of the active layer, so that the current injected from the source electrode or the gate electrode will not enter the channel layer on the side of the channel layer away from the barrier layer, but will cross the active region from the inactive region and then enter the channel layer from the side of the channel layer close to the barrier layer through the source electrode or the gate electrode. The drain electrode is located on the surface of the barrier layer away from the channel layer, and the drain electrode can be electrically connected through the first through hole and the channel layer, so that the current injected by the drain electrode can also enter the channel layer from the side of the channel layer close to the barrier layer. Since the source electrode and the drain electrode are injected from the same surface of the channel layer instead of being injected from opposite surfaces of the channel layer, a high-concentration two-dimensional electron gas channel can be formed at the heterojunction interface of the channel layer and the barrier layer, so that the transistor can utilize the advantages of the two-dimensional electron gas channel. In this way, the transistor not only utilizes the advantages of the two-dimensional electron gas channel, but also forms a vertical structure transistor to reduce the difficulty of application of the transistor.

[0083] The specific process of the preparation method of the transistor in the embodiments of the present disclosure can include the following steps:

[0084] Firstly, a GaN channel layer, an AlGaN barrier layer and a p-type layer are grown on a sapphire substrate by a MOCVD (Metal-organic Chemical Vapor Deposition) process to form an epitaxial wafer.

[0085] The p-type layer can be a p-type GaN layer.

[0086] Secondly, the p-type layer is removed from the positions other than the positions under the gate electrode by a photolithography and etching process, and the AlGaN barrier layer is exposed.

[0087] Thirdly, a TiW layer is deposited on the surface of the barrier layer of the epitaxial wafer, and the TiW metal is etched after photolithography, so as to retain the TiW layer on the surface of the p-type GaN layer, thereby obtaining the gate electrode.

[0088] For example, the thickness of the TiW layer can be 200 nm.

[0089] Fourthly, the positions of the source electrode and the drain electrode are located by a photolithography process, and the AlGaN barrier layer at the positions of the source electrode and the drain electrode is removed by using a dry etching technique to form a first through hole and a second through hole. The first through hole and the second through hole both completely penetrate the AlGaN barrier layer and expose the GaN channel layer.

[0090] Fifthly, the source electrode and the drain electrode are deposited after photolithography. The drain electrode covers the first through hole, and the source electrode covers the second through hole. After high-temperature annealing, the source electrode and the drain electrode form an ohmic contact with the epitaxial wafer. The gate electrode forms a Schottky contact with the p-type layer.

[0091] The sixth step is to implant N+ ions into the isolation channel region of the epitaxial wafer by ion implantation technology, so as to isolate the active region and the invalid region of the device.

[0092] The seventh step is to deposit a dielectric layer and form a through hole penetrating the dielectric layer and exposing the surface of the drain electrode.

[0093] Exemplarily, the dielectric layer can be a silicon oxide layer.

[0094] The eighth step is to evaporate a bonding metal layer on the surface of the dielectric layer, and the bonding metal layer is connected to the drain electrode.

[0095] The ninth step is to bond the bonding metal layer and the conductive substrate together.

[0096] Exemplarily, the conductive substrate can be a silicon substrate.

[0097] The tenth step is to thin the substrate to a desired thickness by grinding and thinning.

[0098] The eleventh step is to position the back surface of the thinned substrate by photolithography, etch the third and fourth through holes in the substrate in the invalid region of the epitaxial wafer by etching technology, and continue to etch the GaN channel layer and the AlGaN barrier layer to form a first through hole connected to the third through hole and a second through hole connected to the fourth through hole.

[0099] The twelfth step is to make a gate pad and a source pad on the back surface of the substrate by evaporation process. The gate pad is connected to the gate electrode through the fourth through hole and the second through hole in sequence. The source pad is connected to the source electrode through the third through hole and the first through hole in sequence.

[0100] The thirteenth step is to thin the conductive substrate.

[0101] The fourteenth step is to deposit a metal on the back surface of the conductive substrate to form a drain pad.

[0102] The fifteenth step is to grow a dielectric layer on the surface by PECVD (Plasma Enhanced Chemical Vapor Deposition) process to protect the device structure and balance the stress. The stress of the final transistor is equivalent to that of the epitaxial wafer.

[0103] The above only describes optional embodiments of the present disclosure and does not limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A transistor, comprising: The transistor comprises an epitaxial wafer (20), a source electrode (31), a drain electrode (32), and a gate electrode (33). The epitaxial wafer (20) comprises a channel layer (21) and a barrier layer (22) stacked in sequence, and has an active region (210) and an inactive region (230), the active region (210) and the inactive region (230) are insulated, and the inactive region (230) has a first via (201) and a second via (202) penetrating through the epitaxial wafer (20). The drain electrode (32) is located on a surface of the barrier layer (22) away from the channel layer (21), and the drain electrode (32) is located in the active region (210), the barrier layer (22) has a first via hole (221) exposing the channel layer (21), and the drain electrode (32) is electrically connected with the channel layer (21) through the first via hole (221). The source electrode (31) and the gate electrode (33) are both located on a surface of the barrier layer (22) away from the channel layer (21), a first part of the source electrode (31) is located in the active region (210), a second part of the source electrode (31) is located in the inactive region (230), the barrier layer (22) further has a second via hole (222) exposing the channel layer (21), the first part of the source electrode (31) is electrically connected with the channel layer (21) through the second via hole (222), and the second part of the source electrode (31) extends to a side of the channel layer (21) away from the barrier layer (22) through the first via (201). A first part of the gate electrode (33) is located in the active region (210), and a second part of the gate electrode (33) is located in the inactive region (230), the first part of the gate electrode (33) is connected with the barrier layer (22), and the second part of the gate electrode (33) extends to a side of the channel layer (21) away from the barrier layer (22) through the second via (202).

2. The transistor of claim 1, wherein The epitaxial wafer (20) further has an isolation channel region (220), the isolation channel region (220) surrounds the active region (210), and the isolation channel region (220) is located between the active region (210) and the inactive region (230).

3. The transistor of claim 2, wherein The isolation channel region (220) is implanted with N+ ions.

4. The transistor according to any one of claims 1 to 3, characterized in that, The transistor further comprises a dielectric layer (40) and a drain pad (52), the dielectric layer (40) is located on a surface of the barrier layer (22) away from the channel layer (21), and the dielectric layer (40) covers the drain electrode (32), the source electrode (31), and the gate electrode (33), a surface of the dielectric layer (40) away from the barrier layer (22) has a via hole exposing the drain electrode (32), and the drain pad (52) is electrically connected with the drain electrode (32) through the via hole.

5. The transistor of claim 4, wherein The transistor further comprises a bonding metal layer (61) and a conductive substrate (62), the bonding metal layer (61) is located on the surface of the dielectric layer (40) away from the barrier layer (22) and is electrically connected with the drain electrode (32) through a via hole, and the conductive substrate (62) is located on the surface of the bonding metal layer (61) away from the dielectric layer (40), and the drain electrode pad (52) is located on the surface of the conductive substrate (62) away from the dielectric layer (40).

6. The transistor according to any one of claims 1 to 3, wherein The transistor further comprises a substrate (10), a source electrode pad (51) and a gate electrode pad (53), the substrate (10) is located on the surface of the channel layer (21) away from the barrier layer (22), and the surface of the substrate (10) has a third via hole (11) and a fourth via hole (12) exposing the invalid region (230); The source electrode pad (51) and the gate electrode pad (53) are both located on the surface of the substrate (10) away from the channel layer (21), the source electrode pad (51) is connected with the source electrode (31) through the third via hole (11) and the first via hole (201) in sequence, and the gate electrode pad (53) is connected with the gate electrode (33) through the fourth via hole (12) and the second via hole (202) in sequence.

7. The transistor according to any one of claims 1 to 3, wherein The epitaxial wafer (20) further comprises a p-type layer (23), the p-type layer (23) is located on the surface of the barrier layer (22) away from the channel layer (21), the source electrode (31) and the drain electrode (32) are arranged in a spaced manner with the p-type layer (23), and the gate electrode (33) is located on the surface of the p-type layer (23) away from the barrier layer (22); In the active region (210), the orthogonal projection of the gate electrode (33) on the surface of the barrier layer (22) is located in the orthogonal projection of the p-type layer (23) on the surface of the barrier layer (22).

8. The transistor according to any one of claims 1 to 3, wherein The first part of the source electrode (31) is in a strip shape, the second part of the source electrode (31) is in a block shape, and one end of the first part of the source electrode (31) is connected with the second part of the source electrode (31); The second via hole (222) is in a strip shape, and the orthogonal projection of the second via hole (222) on the surface of the barrier layer (22) is located in the orthogonal projection of the first part of the source electrode (31) on the surface of the barrier layer (22); The first part of the gate electrode (33) is in a strip shape, the second part of the gate electrode (33) is in a block shape, and one end of the first part of the gate electrode (33) is connected with the second part of the gate electrode (33).

9. The transistor according to any one of claims 1 to 3, wherein The drain electrode (32) is in a strip shape, the first via hole (221) is in a strip shape, and the orthogonal projection of the first via hole (221) on the surface of the barrier layer (22) is located in the orthogonal projection of the first part of the drain electrode (32) on the surface of the barrier layer (22).

10. A method of fabricating a transistor, comprising: The preparation method comprises: Forming an epitaxial wafer on a substrate, the epitaxial wafer comprising a channel layer and a barrier layer stacked in sequence on the substrate, the barrier layer having a first through hole and a second through hole exposing the channel layer, the epitaxial wafer having an active region and an inactive region, the active region and the inactive region being insulated, the inactive region having a first via and a second via penetrating through the epitaxial wafer; Forming a drain electrode, a source electrode and a gate electrode on a surface of the barrier layer away from the channel layer, the drain electrode being located in the active region, the drain electrode being electrically connected with the channel layer through the first through hole, a first part of the source electrode being located in the active region, a second part of the source electrode being located in the inactive region, the source electrode of the first part being electrically connected with the channel layer through the second through hole, the source electrode of the second part extending to a side of the channel layer away from the barrier layer through the first via.

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