Semiconductor structure

Abstract

A semiconductor structure includes a first well, a second well, a third well, a first doped region, a second doped region and a fourth doped region having a first conductivity type, a fourth well and a third doped region having a second conductivity type, a first contact, a second contact, and a gate structure. The second well and the third well are formed in the first well. The fourth well is formed in the first well and located between the second well and the third well. The first doped region is formed in the second well. The second doped region and the third doped region are formed in the fourth well. The fourth doped region is formed in the third well. The first contact is formed on the third well. The second contact is in ohmic contact with the fourth doped region. The gate structure is formed between the first doped region and the second doped region.

Description

Technical Field

[0001] The invention relates to a semiconductor structure of an isolated high-voltage transistor, and in particular to a semiconductor structure of an isolated high-voltage transistor with electrostatic discharge protection. Background Art

[0002] Integrated circuits can be severely damaged by various electrostatic discharge events. One major electrostatic discharge mechanism comes from the human body, called the Human Body Model (HBM). The human body generates a sharp current of several amperes to the integrated circuit within about 100 nanoseconds, burning the circuit. The second electrostatic discharge mechanism comes from metal objects, called the Machine Model (MM), which produces a much higher rise time and current level than the Human Body Model. The third electrostatic discharge mechanism is the Charged-Device Model (CDM), in which the integrated circuit itself accumulates charge and discharges to the ground within a rise time of less than 0.5 nanoseconds. Therefore, we need effective electrostatic protection devices to protect integrated circuits from the hazards of electrostatic discharge. Summary of the invention

[0003] The semiconductor structure of the high-voltage transistor proposed by the present invention is electrically separated from other semiconductor structures by forming an additional isolation region, and the additional isolation region is used to form a silicon-controlled rectifier with the substrate end and the source end, thereby improving the electrostatic discharge protection capability of the semiconductor structure, while maintaining the breakdown voltage between the drain end and the substrate. In addition, the isolation region forms a parasitic bipolar junction transistor with the substrate, and the substrate is often electrically connected to the ground end, thereby providing an additional path for the electrostatic charge of the drain end to be discharged to the ground end.

[0004] In view of this, the present invention proposes a semiconductor structure, including a first well, a second well, a third well, a fourth well, a first doped region, a second doped region, a third doped region, a fourth doped region, a first contact, a second contact and a gate structure. The first well has a first conductivity type. The second well is formed in the first well and has the first conductivity type. The third well is formed in the first well and has the first conductivity type. The fourth well is formed in the first well and is located between the second well and the third well and has a second conductivity type. The first doped region is formed in the second well and has the first conductivity type. The second doped region is formed in the fourth well and has the first conductivity type. The third doped region is formed in the fourth well and has the second conductivity type. The fourth doped region is formed in the third well and has the first conductivity type. The first contact is formed on the third well. The second contact forms an ohmic contact with the fourth doped region. The gate structure is formed between the first doping region and the second doping region.

[0005] According to one embodiment of the present invention, the semiconductor structure is formed into a transistor. The transistor includes a drain terminal, a gate terminal, a source terminal and a body terminal, the first doped region forms the drain terminal, the gate structure forms the gate terminal, the second doped region forms the source terminal, and the third doped region forms the body terminal. The drain terminal, the first contact and the second contact are electrically connected together, and the source terminal and the body terminal are electrically connected together. The first contact, the second contact, the third doped region and the second doped region form a silicon-controlled rectifier, the source terminal is coupled to a ground terminal, and the silicon-controlled rectifier is used to discharge the electrostatic discharge charge received by the drain terminal to the ground terminal.

[0006] According to an embodiment of the present invention, the first contact and the third well form a Schottky contact.

[0007] According to another embodiment of the present invention, the semiconductor structure further comprises an additional doped region. The additional doped region is formed in the third well and has the second conductivity type, wherein the first contact forms an ohmic contact with the additional doped region.

[0008] According to one embodiment of the present invention, the semiconductor structure further includes a fifth well and a fifth doped region. The fifth well surrounds the first well and has the second conductivity type. The fifth doped region is formed in the fifth well and has the second conductivity type, wherein the fifth doped region is coupled to the ground terminal. The first contact, the second contact and the fifth doped region form a parasitic bipolar junction transistor, wherein the parasitic bipolar junction transistor is used to discharge the electrostatic discharge charge received by the drain terminal to the ground terminal.

[0009] According to one embodiment of the present invention, the second well is further formed in the third well. The semiconductor structure further includes a sixth well and a seventh well. The sixth well is formed in the third well and has the first conductivity type, wherein the second doped region is formed in the sixth well. The seventh well is formed in the third well and has the second conductivity type, wherein the third doped region is formed in the seventh well.

[0010] According to an embodiment of the present invention, the fifth well, the first well, the fourth well, the fourth doped region and the fourth well are arranged along a first direction, and the first contact and the second contact are arranged along a second direction, wherein the first direction is different from the second direction.

[0011] The present invention further proposes a semiconductor structure, comprising a substrate, a buried layer, an epitaxial layer, a first well, a second well, a third well, a fourth well, a first doped region, a second doped region, a third doped region, a fourth doped region, a first contact, a second contact and a gate structure. The buried layer is formed in the substrate and has a first conductivity type. The epitaxial layer is formed on the buried layer and has the first conductivity type. The first well surrounds the epitaxial layer and has the first conductivity type. The second well is formed on the buried layer and has the first conductivity type. The third well is formed in the first well and has the first conductivity type. The fourth well is formed in the epitaxial layer and is located between the second well and the third well and has a second conductivity type. The first doped region is formed in the second well and has the first conductivity type. The second doped region is formed in the fourth well and has the first conductivity type. The third doped region is formed in the fourth well and has the second conductivity type. The fourth doped region is formed in the third well and has the first conductivity type. The first contact is formed on the third well. The second contact is formed on the fourth doped region and forms an ohmic contact with the fourth doped region. The gate structure is formed between the first doped region and the second doped region.

[0012] According to one embodiment of the present invention, the semiconductor structure is formed into a transistor. The transistor includes a drain terminal, a gate terminal, a source terminal and a body terminal, the first doped region forms the drain terminal, the gate structure forms the gate terminal, the second doped region forms the source terminal, and the third doped region forms the body terminal. The drain terminal, the first contact and the second contact are electrically connected together, and the source terminal and the body terminal are connected together. The first contact, the second contact, the third doped region and the second doped region form a silicon-controlled rectifier, the source terminal is coupled to a ground terminal, and the silicon-controlled rectifier is used to discharge the electrostatic discharge charge received by the drain terminal to the ground terminal.

[0013] According to an embodiment of the present invention, the first contact and the third well form a Schottky contact.

[0014] According to another embodiment of the present invention, the semiconductor structure further comprises an additional doped region. The additional doped region is formed in the third well, wherein the first contact forms an ohmic contact with the additional doped region.

[0015] According to one embodiment of the present invention, the semiconductor structure further includes a fifth well and a fifth doped region. The fifth well surrounds the first well and has the second conductivity type. The fifth doped region is formed in the fifth well and has the second conductivity type, wherein the fifth doped region is coupled to the ground terminal. The first contact, the second contact and the fifth doped region form a parasitic bipolar junction transistor, wherein the parasitic bipolar junction transistor is used to discharge the electrostatic discharge charge received by the drain terminal to the ground terminal.

[0016] According to an embodiment of the present invention, the second well is formed in the first well.

[0017] According to one embodiment of the present invention, the second well is further formed in the third well. The semiconductor structure further includes a sixth well and a seventh well. The sixth well is formed in the third well and has the first conductivity type, wherein the second doped region is formed in the sixth well. The seventh well is formed in the third well and has the second conductivity type, wherein the third doped region is formed in the seventh well.

[0018] According to an embodiment of the present invention, the fifth well, the first well, the fourth well, the fourth doped region and the fourth well are arranged along a first direction, and the first contact and the second contact are arranged along a second direction, wherein the first direction is different from the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1A cross-sectional view showing a semiconductor structure according to an embodiment of the present invention;

[0020] Figure 2 An equivalent circuit diagram showing a semiconductor structure according to an embodiment of the present invention;

[0021] Figure 3 A circuit diagram showing a driving circuit according to an embodiment of the present invention;

[0022] Figure 4 A cross-sectional view showing a semiconductor structure according to another embodiment of the present invention;

[0023] Figure 5 A cross-sectional view showing a semiconductor structure according to another embodiment of the present invention;

[0024] Figure 6 A cross-sectional view showing a semiconductor structure according to another embodiment of the present invention;

[0025] Figure 7 A cross-sectional view showing a semiconductor structure according to another embodiment of the present invention;

[0026] Figure 8 A cross-sectional view showing a semiconductor structure according to another embodiment of the present invention;

[0027] Fig. 9 A cross-sectional view showing a semiconductor structure according to another embodiment of the present invention;

[0028] Fig.10 A cross-sectional view showing a semiconductor structure according to another embodiment of the present invention;

[0029] Fig.11 The display device according to an embodiment of the present invention Figure 1 A top view of a first region;

[0030] Fig.12 According to another embodiment of the present invention, Figure 1 a top view of a first region of the device; and

[0031] Fig.13 According to another embodiment of the present invention, Figure 1 A top view of a first region of FIG.

[0032] Description of Figure Numbers:

[0033] 100,400,500,600,700,800,900,1000:Semiconductor structure

[0034] 110: Gate structure

[0035] 200: Equivalent circuit

[0036] 300: driving circuit

[0037] 1100,1200,1300:Circuit layout

[0038] SUB:Substrate

[0039] W1: First Well

[0040] W2: Second trap

[0041] W3: The Third Trap

[0042] W4: The Fourth Trap

[0043] W5: The Fifth Trap

[0044] D1: first doped region

[0045] D2: Second doping region

[0046] D3: The third doping region

[0047] D4: Fourth doping region

[0048] D5: Fifth doping region

[0049] DA: Additional doping area

[0050] CT1: First contact

[0051] CT2: Second contact

[0052] I1: First isolation structure

[0053] I2: Second isolation structure

[0054] I3: The third isolation structure

[0055] I4: Fourth Isolation Structure

[0056] I5: Fifth Isolation Structure

[0057] I6: Sixth isolation structure

[0058] T: Transistor

[0059] D: Drain terminal

[0060] G: Gate terminal

[0061] S: Source terminal

[0062] B: Base end

[0063] ISO: Isolation terminal

[0064] GND: Ground terminal

[0065] R1: First Area

[0066] DR1: First Direction

[0067] DR2: Second direction

[0068] SCR: Silicon Controlled Rectifier

[0069] PD: Parasitic Diode

[0070] PD1: First parasitic diode

[0071] PD2: Second parasitic diode

[0072] PBJT: Parasitic Bipolar Junction Transistor

[0073] VB: Supply voltage

[0074] L: Load

[0075] HS: High-side transistor

[0076] LS: Low bridge transistor

[0077] TD1: First drain terminal

[0078] TS1: First source terminal

[0079] TD2: Second drain terminal

[0080] TS2: Second source terminal

[0081] BL:Buried Layer

[0082] EPI: Epitaxial layer

[0083] CT: Metal Contact DETAILED DESCRIPTION

[0084] The following descriptions are examples of the present disclosure, and are intended to illustrate the general principles of the present disclosure, and should not be considered as limitations of the present disclosure, the scope of which shall be determined by the scope of the claims.

[0085] It is noteworthy that the content disclosed below can provide multiple embodiments or examples for practicing the different features of the present disclosure. The special component examples and arrangements described below are only used to simply and concisely explain the spirit of the present disclosure, and are not used to limit the scope of the present disclosure. In addition, the following description may reuse the same component symbols or text in multiple examples. However, the purpose of reuse is only to provide a simplified and clear description, and is not used to limit the relationship between multiple embodiments and / or configurations discussed below. In addition, the description of a feature connected to, coupled to, and / or formed on another feature described in the following description may actually include multiple different embodiments, including direct contact between these features, or including other additional features formed between these features, etc., so that these features are not in direct contact.

[0086] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used in the embodiments to describe the relative relationship of one element of the diagram to another element. It is understood that if the device of the diagram is turned upside down, the element described on the "lower" side will become the element on the "upper" side.

[0087] It is understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or parts. Therefore, a first element, component, region, layer, and / or part discussed below may be referred to as a second element, component, region, layer, and / or part without departing from the teachings of some embodiments of the present disclosure.

[0088] Some embodiments of the present disclosure may be combined with the following Figure 1 It is also understood that the drawings of the embodiments of the present disclosure are also considered as part of the description of the embodiments of the present disclosure. It should be understood that the drawings of the embodiments of the present disclosure are not drawn in proportion to the actual devices and components. The shapes and thicknesses of the embodiments may be exaggerated in the drawings to clearly show the features of the embodiments of the present disclosure. In addition, the structures and devices in the drawings are drawn in a schematic manner to clearly show the features of the embodiments of the present disclosure.

[0089] Here, the terms "about", "approximately" and "generally" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. The numbers given here are approximate numbers, that is, in the absence of specific description of "about", "approximately" or "generally", the meanings of "about", "approximately" or "generally" can still be implied.

[0090] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

[0091] In some embodiments of the present disclosure, terms such as "connection" and "interconnection" may refer to two structures being in direct contact with each other, or may refer to two structures not being in direct contact with each other, with another structure disposed between the two structures, unless otherwise specified. Such terms may also include situations where both structures are movable or both structures are fixed.

[0092] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those skilled in the art. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

[0093] In some embodiments of the present disclosure, relative terms such as "lower", "upper", "horizontal", "vertical", "below", "above", "top", "bottom", etc. should be understood as the orientations shown in the paragraph and related drawings. Such relative terms are only for the convenience of description and do not mean that the device described therein must be manufactured or operated in a specific orientation.

[0094] Figure 1 A cross-sectional view of a semiconductor structure according to an embodiment of the present invention is shown. Figure 1 As shown, the semiconductor structure 100 includes a substrate SUB, a first well W1, a second well W2, a third well W3, a fourth well W4 and a fifth well W5. The substrate SUB has a first conductivity type. According to one embodiment of the present invention, the substrate SUB is a silicon substrate. According to other embodiments of the present invention, the substrate SUB may also be a lightly doped semiconductor substrate having the first conductivity type.

[0095] The first well W1 is formed in the semiconductor substrate SUB and has a second conductivity type. According to one embodiment of the present invention, the first conductivity type is P type and the second conductivity type is N type. According to one embodiment of the present invention, the first well W1 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in a region of the predetermined first well W1 to form the first well W1.

[0096] The second well W2 is formed in the first well W1 and has the second conductivity type. According to one embodiment of the present invention, the second well W2 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in the area of ​​the predetermined second well W2 to form the second well W2. In this embodiment, the doping concentration of the second well W2 is higher than the doping concentration of the first well W1.

[0097] The third well W3 is formed in the first well W1 and has the second conductivity type. According to one embodiment of the present invention, the third well W3 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in a predetermined area of ​​the third well W3 to form the third well W3. In this embodiment, the doping concentration of the third well W3 is higher than the doping concentration of the first well W1.

[0098] The fourth well W4 is formed in the first well W1 and is located between the second well W2 and the third well W3, wherein the fourth well W4 has the first conductivity type. According to one embodiment of the present invention, the fourth well W4 can also be formed by an ion implantation step. For example, boron ions or indium ions can be implanted in the area where the fourth well W4 is to be formed to form the fourth well W4. In this embodiment, the doping concentration of the fourth well W4 is higher than the doping concentration of the semiconductor substrate SUB.

[0099] The fifth well W5 is formed on the substrate SUB and surrounds the first well W1 and is adjacent to the first well W1, wherein the fifth well W5 has the first conductivity type. According to one embodiment of the present invention, the fifth well W5 can also be formed by an ion implantation step. For example, boron ions or indium ions can be implanted in the area where the fifth well W5 is to be formed to form the fifth well W5. In this embodiment, the doping concentration of the fifth well W5 is higher than the doping concentration of the substrate SUB.

[0100] like Figure 1 As shown, the semiconductor structure 100 further includes a first doping region D1, a second doping region D2, a third doping region D3, a fourth doping region D4 and a fifth doping region D5. The first doping region D1 has a second conductivity type and is formed in the second well W2. According to an embodiment of the present invention, the doping concentration of the first doping region D1 is higher than the doping concentration of the second well W2.

[0101] The second doping region D2 has the second conductivity type and is formed in the fourth well W4. According to one embodiment of the present invention, the doping concentration of the second doping region D2 is higher than the doping concentration of the second well W2. The third doping region D3 has the first conductivity type and is formed in the fourth well W4. According to one embodiment of the present invention, the doping concentration of the third doping region D3 is higher than the doping concentration of the fourth well W4.

[0102] The fourth doping region D4 has the second conductivity type and is formed in the third well W3. According to one embodiment of the present invention, the doping concentration of the fourth doping region D4 is higher than the doping concentration of the third well W3. The fifth doping region D5 has the first conductivity type and is formed in the fifth well W5. According to one embodiment of the present invention, the doping concentration of the fifth doping region D5 is higher than the doping concentration of the fifth well W5.

[0103] like Figure 1 As shown, the semiconductor structure 100 further includes a first contact CT1 and a second contact CT2. The first contact CT1 is formed on the third well W3 and is in direct contact with the second well W2. According to one embodiment of the present invention, the first contact CT1 and the second contact CT2 are contacts formed by metal. According to one embodiment of the present invention, the first contact CT1 forms a Schottky contact with the third well W3. The second contact CT2 is formed on the fourth doped region D4 and is in contact with the fourth doped region D4. According to one embodiment of the present invention, the second contact CT2 forms an ohmic contact with the fourth doped region D4.

[0104] like Figure 1 As shown, the semiconductor structure 100 further includes a first isolation structure I1, a second isolation structure I2, a third isolation structure I3 and a fourth isolation structure I4. The first isolation structure I1 is located between the first doping region D1 and the second doping region D2 and is located on the first well W1. Figure 1 As shown, the first isolation structure I1 directly contacts the second well W2, but this is not intended to limit the present invention. According to other embodiments of the present invention, the first isolation structure I1 does not contact the second well W2.

[0105] The second isolation structure I2 is located between the second doping region D2 and the third doping region D3 and on the fourth well W4 to separate the second doping region D2 and the third doping region D3. Figure 1 As shown, the second isolation structure I2 directly contacts the second doping region D2 and the third doping region D3, but this is not intended to limit the present invention. According to other embodiments of the present invention, the second isolation structure I2 does not contact at least one of the second doping region D2 and the third doping region D3.

[0106] The third isolation structure I3 is adjacent to the third doped region D3 and is used to separate the third doped region D3 and the third well W3. Figure 1 As shown, the third isolation structure I3 directly contacts the third doped region D3 and the third well W3, but this is not intended to limit the present invention. According to other embodiments of the present invention, the third isolation structure I3 does not contact at least one of the third doped region D3 and the third well W3.

[0107] The fourth isolation structure I4 is located on the first well W1 and between the second well W2 and the fifth well W5, and is used to separate the first doping region D1 and the fifth doping region D5. Figure 1 As shown, the fourth isolation structure I4 directly contacts the second well W2 and the fifth well W5, but this is not intended to limit the present invention. According to other embodiments of the present invention, the fourth isolation structure I4 does not contact at least one of the second well W2 and the fifth well W5.

[0108] like Figure 1 As shown, the semiconductor structure 100 further includes a gate structure 110. The gate structure 110 is formed between the first doping region D1 and the second doping region D2, and is located on the first well W1 and the fourth well W4.

[0109] like Figure 1 As shown, the semiconductor structure 100 forms a transistor T, wherein the transistor T includes a drain terminal D, a gate terminal G, a source terminal S, and a body terminal B. The first doping region D1 forms the drain terminal D, the gate structure 110 forms the gate terminal G, the second doping region D2 forms the source terminal S, and the third doping region D3 forms the body terminal B. In addition, the source terminal S of the second doping region D2 and the body terminal B of the third doping region D3 are electrically connected to each other.

[0110] The first well W1, the third well W3, the fourth doped region D4, the first contact CT1 and the second contact CT2 form an isolation region for electrically isolating the transistor T from other semiconductor structures. The first contact CT1 and the second contact CT2 are electrically connected to form an isolation terminal ISO, wherein the isolation terminal ISO is electrically connected to the drain terminal D of the first doped region D1. The fifth doped region D5 is electrically connected to the ground terminal GND. According to an embodiment of the present invention, when the substrate SUB is of the first conductivity type, the substrate SUB is electrically connected to the ground terminal GND through the fifth well W5 and the fifth doped region D5.

[0111] Figure 2 An equivalent circuit diagram of a semiconductor structure according to an embodiment of the present invention is shown, wherein Figure 2 The equivalent circuit 200 corresponds to Figure 1 The semiconductor structure 100. Figure 2 As shown, the drain terminal D of the transistor T is electrically connected to the isolation terminal ISO, and the source terminal S is electrically connected to the body terminal B.

[0112] Figure 1 The first contact CT1, the second contact CT2, the third doping region D3 and the second doping region D2 form a silicon controlled rectifier SCR, wherein the silicon controlled rectifier SCR is electrically connected between the isolation terminal ISO and the source terminal S. Since the isolation terminal ISO is electrically connected to the drain terminal D, the silicon controlled rectifier SCR is also electrically connected between the drain terminal D and the source terminal S.

[0113] like Figure 1 As shown, the first well W1 and the fifth well W5 are formed Figure 2 In addition, the first well W1 is electrically connected to the isolation terminal ISO through the fourth doping region D4 and the second contact CT2, and the fifth well W5 is electrically connected to the ground terminal GND through the fifth doping region D5. Figure 2 The parasitic diode PD is electrically connected between the isolation terminal ISO and the ground terminal GND. Figure 1 , Figure 2 As shown, the first contact CT1, the second contact CT2 and the fifth doped region D5 form a parasitic bipolar junction transistor PBJT, wherein the parasitic bipolar junction transistor PBJT is a PNP.

[0114] Figure 3 A circuit diagram of a driving circuit according to an embodiment of the present invention is shown. Figure 3 As shown, the driving circuit 300 is used to drive the load L, including an upper bridge transistor HS and a lower bridge transistor LS, wherein the upper bridge transistor HS and the lower bridge transistor LS are composed of Figure 1 The semiconductor structure 100 is implemented.

[0115] According to some embodiments of the present invention, the supply voltage VB received by the first drain terminal TD1 of the upper bridge transistor HS is a high voltage, and when the upper bridge transistor HS is turned on, the upper bridge transistor HS provides the supply voltage VB to the first source terminal TS1, and the second drain terminal TD2 of the lower bridge transistor LS also receives the supply voltage VB. Figure 1 The first well W1 helps to prevent the first parasitic diode PD1 of the upper bridge transistor HS and the second parasitic diode PD2 of the lower bridge transistor LS from being turned on to cause latch-up, thereby damaging the upper bridge transistor HS and the lower bridge transistor LS.

[0116] According to some embodiments of the present invention, when electrostatic discharge occurs at the first drain terminal TD1 of the upper bridge transistor HS, Figure 2 The parasitic bipolar junction transistor PBJT shown can discharge the electrostatic discharge charge of the first drain terminal TD1 to the ground terminal GND. When the second drain terminal TD2 of the lower bridge transistor LS is electrostatically discharged, Figure 2 The silicon controlled rectifier SCR shown removes the electrostatic discharge charge of the second drain terminal TD2 to the second source terminal TS2 electrically connected to the ground terminal GND, and Figure 2 The parasitic bipolar junction transistor PBJT shown also provides another path leading to the ground terminal GND.

[0117] Back to Figure 1According to other embodiments of the present invention, the first contact CT1 may also be formed on the second well W2 to form a Schottky contact with the second well W2, so that the first contact CT1, the first doping region D1, the third doping region D3 and the second doping region D2 form Figure 2 Although forming a Schottky junction between the first contact CT1 and the second well W2 also helps to improve the electrostatic discharge capability, forming the silicon-controlled rectifier SCR with the first contact CT1, the first doping region D1, the third doping region D3 and the second doping region D2 will affect the electric field distribution of the drain terminal D, thereby causing the breakdown voltage to drop. In other words, forming the silicon-controlled rectifier SCR in the third well W3 not only maintains the original performance of the transistor T, but also improves the electrostatic discharge protection capability of the transistor T.

[0118] Figure 4 A cross-sectional view of a semiconductor structure according to another embodiment of the present invention is shown. Figure 4 The semiconductor structure 400 and Figure 1 Compared with the semiconductor structure 100, the semiconductor structure 400 further includes an additional doping area DA, and the additional doping area DA forms an ohmic contact with the first contact CT1. The additional doping area DA is formed in the third well W3 and has the first conductivity type. According to an embodiment of the present invention, the doping concentration of the additional doping area DA is higher than the doping concentration of the fourth well W4.

[0119] exist Figure 4 In the embodiment, Figure 4 The first contact CT1, the second contact CT2, the third doping region D3 and the second doping region D2 are also formed Figure 2 In addition, Figure 4 In the embodiment, the drain terminal D and the isolation terminal ISO are electrically connected together, so the silicon controlled rectifier SCR is electrically connected between the drain terminal D and the source terminal S. According to some embodiments of the present invention, Figure 4 The semiconductor structure 400 may be Figure 1 The semiconductor structure 100 is applied to Figure 3 The upper bridge transistor HS and the lower bridge transistor LS are not repeated here.

[0120] Figure 5 A cross-sectional view of a semiconductor structure according to another embodiment of the present invention is shown. Figure 5 The semiconductor structure 500 and Figure 1 Compared with the semiconductor structure 100 , the semiconductor structure 500 further includes a sixth well W6 and a seventh well W7 , and the second well W2 is formed in the third well W3 .

[0121] The sixth well W6 is formed in the third well W3 and has the second conductivity type, wherein the second doping region D2 is formed in the sixth well W6. According to an embodiment of the present invention, the doping concentration of the second doping region D2 is greater than the doping concentration of the sixth well W6.

[0122] The seventh well W7 is formed in the third well W3 and has the first conductivity type, wherein the third doping region D3 is formed in the seventh well W7. According to one embodiment of the present invention, the doping concentration of the third doping region D3 is greater than the doping concentration of the seventh well W7, and the doping concentration of the seventh well W7 is greater than the doping concentration of the third well W7.

[0123] Relative to Figure 1 In the semiconductor structure 100, the first isolation structure I1 of the semiconductor structure 500 is divided into a fifth isolation structure I5 ​​and a sixth isolation structure I6, and the gate structure 110 is formed between the fifth isolation structure I5 ​​and the sixth isolation structure I6.

[0124] like Figure 5 As shown, the fifth isolation structure I5 ​​directly contacts the second well W2, but it is not intended to limit the present invention. According to other embodiments of the present invention, the fifth isolation structure I5 ​​does not contact the second well W2. The sixth isolation structure I6 directly contacts the sixth well W6, but it is not intended to limit the present invention. According to other embodiments of the present invention, the sixth isolation structure I6 does not contact the sixth well W6. According to some embodiments of the present invention, Figure 5 The semiconductor structure 500 may be Figure 1 The semiconductor structure 100 is applied to Figure 3 The upper bridge transistor HS and the lower bridge transistor LS are not repeated here.

[0125] Figure 6 A cross-sectional view of a semiconductor structure according to another embodiment of the present invention is shown. Figure 6 The semiconductor structure 600 and Figure 5 Compared with the semiconductor structure 500, the semiconductor structure 600 further includes an additional doping area DA, and the additional doping area DA forms an ohmic contact with the first contact CT1. The additional doping area DA is formed in the third well W3 and has the first conductivity type. According to an embodiment of the present invention, the doping concentration of the additional doping area DA is higher than the doping concentration of the fourth well W4.

[0126] exist Figure 6 In the embodiment, Figure 6 The first contact CT1, the second contact CT2, the third doping region D3 and the second doping region D2 are also formed Figure 2 In addition, Figure 6In the embodiment, the drain terminal D and the isolation terminal ISO and the silicon controlled rectifier SCR are electrically connected together, so the silicon controlled rectifier SCR is electrically connected between the drain terminal D and the source terminal S. According to some embodiments of the present invention, Figure 6 The semiconductor structure 600 may be Figure 1 The semiconductor structure 100 is applied to Figure 3 The upper bridge transistor HS and the lower bridge transistor LS are not repeated here.

[0127] Figure 7 A cross-sectional view of a semiconductor structure according to another embodiment of the present invention is shown. Figure 7 The semiconductor structure 700 and Figure 1 Compared with the semiconductor structure 100, the semiconductor structure 700 further includes a buried layer BL and an epitaxial layer EPI. The buried layer BL is formed in the substrate SUB and has a second conductivity type, wherein the first well W1 is formed on the buried layer BL and connected to the buried layer BL.

[0128] like Figure 7 As shown, the epitaxial layer EPI is formed on the buried layer BL and has the above-mentioned second conductivity type, wherein the fourth well W4 is formed in the epitaxial layer EPI, the first well W1 surrounds the epitaxial layer EPI, and the first well W1 is connected to the epitaxial layer EPI. According to some embodiments of the present invention, the doping concentration of the buried layer BL and the epitaxial layer EPI is similar to the doping concentration of the first well W1.

[0129] According to some embodiments of the present invention, Figure 7 The semiconductor structure 700 may be Figure 1 The semiconductor structure 100 is applied to Figure 3 The upper bridge transistor HS and the lower bridge transistor LS are not repeated here.

[0130] Figure 8 A cross-sectional view of a semiconductor structure according to another embodiment of the present invention is shown. Figure 8 The semiconductor structure 800 and Figure 7 Compared with the semiconductor structure 700, the semiconductor structure 800 further includes an additional doped region DA, wherein the additional doped region DA has the first conductivity type and forms an ohmic contact with the first contact CT1.

[0131] exist Figure 8 In the embodiment, Figure 8 The first contact CT1, the second contact CT2, the third doping region D3 and the second doping region D2 are also formed Figure 2 According to some embodiments of the present invention, Figure 8 The semiconductor structure 800 may be Figure 1 The semiconductor structure 100 is applied to Figure 3 The upper bridge transistor HS and the lower bridge transistor LS are not repeated here.

[0132] Fig. 9 A cross-sectional view of a semiconductor structure according to another embodiment of the present invention is shown. Fig. 9 The semiconductor structure 900 and Figure 7 Compared with the semiconductor structure 700 , the semiconductor structure 900 further includes a sixth well W6 and a seventh well W7 , and the second well W2 is formed in the third well W3 .

[0133] like Fig. 9 As shown, the sixth well W6 and the seventh well W7 are Figure 5 The sixth well W6 and the seventh well W7 are the same, and will not be repeated here. Figure 8 In the semiconductor structure 800 , the first isolation structure I1 of the semiconductor structure 900 is divided into a fifth isolation structure I5 ​​and a sixth isolation structure I6 , and the gate structure 110 is formed between the fifth isolation structure I5 ​​and the sixth isolation structure I6 .

[0134] According to some embodiments of the present invention, Fig. 9 The semiconductor structure 900 may be Figure 1 The semiconductor structure 100 is applied to Figure 3 The upper bridge transistor HS and the lower bridge transistor LS are not repeated here.

[0135] Fig.10 A cross-sectional view of a semiconductor structure according to another embodiment of the present invention is shown. Fig.10 The semiconductor structure 1000 and Fig. 9 Compared with the semiconductor structure 900, the semiconductor structure 1000 further includes an additional doped region DA, wherein the additional doped region DA is as follows: Figure 6 According to some embodiments of the present invention, Fig.10 The semiconductor structure 1000 may be Figure 1 The semiconductor structure 100 is applied to Figure 3 The upper bridge transistor HS and the lower bridge transistor LS are not repeated here.

[0136] Fig.11 The display device according to an embodiment of the present invention Figure 1 A top view of the first region of FIG. Figure 1 As shown, the first region R1 is sequentially composed of the fifth well W5, the first well W1, the fourth well W4, the fourth doping region D4, the fourth well W4 and the first well W1 along the first direction DR1. Fig.11As shown, the semiconductor layers of the circuit layout 1100 are arranged in sequence along the first direction DR1, wherein the first contact CT1 covers the fourth well W4, and the second contact CT2 covers the fourth doped region D4. According to other embodiments of the present invention, Figures 4 to 10 The arrangement of the first region R1 is also the same, and will not be repeated here.

[0137] In other words, the semiconductor layers of the circuit layout 1100 are arranged in the same order along the first direction DR1. Figure 5 , Figure 7 , Fig. 9 The order of the fifth well W5, the first well W1, the fourth well W4, the fourth doped region D4, the fourth well W4 and the first well W1 shown in the semiconductor structures 500, 700 and 900 is consistent. In addition, the first contact CT1 and the second contact CT2 are also arranged along the first direction DR1. According to other embodiments of the present invention, when the circuit layout 1100 is Figure 4 , Figure 6 , Figure 8 , Fig.10 In the semiconductor structures 400, 600, 800, and 1000, the additional doped area DA is located below the first contact CT1.

[0138] Fig.12 According to another embodiment of the present invention, Figure 1 A top view of the first region of FIG. Fig.12 The circuit layout 1200 with Fig.11 Compared with the circuit layout 1100, the order of the first contact CT1 and the second contact CT2 is swapped. According to other embodiments of the present invention, when the circuit layout 1200 is Figure 4 , Figure 6 , Figure 8 , Fig.10 When the semiconductor structures 400, 600, 800, and 1000 are used, the order of the first contact CT1 and the second contact CT2 is switched, and the order of the additional doping area DA and the fourth doping area D4 is also switched accordingly. Fig.11 , Fig.12 As shown, the positions of the first contact CT1 and the second contact CT2 (corresponding to the fourth doping region D4 ) are swapped, which does not affect the performance of the formed silicon controlled rectifier SCR.

[0139] Fig.13 According to another embodiment of the present invention, Figure 1 A top view of the first region of FIG. Fig.13As shown, the semiconductor layer of the circuit layout 1300 is sequentially formed along the first direction DR1 into a fifth well W5, a first well W1, a fourth well W4, a fourth doped region D4, a fourth well W4, and a first well W1, and the first contact CT1 and the second contact CT2 are arranged along the second direction DR2, and the first contact CT1 and the second contact CT2 share a metal contact CT. According to some embodiments of the present invention, the first direction DR1 is different from the second direction DR2. According to some embodiments of the present invention, the first direction DR1 is orthogonal to the second direction DR2.

[0140] According to some embodiments of the present invention, in the second direction DR2, the ratio of the first contact CT1 and the second contact CT2 can be adjusted by the designer at will. Fig.13 The circuit layout 1300 with Fig.11 The circuit layout 1100 and Fig.12 Compared with the circuit layout 1200, since the first contacts CT1 and the second contacts CT2 are arranged in the second direction DR2, the required width of the circuit layout 1300 in the first direction DR1 is smaller than that of the circuit layouts 1100 and 1200, thereby reducing the required area of ​​the circuit layout 1300.

[0141] The semiconductor structure of the high-voltage transistor proposed by the present invention is electrically separated from other semiconductor structures by forming an additional isolation region, and the additional isolation region is used to form a silicon-controlled rectifier with the substrate end and the source end, thereby improving the electrostatic discharge protection capability of the semiconductor structure, while maintaining the breakdown voltage between the drain end and the substrate. In addition, the isolation region forms a parasitic bipolar junction transistor with the substrate, and the substrate is often electrically connected to the ground end, thereby providing an additional path for the electrostatic charge of the drain end to be discharged to the ground end.

[0142] Although the embodiments and advantages of the present disclosure have been disclosed as above, it should be understood that any person skilled in the art may make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufactures, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the current or future developed processes, machines, manufactures, material compositions, devices, methods and steps from the disclosure of some embodiments of the present disclosure. As long as the same functions can be implemented in the embodiments described herein or the same results can be obtained, they can be used according to some embodiments of the present disclosure. Therefore, the scope of protection of the present disclosure includes the above-mentioned processes, machines, manufactures, material compositions, devices, methods and steps. In addition, each patent application constitutes an individual embodiment, and the scope of protection of the present disclosure also includes the combination of the scope of the claims and the embodiments.

Claims

1. A semiconductor structure, characterized in that: include: a first well having a first conductivity type; a second well formed in the first well and having the first conductivity type; a third well formed in the first well and having the first conductivity type; a fourth well, formed in the first well and located between the second well and the third well, and having a second conductivity type; a first doped region formed in the second well and having the first conductivity type; a second doped region formed in the fourth well and having the first conductivity type; a third doped region formed in the fourth well and having the second conductivity type; a fourth doped region formed in the third well and having the first conductivity type; a first contact formed on the third well; a second contact forming an ohmic contact with the fourth doped region; and A gate structure is formed between the first doping region and the second doping region.

2. The semiconductor structure according to claim 1, wherein: The semiconductor structure forms a transistor; The transistor comprises a drain terminal, a gate terminal, a source terminal and a body terminal; The first doped region forms the drain terminal, the gate structure forms the gate terminal, the second doped region forms the source terminal, and the third doped region forms the body terminal; wherein the drain terminal, the first contact and the second contact are electrically connected together, and the source terminal and the substrate terminal are electrically connected together; The first contact, the second contact, the third doped region and the second doped region form a silicon controlled rectifier; The source terminal is coupled to a ground terminal, and the silicon-controlled rectifier is used to discharge the electrostatic discharge charge received by the drain terminal to the ground terminal.

3. The semiconductor structure according to claim 2, wherein: The first contact and the third well form a Schottky contact.

4. The semiconductor structure according to claim 2, characterized in that Also includes: An additional doped region is formed in the third well and has the second conductivity type, wherein the first contact forms an ohmic contact with the additional doped region.

5. The semiconductor structure according to claim 2, wherein: Also includes: a fifth well surrounding the first well and having the second conductivity type; and a fifth doped region formed in the fifth well and having the second conductivity type, wherein the fifth doped region is coupled to the ground terminal; The first contact, the second contact and the fifth doped region form a parasitic bipolar junction transistor, wherein the parasitic bipolar junction transistor is used to discharge the electrostatic discharge charge received by the drain terminal to the ground terminal.

6. The semiconductor structure according to claim 2, wherein: The second well is further formed in the third well; The semiconductor structure further comprises: a sixth well formed in the third well and having the first conductivity type, wherein the second doped region is formed in the sixth well; and A seventh well is formed in the third well and has the second conductivity type, wherein the third doped region is formed in the seventh well.

7. The semiconductor structure according to claim 5, characterized in that The fifth well, the first well, the fourth well, the fourth doped region and the fourth well are arranged along a first direction, and the first contact and the second contact are arranged along a second direction; The first direction is different from the second direction.

8. A semiconductor structure, characterized in that: include: a substrate; a buried layer formed in the substrate and having a first conductivity type; an epitaxial layer, formed on the buried layer, having the first conductivity type; a first well, surrounding the epitaxial layer, and having the first conductivity type; a second well formed on the buried layer and having the first conductivity type; a third well formed in the first well and having the first conductivity type; a fourth well formed in the epitaxial layer and located between the second well and the third well, and having a second conductivity type; a first doped region formed in the second well and having the first conductivity type; a second doped region formed in the fourth well and having the first conductivity type; a third doped region formed in the fourth well and having the second conductivity type; a fourth doped region formed in the third well and having the first conductivity type; a first contact formed on the third well; a second contact formed on the fourth doped region and forming an ohmic contact with the fourth doped region; and A gate structure is formed between the first doping region and the second doping region.

9. The semiconductor structure according to claim 8, characterized in that The semiconductor structure is formed into a transistor; The transistor comprises a drain terminal, a gate terminal, a source terminal and a body terminal; The first doped region forms the drain terminal, the gate structure forms the gate terminal, the second doped region forms the source terminal, and the third doped region forms the body terminal; wherein the drain terminal, the first contact and the second contact are electrically connected together, and the source terminal and the substrate terminal are connected together; The first contact, the second contact, the third doped region and the second doped region form a silicon controlled rectifier; The source terminal is coupled to a ground terminal, and the silicon-controlled rectifier is used to discharge the electrostatic discharge charge received by the drain terminal to the ground terminal.

10. The semiconductor structure according to claim 9, wherein: The first contact and the third well form a Schottky contact.

11. The semiconductor structure according to claim 9, wherein: Also includes: An additional doped region is formed in the third well, wherein the first contact forms an ohmic contact with the additional doped region.

12. The semiconductor structure according to claim 9, wherein: Also includes: a fifth well surrounding the first well and having the second conductivity type; and a fifth doped region formed in the fifth well and having the second conductivity type, wherein the fifth doped region is coupled to the ground terminal; wherein the first contact, the second contact and the fifth doped region form a parasitic bipolar junction transistor; The parasitic bipolar junction transistor is used to discharge the electrostatic discharge charge received by the drain terminal to the ground terminal.

13. The semiconductor structure according to claim 8, wherein: The second well is formed in the first well.

14. The semiconductor structure according to claim 8, wherein: The second well is further formed in the third well; The semiconductor structure further comprises: a sixth well formed in the third well and having the first conductivity type, wherein the second doped region is formed in the sixth well; and A seventh well is formed in the third well and has the second conductivity type, wherein the third doped region is formed in the seventh well.

15. The semiconductor structure according to claim 12, wherein: The fifth well, the first well, the fourth well, the fourth doped region and the fourth well are arranged along a first direction, and the first contact and the second contact are arranged along a second direction; The first direction is different from the second direction.

Images