Chip test control method, chip test system and equipment

Abstract

The invention provides a chip test control method, a chip test system and equipment, and the method comprises the steps: setting a first communication serial port on a processor of a lower computer of the chip test system, and setting a second communication serial port on a controller; a serial port bridging request is sent to the controller through the first communication serial port, the processor and the controller execute a bridging program so that the processor and the controller can be bridged through the first communication serial port and the second communication serial port, and the upper computer and the processor are in communication connection through a network so that the upper computer can access the controller through the processor. Indirect communication between the upper computer and the controller is achieved, the upper computer and the controller do not need to be manually connected through external wiring, operation is easy, the testing efficiency can be improved, and equipment resources such as wiring tools can be saved.

Description

Technical Field

[0001] The present disclosure relates to chip testing technology, and in particular to a chip testing control method, a chip testing system and a chip testing device. Background Art

[0002] In the current chip test system, the control of the micro control unit (MCU) of the lower computer by the upper computer needs to be realized through various serial port tools such as channel transistor logic circuit (TTL) or RS232 interface. The technicians manually connect the serial port tools and configure various serial port programs to realize the data transmission between the upper computer and MCU of the chip test system.

[0003] However, in chip testing scenarios, one host computer usually corresponds to multiple MCUs. In the chip testing system, when the MCU needs to be terminally controlled, especially when the MCU needs to be controlled for business operations and information queries, technicians need to use serial port tools to connect each MCU. The operation process is cumbersome, inefficient, and requires a large number of serial port tools. Summary of the invention

[0004] The embodiments of the present disclosure provide a chip test control method, a chip test system and a device, which are simple to operate, can improve test efficiency, and can save equipment resources such as wiring tools.

[0005] In one aspect of an embodiment of the present disclosure, a chip test control method is provided. The method is applied to a lower computer in a chip test system. The chip test system includes an upper computer and the lower computer. The lower computer is provided with a processor and a controller. The processor is provided with a first communication serial port. The controller is provided with a second communication serial port. The method includes:

[0006] In response to receiving a redirection instruction sent by a host computer through the processor, controlling the processor to initiate a serial port bridge request to the controller through the first communication serial port, the processor and the host computer are connected through network communication, and the redirection instruction is used to instruct access to controller data through the processor;

[0007] Controlling the processor and the controller to execute a bridging program between the first communication serial port and the second communication serial port;

[0008] The controller data includes at least one of test data, log data and alarm information generated by the controller during chip testing.

[0009] Optionally, after controlling the processor and the controller to execute a bridging program between the first communication serial port and the second communication serial port, the method includes:

[0010] When the first communication serial port is successfully bridged with the second communication serial port, controlling the controller to send the controller data to the processor through the second communication serial port;

[0011] Control the processor to receive and store the controller data through the first communication serial port;

[0012] The processor receives and parses the data query instruction sent by the host computer, determines the query result based on the stored controller data, and sends the query result to the host computer.

[0013] Optionally, the upper computer corresponds to a processor connected to at least one lower computer, and different lower computers correspond to different lower computer identifiers;

[0014] Before sending the query result to the host computer, the method includes:

[0015] A data prefix is ​​added to the query result, wherein the data prefix includes a lower computer identifier of the lower computer where the processor is located.

[0016] Optionally, after controlling the processor and the controller to execute a bridging program between the first communication serial port and the second communication serial port, the method includes:

[0017] Receiving and parsing the test control instructions sent by the host computer through the processor;

[0018] The control object in response to the test control instruction is the controller, and the test control instruction is forwarded to the controller through the first communication serial port so that the controller executes the test control instruction. The test control instruction includes at least one of controller restart and controller upgrade.

[0019] Optionally, the controller is provided with a third communication serial port, and the third communication serial port is connected to the host computer via an external transmission line, and the method further includes:

[0020] In response to receiving a redirection cancellation instruction sent by the host computer through the processor, controlling the processor to initiate a serial port bridge cancellation request to the controller through the first communication serial port, wherein the redirection cancellation instruction is used to instruct to stop accessing the controller data through the processor;

[0021] Controlling the processor and the controller to execute a bridge cancellation procedure between the first communication serial port and the second communication serial port;

[0022] In response to receiving the data query instruction through the third communication serial port, controlling the controller to output the controller data through the third communication serial port.

[0023] Optionally, the host computer is used to communicate with the processor via a secure shell protocol (Secure Shell, SSH).

[0024] Optionally, the serial port types of the first communication serial port and the second communication serial port include Universal Asynchronous Receiver Transmitter (UART) serial ports.

[0025] Another aspect of the embodiment of the present disclosure provides a chip testing system, the system comprising a host computer and at least one slave computer, the at least one slave computer being provided with a processor and a controller, the processor being provided with a first communication serial port, the controller being provided with a second communication serial port, the host computer being connected to the processor in the at least one slave computer via network communication;

[0026] The processor is used to initiate a serial port bridge request to the controller through the first communication serial port in response to a redirection instruction sent by the host computer, wherein the redirection instruction is used to instruct to access controller data through the processor;

[0027] The controller is used to execute a bridging program between the first communication serial port and the second communication serial port together with the processor upon receiving the bridging request;

[0028] The controller data includes at least one of test data, log data and alarm information generated by the controller during chip testing.

[0029] Optionally, the system further includes a switch;

[0030] The switch is used to respectively connect the processors in the host computer and the at least one slave computer through SSH to perform data transmission between the host computer and the processors in the at least one slave computer.

[0031] Another aspect of the present disclosure provides an electronic device, including:

[0032] Memory for storing computer programs;

[0033] The processor is used to execute the computer program stored in the memory, and when the computer program is executed, the method described in the above aspects is implemented.

[0034] Another aspect of the embodiments of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the method described in the above aspects is implemented.

[0035] Another aspect of the embodiments of the present disclosure provides a computer program, including computer program instructions, which implement the methods described in the above aspects when executed by a processor.

[0036] Based on the embodiments of the present disclosure, by setting a first communication serial port on the processor of the lower computer and setting a second communication serial port on the controller, when the processor receives a redirection instruction sent by the upper computer, a serial port bridging request is sent to the controller through the first communication serial port, and the processor and the controller execute a bridging program to bridge the processor and the controller through the first communication serial port and the second communication serial port. The upper computer and the processor are connected through network communication, so that the upper computer can access the controller data through the processor, thereby realizing indirect communication between the upper computer and the controller. There is no need to manually connect the upper computer and the controller through external wiring, the operation is simple, the test efficiency can be improved, and equipment resources such as wiring tools can be saved.

[0037] The technical solution of the present disclosure is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0039] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0040] Figure 1 A flowchart of an embodiment of a chip test control method disclosed in the present invention;

[0041] Figure 2 A flowchart of another embodiment of the chip test control method disclosed in the present invention;

[0042] Figure 3 A flowchart of another embodiment of the chip test control method disclosed in the present invention;

[0043] Figure 4 A flowchart of another embodiment of the chip test control method disclosed in the present invention;

[0044] Figure 5 A structural block diagram of an embodiment of a chip testing system disclosed in the present invention;

[0045] Figure 6 It is a structural block diagram of an embodiment of the chip test control device disclosed in the present invention;

[0046] Figure 7 The figure is a schematic diagram of the structure of an application embodiment of the electronic device disclosed in the present invention. DETAILED DESCRIPTION

[0047] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless otherwise specifically stated.

[0048] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0049] It should also be understood that in the embodiments of the present disclosure, “plurality” may refer to two or more than two, and “at least one” may refer to one, two, or more than two.

[0050] It should also be understood that any component, data or structure mentioned in the embodiments of the present disclosure can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0051] In addition, the term "and / or" in the present disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present disclosure generally indicates that the associated objects before and after are in an "or" relationship.

[0052] It should also be understood that the description of the various embodiments in the present disclosure focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0053] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0054] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0055] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0056] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0057] Please refer to Figure 1 , which shows a flow chart of a chip test control method provided by an exemplary embodiment of the present disclosure. The chip test control method of the embodiment of the present disclosure can be implemented by a lower computer in a chip test system. The chip test system includes an upper computer and a lower computer, wherein the lower computer is provided with a processor and a controller, the processor is provided with a first communication serial port, and the controller is provided with a second communication serial port. The method includes the following steps:

[0058] Step 101, in response to receiving a redirection instruction sent by a host computer through a processor, the processor is controlled to initiate a serial port bridge request to a controller through a first communication serial port.

[0059] The processor is connected to the host computer via network communication, and the redirection instruction is used to instruct the processor to access the controller data, wherein the controller data may include, but is not limited to, at least one of the test data, log data, and alarm information generated by the controller during the chip test process.

[0060] In a possible implementation, the user can perform a lower-machine connection operation through the upper computer, so that the upper computer is connected to the processor of the lower computer through the network. For example, the lower-machine connection operation can be implemented by inputting a lower-machine connection instruction in the upper computer operating system, or by inputting a lower-machine connection instruction or triggering a lower-machine connection control through a chip test application running on the upper computer, etc. The embodiment of the present disclosure does not limit the operation form of the lower-machine connection operation.

[0061] After the host computer is successfully connected to the processor, a redirection operation is performed. For example, a redirection instruction can be sent to the host computer through the start up service in the operating system to instruct the processor to trigger the serial port bridge program with the controller, thereby opening up the serial port communication from the processor to the controller.

[0062] After receiving the redirection instruction sent by the host computer, the processor initiates a serial port bridge request to the controller through the first communication serial port.

[0063] Optionally, the processor in the lower computer can adopt a reduced instruction set computer (RISC), such as an advanced RISC processor (ARM), a microprocessor without interlocked pipelined stages (MIPS), etc.; the controller can adopt a micro control unit (MCU), a central processing unit (CPU), etc.

[0064] Step 102: Control the processor and the controller to execute a bridge program between the first communication serial port and the second communication serial port.

[0065] The bridge program between the first communication serial port and the second communication serial port can connect the communication link between the first communication serial port and the second communication serial port, so that the first communication serial port and the second communication serial port can communicate bidirectionally. Schematically, the serial port types of the first communication serial port and the second communication serial port can include but are not limited to UART, RS-232, and transistor-transistor logic (TTL) interface, etc.

[0066] In one possible implementation, the processor and the controller execute a bridging program between the first communication serial port and the second communication serial port. When the first communication serial port and the second communication serial port are successfully bridged, the processor can send a prompt message to the host computer to indicate that the bridging is successful, so as to prompt the user to obtain controller data through the host computer. Alternatively, if the bridging between the first communication serial port and the second communication serial port fails, the processor can send a prompt message to the host computer to indicate that the bridging fails.

[0067] Optionally, after the first communication serial port is successfully bridged with the second communication serial port, the processor may start serial port monitoring of the first communication serial port to timely receive controller data sent by the controller through the second communication serial port.

[0068] Based on the embodiments of the present disclosure, by setting a first communication serial port on the processor of the lower computer and setting a second communication serial port on the controller, when the processor receives a redirection instruction sent by the upper computer, a serial port bridging request is sent to the controller through the first communication serial port, and the processor and the controller execute a bridging program to bridge the processor and the controller through the first communication serial port and the second communication serial port. The upper computer and the processor are connected through network communication, so that the upper computer can access the controller data through the processor, thereby realizing indirect communication between the upper computer and the controller. There is no need to manually connect the upper computer and the controller through external wiring, the operation is simple, the test efficiency can be improved, and equipment resources such as wiring tools can be saved.

[0069] In a possible implementation, after the processor and the controller execute the bridge program between the first communication serial port and the second communication serial port, the host computer can access the controller data through the processor. Figure 2 As shown, after the above step 103, the method provided by the embodiment of the present disclosure further includes the following steps:

[0070] Step 201 , when the first communication serial port and the second communication serial port are successfully bridged, the controller is controlled to send controller data to the processor through the second communication serial port.

[0071] Optionally, after the first communication serial port and the second communication serial port are successfully bridged, the controller can send controller data generated during the chip test process to the processor in real time through the second communication serial port. For example, the controller log can be sent to the processor through the second communication serial port at a preset frequency, and test data such as voltage values ​​and temperature values ​​can be sent to the processor in real time through the second communication serial port during the chip test process, and alarm information can be sent to the processor in real time through the second communication serial port when alarm information is generated.

[0072] Optionally, the controller may also send controller data to the processor through the second communication serial port after receiving the data acquisition request sent by the processor. The embodiment of the present disclosure does not limit the timing of sending the controller data.

[0073] Step 202: The control processor receives and stores controller data via the first communication serial port.

[0074] In a possible implementation, when the first communication serial port is successfully bridged with the second communication serial port, the processor starts serial port monitoring of the first communication serial port to timely receive controller data sent by the controller. A storage unit is provided in the processor, and the storage unit is used to store the received controller data.

[0075] Optionally, the processor may store all received controller data, or the processor may filter and store the received controller data based on preset filtering conditions.

[0076] Step 203, receiving and parsing the data query instruction sent by the host computer through the processor, determining the query result based on the stored controller data, and sending the query result to the host computer.

[0077] During the chip testing process, the user can perform data query operations through the host computer as needed, so that the host computer sends data query instructions to the processor of the subordinate computer through the network. The processor receives the data query instructions sent by the host computer, parses the query conditions indicated by the data query instructions (for example, the query conditions may include but are not limited to data types, data acquisition time), and determines the query results from the stored controller data based on the query conditions obtained by the analysis and feeds them back to the host computer.

[0078] In another possible implementation, for important data such as alarm information, the processor may directly send such data to the host computer without waiting for a data query instruction.

[0079] Optionally, a host computer in the chip test system may correspond to a processor connected to at least one slave computer. To facilitate data management of the host computer, different slave computers correspond to different slave computer identifiers. Before sending the query result to the host computer, the processor further performs the following steps:

[0080] A data prefix is ​​added to the query result, where the data prefix includes a lower computer identifier (ID) of the lower computer where the processor is located.

[0081] Each slave computer may correspond to a unique slave computer identifier. By adding a data prefix including the slave computer identifier to the query result, the upper computer may manage the data reported by each slave computer based on the data prefix.

[0082] In a possible implementation, after the processor and the controller execute the bridge program between the first communication serial port and the second communication serial port, the host computer can also perform service control on the controller through the processor. Figure 3 As shown, after the above step 103, the method provided by the embodiment of the present disclosure further includes the following steps:

[0083] Step 301: Receive and parse the test control instruction sent by the host computer through the processor.

[0084] The user can perform a test control operation on the processor or controller through the host computer, so that the host computer sends a test control instruction to the processor. The processor receives and analyzes the test control instruction sent by the host computer to determine the control object of the test control instruction.

[0085] Step 302 , in response to the control object of the test control instruction being a controller, forwarding the test control instruction to the controller through the first communication serial port, so that the controller executes the test control instruction.

[0086] The test control instruction may include, for example, but is not limited to, at least one of a controller restart and a controller upgrade.

[0087] When the processor parses the test control instruction and obtains that the control object is the processor, the test control instruction is directly executed. When the processor parses the test control instruction and obtains that the control object is the controller, the test control instruction is forwarded to the controller through the first communication serial port, so that the controller executes the test control instruction, and correspondingly implements operations such as controller restart, controller upgrade and update.

[0088] Based on the embodiments of the present disclosure, the host computer can access the controller through the processor, perform log management, alarm information query and test data query on the controller, thereby realizing data compatibility management between the processor and the controller. Moreover, compared with the method of accessing the controller data through external wiring after the chip test is completed, the alarm information generated by the controller can be received in time during the chip test process, which is convenient for technicians to quickly determine the cause of the abnormality when the test is abnormal.

[0089] In a possible implementation, the controller is further provided with a third communication serial port, which is connected to the host computer via an external transmission line, and the host computer can switch between two connection modes with the controller (indirect connection via the processor and direct connection via the external transmission line). Figure 4 As shown, the method provided by the embodiment of the present disclosure may also include the following steps:

[0090] Step 401, in response to receiving a redirection cancellation instruction sent by a host computer through a processor, the control processor initiates a serial port bridge cancellation request to the controller through the first communication serial port.

[0091] The redirect cancel instruction is used to instruct the processor to stop accessing controller data.

[0092] In the processor, the chip test mode is difficult to be compatible with the controller log management in the debug mode. Therefore, in the debug mode, the host computer can switch the access mode of the controller data, directly connect to the controller through an external transmission line and access the data. The user can perform a redirection cancel operation through the host computer to make the host computer send a redirection cancel instruction to the processor. For example, the redirection cancel instruction can be sent to the lower computer through the start up service in the operating system.

[0093] After receiving the redirection cancellation instruction sent by the host computer, the processor initiates a serial port bridge cancellation request to the controller through the first communication serial port to cut off the bridge connection between the first communication serial port and the second communication serial port.

[0094] Step 402: Control the processor and the controller to execute a procedure for canceling the bridge connection between the first communication serial port and the second communication serial port.

[0095] The bridge cancellation procedure between the first communication serial port and the second communication serial port can cut off the communication link between the first communication serial port and the second communication serial port, so that the first communication serial port and the second communication serial port cannot send data to each other. After the processor and the controller execute the bridge cancellation procedure between the first communication serial port and the second communication serial port, the processor stops monitoring the serial port of the first communication serial port, and the controller also stops sending controller data to the processor through the second communication serial port.

[0096] Step 403 , in response to receiving a data query instruction through the third communication serial port, controlling the controller to output controller data through the third communication serial port.

[0097] Based on the embodiments of the present disclosure, the host computer can access the controller data through the processor, and can also restore to the data reading mode of accessing the controller through the external transmission line, which can take into account the chip testing process and the controller data management in the debugging mode.

[0098] Optionally, the host computer is used to communicate with the processor via SSH to improve communication security. Schematically, a switch is also provided in the system, which is connected to the processors in the host computer and the slave computer respectively via SSH, and is responsible for data transmission between the host computer and the processor. In addition, the host computer and the processor can also communicate via security protocols such as the Transport Layer Security Protocol (Secure Sockets Layer, SSL), the Computer Network Authorization Protocol (Kerberos), etc., and the disclosed embodiment does not limit the type of protocol between the host computer and the processor.

[0099] Optionally, the serial port types of the first communication serial port and the second communication serial port include UART serial ports to achieve bidirectional communication between the processor and the controller.

[0100] Please refer to Figure 5 , which shows a block diagram of a chip testing system. The system includes a host computer 501 and at least one slave computer 502, wherein at least one slave computer 502 is provided with a processor 502a and a controller 502b, wherein the processor 502a is provided with a first communication serial port, and the controller 502b is provided with a second communication serial port, and the host computer 501 is connected to the processor 502a in at least one slave computer 502 via network communication.

[0101] The processor 502a is used to initiate a serial port bridge request to the controller 502b through the first communication serial port in response to a redirection instruction sent by the host computer 501, and the redirection instruction is used to instruct to access the controller data through the processor 502a.

[0102] The controller 502b is used to execute a bridging procedure between the first communication serial port and the second communication serial port together with the processor 520a when receiving a bridging request.

[0103] The controller data may include, for example, but is not limited to, at least one of test data, log data, and alarm information generated by the controller 502b during the chip testing process.

[0104] In a possible implementation, the user can perform a lower machine connection operation through the host computer, so that the host computer is connected to the processor of the lower machine through the network. For example, the lower machine connection operation can be implemented by inputting a lower machine connection instruction in the host computer operating system, or by inputting a lower machine connection instruction or triggering a lower machine connection control through a chip test application running on the host computer, etc. The present disclosure embodiment does not limit the operation form of the lower machine connection operation. After the host computer is successfully connected to the processor, a redirection operation is performed, for example, a redirection instruction can be sent to the lower computer through the start up service in the operating system, indicating that the processor triggers the serial port bridge program with the controller, thereby opening up the serial port communication from the processor to the controller. After receiving the redirection instruction sent by the host computer, the processor initiates a serial port bridge request to the controller through the first communication serial port. The processor and the controller execute a bridge program between the first communication serial port and the second communication serial port, and the bridge program can connect the communication link between the first communication serial port and the second communication serial port, so that the first communication serial port and the second communication serial port can communicate bidirectionally. When the first communication serial port and the second communication serial port are successfully bridged, the processor can send a prompt message to the host computer indicating that the bridge is successful, so as to prompt the user to obtain the controller data through the host computer, or, if the first communication serial port and the second communication serial port fail to bridge, the processor can send a prompt message to the host computer indicating that the bridge fails. Optionally, after the first communication serial port and the second communication serial port are successfully bridged, the processor can start the serial port monitoring of the first communication serial port to timely receive the controller data sent by the controller through the second communication serial port.

[0105] Optionally, in a possible implementation, Figure 5 The illustrated system may also include a switch 503 .

[0106] The switch 503 is used to respectively connect the host computer 501 and the processor 502a in at least one slave computer 502 through SSH to perform data transmission between the host computer 501 and the processor 502a in at least one slave computer 502.

[0107] In a possible implementation, in order to facilitate data management of the upper computer, different lower computers correspond to different lower computer identifiers. By adding a data prefix including the lower computer identifier to the query result, the processor can enable the upper computer to manage the data reported by each lower computer based on the data prefix. Accordingly, the upper computer can add an instruction prefix including the lower computer identifier before the issued data query instruction, test control instruction, etc., so that the switch forwards the instruction to the processor in the corresponding lower computer.

[0108] Figure 5Only a chip testing system with one host computer 501, one switch 503 and three slave computers 502 is shown. In other possible application scenarios, more host computers 501, switches 503 and slave computers 502 can be set. The embodiment of the present disclosure does not limit the number of various types of equipment.

[0109] Please refer to Figure 6 , which shows a block diagram of a chip test control device provided by an exemplary embodiment of the present disclosure. The chip test control device provided by this embodiment is applied to a lower computer in a chip test system, and the chip test system includes an upper computer and a lower computer, and a processor and a controller are provided in the lower computer, and a first communication serial port is provided on the processor, and a second communication serial port is provided on the controller. The device includes:

[0110] The receiving module 601 is used to control the processor to initiate a serial port bridge request to the controller through the first communication serial port in response to receiving a redirection instruction sent by the host computer through the processor. The processor is connected to the host computer through network communication. The redirection instruction is used to instruct access to the controller data through the processor.

[0111] The control module 602 is used to control the processor and the controller to execute a bridge program between the first communication serial port and the second communication serial port.

[0112] The controller data may include, for example, but is not limited to, at least one of test data, log data, and alarm information generated by the controller during the chip testing process.

[0113] Optionally, in a possible implementation manner, the control module 602 is further configured to:

[0114] When the first communication serial port is successfully bridged with the second communication serial port, the controller is controlled to send controller data to the processor through the second communication serial port;

[0115] The control processor receives and stores the controller data through the first communication serial port;

[0116] The processor receives and parses the data query instruction sent by the host computer, determines the query result based on the stored controller data, and sends the query result to the host computer.

[0117] Optionally, in a possible implementation manner, the upper computer corresponds to a processor connected to at least one lower computer, and different lower computers correspond to different lower computer identifiers; the control module 602 is further used to:

[0118] A data prefix is ​​added to the query result, where the data prefix includes the lower computer identifier of the lower computer where the processor is located.

[0119] Optionally, in a possible implementation manner, the receiving module 601 is further configured to:

[0120] Receive and analyze the test control instructions sent by the host computer through the processor;

[0121] The control module 602 is also used to respond to the control object of the test control instruction as the controller, and forward the test control instruction to the controller through the first communication serial port so that the controller executes the test control instruction. The test control instruction may include but is not limited to at least one of controller restart and controller upgrade.

[0122] Optionally, in a possible implementation manner, a third communication serial port is provided on the controller, and the third communication serial port is connected to the host computer through an external transmission line; the control module 602 is further used for:

[0123] In response to receiving a redirection cancellation instruction sent by the host computer through the processor, controlling the processor to initiate a serial port bridge cancellation request to the controller through the first communication serial port, wherein the redirection cancellation instruction is used to instruct to stop accessing the controller data through the processor;

[0124] Control the processor and the controller to execute a procedure for canceling the bridge connection between the first communication serial port and the second communication serial port;

[0125] In response to receiving a data query instruction through the third communication serial port, the controller is controlled to output controller data through the third communication serial port.

[0126] Optionally, in a possible implementation manner, the host computer is used to communicate with the processor via SSH.

[0127] Optionally, in a possible implementation manner, the serial port types of the first communication serial port and the second communication serial port include UART serial ports.

[0128] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The parts of the same, similar or corresponding contents between the various embodiments can be referred to each other. Since the system, method, device, and equipment embodiments basically correspond to each other, the relevant parts can be referred to the description of the corresponding parts. The systems, methods, devices, and equipment of the embodiments of the present disclosure also correspond to each other in terms of specific implementation and beneficial technical effects. The relevant contents can be referred to each other and will not be repeated.

[0129] In addition, an embodiment of the present disclosure further provides an electronic device, including:

[0130] Memory for storing computer programs;

[0131] The processor is used to execute the computer program stored in the memory, and when the computer program is executed, the chip test control method described in any of the above embodiments of the present disclosure is implemented.

[0132] Figure 7 This is a schematic diagram of the structure of an application embodiment of the electronic device disclosed in the present invention. Figure 7 The electronic device according to the embodiment of the present disclosure is described. The electronic device may be any one or both of the first device and the second device, or a stand-alone device independent of them, and the stand-alone device may communicate with the first device and the second device to receive the collected input signals from them.

[0133] like Figure 7 As shown, the electronic device includes one or more processors and memory.

[0134] The processor may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0135] The memory may include one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor may execute the program instructions to implement the chip test control method of each embodiment of the present disclosure described above and / or other desired functions.

[0136] In one example, the electronic device may further include: an input device and an output device, and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0137] In addition, the input device may also include, for example, a keyboard, a mouse, and the like.

[0138] The output device can output various information to the outside, including the determined distance information, direction information, etc. The output device can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.

[0139] Of course, to simplify, Figure 7Only some of the components related to the present disclosure in the electronic device are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device may further include any other appropriate components.

[0140] In addition to the above-mentioned methods and devices, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the chip test control method according to various embodiments of the present disclosure described in the above part of this specification.

[0141] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0142] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium on which computer program instructions are stored. When the computer program instructions are executed by a processor, the processor executes the steps of the chip test control method according to various embodiments of the present disclosure described in the above part of this specification.

[0143] The computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0144] A person of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiment; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk, etc., various media that can store program codes.

[0145] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0146] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system embodiment, since it basically corresponds to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0147] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0148] The method and apparatus of the present disclosure may be implemented in many ways. For example, the method and apparatus of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps for the method is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above, unless otherwise specifically stated. In addition, in some embodiments, the present disclosure may also be implemented as a program recorded in a recording medium, which includes machine-readable instructions for implementing the method according to the present disclosure. Therefore, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.

[0149] It should also be noted that in the apparatus, device and method of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present disclosure.

[0150] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0151] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A chip test control method, characterized in that: A lower computer used in a chip testing system, the chip testing system comprising an upper computer and the lower computer, the lower computer being provided with a processor and a controller, the processor being provided with a first communication serial port, the controller being provided with a second communication serial port, the method comprising: In response to receiving a redirection instruction sent by a host computer through the processor, controlling the processor to initiate a serial port bridge request to the controller through the first communication serial port, the processor and the host computer are connected through network communication, and the redirection instruction is used to instruct access to controller data through the processor; Controlling the processor and the controller to execute a bridging program between the first communication serial port and the second communication serial port; The controller data includes at least one of test data, log data and alarm information generated by the controller during chip testing.

2. The method according to claim 1, characterized in that After controlling the processor and the controller to execute a bridging program between the first communication serial port and the second communication serial port, the method includes: When the first communication serial port is successfully bridged with the second communication serial port, controlling the controller to send the controller data to the processor through the second communication serial port; Control the processor to receive and store the controller data through the first communication serial port; The processor receives and parses the data query instruction sent by the host computer, determines the query result based on the stored controller data, and sends the query result to the host computer.

3. The method according to claim 2, characterized in that The upper computer corresponds to a processor connected to at least one lower computer, and different lower computers correspond to different lower computer identifiers; Before sending the query result to the host computer, the method includes: A data prefix is ​​added to the query result, wherein the data prefix includes a lower computer identifier of the lower computer where the processor is located.

4. The method according to claim 1, characterized in that: After controlling the processor and the controller to execute a bridging program between the first communication serial port and the second communication serial port, the method includes: Receiving and parsing the test control instructions sent by the host computer through the processor; The control object in response to the test control instruction is the controller, and the test control instruction is forwarded to the controller through the first communication serial port so that the controller executes the test control instruction. The test control instruction includes at least one of controller restart and controller upgrade.

5. The method according to any one of claims 1 to 4, characterized in that: The controller is provided with a third communication serial port, and the third communication serial port is connected to the host computer through an external transmission line. The method further includes: In response to receiving a redirection cancellation instruction sent by the host computer through the processor, controlling the processor to initiate a serial port bridge cancellation request to the controller through the first communication serial port, wherein the redirection cancellation instruction is used to instruct to stop accessing the controller data through the processor; Controlling the processor and the controller to execute a bridge cancellation procedure between the first communication serial port and the second communication serial port; In response to receiving the data query instruction through the third communication serial port, controlling the controller to output the controller data through the third communication serial port.

6. The method according to any one of claims 1 to 4, characterized in that: The host computer is used to communicate with the processor via the secure shell protocol SSH.

7. The method according to any one of claims 1 to 4, characterized in that: The serial port types of the first communication serial port and the second communication serial port include Universal Asynchronous Receiver / Transmitter (UART) serial ports.

8. A chip testing system, characterized in that: The system comprises an upper computer and at least one lower computer, wherein the at least one lower computer is provided with a processor and a controller, the processor is provided with a first communication serial port, the controller is provided with a second communication serial port, and the upper computer is connected to the processor in the at least one lower computer through network communication; The processor is used to initiate a serial port bridge request to the controller through the first communication serial port in response to a redirection instruction sent by the host computer, wherein the redirection instruction is used to instruct to access controller data through the processor; The controller is used to execute a bridging program between the first communication serial port and the second communication serial port together with the processor upon receiving the bridging request; The controller data includes at least one of test data, log data and alarm information generated by the controller during chip testing.

9. The system according to claim 8, characterized in that Also includes switches; The switch is used to respectively connect the processors in the host computer and the at least one slave computer through SSH to perform data transmission between the host computer and the processors in the at least one slave computer.

10. An electronic device, characterized in that: include: Memory for storing computer programs; A processor is used to execute the computer program stored in the memory, and when the computer program is executed, the method described in any one of claims 1 to 7 is implemented.

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