A low-power reference voltage buffer applied to high-speed high-precision ADC

Abstract

The application discloses a low-power reference voltage buffer applied to a high-speed high-precision ADC, which uses a PMOS tube connected in a diode mode to realize resistance, and combines the high-bandwidth characteristic of an open-loop structure to realize AB class output, so that the power consumption of the output voltage buffer can be effectively reduced while the transient response speed is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of reference voltage buffer, and particularly relates to a low-power reference voltage buffer applied to high-speed high-precision ADC. BACKGROUND

[0002] In recent decades, the ultra-large scale integrated circuit has developed rapidly, and constantly gives birth to new application scenarios. In the mobile terminal application represented by WiFi, the successive approximation register analog-to-digital converter (SAR ADC) with the characteristics of low power consumption and small area is very popular. Under the 802.11ac / ax standard, the signal-to-noise ratio of 60-70dB is a necessary condition to meet the link noise budget (requires the analog-to-digital converter (ADC) to have a resolution of 10-bit or more); at the same time, as the working frequency of the WiFi signal is getting faster and faster, the requirement for the signal is getting higher and higher, these conditions continuously improve the speed and accuracy requirements of the ADC; at the same time, the pursuit of power consumption of the mobile terminal limits the selection of the ADC architecture. The serial working characteristics of the SAR ADC naturally limit its speed, however, its good process compatibility makes its working speed improve with the proportional reduction of the complementary metal oxide semiconductor (CMOS) process, and the current 12-bit SAR ADC can reach a conversion rate of more than 100-MSPS.

[0003] The high-speed conversion greatly improves the requirements of the reference voltage buffer, and even becomes the main bottleneck factor limiting the overall performance. For high-precision ADC, the limited gain bandwidth of the operational amplifier, the comparator offset, the capacitor mismatch and other non-ideal factors will deteriorate the ADC performance, and the accuracy of the reference voltage which determines the quantization standard will also directly affect the conversion accuracy of the ADC. Due to the limited driving ability, the reference voltage circuit inevitably introduces dynamic errors, and such errors are difficult to eliminate through correction technology. Therefore, for the ADC with higher working frequency and conversion accuracy, it is essential to have a high-precision reference voltage with fast response capability.

[0004] The main function of the reference voltage buffer is to output the reference voltage input from the previous stage to drive the capacitor type digital-to-analog converter (DAC) switch array load, while requiring fast response capability to establish the reference voltage to less than one least significant bit (LSB) range in the fast switching of the load. The reference voltage buffer generally adopts the following two ways:

[0005] (1) As shown in Figure 1 , it is a closed-loop structure based on voltage series negative feedback, which is connected to a large capacitor at the output end to obtain a buffer with slow setting time but stable output voltage. This circuit structure design is relatively simple, and it is easy to realize lower output resistance, but a large capacitor needs to be externally connected to the load to ensure low output impedance in a wide frequency band. Since the external capacitor will reach μF level, the integration of the chip will be significantly reduced, and due to the large capacitor connected at the output end, the response speed of the output voltage will be slow. At the same time, due to the stability constraints, the main pole must be very low, so it is only suitable for low-speed occasions.

[0006] (2) As shown in Figure 2 , it is an open-loop structure based on source follower replication. This structure can maintain low output impedance in a wider frequency band due to its open-loop characteristics, and does not need to rely on large capacitors to suppress high-frequency components, so it has the ability of fast response. Since the source of Mn1 is no longer used as an output point, the source of Mn1 does not need to be connected to an additional capacitor to achieve low output impedance in a wide frequency band. The main pole of the loop where the operational amplifier is located is separated from the output tube's gate-source parasitic capacitor (Cgs2), and the negative feedback loop where the operational amplifier is located no longer participates in the formation of the output impedance. The adjustment of the operational amplifier is to generate a suitable output tube gate voltage to generate the required reference voltage value, making the operational amplifier design simple. This structure of the reference voltage buffer has a large swing rate, high bandwidth, and the output voltage can be quickly established. At the same time, achieving large swing rate and high bandwidth means large current. Therefore, under the requirement of low power consumption of the system, this structure has high design difficulty and challenge.

[0007] A good reference voltage buffer should have the ability to quickly drive a low-impedance load, implement front and rear stage circuit isolation, accurate voltage output, and low power consumption.

[0008] As shown in Figure 3 , it is an open-loop structure based on source follower replication Figure 2 ), by adding a symmetric negative feedback loop and a replicated open-loop structure (A2, Mp1, and Mp2) to form an AB class output structure at the output stage. Figure 2Compared with the current multiplexing through the AB class output structure, low output impedance can be maintained in a wider frequency band. However, the circuit structure is increased, the current consumption is increased, and greater power consumption is caused.

[0009] Based on the above, the existing reference voltage buffer circuit mainly has the following disadvantages:

[0010] (1) Power consumption: source follower replication circuit structure ( Figure 1 ), which constitutes an open loop structure to obtain high transient response speed, but at the cost of greater output stage current and power consumption; the AB class output structure based on source follower replication ( Figure 3 ) can maintain low output impedance in a wider frequency band, but at the cost of increasing the power consumption of the circuit.

[0011] (2) Output impedance: the resistance is used as a load ( Figure 2 ) compared with the AB class output structure, the output impedance is greater; although the circuit shown in Figure 3 has reduced output impedance, it increases the complexity and power consumption of the circuit.

[0012] (3) Noise: due to the continuous switching of the load when the reference voltage buffer is normally working, additional coupling and crosstalk are introduced into the loop, which affects the stability of the loop and thus the stability of the output voltage. There is no protective feedback loop to protect the output high-frequency noise from interfering with the output voltage.

[0013] Therefore, it is necessary to provide a low-power reference voltage buffer applied to high-speed high-precision ADC. SUMMARY

[0014] The purpose of the present application is to provide a low-power reference voltage buffer applied to high-speed high-precision ADC, which uses PMOS tubes connected in diode mode to realize resistance, and combines the high bandwidth characteristics of the open loop structure to realize AB class output, which can effectively reduce the power consumption of the output voltage buffer while ensuring the transient response speed.

[0015] The technical scheme of the present application is: a low-power reference voltage buffer applied to high-speed high-precision ADC, comprising a feedback loop, a current mirror and an output branch; wherein,

[0016] The feedback loop comprises an amplifier, a first NMOS tube Mn1 and a first PMOS tube Mp1, the output end of the amplifier is electrically connected to the gate of the first NMOS tube Mn1, the reverse input end of the amplifier is electrically connected to the source of the first NMOS tube Mn1 and the source of the first PMOS tube Mp1 respectively, and the gate and drain of the first PMOS tube Mp1 are grounded;

[0017] The output branch comprises a second NMOS transistor Mn2, a third NMOS transistor Mn3, a second PMOS transistor Mp2 and a third PMOS transistor Mp3, the gate of the second NMOS transistor Mn2 is electrically connected to the gate of the third NMOS transistor Mn3, the source of the second NMOS transistor Mn2 is electrically connected to the source of the second PMOS transistor Mp2, the gate and the drain of the second PMOS transistor Mp2 are grounded and electrically connected to the gate of the third PMOS transistor Mp3, the drain of the third NMOS transistor Mn3 is electrically connected to a first voltage source, the source of the third NMOS transistor Mn3 is electrically connected to the source of the third PMOS transistor Mp3, and the drain of the third PMOS transistor Mp3 is grounded.

[0018] The current mirror comprises a fourth PMOS transistor Mp4 and a fifth PMOS transistor Mp5, the sources of the fourth PMOS transistor Mp4 and the fifth PMOS transistor Mp5 are electrically connected to a second voltage source, the drain of the first NMOS transistor Mn1 is electrically connected to the gate and the drain of the fourth PMOS transistor Mp4 and the gate of the fifth PMOS transistor Mp5 respectively, and the drain of the second NMOS transistor Mn2 is electrically connected to the gate and the drain of the fifth PMOS transistor Mp5.

[0019] In the technical scheme, the positive input end of the amplifier inputs a 0.7V bandgap reference voltage.

[0020] In the technical scheme, the first NMOS transistor Mn1 and the second NMOS transistor Mn2 satisfy:

[0021] Mn2=K1 Mn1

[0022] The first PMOS transistor Mp1 and the second PMOS transistor Mp2 satisfy:

[0023] Mp2=K1 Mp1

[0024] The fourth PMOS transistor Mp4 and the fifth PMOS transistor Mp5 satisfy:

[0025] W / L (Mp5) =K1 W / L (Mp4)

[0026] Wherein, K1 is a proportional coefficient.

[0027] In the technical scheme, the proportional coefficient K1 is associated with the transconductance of the second NMOS transistor Mn2.

[0028] In the technical scheme, the input voltage of the first voltage source is less than the input voltage of the second voltage source.

[0029] In the above technical solution, the first voltage source inputs a voltage of 0.9V.

[0030] In the above technical solution, the second voltage source inputs a voltage of 1.8V.

[0031] In the above technical solution, a resistor R1 is connected in series between the drain of the second NMOS transistor Mn2 and the drain of the fifth PMOS transistor Mp5.

[0032] In the above technical solution, a resistor R2 is connected in series between the gate of the second NMOS transistor Mn2 and the gate of the third NMOS transistor Mn3.

[0033] In the above technical solution, a resistor R2 is connected in series between the gate of the second PMOS transistor Mp2 and the gate of the third PMOS transistor Mp3.

[0034] The advantages of the present invention are:

[0035] The low-power reference voltage buffer of the present invention uses a simple low-resistance implementation method and combines the high bandwidth of the open loop and the current multiplexing of the class AB output to effectively reduce the power consumption of the output voltage buffer and improve the transient response speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The present invention will be further described below with reference to the accompanying drawings and embodiments:

[0037] Figure 1 It is a schematic diagram of a closed-loop structure based on voltage series negative feedback in the background technology.

[0038] Figure 2 Schematic diagram of an open-loop structure based on source follower replication in the background technology.

[0039] Figure 3 Schematic diagram of a class AB output structure based on source follower replication in the background technology.

[0040] Figure 4 Schematic diagram of the buffer circuit structure according to an embodiment of the present invention.

[0041] Figure 5 Schematic diagram of a circuit structure for achieving low resistance based on a gate-drain shorting MOS transistor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0042] Example:

[0043] like Figure 4 As shown, the present invention provides a low-power reference voltage buffer for high-speed and high-precision ADC, including a feedback loop, a current mirror and an output branch; wherein,

[0044] The feedback loop comprises an amplifier, a first NMOS transistor Mn1 and a first PMOS transistor Mp1, an output end of the amplifier is electrically connected to a gate of the first NMOS transistor Mn1, reverse input ends of the amplifier are electrically connected to a source of the first NMOS transistor Mn1 and a source of the first PMOS transistor Mp1 respectively, a gate and a drain of the first PMOS transistor Mp1 are grounded;

[0045] The output branch comprises a second NMOS transistor Mn2, a third NMOS transistor Mn3, a second PMOS transistor Mp2 and a third PMOS transistor Mp3, a gate of the second NMOS transistor Mn2 is electrically connected to a gate of the third NMOS transistor Mn3, a source of the second NMOS transistor Mn2 is electrically connected to a source of the second PMOS transistor Mp2, a gate and a drain of the second PMOS transistor Mp2 are grounded and electrically connected to a gate of the third PMOS transistor Mp3, a drain of the third NMOS transistor Mn3 is electrically connected to a first voltage source, a source of the third NMOS transistor Mn3 is electrically connected to a source of the third PMOS transistor Mp3, a drain of the third PMOS transistor Mp3 is grounded;

[0046] The current mirror comprises a fourth PMOS transistor Mp4 and a fifth PMOS transistor Mp5, a source of the fourth PMOS transistor Mp4 and a source of the fifth PMOS transistor Mp5 are electrically connected to a second voltage source, a drain of the first NMOS transistor Mn1 is electrically connected to a gate and a drain of the fourth PMOS transistor Mp4 and a gate of the fifth PMOS transistor Mp5 respectively, a drain of the second NMOS transistor Mn2 is electrically connected to a gate and a drain of the fifth PMOS transistor Mp5 respectively.

[0047] A reference voltage which is not dependent on PVT variation but has no driving capacity and is output in a bandgap (BG) is taken as an input signal of a reverse input end of the amplifier A1, and a slow feedback loop is formed through the first NMOS transistor Mn1 in a source follower mode, the amplifier A1 has high gain to realize that the source voltage of the first NMOS transistor Mn1 follows the voltage of the BG. When the feedback loop (dotted line frame I) is stable, the DC working point of the circuit can be determined to output the reference voltage with a determined value which has driving load capacity and can quickly recover.

[0048] A copy structure is realized through a current mirror of the fourth PMOS transistor Mp4 and the fifth PMOS transistor Mp5, wherein the fourth PMOS transistor Mp4 and the fifth PMOS transistor Mp5 satisfy W / L (Mp5) = K1 W / L (Mp4)

[0049] (K1 is a proportional coefficient), the proportional coefficient K1 is associated with the transconductance of the second NMOS transistor Mn2, that is, the determination of the proportional coefficient K1 should be specifically determined by the size of the transconductance of the second NMOS transistor Mn2, and the transconductance should be large enough to achieve a small output resistance at point C. At the same time, the first NMOS transistor Mn1 and the second NMOS transistor Mn2 satisfy Mn2=K1 Mn1, and the first PMOS transistor Mp1 and the second PMOS transistor Mp2 satisfy Mp2=K1 Mp1, so as to achieve the same voltage at node B as at node A. The resistor R1 is connected in series between the drain of the second NMOS transistor Mn2 and the drain of the fifth PMOS transistor Mp5, which functions to make the drain-source voltage V DS Similarly, the influence of the channel length modulation effect on the current replication is reduced to obtain better replication accuracy.

[0050] The first voltage source of the output branch is powered by a voltage of 0.9V, because the output stage needs larger current to obtain higher bandwidth, so as to achieve faster transient response speed. By separately supplying lower output voltage, the waste of voltage can be avoided, and the same response speed can be achieved with lower power consumption. The size of the output stage current is set by controlling the proportion of the second NMOS transistor Mn2 and the third NMOS transistor Mn3, the second PMOS transistor Mp2 and the third PMOS transistor Mp3, and the output of the reference voltage is realized by the AB class output structure composed of the third NMOS transistor Mn3 and the third PMOS transistor Mp3. Resistors R2 are connected in series between the gates of the second NMOS transistor Mn2 and the third NMOS transistor Mn3, and between the gates of the second PMOS transistor Mp2 and the third PMOS transistor Mp3. The resistor R2 is a low-pass resistor, which is used as a resistance isolation between the output stage and the replication branch, and reduces the interference of high-frequency noise at the output end on the replication circuit and the slow feedback loop.

[0051] It should be understood that the continuous switching of the load will cause the voltage at the output node to change, and the resistance at point A needs to be small enough to achieve the effect of fast stabilization of point A, so that the output voltage will be quickly stabilized.

[0052] As shown in Figure 2 , a large current I1 is often required to make the output resistance of the amplifier A1 small enough; at the same time, the current I2 cannot be too small to ensure a reliable replication multiple with the output stage. As shown in Figure 5 , the preliminary optimization is made on the circuit structure shown in Figure 2 , the resistance at point A is equal to the inverse of the transconductance of the second NMOS transistor Mn2 in series with the resistance R2, in order to make the inverse of the transconductance of the second NMOS transistor Mn2 reach the same output impedance as the amplifier A1. The same output impedance can be achieved by increasing the amplification factor (proportional coefficient K1) and increasing the current of the replication branch.

[0053] In the condition of realizing the same A point output impedance, Figure 2 The current I1+I2 in the circuit shown is greater than Figure 5 The current I1'+I2'+I3' in the circuit shown, by means of the low-resistance method realized by the gate-drain short circuit, significantly reduces the current consumption, thereby improving the power efficiency.

[0054] Figure 4 The buffer circuit of the application shown is used for realizing the low-power reference voltage buffer Figure 5 The further improvement is made on the basis of the circuit shown,

[0055] Comparison Figure 4 With Figure 5 It can be seen that the buffer circuit of the application uses the diode-connected PMOS tube to replace the resistor to serve as the load.

[0056] Since the gate of the diode-connected PMOS tube is connected to the ground, the output impedance realized at the B point is equal to 0. The PMOS tube serving as the load and the NMOS tube constitute the AB class output at the output stage, so that the output impedance is the parallel connection of the transconductances of the two MOS tubes, reducing the impedance of the output node. Under the condition of the same output stage current, the AB class output structure has a faster response speed. Meanwhile, compared with the AB class output structure based on the source follower replication ( Figure 3 ), although both realize the low output impedance in a wider frequency band, the circuit structure is much simpler, and has a better performance in the power consumption aspect.

[0057] Based on the above, the low-power reference voltage buffer of the application has the following advantages:

[0058] 1. Power consumption: by means of the method of short-circuiting the gate-drain of the MOS tube, the low-resistance gate of the source follower is realized, compared with the traditional structure ( Figure 2 ), the current consumption is reduced, so that the power efficiency is improved. Meanwhile, by means of the setting of the replication ratio of the current mirror, the appropriate current size is divided, the output stage adopts the low-voltage power supply, and the current multiplexing of the AB class output structure, so that the fast transient response speed is obtained while the overall power consumption of the circuit is smaller.

[0059] 2. Output impedance: compared with the output stage with the resistor serving as the load, the diode-connected PMOS tube constitutes the AB class output structure, which can effectively reduce the output resistance, so that under the same current, the greater bandwidth is realized by means of the current multiplexing, to ensure the speed of the buffer.

[0060] 3. Noise: by means of the replication current and the low-pass resistance R2 as the load and the isolation of the replication branch, the coupling noise and crosstalk introduced by the load switching will be well isolated, the feedback loop can work more stably, and the output stable reference voltage is obtained.

[0061] Of course, the above embodiments are only for illustrating the technical concept and characteristics of the present application, and the purpose is to enable those skilled in the art to understand the content of the present application and to implement it, and cannot limit the protection scope of the present application. Any modification made according to the spirit and essence of the main technical solution of the present application should be covered within the protection scope of the present application.

Claims

1. A low-power reference voltage buffer for a high-speed, high-precision ADC, characterized by: It includes feedback loop, current mirror and output branch; among them, The feedback loop includes an amplifier, a first NMOS transistor Mn1, and a first PMOS transistor Mp1. The output of the amplifier is electrically connected to the gate of the first NMOS transistor Mn1. The inverting input of the amplifier is electrically connected to the source of the first NMOS transistor Mn1 and the source of the first PMOS transistor Mp1, respectively. The gate and drain of the first PMOS transistor Mp1 are grounded. The output branch includes a second NMOS transistor Mn2, a third NMOS transistor Mn3, a second PMOS transistor Mp2, and a third PMOS transistor Mp3. The gate of the second NMOS transistor Mn2 is electrically connected to the gate of the third NMOS transistor Mn3, the source of the second NMOS transistor Mn2 is electrically connected to the source of the second PMOS transistor Mp2, the gate and drain of the second PMOS transistor Mp2 are grounded and electrically connected to the gate of the third PMOS transistor Mp3, the drain of the third NMOS transistor Mn3 is electrically connected to a first voltage source, the source of the third NMOS transistor Mn3 is electrically connected to the source of the third PMOS transistor Mp3, and the drain of the third PMOS transistor Mp3 is grounded. The current mirror includes a fourth PMOS transistor Mp4 and a fifth PMOS transistor Mp5, the source of the fourth PMOS transistor Mp4 and the source of the fifth PMOS transistor Mp5 are electrically connected to a second voltage source, the drain of the first NMOS transistor Mn1 is electrically connected to the gate and drain of the fourth PMOS transistor Mp4 and the gate of the fifth PMOS transistor Mp5, respectively, and the drain of the second NMOS transistor Mn2 is electrically connected to its gate and the drain of the fifth PMOS transistor Mp5, respectively.

2. The low-power reference voltage buffer for high-speed and high-precision ADC according to claim 1, wherein: A bandgap reference voltage of 0.7V is input to the positive input terminal of the amplifier.

3. The low-power reference voltage buffer for high-speed and high-precision ADC according to claim 1, wherein: The first NMOS transistor Mn1 and the second NMOS transistor Mn2 meet the following requirements: Mn2=K1Mn1 The first PMOS transistor Mp1 and the second PMOS transistor Mp2 satisfy: Mp2=K1Mp1 The fourth PMOS transistor Mp4 and the fifth PMOS transistor Mp5 satisfy the following conditions: W / L (Mp5) =K1W / L (Mp4) Among them, K1 is the proportional coefficient.

4. The low-power reference voltage buffer for high-speed and high-precision ADC according to claim 3, wherein: The proportionality coefficient K1 is associated with the transconductance of the second NMOS transistor Mn2.

5. The low-power reference voltage buffer for high-speed and high-precision ADC according to claim 1, wherein: The input voltage of the first voltage source is lower than the input voltage of the second voltage source.

6. The low-power reference voltage buffer for high-speed and high-precision ADC according to claim 5, characterized in that: The first voltage source inputs a voltage of 0.9V.

7. The low-power reference voltage buffer for high-speed and high-precision ADC according to claim 5, characterized in that: The second voltage source inputs a voltage of 1.8V.

8. The low-power reference voltage buffer for high-speed and high-precision ADC according to claim 1, wherein: A resistor R1 is connected in series between the drain of the second NMOS transistor Mn2 and the drain of the fifth PMOS transistor Mp5 .

9. The low-power reference voltage buffer for high-speed and high-precision ADC according to claim 1, wherein: A resistor R2 is connected in series between the gate of the second NMOS transistor Mn2 and the gate of the third NMOS transistor Mn3.

10. The low-power reference voltage buffer for high-speed and high-precision ADC according to claim 1, characterized in that: A resistor R2 is connected in series between the gate of the second PMOS transistor Mp2 and the gate of the third PMOS transistor Mp3.

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