Storage device

Abstract

The invention discloses storage equipment. The storage equipment comprises an open industrial standard interconnection interface and a storage module, the open type industrial standard interconnection interface is used for communicating with a main control component, and the storage module is connected with the open type industrial standard interconnection interface; the storage module comprises a cache module and a final storage module; wherein the cache module comprises a static random access memory; wherein the main control component accesses the storage module in sequence according to the sequence of the cache module and the final storage module. The invention provides a storage device structure scheme which can meet the personalized requirement of a product for rich storage devices.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a storage device. Background Art

[0002] With the development of electronic technology, various electronic products have an increasing demand for the performance and capacity of storage devices.

[0003] There are many types of existing storage devices, including memory devices that are randomly accessed by bytes, such as Double Data Rate (DDR) and Static Random Access Memory (SRAM), which generally have the characteristics of fast speed and random address access, but cannot save data when the power is off. There are also hard disk devices that are accessed by block address, such as mechanical hard disks and solid-state hard disks, which generally have slow reading and writing speeds, but can persist data when the power is off.

[0004] Existing storage devices all have their own limitations and are unable to meet the rich and personalized needs of electronic products for storage devices. Summary of the invention

[0005] In view of the above problems, the present invention is proposed to provide a storage device that overcomes the above problems or at least partially solves the above problems.

[0006] In a first aspect, a storage device is provided, comprising: Open industry standard interconnect interfaces and storage modules; The open industry standard interconnection interface is used to communicate with the main control component, and the storage module is connected to the open industry standard interconnection interface; The storage module includes a cache module and a final storage module; wherein the cache module includes a static random access memory; wherein the main control component accesses the storage module in the order of the cache module and the final storage module.

[0007] Optionally, the storage device further includes: a read / write instruction sorting module connected between the open industry standard interconnect interface and the storage module, for sorting the access requests sent by the main control component into a request queue so as to access the storage module in sequence according to the request queue.

[0008] Optionally, the read-write instruction sorting module is further used to divide the access requests according to request type, and sort the access requests of the same type in an adjacent manner; and / or, the read-write instruction sorting module is further used to divide the access requests according to access addresses, and sort the access requests with closer access addresses in an adjacent manner.

[0009] Optionally, in the process of writing write data to the storage module, first query whether the write data matches the data address in the cache module; if so, write the write data to the cache module, and flush the write data to the final storage module; if not, update the data in the cache module with the write data, and flush the write data to the final storage module; in the process of reading read data from the storage module, first query whether the read data matches the data address in the cache module; if so, obtain the read data from the cache module; if not, obtain the read data from the final storage module, and update the data in the cache module with the read data.

[0010] Optionally, each piece of data stored in the cache module includes: a mark bit, an address bit and data content, and the mark bit is used to indicate the validity of the data content of the data and the consistency of the data content with the corresponding data in the final storage module.

[0011] Optionally, in the process of writing write data to the storage module, first query whether the write data matches the data address in the cache module; if so, write the write data to the cache module, and flush the write data into the final storage module; if not, update the original data in the cache module with the write data, flush the write data into the final storage module, and determine whether to flush the original data into the final storage module based on the mark bit of the original data; in the process of reading read data from the storage module, first query whether the read data matches the data address in the cache module, if so, obtain the read data from the cache module; if not, obtain the read data from the final storage module, update the original data in the cache module with the read data, and determine whether to flush the original data into the final storage module based on the mark bit of the original data.

[0012] Optionally, the cache module also includes: a cache memory; wherein the tag bit and the address bit are stored in the static random access memory, and the corresponding data content is stored in the cache memory; wherein the main control component accesses the storage module in the order of the static random access memory, the cache memory and the final storage module.

[0013] Optionally, the cache module and / or the final storage module includes a non-volatile memory; the storage device includes a balancing module; wherein the balancing module is connected to the non-volatile memory to evenly set the mapping address of the non-volatile memory according to the usage of the storage area in the non-volatile memory.

[0014] Optionally, the static random access memory and the open industry standard interconnection interface are integrated through chip stacking technology.

[0015] Optionally, the cache module includes any one or more combinations of the following: static random access memory, phase change memory, double rate synchronous dynamic random access memory, dynamic random access memory and flash memory; the final storage module includes any one or more combinations of the following: phase change memory, double rate synchronous dynamic random access memory, dynamic random access memory and flash memory; wherein, in the process of the main control component accessing the storage module, the static random access memory is accessed first.

[0016] The technical solution provided in the embodiments of the present invention has at least the following technical effects or advantages: The storage device provided by the embodiment of the present invention is based on the extensibility of the open industry standard interconnection interface technology, and the storage module connected to the open industry standard interconnection interface includes a cache module and a final storage module. Such a structural setting can flexibly form a storage module with different types of memories, and can be personalized according to product requirements. The memory combination can fully combine the advantages of various memories and obtain a storage device that meets various product requirements. In addition, the cache module is also set to include a static random access memory, and the main control component is set to preferentially access the cache module. Due to the high-speed performance of the static random access memory, setting it in the cache module can improve the access speed of the entire storage device, and can also make up for its shortcomings of not being able to maintain data for a long time, high cost, insufficient storage space or large chip area through the memory setting of the final storage module.

[0017] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings: Figure 1 Schematic diagram of the structure of the storage device in the embodiment of the present invention Figure 1 ; Figure 2 Schematic diagram of the structure of the storage device in the embodiment of the present invention Figure 2 ; Figure 3 Schematic diagram of the structure of the storage device in the embodiment of the present invention Figure 3 ; Figure 4 Schematic diagram of the structure of the storage device in the embodiment of the present invention Figure 4 ; Figure 5 Schematic diagram of the structure of the storage device in the embodiment of the present invention Figure 5 ; Figure 6 Schematic diagram of the structure of the storage device in the embodiment of the present invention Figure 6 . DETAILED DESCRIPTION

[0019] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to be able to fully convey the scope of the present disclosure to those skilled in the art. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0020] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0021] See also Figure 1 The embodiment of the present application provides a storage device, including: an open industry standard interconnection interface 1 and a storage module 2. The open industry standard interconnection interface 1 is used to communicate with the main control component 101, and the storage module 2 is connected to the open industry standard interconnection interface 1. The storage module 2 includes a cache module 21 and a final storage module 22; wherein the cache module 21 includes a static random access memory 211; wherein the main control component 101 accesses the storage module 2 in the order of the cache module 21 and the final storage module 22.

[0022] It should be noted that the open industry standard interconnect interface 1 is a CXL (Compute Express Link) interface, which can be used to support the connection of processors, accelerators, memory buffers, intelligent network interfaces and various memories. Based on the open industry standard interconnect interface 1, various types of memories such as static random access memory, phase change memory, double rate synchronous dynamic random access memory, dynamic random access memory and flash memory can be combined and connected to form a storage module 2. Using the storage device solution provided by the present application, according to different delay, bandwidth and capacity requirements, personalized storage devices can be realized through different combinations of memories. In addition, by setting the memory type of the final storage module 22, high-performance volatile storage devices can be realized, and non-volatile storage devices can also be realized.

[0023] The following describes in detail the structure and access method of the storage device provided by this application.

[0024] In an optional embodiment, if Figure 2 As shown, the storage device may further include a read / write instruction sorting module 3, which is connected between the open industry standard interconnection interface 1 and the storage module 2, and is used to sort the access requests sent by the main control component 101 into a request queue, so as to sequentially access the storage module 2 according to the request queue. Setting the read / write instruction sorting module 3 can avoid access confusion when multiple access requests are received, and can improve the efficiency and bandwidth through sorting.

[0025] In an optional implementation, the read / write instruction sorting module 3 may divide the access requests according to the request type, and sort the access requests of the same type in an adjacent manner. For example, when the read / write instruction sorting module 3 receives multiple access requests within a preset time period, it divides the access requests according to read requests and write requests, arranges the read requests adjacent to each other, arranges the write requests adjacent to each other, executes the read request (or write request) first, and then executes the write request (or read request), so as to avoid the delay and bandwidth consumption caused by the alternating execution of the read request and the write request, and can effectively improve the efficiency and bandwidth.

[0026] In an optional implementation, the read / write instruction sorting module 3 may further divide the access requests according to the access addresses, and sort the access requests with closer access addresses in an adjacent manner. For example, when the read / write instruction sorting module 3 receives multiple access requests within a time period, it first obtains the access address of each access request, and arranges the access requests with close addresses in an adjacent manner, thereby effectively saving the transmission time of adjacent accesses and effectively improving access efficiency.

[0027] Of course, the above two methods may also be combined to sort the access requests, which is not limited here and will not be listed one by one.

[0028] In the embodiment of the present application, the storage module 2 includes a cache module 21 and a final storage module 22. The cache module 21 may include one or more types of memories, for example, the cache module 21 may include any one or more combinations of the following: static random access memory, phase change memory, double rate synchronous dynamic random access memory, dynamic random access memory, and flash memory. The final storage module 22 may also include one or more types of memories, for example, the final storage module 22 may include any one or more combinations of the following: phase change memory, double rate synchronous dynamic random access memory, dynamic random access memory, and flash memory. There is no limitation here.

[0029] It can also be set that the reading speed of the memory in the cache module 21 is faster than the reading speed of the memory in the final storage module 22, and the storage space of the memory in the final storage module 22 is larger than the storage space of the memory in the cache module 21. This setting can ensure the reading speed through the cache module 21 and also take into account the storage space through the final storage module 22.

[0030] In an optional embodiment, for a personalized storage device formed by a combination of various types of memories, when the main control component 101 accesses the storage module 2, it preferentially accesses the cache module 21 and then accesses the final storage module 22, thereby improving the access speed through the high-speed performance of the cache module 21.

[0031] Specifically, in the process of writing write data to the storage module 2, it is first queried whether the address of the write data matches the address of the data stored in the cache module 21; if they match, the write data is written to the cache module 21, and the write data is flushed into the final storage module 22; if they do not match, the original data in the cache module 21 is updated with the write data, and the write data is flushed into the final storage module 22. In this way, the write data is saved in the cache module 21 so that it can be quickly hit in the cache module 21 when the data is read later, thereby improving the reading speed, and the rewritten data is also saved in the final storage module 22 to prevent it from being replaced and updated by the subsequent written data in the cache module 21, and it can also be read in the final storage module 22. Among them, the step of flushing the write data into the final storage module 22 can be performed synchronously with the storage of the write data in the cache module 21, or it can be flushed into the final storage module 22 for storage when the write data in the cache module 21 is replaced and updated by the subsequent written data, which is not limited here.

[0032] Specifically, in the process of reading the read data from the storage module 2, it is also first queried whether the read data matches the data address in the cache module 21; if they match, the read data is obtained from the cache module 21; if they do not match, the read data is obtained from the final storage module 22, and the data in the cache module 21 is updated with the read data. In this way, by first querying the data in the cache module 21 with a faster reading speed, the speed of data reading can be effectively improved, and the read data is also saved in the cache module 21 so that it can be quickly hit in the cache module 21 when the data is read later.

[0033] In an optional embodiment, each piece of data stored in the cache module 21 may also be configured to include: a mark bit, an address bit, and data content, and the mark bit is used to indicate the validity of the data content of the piece of data, and the consistency of its data content with the corresponding data in the final storage module 22. For example, the flag bit may have three value assignment states: "00" indicates that the data is invalid. "01" indicates that the data is valid, and the data in the cache module 21 is consistent with the data in the final storage module 22. "10" indicates that the data is valid, but the data in the cache module 21 is inconsistent with the data in the final storage module 22 (inconsistency includes that there is no address matching the data in the final storage module 22, or there is an address matching the data in the final storage module 22, but the data content is inconsistent). The generation and modification of the mark bit may be performed by a mark module of the storage device, which generates a corresponding mark position at the head or tail of the data content when the data is written into the cache module 21, and retains or modifies the mark bit after detecting the validity and consistency of the data content.

[0034] In the case where the data is set with a flag bit, in the process of writing write data to the 2 storage modules, first check whether the address of the write data matches the address of the data in the cache module 21; if it matches, the write data is written to the cache module 21, and the write data is flushed into the final storage module; if it does not match, the original data in the cache module is updated with the write data, and the write data is flushed into the final storage module, and whether to flush the original data into the final storage module is determined according to the flag bit of the original data. For example, assuming that the flag bit representation data of the updated original data in the cache module 21 is invalid, the original data is directly deleted; assuming that the flag bit representation data of the original data is valid and consistent with the data in the final storage module 22, the original data is also directly deleted to avoid duplicate storage; assuming that the flag bit representation data of the original data is valid and inconsistent with the data in the final storage module 22, in order to avoid data loss, the original data is flushed into the final storage module 22 for storage.

[0035] In the case where the data is set with a flag bit, in the process of reading the read data from the storage module 2, it is first checked whether the read data matches the data address in the cache module 21. If they match, the read data is obtained from the cache module 21; if they do not match, the read data is obtained from the final storage module 22, and the original data in the cache module 21 is updated with the read data, and it is determined whether to flush the original data into the final storage module 22 according to the flag bit of the original data. The method of determining whether to flush the original data into the final storage module 22 according to the flag bit is the same as that of writing data, and will not be repeated here.

[0036] Specifically, setting a mark bit in the data stored in the cache module 21 can effectively avoid resources consumed by repeated storage, and can also avoid data loss, thereby ensuring data integrity.

[0037] In the embodiment of the present application, the cache module 21 is also provided to include a static random access memory 211. Since the static random access memory 211 has advantages such as high read and write performance and does not require dynamic refresh, it is provided in the cache module 21 to better ensure the access speed of the storage device. Furthermore, it is also provided that during the access process of the main control component 101 to the storage module 2, the static random access memory 211 is accessed first, then other memories in the cache module 21 are accessed (other memories may not be provided), and finally the memory in the final storage module 22 is accessed, thereby further ensuring the access efficiency.

[0038] In an optional implementation, the static random access memory 211 and the open industry standard interconnection interface 1 can also be integrated together through chip stacking technology (2D interconnection technology, 2.5D interconnection technology or 3D interconnection technology), that is, a built-in static random access memory 211 is used, so that the duration of data communication between the static random access memory 211 and the open industry standard interconnection interface 1 can be significantly shortened, and the access efficiency can be improved. Of course, the static random access memory 211 can also be an independent memory, and can be connected to the open industry standard interconnection interface 1 by plugging, welding, wire connection, etc., which is not limited here.

[0039] Furthermore, considering that the static random access memory 211 has the limitations of low integration, high cost and limited capacity, other types of memory can be set in the cache module 21 to cooperate with the static random access memory 211 to achieve a cache with larger capacity and lower cost. Specifically, Figure 2 As shown, the cache module 21 may also include one or more cache memories 212 .

[0040] It can also be set that the reading speed of the static random access memory 211 is faster than the reading speed of the cache memory 212, and the storage space of the cache memory 212 is larger than the storage space of the static random access memory 211. This setting can ensure the reading speed through the static random access memory 211, and can also take into account the storage space of the cache through the cache memory 212. Among them, the cache memory 212 can include any one or more combinations of the following: phase change memory, double rate synchronous dynamic random access memory, dynamic random access memory and flash memory, etc., which are not limited here.

[0041] In an optional implementation, a static random access memory 211 may be configured to store a flag bit and an address bit, and a cache memory 212 may be configured to store corresponding data content (of course, the flag bit, address bit, and data content format may also be used for storage in both the static random access memory 211 and the cache memory 212, which is not limited here). In this way, the flag bit and address bit of the data are stored separately from the corresponding data content in different memories, which can avoid the limitation that the static random access memory 211 cannot be used to provide a large cache due to its high cost, and also take into account the performance and capacity of the cache by storing the data content that occupies a large space in the cache memory 212 with a lower cost.

[0042] Among them, for the personalized storage device formed by the combination of various types of memories, the main control component 101 accesses the storage module 2 in the order of static random access memory 211, cache memory 212 and final storage module 22, so as to improve the access speed through the high-speed performance of the static random access memory 211.

[0043] Taking the static random access memory 211 for storing the mark bit and the address bit as an example, in the process of writing write data to the storage module 2, the static random access memory 211 is first accessed to query whether the address of the write data matches the address of the data stored in the static random access memory 211; if they match, the mark bit and the address bit of the write data are written into the static random access memory 211, and the data content is correspondingly written into the cache memory 212, and the write data is flushed into the final storage module 22; if they do not match, the mark bit and the address bit of the original data in the static random access memory 211 are updated with the write data, and the data content of the cache memory 212 is correspondingly updated, and the write data is flushed into the final storage module 22.

[0044] Taking the static random access memory 211 for storing the mark bit and the address bit as an example, in the process of reading the read data from the storage module 2, it is also first checked whether the read data matches the data address in the static random access memory 211; if it matches, the corresponding data content is obtained from the cache memory 212; if it does not match, the read data is obtained from the final storage module 22, and the mark bit and the address bit of the original data in the static random access memory 211 are updated with the read data, and the data content of the cache memory 212 is updated accordingly.

[0045] In an optional embodiment, the cache module 21 and / or the final storage module 22 may include a non-volatile memory (such as a phase change memory or a flash memory, etc.), and correspondingly, the storage device may include a balancing module. The balancing module is connected to the non-volatile memory to evenly set the mapping address of the non-volatile memory according to the usage of the storage area in the non-volatile memory. Specifically, the balancing module stores a storage address mapping table of the non-volatile memory, which represents the mapping relationship between the logical address and the physical address. According to the query of the mapping table, the logical address of the access request can be mapped to the physical address of the non-volatile memory. The balancing module records the usage of each physical area in the non-volatile memory to evenly set the storage address mapping table, avoid excessive use of some storage blocks, resulting in consumption of the life of the storage blocks, and try to evenly set the physical address of the data storage to ensure balanced loss of the storage blocks.

[0046] In an optional implementation, multiple master control devices 101 (mainboard or CPU, etc.) may be connected to the storage device provided in the present application based on the pooling technology of CXL to realize storage sharing.

[0047] Next, combine Figure 3~Figure 6 An example is given of a personalized storage device solution composed of different types of memories based on the inventive concept of the present application.

[0048] Please refer to Figure 3 , providing a high-performance, large-capacity volatile storage device. Its cache module 21 uses a static random access memory 211 ( Figure 3 The final storage module 22 uses a dynamic random access memory ( Figure 3 The cache data stored in the static random access memory 211 may adopt a structure including a flag bit, an address bit and data content.

[0049] Figure 3The data access steps of the storage device shown can be: after receiving an access request through the open industry standard interconnection interface 1, first determine whether the read and write instruction sorting module 3 is idle. If it is idle, directly access the storage module 2. If it is not idle, the read and write instruction sorting module 3 sorts the access instructions and waits for execution.

[0050] When the access request is to write write data, first check whether the address of the write data matches the address of the data in the static random access memory 211; if they match, the write data is written into the static random access memory 211, and the write data is flushed into the dynamic random access memory; if they do not match, the original data in the static random access memory 211 is updated with the write data, and the write data is flushed into the dynamic random access memory, and whether to flush the original data into the dynamic random access memory is determined based on the mark bit of the original data.

[0051] When the access request is to read the read data, first check whether the read data matches the data address in the static random access memory 211. If so, obtain the read data from the static random access memory 211; if not, obtain the read data from the dynamic random access memory, and use the read data to update the original data in the static random access memory 211, and determine whether to flush the original data into the dynamic random access memory based on the mark bit of the original data.

[0052] use Figure 3 The storage device shown combines the high speed advantage of the static random access memory 211 and the large capacity and low cost advantage of the dynamic random access memory, providing a high performance and large capacity volatile storage device.

[0053] Please refer to Figure 4 , providing a high-performance, large-capacity non-volatile storage device. Its cache module 21 uses a static random access memory 211 ( Figure 4 Indicated as SRAM Cache in the figure), the final storage module 22 adopts phase change memory ( Figure 4 The cache data stored in the static random access memory 211 may adopt a structure including a flag bit, an address bit and data content. The phase change memory is connected to the balancing module 4. When reading and writing particles of the phase change memory, the storage address needs to be remapped through the balancing module 4. When writing data, the balancing operation of the balancing module 4 must be triggered according to the write amount, so as to balance the mapping address of the non-volatile memory according to the usage of the storage area in the non-volatile memory to prevent overwork of some areas. The balancing module can be a software algorithm for balancing configuration addresses, which can be stored in any hardware as a balancing module, which balances the usage of various areas of the non-volatile memory by mapping different areas of the non-volatile memory to the same mapping address.

[0054] Figure 4The data access steps of the storage device shown can be: after receiving an access request through the open industry standard interconnection interface 1, first determine whether the read and write instruction sorting module 3 is idle. If it is idle, directly access the storage module 2. If it is not idle, the read and write instruction sorting module 3 sorts the access instructions and waits for execution.

[0055] When the access request is to write write data, first check whether the address of the write data matches the address of the data in the static random access memory 211; if they match, the write data is written into the static random access memory 211, and the address mapping table in the equalization module 4 is queried and modified as needed to flush the write data into the phase change memory; if they do not match, the original data in the static random access memory 211 is updated with the write data, and the address mapping table in the equalization module 4 is queried and modified as needed to flush the write data into the phase change memory, and whether to flush the original data into the phase change memory is determined based on the mark bit of the original data.

[0056] When the access request is to read the read data, first query whether the read data matches the data address in the static random access memory 211. If so, obtain the read data from the static random access memory 211; if not, query the address mapping table in the equalization module 4, obtain the read data from the phase change memory according to the mapping address, and update the original data in the static random access memory 211 with the read data, and determine whether to flush the original data into the dynamic random access memory according to the mark bit of the original data.

[0057] use Figure 4 The storage device shown combines the high speed advantage of the static random access memory 211 and the large capacity and non-volatility advantage of the phase change memory, providing a high-performance and large-capacity non-volatile storage device.

[0058] Please refer to Figure 5 , providing a high-performance, large-capacity non-volatile storage device. Its cache module 21 uses a static random access memory 211 ( Figure 5 SRAM TAG) and double rate synchronous dynamic random access memory ( Figure 5 Indicated as DDR Cache), the final storage module 22 adopts phase change memory ( Figure 5 The data stored in the cache module 21 may adopt a structure in which the tag bit and the address bit are stored in the static random access memory 211, and the corresponding data content is stored in the double-speed synchronous dynamic random access memory (of course, the format in which both the static random access memory 211 and the double-speed synchronous dynamic random access memory store the tag bit, the address bit and the data content may also be adopted, which is not limited here). Figure 4 The storage device provided is the same, and the phase change memory is also connected to the equalization module 4.

[0059] Figure 5 The data access steps of the storage device shown can be: after receiving an access request through the open industry standard interconnection interface 1, first determine whether the read and write instruction sorting module 3 is idle. If it is idle, directly access the storage module 2. If it is not idle, the read and write instruction sorting module 3 sorts the access instructions and waits for execution.

[0060] For the case where the access request is to write write data, first query whether the write data matches the address in the static random access memory 211; if they match, write the mark bit and address bit of the write data into the static random access memory 211, and write the data content of the write data into the double-rate synchronous dynamic random access memory accordingly, and flush the write data into the phase change memory through the address mapping table in the equalization module 4; if they do not match, update the mark bit and address bit of the original data in the static random access memory 211 with the write data, and correspondingly update the data content of the double-rate synchronous dynamic random access memory, and query the address mapping table in the equalization module 4, modify the mapping table as needed, flush the write data into the phase change memory, and determine whether to flush the original data into the phase change memory based on the mark bit of the original data.

[0061] When the access request is to read the read data, first query whether the read data matches the address in the static random access memory 211. If so, obtain the corresponding data content from the double-rate synchronous dynamic random access memory. If not, query the address mapping table in the equalization module 4, obtain the read data from the phase change memory according to the mapping address, and use the read data to update the mark bit and address bit of the original data in the static random access memory 211, and correspondingly update the data content of the double-rate synchronous dynamic random access memory, and determine whether to flush the original data into the phase change memory according to the mark bit of the original data.

[0062] use Figure 5 The storage device shown combines the high speed advantage of static random access memory 211 and the large capacity and low cost advantage of double rate synchronous dynamic random access memory in the cache module 21, thereby increasing the cache capacity. Combined with the large capacity and non-volatility advantage of phase change memory, a high performance and ultra-large capacity non-volatile storage device is provided.

[0063] Please refer to Figure 6 , providing a high-performance, ultra-large capacity non-volatile storage device. Its cache module 21 uses a static random access memory 211 ( Figure 6 SRAM TAG), double rate synchronous dynamic random access memory ( Figure 6 DDR Cache) and phase change memory ( Figure 6 The final storage module 22 uses flash memory ( Figure 6The data stored in the cache module 21 may adopt a structure in which the tag bit and the address bit are stored in the static random access memory 211, and the corresponding data content is stored in the double-speed synchronous dynamic random access memory and the phase change memory (of course, the format in which the tag bit, the address bit and the data content are all stored in the static random access memory 211, the double-speed synchronous dynamic random access memory and the phase change memory may also be adopted, which is not limited here). Figure 4 The storage devices provided are the same, the phase change memory is also connected to the balancing module 4 , and the flash memory is also connected to the balancing module 4 .

[0064] Figure 6 The data access steps of the storage device shown can be: after receiving an access request through the open industry standard interconnection interface 1, first determine whether the read and write instruction sorting module 3 is idle. If it is idle, directly access the storage module 2. If it is not idle, the read and write instruction sorting module 3 sorts the access instructions and waits for execution.

[0065] In the case where the access request is to write write data, first query in the static random access memory 211 to see whether the write data matches the address corresponding to the data content in the double-rate synchronous dynamic random access memory in the static random access memory 211; if they match, the mark bit and address bit of the write data are written into the static random access memory 211, and the data content of the write data is correspondingly written into the double-rate synchronous dynamic random access memory, and the write data is flushed into the phase change memory and the flash memory step by step through the address mapping table in each equalization module 4; if they do not match, query in the static random access memory 211 to see whether the write data matches the data content in the phase change memory in the static random access memory 211. whether the corresponding address in matches; if so, the mark bit and address bit of the write data are written into the static random access memory 211, and the data content of the write data is correspondingly written into the phase change memory, and the write data is flushed into the flash memory through the address mapping table in the equalization module 4; if not, the mark bit and address bit of the original data in the static random access memory 211 are updated with the write data, and the data content of the double-rate synchronous dynamic random access memory is correspondingly updated, and the address mapping tables in the respective equalization modules 4 are queried, and the mapping tables are modified as needed, and the write data is flushed into the phase change memory and the flash memory step by step, and whether the original data is flushed into the flash memory is determined according to the mark bit of the original data.

[0066] For the case where the access request is to read the read data, first query in the static random access memory 211 whether the read data matches the address corresponding to the data content in the double-rate synchronous dynamic random access memory in the static random access memory 211; if they match, obtain the corresponding data content from the double-rate synchronous dynamic random access memory; if they do not match, query in the static random access memory 211 whether the read data matches the address corresponding to the data content in the phase change memory in the static random access memory 211; if they match, obtain the corresponding data content from the phase change memory; if they do not match, query the address mapping table in the equalization module 4, obtain the read data from the flash memory according to the mapping address, and use the read data to update the mark bit and address bit of the original data in the static random access memory 211, and correspondingly update the data content of the double-rate synchronous dynamic random access memory and the phase change memory, and determine whether to flush the original data into the flash memory according to the mark bit of the original data.

[0067] use Figure 6 The storage device shown combines the high speed advantage of static random access memory 211, the large capacity and low cost advantage of double rate synchronous dynamic random access memory, and the large capacity and low cost advantage of phase change memory in the cache module 21, and further increases the cache capacity through a two-level cascade method. Combined with the large capacity and non-volatility advantages of flash memory, a high-performance and ultra-large capacity non-volatile storage device is provided.

[0068] Of course, in the specific implementation process, the structure of the storage device is not limited to Figure 3~Figure 6 The combination shown can be used to personalize the combination of various types of memory according to the product's requirements for storage capacity, response speed, cost, etc., to form volatile and non-volatile storage devices of different performance levels and different capacity levels that meet rich personalized needs.

[0069] The technical solution provided in the embodiments of the present invention has at least the following technical effects or advantages: The storage device provided by the embodiment of the present invention is based on the extensibility of the open industry standard interconnection interface technology, and the storage module connected to the open industry standard interconnection interface includes a cache module and a final storage module. Such a structural setting can flexibly form a storage module with different types of memories, and can be personalized according to product requirements. The memory combination can fully combine the advantages of various memories and obtain a storage device that meets various product requirements. In addition, the cache module is also set to include a static random access memory, and the main control component is set to preferentially access the cache module. Due to the high-speed performance of the static random access memory, setting it in the cache module can improve the access speed of the entire storage device, and can also make up for its shortcomings of not being able to maintain data for a long time, high cost, insufficient storage space or large chip area through the memory setting of the final storage module.

[0070] The algorithm and display provided herein are not inherently related to any particular computer, virtual system or other device. Various general purpose systems can also be used together with the teachings based on this. According to the above description, it is obvious that the structure required for constructing such systems. In addition, the present invention is not directed to any specific programming language either. It should be understood that various programming languages ​​can be utilized to realize the content of the present invention described herein, and the description of the above specific languages ​​is for disclosing the best mode of the present invention.

[0071] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0072] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof.

[0073] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and further may be divided into a plurality of submodules or subunits or subcomponents. All features disclosed in this specification (including the abstract and drawings) and all processes or units of any method or device disclosed in this manner may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying abstract and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0074] Furthermore, those skilled in the art will appreciate that although some embodiments herein include certain features included in other embodiments but not other features, the combination of features from different embodiments is meant to be within the scope of the present invention and to form different embodiments.

[0075] It should be noted that the above embodiments illustrate the present invention rather than limiting it. Any reference symbol between brackets should not be constructed as a limitation of the present invention. The word "comprising" does not exclude the presence of components or steps not listed in the present invention. The word "one" or "an" preceding a component does not exclude the presence of multiple such components. The present invention can be implemented by means of hardware including several different components and by means of appropriately programmed computers. In the embodiments in which several devices are listed, several of these devices can be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.

Claims

1. A storage device, characterized in that: include: Open industry standard interconnect interfaces and storage modules; The open industry standard interconnection interface is used to communicate with the main control component, and the storage module is connected to the open industry standard interconnection interface; The storage module includes a cache module and a final storage module; wherein the cache module includes a static random access memory; wherein the main control component accesses the storage module in the order of the cache module and the final storage module.

2. The storage device according to claim 1, wherein: Also includes: A read / write instruction sorting module is connected between the open industry standard interconnection interface and the storage module, and is used to sort the access requests sent by the main control component into a request queue so as to access the storage module in sequence according to the request queue.

3. The storage device according to claim 2, wherein: The read / write instruction sorting module is further used to classify the access requests according to request types, and sort the access requests of the same type in an adjacent manner; And / or, the read / write instruction sorting module is further used to divide the access requests according to access addresses, and sort the access requests in a manner such that access requests with closer access addresses are adjacent to each other.

4. The storage device according to claim 1, wherein: In the process of writing write data to the storage module, first query whether the write data matches the data address in the cache module; if so, write the write data to the cache module and flush the write data into the final storage module; if not, update the data in the cache module with the write data and flush the write data into the final storage module; In the process of reading read data from the storage module, first query whether the read data matches the data address in the cache module; if so, obtain the read data from the cache module; if not, obtain the read data from the final storage module, and update the data in the cache module with the read data.

5. The storage device according to claim 1, wherein: Each piece of data stored in the cache module includes: a mark bit, an address bit and data content, and the mark bit is used to indicate the validity of the data content of the data and the consistency of the data content with the corresponding data in the final storage module.

6. The storage device according to claim 5, characterized in that: In the process of writing write data to the storage module, first query whether the write data matches the data address in the cache module; if so, write the write data to the cache module, and flush the write data into the final storage module; if not, update the original data in the cache module with the write data, flush the write data into the final storage module, and determine whether to flush the original data into the final storage module according to the flag bit of the original data; In the process of reading read data from the storage module, first query whether the read data matches the data address in the cache module. If so, obtain the read data from the cache module; if not, obtain the read data from the final storage module, and use the read data to update the original data in the cache module, and determine whether to flush the original data into the final storage module based on the mark bit of the original data.

7. The storage device according to claim 5, characterized in that: The cache module further includes: a cache memory; wherein the tag bit and the address bit are stored in the static random access memory, and the corresponding data content is stored in the cache memory; The main control component accesses the storage module in the order of the static random access memory, the cache memory and the final storage module.

8. The storage device according to claim 1, wherein: The cache module and / or the final storage module includes a non-volatile memory; the storage device includes a balancing module; The balancing module is connected to the non-volatile memory to evenly set the mapping address of the non-volatile memory according to the usage of the storage area in the non-volatile memory.

9. The storage device according to claim 1, wherein: The static random access memory and the open industry standard interconnection interface are integrated through chip stacking technology.

10. The storage device according to claim 1, wherein: The cache module includes any one or more combinations of the following: static random access memory, phase change memory, double rate synchronous dynamic random access memory, dynamic random access memory and flash memory; The final storage module includes any one or more of the following combinations: phase change memory, double rate synchronous dynamic random access memory, dynamic random access memory and flash memory; Among them, during the process of the main control component accessing the storage module, the static random access memory is accessed first.

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