A device and method for improving test coverage of low-power digital-analog hybrid chips
By creating isolation point winding back the module during the RTL design stage and setting up isolation units, the problem of low test coverage in low-power digital-to-analog hybrid chips is solved, and higher test coverage and design accuracy are achieved.
Patent Information
- Application Number
- CN202411533325.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-05-13
- Estimated Expiration
- 2044-10-31
AI Technical Summary
The prior art is difficult to improve the test coverage between the digital module switched power domain and the analog module in a low-power digital-to-analog hybrid chip, especially in the presence of an isolation unit, resulting in a loss of test coverage.
During the RTL design phase, an isolation point winding module is created, the isolation unit is set inside the module, and observation and testing is carried out through the winding logic test module, reducing the complexity and error probability of manually instantiating the isolation unit.
Improves the logical measurability of digital modules to analog modules in low-power digital-to-analog hybrid chips, enhances test coverage, reduces design complexity and error rates, and simplifies the testing process.
Smart Images
Figure CN119336561B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of chip testing, and in particular to a device and method for improving the test coverage of a low-power digital-analog hybrid chip. Background Art
[0002] As chip testing requirements become increasingly stringent, chip-level DFT (design for testability) becomes increasingly important, especially as the chip DPPM (number of defective products per million) requirements become increasingly stringent, resulting in higher and higher requirements for chip test coverage.
[0003] In order to meet the DPPM requirements of automotive-grade chips, DFT design engineers need to improve the chip test coverage as much as possible during the chip design stage. In order to reduce the power consumption of the chip, a low-power chip usually contains more than one power domain, at least one normally-on power domain and a turn-off power domain. In order to ensure that the signal transmitted from the turn-off power domain to the normally-on power domain is a fixed value in low-power mode, an isolation unit needs to be inserted between the two power domains; at the same time, in a mixed-signal chip, many signals are directly transmitted from the turn-off power domain of the digital module to the analog module, and an isolation unit must also be inserted between the two modules.
[0004] Since the analog module is a black box for the DFT tool, the signals input to and output from the analog module cannot be observed, which has a great impact on the test coverage of the digital logic. In particular, when there are isolation units on the path of the input to the analog module, the loss of test coverage is more significant.
[0005] For the logic of the digital module in the low-power mixed-analog chip that can turn off the power domain to the analog module, it is difficult to observe the loop back in the design stage, because the isolation unit cannot be specified to be inserted before the loop back point in the logic synthesis stage. Figure 1 As shown in the figure, the position of the expected isolation unit loop point and the position of the actual loop point after logic synthesis are marked. The current solution is to manually instantiate the isolation unit directly in the design during the RTL (register transfer level) design stage, and then perform loop observation at the output of the isolation unit. However, this method is very complicated and it is difficult to ensure the accuracy of manual instantiation for designs with many digital-analog interaction signals.
[0006] Existing technologies can no longer meet people's needs at this stage. Based on the current situation, it is urgent to improve existing technologies. Summary of the invention
[0007] The object of the present invention is to provide a device and method for improving the test coverage of a low-power digital-analog hybrid chip, so as to solve the problems raised in the above-mentioned background technology.
[0008] On the one hand, the present invention provides the following technical solution: a device for improving the test coverage of a low-power digital-analog hybrid chip, comprising: a digital module and an analog module, wherein:
[0009] The digital module includes: a power domain that can be turned off, a first isolation unit, a second isolation unit, a third isolation unit, a fourth isolation unit, a normally open power domain, an isolation point wraparound module and a wraparound logic test module;
[0010] The input ends of the first isolation unit and the second isolation unit are both connected to a power domain that can be turned off, and the output ends are connected to the analog module through a normally open power domain;
[0011] The input ends of the third isolation unit and the fourth isolation unit are both connected to the shut-down power domain, and the output ends are directly connected to the analog module;
[0012] The isolation point wraparound module is provided with a first wraparound point of the output end of the third isolation unit and a second wraparound point of the output end of the fourth isolation unit outside, and the first wraparound point and the second wraparound point are both connected to the wraparound logic test module;
[0013] The wrap-around logic test module includes: a first multiplexer, a second multiplexer, a third multiplexer, a first register and a second register.
[0014] The first wrap-around point and the second wrap-around point are both connected to one of the input terminals of the first multiplexer,
[0015] The output end of the first multiplexer is connected to one input end of the second multiplexer;
[0016] The output end of the second multiplexer is connected to the input end of the first register;
[0017] The output end of the first register is connected to an input end of a third multiplexer, and the output end of the third multiplexer is connected to an input end of a second register, and the second register has an output end. In a test mode, the output end of the second register is used as a signal output of a scan chain in a test mode.
[0018] On the other hand, the present invention also provides another technical solution as follows: a method for improving the test coverage of a low-power digital-analog hybrid chip, the specific steps comprising:
[0019] Step S100: In the RTL design stage, a dedicated module is created on the top level of the digital module: an isolation point wraparound module, so that all inputs of the isolation point wraparound module come from the power domain that can be turned off, and the output of the isolation point wraparound module is directly used as the input of the analog module;
[0020] Step S200: the signal lines of all signals in the module are respectively instantiated as a buffer inside the module by looping the isolation point back to the module, and in the process of logic synthesis, the isolation unit is set inside the module by the synthesis tool by looping the isolation point back to the module;
[0021] Step S300: Wrapping back the wrapping points of all outputs of the isolation point wrapping back module to the register input end in the wrapping back logic test module for observation;
[0022] Step S400: using an ATE test machine to compare the output value of the wrap-around logic test module with the test pattern generated by the DFT tool to determine whether there is a manufacturing defect in the chip.
[0023] The present invention has the following beneficial effects:
[0024] (1) Improved the testability of the logic between the power domain of the digital module and the analog module in the low-power mixed-analog chip, which helps to improve the test coverage of the entire digital module to meet the increasingly stringent DPPM requirements;
[0025] (2) The isolation unit and the logic inserted during timing repair are placed in the isolation point wraparound module, that is, before the wraparound logic point; there is no need to manually instantiate the isolation unit in the RTL design stage, which reduces the workload and improves the design accuracy;
[0026] (3) For the test of the isolation unit, there is no need to switch the power domain on or off. In the test mode, all power domains of the entire chip are in the on state. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 It is a schematic diagram of the location structure of the winding point of the isolation unit in the prior art;
[0028] Figure 2 The overall structural diagram of the device for improving the test coverage of low-power digital-analog hybrid chips of the present invention;
[0029] Figure 3 Schematic diagram of the internal structure of the wrap-around logic test module of the present invention. DETAILED DESCRIPTION
[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in the field of the present invention without creative work are within the scope of protection of the present invention.
[0031] refer to Figure 2On the one hand, the present invention provides the following technical solution: a device for improving the test coverage of low-power digital-analog hybrid chips, comprising: a digital module and an analog module, wherein:
[0032] The digital module includes: a power domain that can be turned off, a first isolation unit, a second isolation unit, a third isolation unit, a fourth isolation unit, a normally open power domain, an isolation point wraparound module and a wraparound logic test module;
[0033] The first isolation unit and the second isolation unit both have input ends connected to a power domain that can be turned off and output ends connected to the analog module through a normally open power domain;
[0034] The third isolation unit and the fourth isolation unit are both connected to a power domain that can be shut down at the input end and directly connected to the analog module at the output end; and the third isolation unit and the fourth isolation unit are arranged inside the isolation point wraparound module; the outside of the isolation point wraparound module is provided with a first wraparound point of the output end of the third isolation unit and a second wraparound point of the output end of the fourth isolation unit, and the first wraparound point and the second wraparound point are both connected to the wraparound logic test module;
[0035] The first isolation unit, the second isolation unit, the third isolation unit, and the fourth isolation unit all have a signal control terminal (iso_en), and when iso_en is valid, the first isolation unit, the second isolation unit, the third isolation unit, and the fourth isolation unit all output a stable isolated signal (isolated signal); the signal control terminal iso_en generates a control signal through the internal logic of the chip, and for different types of isolation units, the corresponding isolated signal isolated signal is output according to the different effective states of the control signal. For example, when the control signal is 0, the effective isolation unit outputs a stable isolated signal isolated signal "0"; when the control signal is 1, the effective isolation unit outputs a stable isolated signal isolated signal "1".
[0036] refer to Figure 3 , the wrap-around logic test module includes: a first multiplexer (mux0), a second multiplexer (mux1), a third multiplexer (mux2), a first register (reg0) and a second register (reg1);
[0037] Wherein: the first wrap-around point and the second wrap-around point are both connected to one of the input terminals of the first multiplexer,
[0038] The first multiplexer also has a test mode selection terminal (test_mode). When test_mode is 1, the chip enters the test mode, and when test_mode is 0, the chip enters the function mode.
[0039] The output terminal of the first multiplexer is connected to an input terminal of the second multiplexer, and the second multiplexer further has a signal terminal (scan_en) for controlling a scanning process.
[0040] When scan_en is 1, the test vector generated by the DFT tool is injected into the chip, so that all the testable registers in the chip are at a certain value, which represents the shift process. In this embodiment, the shift process is to assign the specific value in the test vector to each testable register in the chip by shifting through the test clock, and at the same time, the value originally stored in the register is transmitted to the scan_out port of the chip through the serial register scan chain (a port on the chip specifically used to output the test vector from the register scan chain to the ATE automatic test machine in test mode).
[0041] When scan_en is 0, it represents the capture process. In this embodiment, the capture process is a process in which each testable register captures the value passed by the functional path in front of it and saves it in the register through the test clock. After the internal register of the chip obtains the new value from the functional path and saves it, it will wait for the next shift process to pass the value down.
[0042] The output end of the second multiplexer is connected to the input end of the first register, and the first register also has a clock test end (test_clock). When the chip is tested on an ATE automatic test machine, the ATE automatic test machine provides a test clock through the clock test end;
[0043] The output end of the first register is connected to one input end of the third multiplexer, and the third multiplexer also has the same signal end (scan_en) for controlling the scanning process as the second multiplexer, and the working principles of the two are the same;
[0044] The output end of the third multiplexer is connected to the input end of the second register, and the second register also has the same clock test end (test_clock) as the first register, and the working principles of the two are the same;
[0045] The second register has an output terminal (scan_out). When test_mode is 1, the chip enters the test mode. The output terminal of the second register is used as a signal output of the scan chain in the test mode.
[0046] As an embodiment of the present invention, the test process of this embodiment is as follows: first, the chip is configured to enter the test mode, and the test mode signal is pulled high to 1. In the test mode, all power domains of the entire chip are in the on state, and the control signal output by the signal control terminal iso_en of all isolation units is in an invalid state (that is, the data input and output of the isolation unit are the same).
[0047] During the shift process, that is, when scan_en = 1, as the test clock flips, reg0 obtains the data from the previous register from the 1-end input port of mux1, and reg1 obtains the data from reg0 from the 1-end input port of mux2. After the shift is completed, both reg0 and reg1 will store certain values; when entering the capture process, that is, scan_en = 1, as the test clock flips, reg0 will obtain the output value from the isolation unit of mux0 from the 0-end input port of mux1 and save it.
[0048] By repeatedly performing the shift and capture processes, the output value of the isolation unit can be output from the scan out port; the ATE automatic test machine compares these output values with the test vectors generated by the DFT tool to determine whether there are manufacturing defects in the chip. This process also completes the scan test of the isolation unit and other logic in the newly added module. In this embodiment, the test vector generated by the DFT includes both the vector injected into the chip and the value expected to be observed at the scan_out port of the chip. Through the shift process, the ATE test machine injects the test vector into the chip, and then through the capture process, the output value of the register scan chain inside the chip can be obtained at the scan_out port of the chip. These output values are compared with the expected values in the test vector. If the comparison results are consistent, it indicates that there are no manufacturing defects in the chip, otherwise it indicates that there may be manufacturing defects in the chip.
[0049] On the other hand, the present invention also provides another technical solution as follows: a method for improving the test coverage of a low-power digital-analog hybrid chip, the specific steps comprising:
[0050] Step S100: In the RTL design stage, a dedicated module is created on the top level of the digital module: an isolation point wraparound module, so that all inputs of the isolation point wraparound module come from the power domain that can be turned off, and the output of the isolation point wraparound module is directly used as the input of the analog module;
[0051] Step S200: the signal lines of all signals in the module are respectively instantiated as a buffer inside the module by looping the isolation point back, and in the process of logic synthesis, the isolation unit is set inside the module by the synthesis tool by looping the isolation point back;
[0052] Step S300: Wrapping back the wrapping points of all outputs of the isolation point wrapping back module to the register input end in the wrapping back logic test module for observation;
[0053] In this embodiment, when the output signals of the isolation point wrap-around module are greater than 2, these signals may be XORed and then wrapped around the register input end of the wrap-around logic test module for observation;
[0054] Step S400: using an ATE test machine to compare the output value of the wrap-around logic test module with the test pattern generated by the DFT tool to determine whether there is a manufacturing defect in the chip.
[0055] Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
Claims
1. A device for improving the test coverage of a low-power digital-analog hybrid chip, comprising: a digital module and an analog module, characterized in that: The digital module comprises: a power domain that can be turned off, a first isolation unit, a second isolation unit, a third isolation unit, a fourth isolation unit, a normally open power domain, an isolation point wraparound module and a wraparound logic test module; the third isolation unit and the fourth isolation unit are both arranged inside the isolation point wraparound module; The input ends of the first isolation unit and the second isolation unit are both connected to a power domain that can be turned off, and the output ends are connected to the analog module through a normally open power domain; The input ends of the third isolation unit and the fourth isolation unit are both connected to the shut-down power domain, and the output ends are directly connected to the analog module; The isolation point wraparound module is provided with a first wraparound point of the output end of the third isolation unit and a second wraparound point of the output end of the fourth isolation unit outside, and the first wraparound point and the second wraparound point are both connected to the wraparound logic test module; The wrap-around logic test module includes: a first multiplexer, a second multiplexer, a third multiplexer, a first register and a second register; wherein: The first wrap-around point and the second wrap-around point are both connected to one of the input terminals of the first multiplexer, The output end of the first multiplexer is connected to one input end of the second multiplexer; The output end of the second multiplexer is connected to the input end of the first register; The output end of the first register is connected to an input end of a third multiplexer, and the output end of the third multiplexer is connected to an input end of a second register, and the second register has an output end. In a test mode, the output end of the second register is used as a signal output of a scan chain in a test mode.
2. The device for improving the test coverage of low-power digital-analog hybrid chips according to claim 1, characterized in that: The first isolation unit, the second isolation unit, the third isolation unit, and the fourth isolation unit all have a signal control end, and when the signal control end is valid, the first isolation unit, the second isolation unit, the third isolation unit, and the fourth isolation unit all output stable isolation signals.
3. The device for improving test coverage of low-power digital-analog hybrid chips according to claim 2, characterized in that: The signal control end generates a control signal through the internal logic of the chip, and outputs corresponding isolation signals for different types of isolation units according to the different effective states of the control signal, including: when the control signal is 0, the effective isolation unit outputs a stable isolation signal "0"; when the control signal is 1, the effective isolation unit outputs a stable isolation signal "1".
4. The device for improving test coverage of low-power digital-analog hybrid chips according to claim 1, characterized in that: The first multiplexer also has a test mode selection terminal. When the test mode selection terminal is 1, the chip enters the test mode; when the test mode selection terminal is 0, the chip enters the functional mode.
5. The device for improving test coverage of low-power digital-analog hybrid chips according to claim 1, characterized in that: The second multiplexer also has a signal terminal for controlling the scanning process. When the signal terminal for controlling the scanning process is 1, a test vector generated by a DFT tool is injected into the chip so that all testable registers in the chip are at a certain value. When the signal end of the control scanning process is 0, the internal register of the chip obtains a new value from the functional path and saves it, and waits for the next shift process to pass the value down. The shift process is a shift process.
6. The device for improving test coverage of low-power digital-analog hybrid chips according to claim 1, characterized in that: The first register also has a clock test terminal, and when the chip is tested on an ATE automatic test machine, the ATE automatic test machine tests the clock through the clock test terminal.
7. The device for improving test coverage of low-power digital-analog hybrid chips according to claim 1, characterized in that: The third multiplexer has the same signal terminal for controlling the scanning process as the second multiplexer; the second register has the same clock test terminal as the first register.
8. A method for improving the test coverage of a low-power digital-analog hybrid chip, characterized in that: The method is implemented based on the device for improving the test coverage of low-power digital-analog hybrid chips as described in any one of claims 1 to 7, and the steps include: S100: In the RTL design stage, create a dedicated module on the top level of the digital module: the isolation point bypass module, so that all inputs of the isolation point bypass module come from the power domain that can be turned off, and the output of the isolation point bypass module is directly used as the input of the analog module; S200: The signal lines of all signals in the module are respectively instantiated as a buffer inside the module by looping the isolation point back. In the process of logic synthesis, the isolation unit is set inside the module by the synthesis tool at the isolation point; S300: Wrapping back all the output wrapping points of the isolation point wrapping back module back to the register input end in the wrapping back logic test module for observation; S400: The output value of the loop-back logic test module is compared with the test vector generated by the DFT tool through the ATE test machine to determine whether there is a manufacturing defect in the chip. When the comparison result is inconsistent, it indicates that there is a manufacturing defect in the chip.
9. The method for improving the test coverage of a low-power digital-analog hybrid chip according to claim 8, characterized in that: The output of the isolation point wraparound module is directly used as the input of the simulation module, and also includes, when the number of output signals of the isolation point wraparound module is greater than 2, observing by performing an XOR operation on the signal and then wrapping it back to the register input end in the wraparound logic test module.
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